v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
verilog_primitive=true
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -90 130 -90 {}
L 4 -130 90 130 90 {}
L 4 -130 -90 -130 90 {}
L 4 130 -90 130 90 {}
L 4 -150 -80 -130 -80 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 -40 -130 -40 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 60 -130 60 {}
L 7 130 -80 150 -80 {}
L 7 130 -60 150 -60 {}
L 7 130 -40 150 -40 {}
L 7 130 -20 150 -20 {}
L 7 130 0 150 0 {}
L 7 130 20 150 20 {}
L 7 130 40 150 40 {}
L 7 130 60 150 60 {}
L 7 130 80 150 80 {}
B 5 147.5 -82.5 152.5 -77.5 {name=VPWR dir=inout }
B 5 147.5 -62.5 152.5 -57.5 {name=OUTPUT1 dir=inout }
B 5 -152.5 -82.5 -147.5 -77.5 {name=SELECT1 dir=in }
B 5 147.5 -42.5 152.5 -37.5 {name=INPUT1_1 dir=inout }
B 5 147.5 -22.5 152.5 -17.5 {name=OUTPUT2 dir=inout }
B 5 -152.5 -62.5 -147.5 -57.5 {name=SELECT2 dir=in }
B 5 147.5 -2.5 152.5 2.5 {name=INPUT1_2 dir=inout }
B 5 147.5 17.5 152.5 22.5 {name=OUTPUT3 dir=inout }
B 5 -152.5 -42.5 -147.5 -37.5 {name=SELECT3 dir=in }
B 5 147.5 37.5 152.5 42.5 {name=INPUT1_3 dir=inout }
B 5 147.5 57.5 152.5 62.5 {name=OUTPUT4 dir=inout }
B 5 -152.5 -22.5 -147.5 -17.5 {name=SELECT4 dir=in }
B 5 147.5 77.5 152.5 82.5 {name=INPUT1_4 dir=inout }
B 5 -152.5 57.5 -147.5 62.5 {name=VGND dir=inout }
T {Tgate4Single01} -81 -6 0 0 0.3 0.3 {}
T {@name} 135 -102 0 0 0.2 0.2 {}
T {VPWR} 125 -84 0 1 0.2 0.2 {}
T {OUTPUT1} 125 -64 0 1 0.2 0.2 {}
T {SELECT1} -125 -84 0 0 0.2 0.2 {}
T {INPUT1_1} 125 -44 0 1 0.2 0.2 {}
T {OUTPUT2} 125 -24 0 1 0.2 0.2 {}
T {SELECT2} -125 -64 0 0 0.2 0.2 {}
T {INPUT1_2} 125 -4 0 1 0.2 0.2 {}
T {OUTPUT3} 125 16 0 1 0.2 0.2 {}
T {SELECT3} -125 -44 0 0 0.2 0.2 {}
T {INPUT1_3} 125 36 0 1 0.2 0.2 {}
T {OUTPUT4} 125 56 0 1 0.2 0.2 {}
T {SELECT4} -125 -24 0 0 0.2 0.2 {}
T {INPUT1_4} 125 76 0 1 0.2 0.2 {}
T {VGND} -125 56 0 0 0.2 0.2 {}