diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
index 2422d93..6f575d0 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1.c
@@ -3,11 +3,11 @@
 
 void main()
 {
-  // reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-  // reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
-  // reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
-  // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
-  // reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+   //reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+   //reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
   reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
   // reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
   // reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
index 725a32d..900ef3b 100644
--- a/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
+++ b/verilog/dv/BrqRV_EB1/BrqRV_EB1_tb.v
@@ -83,13 +83,13 @@
             wait(mprj_io_0 == 28'd13);*/
             
             // Observe Output pins [35:8] for multliplication_table
-            /*wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd5);
             wait(mprj_io_0 == 28'd10);
             wait(mprj_io_0 == 28'd15);
             wait(mprj_io_0 == 28'd20);
             wait(mprj_io_0 == 28'd25);
             wait(mprj_io_0 == 28'd30);
-            */
+            
             // Observe Output pins [35:8] for mean & Determinant
             //wait(mprj_io_0 == 28'd5);
             
@@ -100,30 +100,31 @@
             //wait(mprj_io_0 == 28'd4889874);
             
             // Observe Output pins [35:8] for Queue 
-            //wait(mprj_io_0 == 28'd5);
-            //wait(mprj_io_0 == 28'd6);
-            //wait(mprj_io_0 == 28'd7);
+           // wait(mprj_io_0 == 28'd5);
+           // wait(mprj_io_0 == 28'd6);
+           // wait(mprj_io_0 == 28'd7);
             
             // Observe Output pins [35:8] for perfect square
             //wait(mprj_io_0 == 28'd5);
             
             // Observe Output pins [35:8] for counter / ascending / reverse
-            wait(mprj_io_0 == 28'd15);
-            wait(mprj_io_0 == 28'd14);
-            wait(mprj_io_0 == 28'd13);
-            wait(mprj_io_0 == 28'd12);
-            wait(mprj_io_0 == 28'd11);
-            wait(mprj_io_0 == 28'd10);
-            wait(mprj_io_0 == 28'd9);
-            wait(mprj_io_0 == 28'd8);
-            wait(mprj_io_0 == 28'd7);
-            wait(mprj_io_0 == 28'd6);
-            wait(mprj_io_0 == 28'd5);
-            wait(mprj_io_0 == 28'd4);
-            wait(mprj_io_0 == 28'd3);
-            wait(mprj_io_0 == 28'd2);
+           /* wait(mprj_io_0 == 28'd0);
             wait(mprj_io_0 == 28'd1);
-            wait(mprj_io_0 == 28'd0);
+            wait(mprj_io_0 == 28'd2);
+            wait(mprj_io_0 == 28'd3);
+            wait(mprj_io_0 == 28'd4);
+            wait(mprj_io_0 == 28'd5);
+            wait(mprj_io_0 == 28'd6);
+            wait(mprj_io_0 == 28'd7);
+            wait(mprj_io_0 == 28'd8);
+            wait(mprj_io_0 == 28'd9);
+            wait(mprj_io_0 == 28'd10);
+            wait(mprj_io_0 == 28'd11);
+            */
+            //wait(mprj_io_0 == 28'd3);
+            //wait(mprj_io_0 == 28'd2);
+            //wait(mprj_io_0 == 28'd1);
+            //wait(mprj_io_0 == 28'd0);
             $display("MPRJ-IO state = %d ", mprj_io[35:8]);  
 		
 		`ifdef GL
@@ -169,6 +170,7 @@
 	wire flash_io1;
 	wire r_Rx_Serial;
 	assign mprj_io[5] = r_Rx_Serial;
+	assign mprj_io[3:0] = 4'h0;
 
 	wire VDD3V3 = power1;
 	wire VDD1V8 = power2;
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 432879e..3483216 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -22,10 +22,13 @@
     // Assume default net type to be wire because GL netlists don't have the wire definitions
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
-    `include "gl/user_proj_example.v"
+    //`include "gl/user_proj_example.v"
+    `include "powered_netlist.v"
+    `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `else
     `include "user_project_wrapper.v"
-    `include "user_proj_example.v"
-    `include "BrqRV_EB1/BrqRV_EB1.v"
+    `include "powered_netlist.v"
+    //`include "user_proj_example.v"
+    //`include "BrqRV_EB1/BrqRV_EB1.v"
     `include "BrqRV_EB1/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `endif
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 0bab84b..5ed2484 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -70,7 +70,17 @@
     input  [`MPRJ_IO_PADS-1:0] io_in,
     output [`MPRJ_IO_PADS-1:0] io_out,
     output [`MPRJ_IO_PADS-1:0] io_oeb,
-
+ 
+    
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+    
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+    
     // IRQ
     output [2:0] irq
 );
@@ -90,6 +100,7 @@
     wire [63:0]	lsu_axi_wdata;
     wire [7:0]         lsu_axi_wstrb;
     reg		lsu_axi_bvalid;
+    reg  [2:0]	        lsu_axi_bid;
 
 
     // WB MI A
@@ -101,11 +112,14 @@
     assign io_out[35:8] = (| lsu_axi_wstrb[3:0]) ? lsu_axi_wdata[27:0] : (| lsu_axi_wstrb[7:4]) ? lsu_axi_wdata[59:32] : {28{1'b0}};
     
     assign io_oeb[35:8] = {28{~lsu_axi_wvalid}};
-    assign io_oeb[7:0] = {8{~rst}};
-    assign io_oeb[37:36] = {2{~rst}};
+    assign io_oeb[3:0]  = 4'hf;
+    assign io_oeb[4]    = 1'b0;
+    assign io_oeb[6:5]  = 2'b01;
+    assign io_oeb[7]    = 1'b0;
     
     always @(posedge wb_clk_i) begin
     	lsu_axi_bvalid = (lsu_axi_wvalid) ? 1'b1 : 1'b0;
+    	lsu_axi_bid    = (| lsu_axi_wstrb[3:0]) ? 3'b000 : (| lsu_axi_wstrb[7:4]) ? 3'b001 : 3'b000;
     end
     // IRQ
     assign irq = 3'b000;	// Unused
@@ -115,7 +129,6 @@
 
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
     assign clk = (~la_oenb[65]) ? la_data_in[65] :  wb_clk_i;
-    //assign clk = wb_clk_i;
     assign rst = (~la_oenb[64]) ? la_data_in[64] : ~wb_rst_i;
     assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];
     assign reset_vector = 32'haffff000;
@@ -232,7 +245,7 @@
     .lsu_axi_bvalid         (lsu_axi_bvalid),
     .lsu_axi_bready         (),
     .lsu_axi_bresp          (2'b00),
-    .lsu_axi_bid            (3'b000),
+    .lsu_axi_bid            (lsu_axi_bid),
 
 
     .lsu_axi_arvalid        (),
@@ -404,11 +417,11 @@
     .trace_rv_i_interrupt_ip(),
     .trace_rv_i_tval_ip     (),
 
-    .jtag_tck               ( (io_oeb[0]) ? io_in[0] : 1'b0 ),
-    .jtag_tms               ( (io_oeb[1]) ? io_in[1] : 1'b0 ),
-    .jtag_tdi               ( (io_oeb[3]) ? io_in[3] : 1'b0 ),
-    .jtag_trst_n            ( (io_oeb[2]) ? io_in[2] : 1'b0  ),
-    .jtag_tdo               ( io_out[4]  ),
+    .jtag_tck               ( io_in[0] ),
+    .jtag_tms               ( io_in[1] ),
+    .jtag_tdi               ( io_in[3] ),
+    .jtag_trst_n            ( io_in[2] ),
+    .jtag_tdo               ( io_out[4]),
 
     .mpc_debug_halt_ack     ( ),
     .mpc_debug_halt_req     ( 1'b0),