)]}'
{
  "commit": "de5e4e11078391cc7efa567e19634b7dda1cb292",
  "tree": "7da67122ecc81e28a91631a98d063a5b33c7e320",
  "parents": [
    "f28a12c47ab36077864be3e13dc259476cde2291"
  ],
  "author": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Mon Jun 07 12:47:23 2021 +0500"
  },
  "committer": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Mon Jun 07 12:47:23 2021 +0500"
  },
  "message": "gpio output fixed\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "51bd7609da5148f84ae55bf97fb4bc735df6fb43",
      "old_mode": 33188,
      "old_path": "verilog/rtl/registers.sv",
      "new_id": "12c99b9b97e916261352db623865d05cde089b1b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/registers.sv"
    },
    {
      "type": "modify",
      "old_id": "0956d0d88bc5df3825a46705338fb22e3358d3a4",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.sv",
      "new_id": "3389db72a3c37d8367c16c05010da5c6e43cc49e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.sv"
    }
  ]
}