)]}'
{
  "commit": "d52549c1ef8455767381c7af55c63b4933a0f5e8",
  "tree": "3b26950c8709440667c07b2645b2f03e84cb54dc",
  "parents": [
    "c59c401c184f32c7fd41d92f84fd3aee1c48a30b"
  ],
  "author": {
    "name": "haseebahmad-lm",
    "email": "haseeb.ahmad@lampromellon.com",
    "time": "Thu May 27 10:44:13 2021 +0500"
  },
  "committer": {
    "name": "haseebahmad-lm",
    "email": "haseeb.ahmad@lampromellon.com",
    "time": "Thu May 27 10:44:13 2021 +0500"
  },
  "message": "added missing reset declaration in registers.v\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f460269c150a383aa0a464f6a583ed972c66b58c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/registers.sv",
      "new_id": "bbfaa17bcef47b2f0bdf0745e84b65451f7dccfc",
      "new_mode": 33188,
      "new_path": "verilog/rtl/registers.sv"
    }
  ]
}