commit c342274c3796ee290715cca3d13077c5b6ef198d
author aghaalizeb-lm <agha.ali@lampromellon.com> Thu May 27 12:52:55 2021 +0500
committer aghaalizeb-lm <agha.ali@lampromellon.com> Thu May 27 12:52:55 2021 +0500
tree 7908bd6da3e430dab1c30ecfbc1f7af4bea7ef8f
parent d2a00104f68068df90c23c001ac712f62902a3d2

ack logic update(read ack)

verilog/rtl/registers.sv

diff --git a/verilog/rtl/registers.sv b/verilog/rtl/registers.sv
index f2bfb43..582db3b 100644
--- a/verilog/rtl/registers.sv
+++ b/verilog/rtl/registers.sv
@@ -189,6 +189,7 @@
                       ({32{fflags_addr}}   & {27'b0, fflags})    |
                       ({32{fcsr_addr}}     & {24'b0, fcsr_read});
 
-    assign ack = inter_gen | wr_opA | wr_opB | wr_opC | wr_op | wr_fflags_r | wr_frm_r | wr_fcsr_r;
+    assign ack = inter_gen | (addr == OPERAND_A) | (addr == OPERAND_B) | (addr == OPERAND_C) | (addr == OPERATION) | 
+                 (addr == FFLAGS) | (addr == FRM) | (addr == FCSR) | (addr == OPERATION_COMPLETED) | (addr == RESULT);
 
 endmodule