diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index 1c056fc..c660de5 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -86,6 +86,7 @@
   wire [31:0] addr;        
 
   wire        wb_valid_f;
+  wire        wb_valid_ns;
 
   assign la_write_en              = |la_write;
   assign addr                     = la_write_en ? la_addr : rdwraddr;
@@ -190,7 +191,9 @@
   
   assign valid_out                = {sqrt_valid_out,div_valid_out,valid_in[8:0]};
 
-  rvdff #(1) wb_valid_ff (.clk(clk), .rst_l(rst_l), .din(wb_valid), .dout(wb_valid_f));
+  assign wb_valid_ns              = |valid_out ? wb_valid : wb_valid_f;
+
+  rvdff #(1) wb_valid_ff (.clk(clk), .rst_l(rst_l), .din(wb_valid_ns), .dout(wb_valid_f));
 
 // return output data according to module enable
   assign {out, exceptions}        = ({37{illegal_op}}                   & {32'b0      ,5'b0              })  |