diff --git a/verilog/rtl/fpu_lib.sv b/verilog/rtl/fpu_lib.sv
index 92cffb2..5953873 100644
--- a/verilog/rtl/fpu_lib.sv
+++ b/verilog/rtl/fpu_lib.sv
@@ -300,7 +300,7 @@
      output wire [WIDTH-1:0] dout
      );
 
-   wire                      l1clk;
+   wire          [WIDTH-1:0] in;
 
 if (SHORT == 1) begin : genblock
    if (1) begin : genblock
@@ -313,7 +313,9 @@
 //    if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
 // `endif
 
-      rvdff #(WIDTH) dff (.din(din), .dout(dout), .rst_l(rst_l), .clk(l1clk));
+			assign in = en ? din : dout;
+
+      rvdff #(WIDTH) dff (.din(in), .dout(dout), .rst_l(rst_l), .clk(clk));
 
 // `ifndef RV_PHYSICAL
 //    end