diff --git a/verilog/rtl/fpu.sv b/verilog/rtl/fpu.sv
index c6c5b01..04326bb 100644
--- a/verilog/rtl/fpu.sv
+++ b/verilog/rtl/fpu.sv
@@ -26,7 +26,7 @@
   input  wire [31:0]     la_addr,                // wire analyzer address
 //outputs
   output wire            illegal_op,
-  output wire            inter_gen,
+  output wire            ack,
 
   output wire [31:0]     rddata,                 // read  data sent to wb
   output wire [31:0]     out,                    // to GPIO
@@ -102,7 +102,7 @@
                                    .opC             (c                        ),
                                    .frm             (round_mode               ),
                                    .op_valids       ({valid_in, op_in}        ),
-                                   .inter_gen       (inter_gen                ));  
+                                   .ack             (ack                      ));  
 
   f_class #(8,24) fpu_fclass      ( .in             (a                        ),
                                     .result         (fclass_out               ) );
diff --git a/verilog/rtl/registers.sv b/verilog/rtl/registers.sv
index bbfaa17..f2bfb43 100644
--- a/verilog/rtl/registers.sv
+++ b/verilog/rtl/registers.sv
@@ -1,14 +1,14 @@
 module fpu_registers(
-    input  wire        clk,
-    input  wire        rst_l,
-    input  wire [31:0] fpu_result,
-    input  wire [12:0] fpu_valids,
-    input  wire [31:0] addr,
-    input  wire        wren,
-    input  wire [31:0] wrdata,
-    input  wire [4:0]  exceptions,
+    input  wire         clk,
+    input  wire         rst_l,
+    input  wire  [31:0] fpu_result,
+    input  wire  [12:0] fpu_valids,
+    input  wire  [31:0] addr,
+    input  wire         wren,
+    input  wire  [31:0] wrdata,
+    input  wire  [4:0]  exceptions,
 
-    output wire        inter_gen,
+    output wire         ack,
     output wire  [31:0] rddata,
     output wire  [31:0] opA,
     output wire  [31:0] opB,
@@ -117,7 +117,7 @@
    wire        addr_intr_gen;
    wire        wr_intr_gen;
    wire        intr_gen_ns;
-   //wire        inter_gen;
+   wire        inter_gen;
 
    assign addr_intr_gen = (addr[31:0] == INTERRUPT_GENERATION);
    assign wr_intr_gen   = (addr_intr_gen && !wren) || fpu_result_valid;
@@ -189,4 +189,6 @@
                       ({32{fflags_addr}}   & {27'b0, fflags})    |
                       ({32{fcsr_addr}}     & {24'b0, fcsr_read});
 
+    assign ack = inter_gen | wr_opA | wr_opB | wr_opC | wr_op | wr_fflags_r | wr_frm_r | wr_fcsr_r;
+
 endmodule
diff --git a/verilog/rtl/user_proj_example.sv b/verilog/rtl/user_proj_example.sv
index a85198d..569ae4f 100644
--- a/verilog/rtl/user_proj_example.sv
+++ b/verilog/rtl/user_proj_example.sv
@@ -333,7 +333,7 @@
 	.wrdata(wdata),
 	.rddata(rdata),
 	.illegal_op(illegal_op),
-	.inter_gen(wbs_ack_o),
+	.ack(wbs_ack_o),
 	.exceptions(exceptions),
 	.out(io_out[31:0]));