diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d87238f..dfbfe51 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = fpu_test_add_sub fpu_test_comp fpu_test_div fpu_test_f2i fpu_test_fclass fpu_test_fma fpu_test_i2f fpu_test_min_max fpu_test_multiply fpu_test_sign_inject fpu_test_sqrt io_ports_fpu_test la_test2_fpu
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 1a834f7..4c8da3e 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -16,129 +16,20 @@
 # SPDX-License-Identifier: Apache-2.0
 -->
 
-# Simulation Environment Setup
-
-There are two options for setting up the simulation environment: 
-
-* Pulling a pre-built docker image 
-* Installing the dependecies locally
-
-## 1. Docker
-
-There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup) 
-
-Run the following to pull the image: 
-
-```
-docker pull efabless/dv_setup:latest
-```
-
-## 2. Local Installion (Linux)
-
-You will need to fullfil these dependecies: 
-
-* Icarus Verilog (10.2+)
-* RV32I Toolchain
-
-Using apt, you can install Icarus Verilog:
-
-```bash
-sudo apt-get install iverilog
-```
-
-Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain, 
-
-```bash
-export GCC_PATH=<gcc-installation-path>
-```
-
-Then, run the following: 
-
-```bash
-# packages needed:
-sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
-    libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
-    gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
-
-sudo mkdir $GCC_PATH
-sudo chown $USER $GCC_PATH
-
-git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
-cd riscv-gnu-toolchain-rv32i
-git checkout 411d134
-git submodule update --init --recursive
-
-mkdir build; cd build
-../configure --with-arch=rv32i --prefix=$GCC_PATH
-make -j$(nproc)
-```
-
-# Running Simulation
-
-## Docker
-
-First, you will need to export a number of environment variables: 
-
-```bash
-export PDK_PATH=<pdk-location/sky130A>
-export CARAVEL_ROOT=<caravel_root>
-export UPRJ_ROOT=<user_project_root>
-```
-
-Then, run the following command to start the docker container :
-
-```
-docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
-```
-
-Then, navigate to the directory where the DV tests reside : 
-
-```bash
-cd $UPRJ_ROOT/verilog/dv/
-```
-
-Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
-
-## Local
-
-You will need to export these environment variables: 
-
-```bash
-export GCC_PATH=<gcc-installation-path>
-export PDK_PATH=<pdk-location/sky130A>
-```
-
-Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
-
-## Both
-
-To run RTL simulation for one of the DV tests, 
-
-```bash
-cd <dv-test>
-make
-```
-
-To run gate level simulation for one of the DV tests, 
-
-```bash
-cd <dv-test>
-SIM=GL make
-```
 
 # User Project Example DV
 
-The directory includes four tests for the counter user-project example: 
+The directory includes multiple tests for the FPU user-project example: 
 
 ### IO Ports Test 
 
-* This test is meant to verify that we can configure the pads for the user project area. The firmware configures the lower 8 IO pads in the user space as outputs:
+* This test is meant to verify that we can configure the pads for the user project area. The firmware configures the lower 32 IO pads in the user space as outputs:
 
 	```c
-	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_0 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 	=  GPIO_MODE_USER_STD_OUTPUT;
 	.....
-	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_32 	=  GPIO_MODE_USER_STD_OUTPUT;
 	```
 
 * Then, the firmware applies the pad configuration by enabling the serial transfer on the shift register responsible for configuring the pads and waits until the transfer is done. 
@@ -147,19 +38,16 @@
 	while (reg_mprj_xfer == 1);
 	```
 
-* The testbench success criteria is that we can observe the counter value on the lower 8 I/O pads. This criteria is checked by the testbench through observing the values on the I/O pads as follows: 
+* The testbench success criteria is that we can observe the fpu_result output value on the lower 32 I/O pads. This criteria is checked by the testbench through observing the values on the I/O pads as follows: 
 
 	```verilog
-	wait(mprj_io_0 == 8'h01);
-	wait(mprj_io_0 == 8'h02);
-	wait(mprj_io_0 == 8'h03);
-	....
-	wait(mprj_io_0 == 8'hFF);
+	wait(mprj_io == 32'h00000003); //(in our case result was 0x00000003)
+
 	```
 
 * If the testbench fails, it will print a timeout message to the terminal. 
 
-### Logic Analyzer Test 1
+### Logic Analyzer Test
  
 * This test is meant to verify that we can use the logic analyzer to monitor and write signals in the user project from the management SoC. Firstly, the firmware configures the upper 16 of the first 32 GPIO pads as outputs from the managent SoC, applies the configuration by initiating the serial transfer on the shift register, and writes a value on the pads to indicate the end of pad configuration and the start of the test. 
 
@@ -173,64 +61,69 @@
 	while (reg_mprj_xfer == 1);
 
 	// Flag start of the test 
-	reg_mprj_datal = 0xAB400000;
+	reg_mprj_datal = 0xAB600000;
 	```
 	
-	This is done to flag the start/success/end of the simulation by writing a certain value to the I/Os which is then checked by the testbench to know whether the test started/ended/succeeded. For example, the testbench checks on the value of the upper 16 of 32 I/Os, if it is equal to `16'hAB40`, then we know that the test started.  
+	This is done to flag the start/success/end of the simulation by writing a certain value to the I/Os which is then checked by the testbench to know whether the test started/ended/succeeded. For example, the testbench checks on the value of the upper 16 of 32 I/Os, if it is equal to `16'hAB60`, then we know that the test started.  
 
 	```verilog
-	wait(checkbits == 16'hAB40);
-	$display("LA Test 1 started");
+	wait(checkbits == 16'hAB60);
+	$display("LA Test started");
 	```
 	
-* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the management SoC to monitor the counter value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_proj_example) to set the counter initial value. This is done by writing to the LA probes enable registers.   Note that the output enable is active low, while the input enable is active high.  Every channel can be configured for input, output, or both independently.
+* Then, the firmware configures the logic analyzer (LA) probes `[31:0]` as inputs to the user project example to send the address value, and configure the logic analyzer probes `[63:32]` as outputs from the management SoC (inputs to the user_proj_example) to set the data value to that particular address set earlier. This is done by writing to the LA probes enable registers.   Note that the output enable is active low, while the input enable is active high.  Every channel can be configured for input, output, or both independently.
 
  
 	```c
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0] inputs to mgmt_soc
-	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32] outputs from mgmt_soc
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    
 	```
 
-* Then, the firmware writes an initial value to the counter through the LA1 data register. Afte writing the counter value, the LA probes are disabled to prevent the counter write signal from being always set to one. 
+ * In the user_proj_example RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`.  The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register. 
 
-	```c
-	reg_la1_data = 0x00000000;     // Write zero to count register
-	reg_la1_oenb  = reg_la1_iena = 0xFFFFFFFF;     // Disable probes
-	```
-
-* The firmware then waits until the count value exceeds 500 and flags the success of the test by writing `0xAB41` to pads 16 to 31.  The firmware reads the count value through the logic analyzer probes `[31:0]` 
-
-	```c
-	if (reg_la0_data > 0x1F4) {	     // Read current count value through LA
-		reg_mprj_datal = 0xAB410000; // Flag success of the test
-		break;
-	}
-	```
-  
-### Logic Analyzer Test 2
- 
-* This test is meant to verify that we can drive the clock and reset signals for the user project example through the logic analyzer. In the [user_proj_example](verilog/rtl/user_proj_example.v) RTL, the clock can either be supplied from the `wb_clk_i` or from the logic analyzer through bit `[64]`. Similarly, the reset signal can be supplied from the `wb_rst_i` or through `LA[65]`.  The firmware configures the clk and reset LA probes as outputs from the management SoC by writing to the LA2 enable register. 
-
+	
 	```c
 	reg_la2_oenb  = reg_la2_iena = 0xFFFFFFFC; 	// Configure LA[64] LA[65] as outputs from the cpu
 	```
 
-* Then, the firmware supplies both clock reset signals through LA2 data register. First, both are set to one. Then, reset is driven to zero and the clock is toggled for 6 clock cycles. 
+* Then, the firmware supplies both clock reset signals through LA2 data register. First, both are set to one. Then, reset is driven to zero and the clock is toggled for 6 clock cycles and it writes the values to the input csrs of fpu at each clock cycle. And then disable probs as inputs to read the result value. 
 
 	```c
 	reg_la2_data = 0x00000003;	// Write one to LA[64] and LA[65]
-	for (i=0; i<11; i=i+1) {   	// Toggle clk & de-assert reset
+	for (i=0; i<12; i=i+1) {   	// Toggle clk & de-assert reset
 		clk = !clk;               	
 		reg_la2_data = 0x00000000 | clk;
+		if(i==0)
+            {reg_la0_data = 0x30000000;
+            reg_la1_data = 0x00000001; }
+		...
+		...
+	}
+	``` 
+
+	```c
+	
+	reg_la0_oenb  = reg_la0_iena = 0xFFFFFFFF;     // Disable probes
+	reg_la1_oenb  = reg_la1_iena = 0xFFFFFFFF;     // Disable probes
+	```
+
+* The firmware then checks the result value equal to 0x00000003 and flags the success of the test by writing `0xAB461` to pads 16 to 31.  The firmware reads the result value through the logic analyzer probes `[31:0]` 
+
+	```c
+	if (reg_la0_data == 0x00000003) {	     // Read current result value through LA
+		reg_mprj_datal = 0xAB610000; // Flag success of the test
+		break;
 	}
 	```
-* The testbench success criteria is that the firmware reads a count value of five through the LA probes. 
-	```c
-	if (reg_la0_data == 0x05) {
-		reg_mprj_datal = 0xAB610000;   // FLag success of the test
-	}
+
 	```
 	
-### Wishbone Test
+### Wishbone Tests
 
-* This test is meant to verify that we can read and write to the count register through the wishbone port. The firmware writes a value of `0x2710` to the count register, then reads back the count value after some time. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus. 
+* This test is meant to verify that we can read and write to the fpu registers through the wishbone port. The firmware writes a value to the input csrs which are operands and operation conntrol csr that controls which fpu operation to perform. Then it waits untill the interrupt csr value becomes 1 which indicates the completion of fpu operation. After completion of fpu operation final thing is to read the result and exception csr values and check whether it is according to the expected result depending upon the operaton. The read and write transactions happen through the management SoC wishbone bus and are initiated by either writing or reading from the user project address on the wishbone bus. These tests starting from fpu_test prefix use the same approach but they target different sub modules of FPU i.e.
+  * fpu_test_add_sub 
+  * ...
+  * ...
+  * fpu_test_sqrt
+
+* The defines which target the user project example csrs are defined in dv_defs.h 
diff --git a/verilog/dv/dv_defs.h b/verilog/dv/dv_defs.h
new file mode 100644
index 0000000..80f17fb
--- /dev/null
+++ b/verilog/dv/dv_defs.h
@@ -0,0 +1,13 @@
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ups_operand_a		            	(*(volatile uint32_t*)0x30000000)
+#define ups_operand_b		            	(*(volatile uint32_t*)0x30000004)
+#define ups_operand_c		            	(*(volatile uint32_t*)0x30000008)
+#define ups_result     		            	(*(volatile uint32_t*)0x3000000c)
+#define ups_operation_completed 		(*(volatile uint32_t*)0x30000010)
+#define ups_interrupt_generation		(*(volatile uint32_t*)0x30000014)
+#define ups_operation		            	(*(volatile uint32_t*)0x3000001c)
+#define ups_fflags		                (*(volatile uint32_t*)0x30000020)
+#define ups_frm		                    	(*(volatile uint32_t*)0x30000024)
+#define ups_fcsr		                (*(volatile uint32_t*)0x30000028)
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_add_sub/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_add_sub/Makefile
index 132a1cc..299d4bd 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_add_sub/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_add_sub
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog   -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_add_sub/fpu_test_add_sub.c b/verilog/dv/fpu_test_add_sub/fpu_test_add_sub.c
new file mode 100644
index 0000000..d2804da
--- /dev/null
+++ b/verilog/dv/fpu_test_add_sub/fpu_test_add_sub.c
@@ -0,0 +1,125 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	= 0x00000001;
+	ups_operand_b 	= 0x00000002;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000100000000;
+
+	 while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	 while (ups_operation_completed != 256); //waiting for the operation to be completed
+
+     while (ups_result != 0x00000003);
+     while (ups_fflags != 0x00000000);
+
+    	
+        reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0x7f7fffff;
+	ups_operand_b 	= 0x00000002;
+	ups_frm		= 0x00000001;
+	ups_operation	= 0b00000000000000000000000100000000;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 256);
+
+    while (ups_result != 0x7f7fffff);
+    while (ups_fflags != 0x00000001);	
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0x7F000000;
+	ups_operand_b 	= 0x7F700000;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000100000001;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 257);
+
+    while (ups_result != 0xFEE00000);
+    while (ups_fflags != 0x00000000);
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+    reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_add_sub/fpu_test_add_sub_tb.v b/verilog/dv/fpu_test_add_sub/fpu_test_add_sub_tb.v
new file mode 100644
index 0000000..b663c04
--- /dev/null
+++ b/verilog/dv/fpu_test_add_sub/fpu_test_add_sub_tb.v
@@ -0,0 +1,204 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_add_sub_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+	    //RAND MEM
+    parameter RAND1 = 8'h00;
+    parameter RAND4 = 8'h04;
+    parameter RAND8 = 8'h08;
+    parameter RANDc = 8'h0c;
+    parameter RANDf = 8'h0f;
+	parameter MEM_BASE_ADR   =  32'h a000_0000;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_add_sub.vcd");
+		$dumpvars(0, fpu_test_add_sub_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (10000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+
+	spiflash #(
+		.FILENAME("fpu_test_add_sub.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_comp/Makefile
similarity index 94%
rename from verilog/dv/wb_port/Makefile
rename to verilog/dv/fpu_test_comp/Makefile
index 132a1cc..133a723 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_comp/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_comp
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_comp/fpu_test_comp.c b/verilog/dv/fpu_test_comp/fpu_test_comp.c
new file mode 100644
index 0000000..ba33f2e
--- /dev/null
+++ b/verilog/dv/fpu_test_comp/fpu_test_comp.c
@@ -0,0 +1,125 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x7f700000;
+	ups_operand_b 	    = 0x7f800000;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000000000010000;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000010); //waiting for the operation to be completed
+
+    while (ups_result != 0x00000001);
+    while (ups_fflags != 0x00000000);
+
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f700000;
+	ups_operand_b 	    = 0x7f800000;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000000000010001;
+
+
+    while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00000011);
+
+    while (ups_result != 0x00000001);
+    while (ups_fflags != 0x00000000);	
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0xff7fffff;
+	ups_operand_b 	= 0xff7fffff;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000000010010;
+
+
+	while (ups_interrupt_generation != 1);
+    while (ups_operation_completed != 0x00000012);
+
+    while (ups_result != 0x00000001);
+    while (ups_fflags != 0x00000000);	
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_comp/fpu_test_comp_tb.v b/verilog/dv/fpu_test_comp/fpu_test_comp_tb.v
new file mode 100644
index 0000000..fd3bf52
--- /dev/null
+++ b/verilog/dv/fpu_test_comp/fpu_test_comp_tb.v
@@ -0,0 +1,192 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_comp_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_comp.vcd");
+		$dumpvars(0, fpu_test_comp_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+		initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_comp.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_div/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_div/Makefile
index 132a1cc..24b25e3 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_div/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_div
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_div/fpu_test_div.c b/verilog/dv/fpu_test_div/fpu_test_div.c
new file mode 100644
index 0000000..710bc51
--- /dev/null
+++ b/verilog/dv/fpu_test_div/fpu_test_div.c
@@ -0,0 +1,127 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x00000001;
+	ups_frm		        = 0x00000000;
+
+	ups_operation	    = 0b00000000000000000000100000000000;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000800); //waiting for the operation to be completed
+
+    while (ups_result != 0x3f800000);
+    while (ups_fflags != 0x00000000);
+
+        reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x7f7fffff;
+	ups_frm		        = 0x00000000;
+
+	ups_operation	    = 0b00000000000000000000100000000000;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000800);
+
+    while (ups_result != 0);
+    while (ups_fflags != 0x00000003);	
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x00000000;
+	ups_frm		        = 0x00000000;
+
+	ups_operation	    = 0b00000000000000000000100000000000;
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000800);
+
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000008);
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_div/fpu_test_div_tb.v b/verilog/dv/fpu_test_div/fpu_test_div_tb.v
new file mode 100644
index 0000000..3f9c72c
--- /dev/null
+++ b/verilog/dv/fpu_test_div/fpu_test_div_tb.v
@@ -0,0 +1,193 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_div_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    wire gpio;
+    wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_div.vcd");
+		$dumpvars(0, fpu_test_div_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_div.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_f2i/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_f2i/Makefile
index 132a1cc..f726e0f 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_f2i/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_f2i
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_f2i/fpu_test_f2i.c b/verilog/dv/fpu_test_f2i/fpu_test_f2i.c
new file mode 100644
index 0000000..62de2e4
--- /dev/null
+++ b/verilog/dv/fpu_test_f2i/fpu_test_f2i.c
@@ -0,0 +1,125 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000000010000001;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000081); //waiting for the operation to be completed
+ 
+    while (ups_result != 0x7fffffff);
+    while (ups_fflags != 0x00000010);
+
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0xff7fffff;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000000010000001;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 0x00000081);
+
+    while (ups_result != 0x80000000);
+    while (ups_fflags != 0x00000004);
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0xff7fffff;
+	ups_operand_b 	= 0x7F700000;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000010000000;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+    while (ups_operation_completed != 0x00000080);
+
+    while (ups_result != 0x00000000);
+    while (ups_fflags != 0x00000004);
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_f2i/fpu_test_f2i_tb.v b/verilog/dv/fpu_test_f2i/fpu_test_f2i_tb.v
new file mode 100644
index 0000000..7933d3f
--- /dev/null
+++ b/verilog/dv/fpu_test_f2i/fpu_test_f2i_tb.v
@@ -0,0 +1,185 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_f2i_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_f2i.vcd");
+		$dumpvars(0, fpu_test_f2i_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+		initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_f2i.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_fclass/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_fclass/Makefile
index 132a1cc..b0f8e94 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_fclass/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_fclass
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_fclass/fpu_test_fclass.c b/verilog/dv/fpu_test_fclass/fpu_test_fclass.c
new file mode 100644
index 0000000..a7085e6
--- /dev/null
+++ b/verilog/dv/fpu_test_fclass/fpu_test_fclass.c
@@ -0,0 +1,121 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0xff800000;
+
+	ups_operation	    = 0b00000000000000000000000000000100;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 4); //waiting for the operation to be completed
+   
+    while (ups_result != 0x00000001);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x00000000;
+
+	ups_operation	    = 0b00000000000000000000000000000100;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 4);
+    
+    while (ups_result != 16);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x77770000;
+	ups_operation	    = 0b00000000000000000000000000000100;
+
+
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 4);
+
+    while (ups_result != 64);
+    while (ups_fflags != 0x00000000);
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_fclass/fpu_test_fclass_tb.v b/verilog/dv/fpu_test_fclass/fpu_test_fclass_tb.v
new file mode 100644
index 0000000..44dd75e
--- /dev/null
+++ b/verilog/dv/fpu_test_fclass/fpu_test_fclass_tb.v
@@ -0,0 +1,178 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_fclass_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_fclass.vcd");
+		$dumpvars(0, fpu_test_fclass_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+		initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_fclass.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_fma/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_fma/Makefile
index 132a1cc..3f4a30f 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_fma/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_fma
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_fma/fpu_test_fma.c b/verilog/dv/fpu_test_fma/fpu_test_fma.c
new file mode 100644
index 0000000..3aa32e5
--- /dev/null
+++ b/verilog/dv/fpu_test_fma/fpu_test_fma.c
@@ -0,0 +1,131 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x00000002;
+	ups_operand_c 	    = 0x00000003;
+	ups_frm		    = 0x00000003;
+	ups_operation	    = 0b00000000000000000000010000000000;
+	//expected_result     = 0x00000004;
+    //expected_exception  = 0x00000003;
+
+	//waiting for operation to be completed
+	while (ups_interrupt_generation != 1); //waiting for the operation to be completed
+	while (ups_operation_completed != 1024);
+
+    while (ups_result != 0x00000004);
+    while (ups_fflags != 0x00000003);
+	
+        reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f7fffff;
+	ups_operand_b 	    = 0x00000002;
+	ups_operand_c 	    = 0xf0000002;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000010000000000;
+	//expected_result     = 0xf0000001;
+    //expected_exception  = 0x00000001;
+
+    while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 1024);
+	
+    while (ups_result != 0xf0000001);
+    while (ups_fflags != 0x00000001); 
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x76000000;
+	ups_operand_b 	    = 0x7F700000;
+	ups_operand_c 	    = 0x78000000;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000010000000000;
+	//expected_result     = 0x7f800000;
+    //expected_exception  = 0x00000005;
+
+	while (ups_interrupt_generation != 1);
+    while (ups_operation_completed != 1024);
+	
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000005);
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test3
+    reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_fma/fpu_test_fma_tb.v b/verilog/dv/fpu_test_fma/fpu_test_fma_tb.v
new file mode 100644
index 0000000..97c1814
--- /dev/null
+++ b/verilog/dv/fpu_test_fma/fpu_test_fma_tb.v
@@ -0,0 +1,200 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_fma_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_fma.vcd");
+		$dumpvars(0, fpu_test_fma_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000008) begin//operand c			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.c)
+								$display("\nc NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.c);
+							else
+								$display("\ntime = %0d \n c is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_fma.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_i2f/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_i2f/Makefile
index 132a1cc..b552747 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_i2f/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_i2f
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_i2f/fpu_test_i2f.c b/verilog/dv/fpu_test_i2f/fpu_test_i2f.c
new file mode 100644
index 0000000..f0817bf
--- /dev/null
+++ b/verilog/dv/fpu_test_i2f/fpu_test_i2f.c
@@ -0,0 +1,128 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000000001000001;
+	//expected_result     = 0x4eff0000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+    while (ups_operation_completed != 0x00000041); //waiting for the operation to be completed
+
+    while (ups_result != 0x4eff0000);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0xff7fffff;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000000001000001;
+	//expected_result     = 0xcb000001;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+    while (ups_operation_completed != 0x00000041); //waiting for the operation to be completed
+
+    while (ups_result != 0xcb000001);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0xff7fffff;
+	ups_operand_b 	= 0x7F700000;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000001000000;
+	//expected_result = 0x4f7f8000;
+    //expected_exception = 0x00000001;
+
+	while (ups_interrupt_generation != 1);
+    while (ups_operation_completed != 0x00000040); //waiting for the operation to be completed
+
+    while (ups_result != 0x4f7f8000);
+    while (ups_fflags != 0x00000001);	
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test3
+
+    reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_i2f/fpu_test_i2f_tb.v b/verilog/dv/fpu_test_i2f/fpu_test_i2f_tb.v
new file mode 100644
index 0000000..38a7f32
--- /dev/null
+++ b/verilog/dv/fpu_test_i2f/fpu_test_i2f_tb.v
@@ -0,0 +1,185 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_i2f_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_i2f.vcd");
+		$dumpvars(0, fpu_test_i2f_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_i2f.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_min_max/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_min_max/Makefile
index 132a1cc..47c4e75 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_min_max/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_min_max
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_min_max/fpu_test_min_max.c b/verilog/dv/fpu_test_min_max/fpu_test_min_max.c
new file mode 100644
index 0000000..8e43f35
--- /dev/null
+++ b/verilog/dv/fpu_test_min_max/fpu_test_min_max.c
@@ -0,0 +1,126 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x7f700000;
+	ups_operand_b 	    = 0x7f800000;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000000000100000;
+	//expected_result     = 0x7f700000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00000020); //waiting for the operation to be completed
+    
+    while (ups_result != 0x7f700000);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f700000;
+	ups_operand_b 	    = 0x7f800000;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000000000100001;
+	//expected_result     = 0x7f800000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00000021);
+
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000000);
+
+        reg_mprj_datal  = 0xAB610000;  //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	= 0xff7fffff;
+	ups_operand_b 	= 0xff7fffff;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000000100000;
+	//expected_result = 0xff7fffff;
+    //expected_exception = 0x00000000;
+
+	 while (ups_operation_completed != 0x00000020);
+
+    while (ups_result != 0xff7fffff);
+    while (ups_fflags != 0x00000000);	
+
+    reg_mprj_datal  = 0xAB610000;  //flag end of test3
+    reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_min_max/fpu_test_min_max_tb.v b/verilog/dv/fpu_test_min_max/fpu_test_min_max_tb.v
new file mode 100644
index 0000000..4c9b84c
--- /dev/null
+++ b/verilog/dv/fpu_test_min_max/fpu_test_min_max_tb.v
@@ -0,0 +1,193 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_min_max_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_min_max.vcd");
+		$dumpvars(0, fpu_test_min_max_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_min_max.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_multiply/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_multiply/Makefile
index 132a1cc..bc2572b 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_multiply/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_multiply
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_multiply/fpu_test_multiply.c b/verilog/dv/fpu_test_multiply/fpu_test_multiply.c
new file mode 100644
index 0000000..2bedcbf
--- /dev/null
+++ b/verilog/dv/fpu_test_multiply/fpu_test_multiply.c
@@ -0,0 +1,128 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000003;
+	ups_operation	    = 0b00000000000000000000001000000000;
+	//expected_result     = 0x00000001;
+    //expected_exception  = 0x00000003;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 512); //waiting for the operation to be completed
+    
+    while (ups_result != 0x00000001);
+    while (ups_fflags != 0x00000003);	
+       
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f7fffff;
+	ups_operand_b 	    = 0x00000002;
+	ups_frm		        = 0x00000001;
+	ups_operation	    = 0b00000000000000000000001000000000;
+	//expected_result     = 0x357fffff;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 512); //waiting for the operation to be completed
+    
+    while (ups_result != 0x357fffff);
+    while (ups_fflags != 0x00000000);	
+       
+    reg_mprj_datal  = 0xAB610000; //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7F000000;
+	ups_operand_b 	    = 0x7F700000;
+	ups_frm		        = 0x00000000;
+	ups_operation	    = 0b00000000000000000000001000000000;
+	//expected_result     = 0x7f800000;
+    //expected_exception  = 0x00000005;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 512); //waiting for the operation to be completed
+    
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000005);	
+       
+    reg_mprj_datal  = 0xAB610000; //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_multiply/fpu_test_multiply_tb.v b/verilog/dv/fpu_test_multiply/fpu_test_multiply_tb.v
new file mode 100644
index 0000000..79d8de5
--- /dev/null
+++ b/verilog/dv/fpu_test_multiply/fpu_test_multiply_tb.v
@@ -0,0 +1,193 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_multiply_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_multiply.vcd");
+		$dumpvars(0, fpu_test_multiply_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_multiply.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_sign_inject/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_sign_inject/Makefile
index 132a1cc..3888b89 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_sign_inject/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_sign_inject
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject.c b/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject.c
new file mode 100644
index 0000000..d8af9f8
--- /dev/null
+++ b/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject.c
@@ -0,0 +1,127 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0xff800770;
+
+	ups_operation	    = 0b00000000000000000000000000001000;
+	//expected_result     = 0xff800000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 8); //waiting for the operation to be completed
+    
+    while (ups_result != 0xff800000);
+    while (ups_fflags != 0x00000000);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0xff800770;
+
+	ups_operation	    = 0b00000000000000000000000000001001;
+	//expected_result     = 0x7f800000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 9); //waiting for the operation to be completed
+    
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000000);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0xff800770;
+	ups_operation	    = 0b00000000000000000000000000001010;
+	//expected_result     = 0xff800000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 10); //waiting for the operation to be completed
+    
+    while (ups_result != 0xff800000);
+    while (ups_fflags != 0x00000000);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject_tb.v b/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject_tb.v
new file mode 100644
index 0000000..1fcf107
--- /dev/null
+++ b/verilog/dv/fpu_test_sign_inject/fpu_test_sign_inject_tb.v
@@ -0,0 +1,186 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_sign_inject_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_sign_inject.vcd");
+		$dumpvars(0, fpu_test_sign_inject_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_sign_inject.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/fpu_test_sqrt/Makefile
similarity index 94%
copy from verilog/dv/wb_port/Makefile
copy to verilog/dv/fpu_test_sqrt/Makefile
index 132a1cc..c1f5d99 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/fpu_test_sqrt/Makefile
@@ -37,7 +37,7 @@
 
 .SUFFIXES:
 
-PATTERN = wb_port
+PATTERN = fpu_test_sqrt
 
 all:  ${PATTERN:=.vcd}
 
@@ -45,12 +45,13 @@
 
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
+
 else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	iverilog  -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
 	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
 	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
 	$< -o $@ 
diff --git a/verilog/dv/fpu_test_sqrt/fpu_test_sqrt.c b/verilog/dv/fpu_test_sqrt/fpu_test_sqrt.c
new file mode 100644
index 0000000..9962221
--- /dev/null
+++ b/verilog/dv/fpu_test_sqrt/fpu_test_sqrt.c
@@ -0,0 +1,128 @@
+/* SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+/*
+    Wishbone Test:
+        - Configures MPRJ lower 8-IO pins as outputs
+        - Checks counter value through the wishbone port
+*/
+int i = 0;
+int clk = 0;
+void main()
+{
+   // volatile unit32_t *base_address;
+    /*
+    IO Control Registers
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+    Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+    Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+    | DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+    | 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+    */
+    /* Set up the housekeeping SPI to be connected internally so    */
+    /* that external pin changes don't affect it.           */
+    reg_spimaster_config = 0xa002;  // Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+    // Connect the housekeeping SPI to the SPI master
+    // so that the CSB line is not left floating.  This allows
+    // all of the GPIO pins to be used for user functions.
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+     /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    reg_mprj_datal = 0xAB600000;
+
+    //writing into input csrs
+	ups_operand_a 	    = 0x00000001;
+	ups_operand_b 	    = 0x00000001;
+    ups_frm             = 0x00000000;
+	ups_operation	    = 0b00000000000000000001000000000000;
+	//expected_result     = 0x1a3504f3;
+    //expected_exception  = 0x00000001;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00001000); //waiting for the operation to be completed
+    
+    while (ups_result != 0x1a3504f3);
+    while (ups_fflags != 0x00000001);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test1
+
+     // Flag start of the test2
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x00800000;
+	ups_operand_b 	    = 0x7f7fffff;
+    ups_frm             = 0x00000000;
+	ups_operation	    = 0b00000000000000000001000000000000;
+	//expected_result     = 0x20000000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00001000); //waiting for the operation to be completed
+    
+    while (ups_result != 0x20000000);
+    while (ups_fflags != 0x00000000);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test2
+
+         // Flag start of the test3
+    reg_mprj_datal = 0xAB600000;
+
+	ups_operand_a 	    = 0x7f800000;
+	ups_operand_b 	    = 0x00000000;
+    ups_frm             = 0x00000000;
+	ups_operation	    = 0b00000000000000000001000000000000;
+	//expected_result     = 0x7f800000;
+    //expected_exception  = 0x00000000;
+
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 0x00001000); //waiting for the operation to be completed
+    
+    while (ups_result != 0x7f800000);
+    while (ups_fflags != 0x00000000);	
+        
+    reg_mprj_datal  = 0xAB610000; //flag end of test3
+
+        reg_mprj_datal  = 0xAB620000; //flag end of all test to finish
+
+}
+
+
diff --git a/verilog/dv/fpu_test_sqrt/fpu_test_sqrt_tb.v b/verilog/dv/fpu_test_sqrt/fpu_test_sqrt_tb.v
new file mode 100644
index 0000000..dfb4a06
--- /dev/null
+++ b/verilog/dv/fpu_test_sqrt/fpu_test_sqrt_tb.v
@@ -0,0 +1,193 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+//`include "fpu.c"
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+/*import "DPI-C" context function void fpu_c (input int a,b,c,roundingMode,
+                                            input bit add_op,
+                                            input int COMP_op,MAC_op,min_max_op,signed_conv,
+                                            input int finalStage_valid,
+                                            output int result,exceptionFlags                                          );*/
+
+module fpu_test_sqrt_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+
+	reg power1, power2;
+
+    	wire gpio;
+    	wire [37:0] mprj_io;
+	wire [15:0] checkbits;
+
+	assign checkbits = mprj_io[31:16];
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("fpu_test_sqrt.vcd");
+		$dumpvars(0, fpu_test_sqrt_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+	reg [32:0]i=1;
+	initial begin
+		fork begin
+			forever begin
+				wait(checkbits == 16'h AB60) begin
+					$display("Monitor: Test %0d Started",i);
+					fork
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000000) begin//operand a			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.a)
+								$display("\na NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.a);
+							else
+								$display("\ntime = %0d \n a is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000004) begin//operand b			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.b)
+								$display("\nb NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.b);
+							else
+								$display("\ntime = %0d \n b is correct\n",$time);
+						end
+
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h30000024) begin//operand rm			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != uut.mprj.mprj.fpu.round_mode)
+								$display("\nrm NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,uut.mprj.mprj.fpu.round_mode);
+							else
+								$display("\ntime = %0d \n rm is correct\n",$time);
+						end
+						wait(uut.mprj.mprj.wbs_adr_i == 32'h3000001c) begin //operand operation			
+							repeat(2)@(negedge uut.mprj.mprj.wb_clk_i);
+							if(uut.mprj.mprj.wbs_dat_i != {19'b0,uut.mprj.mprj.fpu.valid_in,uut.mprj.mprj.fpu.op_in})
+								$display("\noperation NOT CORRECT \ntime = %0d\tactual = 32'h%0h\ expected = 32'h%0h",$time,uut.mprj.mprj.wbs_dat_i,{19'b0,uut.mprj.mprj.fpu.valid_in, uut.mprj.mprj.fpu.op_in});
+							else
+								$display("\ntime = %0d \n operation is correct\n",$time	);
+						end
+					join
+						wait(checkbits == 16'h AB61) begin
+							$display("Monitor: Test %0d Passed\n",i);
+							i = i+1;
+						end
+				end
+			end
+		end
+		begin
+			wait(checkbits == 16'h AB62)
+			begin
+				$display("Monitor: ALL Test Finished");
+				$finish;
+				//disable fork;
+			end
+		end
+		join
+
+	end
+
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;		// Force CSB high
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#170000;
+		CSB = 1'b0;		// CSB can be released
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("fpu_test_sqrt.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
deleted file mode 100644
index 0b23571..0000000
--- a/verilog/dv/io_ports/io_ports.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
-	IO Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
-	/* 
-	IO Control Registers
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
-
-	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
-	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-
-	*/
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-	// Configure lower 8-IOs as user output
-	// Observe counter value in the testbench
-	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
-	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
-
-	/* Apply configuration */
-	reg_mprj_xfer = 1;
-	while (reg_mprj_xfer == 1);
-
-}
-
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports_fpu_test/Makefile
similarity index 100%
rename from verilog/dv/io_ports/Makefile
rename to verilog/dv/io_ports_fpu_test/Makefile
diff --git a/verilog/dv/io_ports_fpu_test/io_ports.c b/verilog/dv/io_ports_fpu_test/io_ports.c
new file mode 100644
index 0000000..950e3ec
--- /dev/null
+++ b/verilog/dv/io_ports_fpu_test/io_ports.c
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "../verilog/dv/dv_defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+	IO Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	/* Set up the housekeeping SPI to be connected internally so	*/
+	/* that external pin changes don't affect it.			*/
+
+	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+                                        // connect to housekeeping SPI
+
+	// Connect the housekeeping SPI to the SPI master
+	// so that the CSB line is not left floating.  This allows
+	// all of the GPIO pins to be used for user functions.
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_8 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_9 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_10 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_11 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_12 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_13 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_14 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_15 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_16 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_17 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_18 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_19 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_20 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_21 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_22 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_23 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_24 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_25 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_26 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_27 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_28 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_29 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_30 	=  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_31 	=  GPIO_MODE_USER_STD_OUTPUT;
+/*
+	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+*/
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+	//reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+    
+    // Flag start of the test1
+    //reg_mprj_datah = 0xAB600001;
+
+    //writing into input csrs
+	ups_operand_a 	= 0x00000001;
+	ups_operand_b 	= 0x00000002;
+	ups_frm		= 0x00000000;
+	ups_operation	= 0b00000000000000000000000100000000;
+	
+	while (ups_interrupt_generation != 1);
+	while (ups_operation_completed != 256); //waiting for the operation to be completed
+   
+    while (ups_result != 0x00000003);
+    while (ups_fflags != 0x00000000);	
+
+}
+
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports_fpu_test/io_ports_tb.v
similarity index 87%
rename from verilog/dv/io_ports/io_ports_tb.v
rename to verilog/dv/io_ports_fpu_test/io_ports_tb.v
index f7628bc..e292ccc 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports_fpu_test/io_ports_tb.v
@@ -30,9 +30,9 @@
 
     	wire gpio;
     	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
+	wire [31:0] mprj_io_0;
 
-	assign mprj_io_0 = mprj_io[7:0];
+	assign mprj_io_0 = mprj_io[31:0];
 	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
 
 	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -54,7 +54,7 @@
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (25) begin
-			repeat (1000) @(posedge clock);
+			repeat (5000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
@@ -69,24 +69,14 @@
 
 	initial begin
 	    // Observe Output pins [7:0]
-	    wait(mprj_io_0 == 8'h01);
-	    wait(mprj_io_0 == 8'h02);
-	    wait(mprj_io_0 == 8'h03);
-    	    wait(mprj_io_0 == 8'h04);
-	    wait(mprj_io_0 == 8'h05);
-            wait(mprj_io_0 == 8'h06);
-	    wait(mprj_io_0 == 8'h07);
-            wait(mprj_io_0 == 8'h08);
-	    wait(mprj_io_0 == 8'h09);
-            wait(mprj_io_0 == 8'h0A);   
-	    wait(mprj_io_0 == 8'hFF);
-	    wait(mprj_io_0 == 8'h00);
+	    wait(mprj_io_0 == 32'h00000003);
 		
 		`ifdef GL
 	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
 		`else
 		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
 		`endif
+		#100;
 	    $finish;
 	end
 
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
deleted file mode 100644
index b23075d..0000000
--- a/verilog/dv/la_test1/Makefile
+++ /dev/null
@@ -1,78 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-## Simulation mode: RTL/GL
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = la_test1
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
deleted file mode 100644
index 220bdfe..0000000
--- a/verilog/dv/la_test1/la_test1.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-// --------------------------------------------------------
-
-/*
-	MPRJ Logic Analyzer Test:
-		- Observes counter value through LA probes [31:0] 
-		- Sets counter initial value through LA probes [63:32]
-		- Flags when counter value exceeds 500 through the management SoC gpio
-		- Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-	// The upper GPIO pins are configured to be output
-	// and accessble to the management SoC.
-	// Used to flad the start/end of a test 
-	// The lower GPIO pins are configured to be output
-	// and accessible to the user project.  They show
-	// the project count value, although this test is
-	// designed to read the project count through the
-	// logic analyzer probes.
-	// I/O 6 is configured for the UART Tx line
-
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-        reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-	// Set UART clock to 64 kbaud (enable before I/O configuration)
-	reg_uart_clkdiv = 625;
-	reg_uart_enable = 1;
-
-        /* Apply configuration */
-        reg_mprj_xfer = 1;
-        while (reg_mprj_xfer == 1);
-
-	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
-	// Configure LA probes [63:32] as outputs from the cpu
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
-
-	// Flag start of the test 
-	reg_mprj_datal = 0xAB400000;
-
-	// Set Counter value to zero through LA probes [63:32]
-	reg_la1_data = 0x00000000;
-
-	// Configure LA probes from [63:32] as inputs to disable counter write
-	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    
-
-	while (1) {
-		if (reg_la0_data > 0x1F4) {
-			reg_mprj_datal = 0xAB410000;
-			break;
-		}
-	}
-	print("\n");
-	print("Monitor: Test 2 Passed\n\n");	// Makes simulation very long!
-	reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
deleted file mode 100644
index 626e390..0000000
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module la_test1_tb;
-	reg clock;
-    reg RSTB;
-	reg CSB;
-
-	reg power1, power2;
-
-    	wire gpio;
-	wire uart_tx;
-    	wire [37:0] mprj_io;
-	wire [15:0] checkbits;
-
-	assign checkbits  = mprj_io[31:16];
-	assign uart_tx = mprj_io[6];
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-	initial begin
-		// $dumpfile("la_test1.vcd");
-		// $dumpvars(0, la_test1_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (200) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test LA (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test LA (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		wait(checkbits == 16'hAB40);
-		$display("LA Test 1 started");
-		wait(checkbits == 16'hAB41);
-		wait(checkbits == 16'hAB51);
-		#10000;
-		$finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#170000;
-		CSB = 1'b0;		// CSB can be released
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		#200;
-		power1 <= 1'b1;
-		#200;
-		power2 <= 1'b1;
-	end
-
-    	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD1V8;
-    	wire VDD3V3;
-	wire VSS;
-    
-	assign VDD3V3 = power1;
-	assign VDD1V8 = power2;
-	assign VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (VDD3V3),
-		.vdda2    (VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (VDD1V8),
-		.vccd2	  (VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("la_test1.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-	// Testbench UART
-	tbuart tbuart (
-		.ser_rx(uart_tx)
-	);
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2_fpu/Makefile
similarity index 100%
rename from verilog/dv/la_test2/Makefile
rename to verilog/dv/la_test2_fpu/Makefile
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2_fpu/la_test2.c
similarity index 68%
rename from verilog/dv/la_test2/la_test2.c
rename to verilog/dv/la_test2_fpu/la_test2.c
index f9a293c..4233337 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/verilog/dv/la_test2_fpu/la_test2.c
@@ -81,12 +81,12 @@
         /* Apply configuration */
         reg_mprj_xfer = 1;
         while (reg_mprj_xfer == 1);
-
+        reg_la2_data = 0x00000000;
 	// Configure All LA probes as inputs to the cpu 
-	reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+	reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]  //output
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32] //output
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64] //input
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96] //input
 
 	// Flag start of the test
 	reg_mprj_datal = 0xAB600000;
@@ -98,13 +98,51 @@
 	reg_la2_data = 0x00000003;
 
 	// Toggle clk & de-assert reset
-	for (i=0; i<11; i=i+1) {
+	for (i=0; i<12; i=i+1) {
 		clk = !clk;
 		reg_la2_data = 0x00000000 | clk;
-	}
+                if(i==0)
+                {reg_la0_data = 0x30000000;
+                reg_la1_data = 0x00000001; }
+                else if(i==2)
+                {reg_la0_data = 0x30000004;
+                reg_la1_data = 0x00000002; }
+                else if(i==4)
+                {reg_la0_data = 0x30000024;
+                reg_la1_data = 0x00000003; }
+                else if(i==6)
+                {
+                        reg_la0_data = 0x3000001c;
+                        reg_la1_data = 0x00000100;
+                }
+                else if(i==8)
+                {
+                        reg_la0_data = 0x30000010;
+                         
+                }
+                else if(i>=10)
+                {
+                      if(reg_la1_data = 0x00000100)
+                         {
+                                
+                                reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
+                                reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
 
-	if (reg_la0_data == 0x05) {
-		reg_mprj_datal = 0xAB610000;
+                         }
+                
+                       
+                }
+
+                            
+
+	}
+        reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
+        reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;
+
+	
+		if (reg_la0_data == 0x00000003) {
+		        reg_mprj_datal = 0xAB610000;
+		        reg_mprj_datal = 0xAB610000;
 	}
 
 }
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2_fpu/la_test2_tb.v
similarity index 98%
rename from verilog/dv/la_test2/la_test2_tb.v
rename to verilog/dv/la_test2_fpu/la_test2_tb.v
index e09905e..ee676b4 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2_fpu/la_test2_tb.v
@@ -47,7 +47,7 @@
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (30) begin
-			repeat (1000) @(posedge clock);
+			repeat (5500) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
deleted file mode 100644
index 304d32c..0000000
--- a/verilog/dv/mprj_stimulus/Makefile
+++ /dev/null
@@ -1,78 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
-
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
-
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-## Simulation mode: RTL/GL
-SIM?=RTL
-
-.SUFFIXES:
-
-PATTERN = mprj_stimulus
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
-	iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
-	$< -o $@ 
-else  
-	iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
-endif
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
-	${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
deleted file mode 100644
index e4d0a2d..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-
-// --------------------------------------------------------
-
-void main()
-{
-    // The upper GPIO pins are configured to be output
-    // and accessble to the management SoC.
-    // Used to flag the start/end of a test
-    // The lower GPIO pins are configured to be output
-    // and accessible to the user project.  They show
-    // the project count value, although this test is
-    // designed to read the project count through the
-    // logic analyzer probes.
-    // I/O 6 is configured for the UART Tx line
-    uint32_t testval;
-
-    reg_spimaster_config = 0xa002;	// Enable, prescaler = 2
-
-    reg_mprj_datal = 0x00000000;
-    reg_mprj_datah = 0x00000000;
-
-    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
-    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
-    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUT_MONITORED;
-    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
-    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
-
-    reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Set UART clock to 64 kbaud (enable before I/O configuration)
-    reg_uart_clkdiv = 625;
-    reg_uart_enable = 1;
-
-    /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-    /* TEST:  Recast channels 35 to 32 to allow input to user project	*/
-    /* This is done locally only:  Do not run reg_mprj_xfer!		*/
-    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-    // Configure LA probes [31:0], [127:64] as inputs to the cpu
-    // Configure LA probes [63:32] as outputs from the cpu
-    reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
-    reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
-    reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-    reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
-
-    // Flag start of the test
-    reg_mprj_datal = 0xAB400000;
-
-    // Set Counter value to zero through LA probes [63:32]
-    reg_la1_data = 0x00000000;
-
-    // Configure LA probes from [63:32] as inputs to disable counter write
-    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
-
-    reg_mprj_datal = 0xAB410000;
-    reg_mprj_datah = 0x00000000;
-
-    // Test ability to force data on channel 37
-    // NOTE:  Only the low 6 bits of reg_mprj_datah are meaningful
-    reg_mprj_datah = 0xffffffca;
-    reg_mprj_datah = 0x00000000;
-    reg_mprj_datah = 0x0f0f0fc5;
-    reg_mprj_datah = 0x00000000;
-
-    // Test ability to read back data generated by the user project
-    // on the "monitored" outputs.  Read from the lower 16 bits and
-    // copy the value to the upper 16 bits.
-
-    testval = reg_mprj_datal;
-    reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
-
-    // Flag end of the test
-    reg_mprj_datal = 0xAB510000;
-}
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
deleted file mode 100644
index 1409015..0000000
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype wire
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module mprj_stimulus_tb;
-    // Signals declaration
-    reg clock;
-    reg RSTB;
-    reg CSB;
-    reg power1, power2;
-    reg power3, power4;
-
-    wire HIGH;
-    wire LOW;
-    wire TRI;
-    assign HIGH = 1'b1;
-    assign LOW = 1'b0;
-    assign TRI = 1'bz;
-
-    wire gpio;
-    wire uart_tx;
-    wire [37:0] mprj_io;
-    wire [15:0] checkbits;
-    wire [3:0] status;
-
-    // Signals Assignment
-    assign checkbits  = mprj_io[31:16];
-    assign status = mprj_io[35:32];
-    assign uart_tx = mprj_io[6];
-    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-    always #12.5 clock <= (clock === 1'b0);
-
-    initial begin
-        clock = 0;
-    end
-
-    initial begin
-        $dumpfile("mprj_stimulus.vcd");
-        $dumpvars(0, mprj_stimulus_tb);
-
-        // Repeat cycles of 1000 clock edges as needed to complete testbench
-        repeat (150) begin
-            repeat (1000) @(posedge clock);
-        end
-        $display("%c[1;31m",27);
-        $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
-        $display("%c[0m",27);
-        $finish;
-    end
-
-    initial begin
-        wait(checkbits == 16'hAB40);
-        $display("Monitor: mprj_stimulus test started");
-        wait(status == 4'ha);
-        wait(status == 4'h5);
-	// Value 0009 reflects copying user-controlled outputs to memory and back
-	// to management-controlled outputs.
-        wait(checkbits == 16'h0009);
-        wait(checkbits == 16'hAB51);
-        $display("Monitor: mprj_stimulus test Passed");
-        #10000;
-        $finish;
-    end
-
-   // Reset Operation
-    initial begin
-        RSTB <= 1'b0;
-        CSB  <= 1'b1;       // Force CSB high
-        #2000;
-        RSTB <= 1'b1;       // Release reset
-        #170000;
-        CSB = 1'b0;         // CSB can be released
-    end
-
-    initial begin		// Power-up sequence
-        power1 <= 1'b0;
-        power2 <= 1'b0;
-        #200;
-        power1 <= 1'b1;
-        #200;
-        power2 <= 1'b1;
-    end
-
-    wire flash_csb;
-    wire flash_clk;
-    wire flash_io0;
-    wire flash_io1;
-
-    wire VDD3V3 = power1;
-    wire VDD1V8 = power2;
-    wire VSS = 1'b0;
-
-    caravel uut (
-        .vddio	  (VDD3V3),
-        .vssio	  (VSS),
-        .vdda	  (VDD3V3),
-        .vssa	  (VSS),
-        .vccd	  (VDD1V8),
-        .vssd	  (VSS),
-        .vdda1    (VDD3V3),
-        .vdda2    (VDD3V3),
-        .vssa1	  (VSS),
-        .vssa2	  (VSS),
-        .vccd1	  (VDD1V8),
-        .vccd2	  (VDD1V8),
-        .vssd1	  (VSS),
-        .vssd2	  (VSS),
-        .clock	  (clock),
-        .gpio     (gpio),
-        .mprj_io  (mprj_io),
-        .flash_csb(flash_csb),
-        .flash_clk(flash_clk),
-        .flash_io0(flash_io0),
-        .flash_io1(flash_io1),
-        .resetb	  (RSTB)
-    );
-
-
-    spiflash #(
-        .FILENAME("mprj_stimulus.hex")
-    ) spiflash (
-        .csb(flash_csb),
-        .clk(flash_clk),
-        .io0(flash_io0),
-        .io1(flash_io1),
-        .io2(),         // not used
-        .io3()          // not used
-    );
-
-    // Testbench UART
-    tbuart tbuart (
-        .ser_rx(uart_tx)
-    );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
deleted file mode 100644
index 425c115..0000000
--- a/verilog/dv/wb_port/wb_port.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020 Efabless Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
-
-/*
-	Wishbone Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Checks counter value through the wishbone port
-*/
-int i = 0; 
-int clk = 0;
-
-void main()
-{
-
-	/* 
-	IO Control Registers
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
-	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
-	
-	 
-	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-	*/
-
-	/* Set up the housekeeping SPI to be connected internally so	*/
-	/* that external pin changes don't affect it.			*/
-
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
-                                        // connect to housekeeping SPI
-
-	// Connect the housekeeping SPI to the SPI master
-	// so that the CSB line is not left floating.  This allows
-	// all of the GPIO pins to be used for user functions.
-
-    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
-     /* Apply configuration */
-    reg_mprj_xfer = 1;
-    while (reg_mprj_xfer == 1);
-
-	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
-
-    // Flag start of the test
-	reg_mprj_datal = 0xAB600000;
-
-    reg_mprj_slave = 0x00002710;
-    if (reg_mprj_slave == 0x2752) {
-        reg_mprj_datal = 0xAB610000;
-    } else {
-        reg_mprj_datal = 0xAB600000;
-    }
-}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
deleted file mode 100644
index b32f900..0000000
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
-module wb_port_tb;
-	reg clock;
-	reg RSTB;
-	reg CSB;
-	reg power1, power2;
-	reg power3, power4;
-
-	wire gpio;
-	wire [37:0] mprj_io;
-	wire [7:0] mprj_io_0;
-	wire [15:0] checkbits;
-
-	assign checkbits = mprj_io[31:16];
-
-	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("wb_port.vcd");
-		$dumpvars(0, wb_port_tb);
-
-		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (30) begin
-			repeat (1000) @(posedge clock);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		`ifdef GL
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
-		`else
-			$display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
-		`endif
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-	   wait(checkbits == 16'h AB60);
-		$display("Monitor: MPRJ-Logic WB Started");
-		wait(checkbits == 16'h AB61);
-		`ifdef GL
-	    	$display("Monitor: Mega-Project WB (GL) Passed");
-		`else
-		    $display("Monitor: Mega-Project WB (RTL) Passed");
-		`endif
-	    $finish;
-	end
-
-	initial begin
-		RSTB <= 1'b0;
-		CSB  <= 1'b1;		// Force CSB high
-		#2000;
-		RSTB <= 1'b1;	    	// Release reset
-		#170000;
-		CSB = 1'b0;		// CSB can be released
-	end
-
-	initial begin		// Power-up sequence
-		power1 <= 1'b0;
-		power2 <= 1'b0;
-		power3 <= 1'b0;
-		power4 <= 1'b0;
-		#100;
-		power1 <= 1'b1;
-		#100;
-		power2 <= 1'b1;
-		#100;
-		power3 <= 1'b1;
-		#100;
-		power4 <= 1'b1;
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-
-	wire VDD3V3 = power1;
-	wire VDD1V8 = power2;
-	wire USER_VDD3V3 = power3;
-	wire USER_VDD1V8 = power4;
-	wire VSS = 1'b0;
-
-	caravel uut (
-		.vddio	  (VDD3V3),
-		.vssio	  (VSS),
-		.vdda	  (VDD3V3),
-		.vssa	  (VSS),
-		.vccd	  (VDD1V8),
-		.vssd	  (VSS),
-		.vdda1    (USER_VDD3V3),
-		.vdda2    (USER_VDD3V3),
-		.vssa1	  (VSS),
-		.vssa2	  (VSS),
-		.vccd1	  (USER_VDD1V8),
-		.vccd2	  (USER_VDD1V8),
-		.vssd1	  (VSS),
-		.vssd2	  (VSS),
-		.clock	  (clock),
-		.gpio     (gpio),
-        .mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.resetb	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("wb_port.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(),			// not used
-		.io3()			// not used
-	);
-
-endmodule
-`default_nettype wire
\ No newline at end of file