)]}'
{
  "commit": "80b76c7cd1aeec74a7d11d08a2221df18600e581",
  "tree": "29805af7c14987089a68646233fb779151acec6b",
  "parents": [
    "de5e4e11078391cc7efa567e19634b7dda1cb292"
  ],
  "author": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Mon Jun 07 17:32:04 2021 +0500"
  },
  "committer": {
    "name": "aghaalizeb-lm",
    "email": "agha.ali@lampromellon.com",
    "time": "Mon Jun 07 17:32:04 2021 +0500"
  },
  "message": "logic analyzer write bug fixed\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3389db72a3c37d8367c16c05010da5c6e43cc49e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.sv",
      "new_id": "f5dbf40b38b4fc382c25e1b94d3be6fb2d56f7b3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.sv"
    }
  ]
}