diff --git a/gds/caravan.gds.gz b/gds/caravan.gds.gz
index 1870f6e..8e3b335 100644
--- a/gds/caravan.gds.gz
+++ b/gds/caravan.gds.gz
Binary files differ
diff --git a/gds/caravel_00020021.gds.gz.00.split b/gds/caravel_00020021.gds.gz.00.split
index 8332c07..eba9f85 100644
--- a/gds/caravel_00020021.gds.gz.00.split
+++ b/gds/caravel_00020021.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_00020021.gds.gz.01.split b/gds/caravel_00020021.gds.gz.01.split
index fb2b7bf..1e2d53d 100644
--- a/gds/caravel_00020021.gds.gz.01.split
+++ b/gds/caravel_00020021.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_00020021.gds.gz.02.split b/gds/caravel_00020021.gds.gz.02.split
index e25e4d6..ed4f8b1 100644
--- a/gds/caravel_00020021.gds.gz.02.split
+++ b/gds/caravel_00020021.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_00020021.gds.gz.03.split b/gds/caravel_00020021.gds.gz.03.split
index fdbf9e1..16334a4 100644
--- a/gds/caravel_00020021.gds.gz.03.split
+++ b/gds/caravel_00020021.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_00020021.gds.gz.04.split b/gds/caravel_00020021.gds.gz.04.split
index f13efc3..097bf56 100644
--- a/gds/caravel_00020021.gds.gz.04.split
+++ b/gds/caravel_00020021.gds.gz.04.split
Binary files differ
diff --git a/gds/caravel_00020021.oas b/gds/caravel_00020021.oas
deleted file mode 100644
index 05a53b7..0000000
--- a/gds/caravel_00020021.oas
+++ /dev/null
Binary files differ
diff --git a/gds/caravel_00020021_fill_pattern.gds.gz.00.split b/gds/caravel_00020021_fill_pattern.gds.gz.00.split
index b45e735..3a25e4f 100644
--- a/gds/caravel_00020021_fill_pattern.gds.gz.00.split
+++ b/gds/caravel_00020021_fill_pattern.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_00020021_fill_pattern.gds.gz.01.split b/gds/caravel_00020021_fill_pattern.gds.gz.01.split
index 17239b9..fefaf4c 100644
--- a/gds/caravel_00020021_fill_pattern.gds.gz.01.split
+++ b/gds/caravel_00020021_fill_pattern.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_00020021_fill_pattern.gds.gz.02.split b/gds/caravel_00020021_fill_pattern.gds.gz.02.split
index eebe06a..5907cb3 100644
--- a/gds/caravel_00020021_fill_pattern.gds.gz.02.split
+++ b/gds/caravel_00020021_fill_pattern.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_00020021_fill_pattern.gds.gz.03.split b/gds/caravel_00020021_fill_pattern.gds.gz.03.split
index 6e1af27..f3046d7 100644
--- a/gds/caravel_00020021_fill_pattern.gds.gz.03.split
+++ b/gds/caravel_00020021_fill_pattern.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_00020021_fill_pattern.gds.gz.04.split b/gds/caravel_00020021_fill_pattern.gds.gz.04.split
index ee0b5af..fccf63a 100644
--- a/gds/caravel_00020021_fill_pattern.gds.gz.04.split
+++ b/gds/caravel_00020021_fill_pattern.gds.gz.04.split
Binary files differ
diff --git a/info.yaml b/info.yaml
index ca62dd0..6637ea3 100644
--- a/info.yaml
+++ b/info.yaml
@@ -5,7 +5,7 @@
     for SKY130.
   foundry: SkyWater
   git_url: https://github.com/mabrains/caravel_user_project_LDO_DPLL.git
-  layout_image: ./gds/caravan.png
+  layout_image: ./signoff/caravel_layout.png
   organization: Mabrains
   organization_url: https://mabrains.com
   owner: Amro Tork
diff --git a/mag/caravan.mag b/mag/caravan.mag
index 34c7af2..6922c11 100644
--- a/mag/caravan.mag
+++ b/mag/caravan.mag
@@ -55396,7 +55396,7 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 245800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_37
+use gpio_defaults_block_0403 gpio_defaults_block_37
 timestamp 1638587925
 transform 1 0 8367 0 1 215600
 box -38 0 6018 2224
@@ -55428,7 +55428,7 @@
 timestamp 1638299091
 transform -1 0 709467 0 1 224200
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_36
+use gpio_defaults_block_0403 gpio_defaults_block_36
 timestamp 1638587925
 transform 1 0 8367 0 1 258800
 box -38 0 6018 2224
@@ -55444,7 +55444,7 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 289000
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_35
+use gpio_defaults_block_0403 gpio_defaults_block_35
 timestamp 1638587925
 transform 1 0 8367 0 1 302000
 box -38 0 6018 2224
@@ -55468,15 +55468,15 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 332200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_32
+use gpio_defaults_block_0403 gpio_defaults_block_32
 timestamp 1638587925
 transform 1 0 8367 0 1 431600
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_33
+use gpio_defaults_block_0403 gpio_defaults_block_33
 timestamp 1638587925
 transform 1 0 8367 0 1 388400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_34
+use gpio_defaults_block_0403 gpio_defaults_block_34
 timestamp 1638587925
 transform 1 0 8367 0 1 345200
 box -38 0 6018 2224
@@ -55492,15 +55492,15 @@
 timestamp 1638030917
 transform -1 0 710203 0 1 479800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_5
+use gpio_defaults_block_0403 gpio_defaults_block_5
 timestamp 1638587925
 transform -1 0 709467 0 1 359400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_6
+use gpio_defaults_block_0403 gpio_defaults_block_6
 timestamp 1638587925
 transform -1 0 709467 0 1 404600
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_7
+use gpio_defaults_block_0403 gpio_defaults_block_7
 timestamp 1638587925
 transform -1 0 709467 0 1 492800
 box -38 0 6018 2224
@@ -55516,11 +55516,11 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 546200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_30
+use gpio_defaults_block_0403 gpio_defaults_block_30
 timestamp 1638587925
 transform 1 0 8367 0 1 602400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_31
+use gpio_defaults_block_0403 gpio_defaults_block_31
 timestamp 1638587925
 transform 1 0 8367 0 1 559200
 box -38 0 6018 2224
@@ -55536,15 +55536,15 @@
 timestamp 1638030917
 transform -1 0 710203 0 1 614000
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_10
+use gpio_defaults_block_0403 gpio_defaults_block_10
 timestamp 1638587925
 transform -1 0 709467 0 1 627000
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_8
+use gpio_defaults_block_0403 gpio_defaults_block_8
 timestamp 1638587925
 transform -1 0 709467 0 1 536800
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_9
+use gpio_defaults_block_0403 gpio_defaults_block_9
 timestamp 1638587925
 transform -1 0 709467 0 1 581800
 box -38 0 6018 2224
@@ -55556,15 +55556,15 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 675800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_27
+use gpio_defaults_block_0403 gpio_defaults_block_27
 timestamp 1638587925
 transform 1 0 8367 0 1 732000
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_28
+use gpio_defaults_block_0403 gpio_defaults_block_28
 timestamp 1638587925
 transform 1 0 8367 0 1 688800
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_29
+use gpio_defaults_block_0403 gpio_defaults_block_29
 timestamp 1638587925
 transform 1 0 8367 0 1 645600
 box -38 0 6018 2224
@@ -55576,11 +55576,11 @@
 timestamp 1638030917
 transform -1 0 710203 0 1 704200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_11
+use gpio_defaults_block_0403 gpio_defaults_block_11
 timestamp 1638587925
 transform -1 0 709467 0 1 672000
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_12
+use gpio_defaults_block_0403 gpio_defaults_block_12
 timestamp 1638587925
 transform -1 0 709467 0 1 717200
 box -38 0 6018 2224
@@ -55592,11 +55592,11 @@
 timestamp 1638030917
 transform 1 0 7631 0 1 762200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_14
+use gpio_defaults_block_0403 gpio_defaults_block_14
 timestamp 1638587925
 transform 1 0 8367 0 1 818400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_26
+use gpio_defaults_block_0403 gpio_defaults_block_26
 timestamp 1638587925
 transform 1 0 8367 0 1 775200
 box -38 0 6018 2224
@@ -55604,7 +55604,7 @@
 timestamp 1638030917
 transform -1 0 710203 0 1 884800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_13
+use gpio_defaults_block_0403 gpio_defaults_block_13
 timestamp 1638587925
 transform -1 0 709467 0 1 897800
 box -38 0 6018 2224
diff --git a/mag/caravel.mag b/mag/caravel.mag
index c9b0cbf..c4c0925 100644
--- a/mag/caravel.mag
+++ b/mag/caravel.mag
@@ -64868,7 +64868,7 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 245800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_37
+use gpio_defaults_block_0403 gpio_defaults_block_37
 timestamp 1638492834
 transform 1 0 8367 0 1 215600
 box -38 0 6018 2224
@@ -64896,7 +64896,7 @@
 timestamp 1638492834
 transform -1 0 709467 0 1 224200
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_36
+use gpio_defaults_block_0403 gpio_defaults_block_36
 timestamp 1638492834
 transform 1 0 8367 0 1 258800
 box -38 0 6018 2224
@@ -64912,7 +64912,7 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 289000
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_35
+use gpio_defaults_block_0403 gpio_defaults_block_35
 timestamp 1638492834
 transform 1 0 8367 0 1 302000
 box -38 0 6018 2224
@@ -64936,11 +64936,11 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 332200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_32
+use gpio_defaults_block_0403 gpio_defaults_block_32
 timestamp 1638492834
 transform 1 0 8367 0 1 431600
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_33
+use gpio_defaults_block_0403 gpio_defaults_block_33
 timestamp 1638492834
 transform 1 0 8367 0 1 388400
 box -38 0 6018 2224
@@ -64960,23 +64960,23 @@
 timestamp 1638492834
 transform -1 0 710203 0 1 479800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_6
+use gpio_defaults_block_0403 gpio_defaults_block_6
 timestamp 1638492834
 transform -1 0 709467 0 1 404600
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_5
+use gpio_defaults_block_0403 gpio_defaults_block_5
 timestamp 1638492834
 transform -1 0 709467 0 1 359400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_7
+use gpio_defaults_block_0403 gpio_defaults_block_7
 timestamp 1638492834
 transform -1 0 709467 0 1 492800
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_30
+use gpio_defaults_block_0403 gpio_defaults_block_30
 timestamp 1638492834
 transform 1 0 8367 0 1 602400
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_31
+use gpio_defaults_block_0403 gpio_defaults_block_31
 timestamp 1638492834
 transform 1 0 8367 0 1 559200
 box -38 0 6018 2224
@@ -64988,11 +64988,11 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 589400
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_9
+use gpio_defaults_block_0403 gpio_defaults_block_9
 timestamp 1638492834
 transform -1 0 709467 0 1 581800
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_8
+use gpio_defaults_block_0403 gpio_defaults_block_8
 timestamp 1638492834
 transform -1 0 709467 0 1 536800
 box -38 0 6018 2224
@@ -65004,11 +65004,11 @@
 timestamp 1638492834
 transform -1 0 710203 0 1 523800
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_28
+use gpio_defaults_block_0403 gpio_defaults_block_28
 timestamp 1638492834
 transform 1 0 8367 0 1 688800
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_29
+use gpio_defaults_block_0403 gpio_defaults_block_29
 timestamp 1638492834
 transform 1 0 8367 0 1 645600
 box -38 0 6018 2224
@@ -65020,11 +65020,11 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 632600
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_11
+use gpio_defaults_block_0403 gpio_defaults_block_11
 timestamp 1638492834
 transform -1 0 709467 0 1 672000
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_10
+use gpio_defaults_block_0403 gpio_defaults_block_10
 timestamp 1638492834
 transform -1 0 709467 0 1 627000
 box -38 0 6018 2224
@@ -65036,11 +65036,11 @@
 timestamp 1638492834
 transform -1 0 710203 0 1 614000
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_26
+use gpio_defaults_block_0403 gpio_defaults_block_26
 timestamp 1638492834
 transform 1 0 8367 0 1 775200
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_27
+use gpio_defaults_block_0403 gpio_defaults_block_27
 timestamp 1638492834
 transform 1 0 8367 0 1 732000
 box -38 0 6018 2224
@@ -65052,11 +65052,11 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 762200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_13
+use gpio_defaults_block_0403 gpio_defaults_block_13
 timestamp 1638492834
 transform -1 0 709467 0 1 762200
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_12
+use gpio_defaults_block_0403 gpio_defaults_block_12
 timestamp 1638492834
 transform -1 0 709467 0 1 717200
 box -38 0 6018 2224
@@ -65068,7 +65068,7 @@
 timestamp 1638492834
 transform -1 0 710203 0 1 704200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_25
+use gpio_defaults_block_0403 gpio_defaults_block_25
 timestamp 1638492834
 transform 1 0 8367 0 1 818400
 box -38 0 6018 2224
@@ -65076,7 +65076,7 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 805400
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_24
+use gpio_defaults_block_0403 gpio_defaults_block_24
 timestamp 1638492834
 transform 1 0 8367 0 1 944200
 box -38 0 6018 2224
@@ -65084,7 +65084,7 @@
 timestamp 1638492834
 transform 1 0 7631 0 1 931200
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_14
+use gpio_defaults_block_0403 gpio_defaults_block_14
 timestamp 1638492834
 transform -1 0 709467 0 1 940600
 box -38 0 6018 2224
@@ -65092,11 +65092,11 @@
 timestamp 1638492834
 transform -1 0 710203 0 1 927600
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_22
+use gpio_defaults_block_0403 gpio_defaults_block_22
 timestamp 1638492834
 transform 0 1 161594 -1 0 1029341
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_23
+use gpio_defaults_block_0403 gpio_defaults_block_23
 timestamp 1638492834
 transform 0 1 110194 -1 0 1029341
 box -38 0 6018 2224
@@ -65108,7 +65108,7 @@
 timestamp 1638492834
 transform 0 1 148600 -1 0 1030077
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_21
+use gpio_defaults_block_0403 gpio_defaults_block_21
 timestamp 1638492834
 transform 0 1 212994 -1 0 1029341
 box -38 0 6018 2224
@@ -65120,11 +65120,11 @@
 timestamp 1638492834
 transform 0 1 251400 -1 0 1030077
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_19
+use gpio_defaults_block_0403 gpio_defaults_block_19
 timestamp 1638492834
 transform 0 1 315994 -1 0 1029341
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_20
+use gpio_defaults_block_0403 gpio_defaults_block_20
 timestamp 1638492834
 transform 0 1 264394 -1 0 1029341
 box -38 0 6018 2224
@@ -65132,11 +65132,11 @@
 timestamp 1638492834
 transform 0 1 303000 -1 0 1030077
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_17
+use gpio_defaults_block_0403 gpio_defaults_block_17
 timestamp 1638492834
 transform 0 1 433794 -1 0 1029341
 box -38 0 6018 2224
-use gpio_defaults_block_1800 gpio_defaults_block_18
+use gpio_defaults_block_0403 gpio_defaults_block_18
 timestamp 1638492834
 transform 0 1 366394 -1 0 1029341
 box -38 0 6018 2224
@@ -65148,7 +65148,7 @@
 timestamp 1638492834
 transform 0 1 353400 -1 0 1030077
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_16
+use gpio_defaults_block_0403 gpio_defaults_block_16
 timestamp 1638492834
 transform 0 1 510794 -1 0 1029341
 box -38 0 6018 2224
@@ -65156,7 +65156,7 @@
 timestamp 1638492834
 transform 0 1 497800 -1 0 1030077
 box 882 167 34000 13000
-use gpio_defaults_block_1800 gpio_defaults_block_15
+use gpio_defaults_block_0403 gpio_defaults_block_15
 timestamp 1638492834
 transform 0 1 562194 -1 0 1029341
 box -38 0 6018 2224
diff --git a/mag/gpio_defaults_block_1800.mag b/mag/gpio_defaults_block_0403.mag
similarity index 99%
rename from mag/gpio_defaults_block_1800.mag
rename to mag/gpio_defaults_block_0403.mag
index 5e064c7..e15b2ba 100644
--- a/mag/gpio_defaults_block_1800.mag
+++ b/mag/gpio_defaults_block_0403.mag
@@ -3,9 +3,9 @@
 magscale 1 2
 timestamp 1638587925
 << viali >>
-rect 1087 833 1121 867
+rect 949 833 983 867
 rect 1639 833 1673 867
-rect 4583 833 4617 867
+rect 4721 833 4755 867
 rect 1225 765 1259 799
 rect 1915 765 1949 799
 rect 2191 765 2225 799
@@ -15,7 +15,7 @@
 rect 3893 765 3927 799
 rect 4353 765 4387 799
 rect 4813 765 4847 799
-rect 5273 765 5307 799
+rect 5411 765 5445 799
 << metal1 >>
 rect 0 2202 5980 2224
 rect 0 2150 78 2202
diff --git a/signoff/build/generate_fill.out b/signoff/build/generate_fill.out
index 4576645..80d3cbc 100644
--- a/signoff/build/generate_fill.out
+++ b/signoff/build/generate_fill.out
@@ -15,7 +15,7 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill.tcl" from command line.
-Started: 12/10/2021 00:25:00
+Started: 12/27/2021 07:49:21
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 3.0
 Library name: caravan
@@ -98,35 +98,35 @@
 Reading "sky130_fd_sc_hd__o2bb2ai_2".
 Reading "sky130_fd_sc_hd__dfrtp_2".
 Reading "sky130_fd_sc_hd__mux2_1".
-Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
-Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
 Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
 Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
 Reading "sky130_fd_sc_hd__clkinv_2".
 Reading "sky130_fd_sc_hd__clkinv_4".
-Reading "sky130_fd_sc_hd__buf_12".
-Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__clkbuf_2".
-Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__and2_1".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__diode_2".
 Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
 Reading "sky130_fd_sc_hd__mux2_2".
 Reading "sky130_fd_sc_hd__decap_8".
-Reading "sky130_fd_sc_hd__nand2_2".
-Reading "sky130_fd_sc_hd__inv_2".
-Reading "sky130_fd_sc_hd__decap_6".
-Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
 Reading "sky130_fd_sc_hd__decap_3".
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__inv_2".
 Reading "caravel_clocking".
 Reading "sky130_fd_sc_hd__o2111ai_2".
 Reading "sky130_fd_sc_hd__and4_2".
@@ -148,6 +148,7 @@
 Reading "sky130_fd_sc_hd__or3_2".
 Reading "sky130_fd_sc_hd__or2_2".
 Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_1".
 Reading "sky130_fd_sc_hd__einvn_8".
 Reading "sky130_fd_sc_hd__einvn_4".
@@ -161,11 +162,16 @@
 Reading "sky130_fd_sc_hd__a311o_2".
 Reading "sky130_fd_sc_hd__a21oi_2".
 Reading "sky130_fd_sc_hd__a22oi_2".
-Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_8".
 Reading "sky130_fd_sc_hd__nor2_2".
 Reading "digital_pll".
 Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
 Reading "sky130_fd_sc_hd__a221o_1".
 Reading "sky130_fd_sc_hd__or4bb_1".
 Reading "sky130_fd_sc_hd__or4b_1".
@@ -203,7 +209,6 @@
 Reading "sky130_fd_sc_hd__a32o_1".
 Reading "sky130_fd_sc_hd__ebufn_2".
 Reading "sky130_fd_sc_hd__or3b_2".
-Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__a22oi_1".
 Reading "sky130_fd_sc_hd__mux2_4".
 Reading "sky130_fd_sc_hd__a41o_1".
@@ -242,15 +247,14 @@
 Reading "sky130_fd_sc_hd__o21ai_4".
 Reading "sky130_fd_sc_hd__nor2_8".
 Reading "sky130_fd_sc_hd__a31oi_1".
-Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__inv_12".
 Reading "sky130_fd_sc_hd__and2b_1".
 Reading "sky130_fd_sc_hd__buf_8".
-Reading "sky130_fd_sc_hd__buf_6".
 Reading "sky130_fd_sc_hd__nand2_8".
 Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__inv_8".
 Reading "housekeeping".
     5000 uses
@@ -267,10 +271,6 @@
 Reading "R2_sky130_fd_sc_hd__decap_12".
 Reading "user_id_programming".
 Reading "gpio_defaults_block_1803".
-Reading "sky130_fd_sc_hd__dfbbn_1".
-Reading "sky130_fd_sc_hd__ebufn_1".
-Reading "gpio_logic_high".
-Reading "gpio_control_block".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
 Reading "DN_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
@@ -711,10 +711,10 @@
     140000 uses
     145000 uses
 Reading "mgmt_core_wrapper".
-Reading "gpio_defaults_block_1800".
-Reading "sky130_fd_sc_hd__einvp_4".
-Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__clkinv_16".
 Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__inv_16".
 Reading "sky130_fd_sc_hvl__conb_1".
 Reading "mgmt_protect_hv".
 Reading "mprj_logic_high".
@@ -723,7 +723,6 @@
     5000 uses
     10000 uses
     15000 uses
-    20000 uses
 Reading "sky130_fd_sc_hd__dfbbp_1".
 Reading "spare_logic_block".
 Reading "gpio_defaults_block_0403".
@@ -1610,42 +1609,42 @@
 Error message output from magic:
 CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
 CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223975090): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223975122): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977714): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977746): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977778): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977810): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977842): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977938): NODE elements not supported: skipping.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223371174): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223371206): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373798): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373830): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373862): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373894): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373926): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223374022): NODE elements not supported: skipping.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -3180,343 +3179,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_1_1: 10000 rects
-caravel_00020021_fill_pattern_1_1: 20000 rects
-caravel_00020021_fill_pattern_1_1: 30000 rects
-caravel_00020021_fill_pattern_1_1: 40000 rects
-caravel_00020021_fill_pattern_1_1: 50000 rects
-caravel_00020021_fill_pattern_1_1: 60000 rects
-caravel_00020021_fill_pattern_1_1: 70000 rects
-caravel_00020021_fill_pattern_1_1: 80000 rects
-caravel_00020021_fill_pattern_1_1: 90000 rects
-caravel_00020021_fill_pattern_1_1: 100000 rects
-caravel_00020021_fill_pattern_1_1: 110000 rects
-caravel_00020021_fill_pattern_1_1: 120000 rects
-caravel_00020021_fill_pattern_1_1: 130000 rects
-caravel_00020021_fill_pattern_1_1: 140000 rects
-caravel_00020021_fill_pattern_1_1: 150000 rects
-caravel_00020021_fill_pattern_1_1: 160000 rects
-caravel_00020021_fill_pattern_1_1: 170000 rects
-caravel_00020021_fill_pattern_1_1: 180000 rects
-caravel_00020021_fill_pattern_1_1: 190000 rects
-caravel_00020021_fill_pattern_1_1: 200000 rects
-caravel_00020021_fill_pattern_1_1: 210000 rects
-caravel_00020021_fill_pattern_1_1: 220000 rects
-caravel_00020021_fill_pattern_1_1: 230000 rects
-caravel_00020021_fill_pattern_1_1: 240000 rects
-caravel_00020021_fill_pattern_1_1: 250000 rects
-caravel_00020021_fill_pattern_1_1: 260000 rects
-caravel_00020021_fill_pattern_1_1: 270000 rects
-caravel_00020021_fill_pattern_1_1: 280000 rects
-caravel_00020021_fill_pattern_1_1: 290000 rects
-caravel_00020021_fill_pattern_1_1: 300000 rects
-caravel_00020021_fill_pattern_1_1: 310000 rects
-caravel_00020021_fill_pattern_1_1: 320000 rects
-caravel_00020021_fill_pattern_1_1: 330000 rects
-caravel_00020021_fill_pattern_1_1: 340000 rects
-caravel_00020021_fill_pattern_1_1: 350000 rects
-caravel_00020021_fill_pattern_1_1: 360000 rects
-caravel_00020021_fill_pattern_1_1: 370000 rects
-caravel_00020021_fill_pattern_1_1: 380000 rects
-caravel_00020021_fill_pattern_1_1: 390000 rects
-caravel_00020021_fill_pattern_1_1: 400000 rects
-caravel_00020021_fill_pattern_1_1: 410000 rects
-caravel_00020021_fill_pattern_1_1: 420000 rects
-caravel_00020021_fill_pattern_1_1: 430000 rects
-caravel_00020021_fill_pattern_1_1: 440000 rects
-caravel_00020021_fill_pattern_1_1: 450000 rects
-caravel_00020021_fill_pattern_1_1: 460000 rects
-caravel_00020021_fill_pattern_1_1: 470000 rects
-caravel_00020021_fill_pattern_1_1: 480000 rects
-caravel_00020021_fill_pattern_1_1: 490000 rects
-caravel_00020021_fill_pattern_1_1: 500000 rects
-caravel_00020021_fill_pattern_1_1: 510000 rects
-caravel_00020021_fill_pattern_1_1: 520000 rects
-caravel_00020021_fill_pattern_1_1: 530000 rects
-caravel_00020021_fill_pattern_1_1: 540000 rects
-caravel_00020021_fill_pattern_1_1: 550000 rects
-caravel_00020021_fill_pattern_1_1: 560000 rects
-caravel_00020021_fill_pattern_1_1: 570000 rects
-caravel_00020021_fill_pattern_1_1: 580000 rects
-caravel_00020021_fill_pattern_1_1: 590000 rects
-caravel_00020021_fill_pattern_1_1: 600000 rects
-caravel_00020021_fill_pattern_1_1: 610000 rects
-caravel_00020021_fill_pattern_1_1: 620000 rects
-caravel_00020021_fill_pattern_1_1: 630000 rects
-caravel_00020021_fill_pattern_1_1: 640000 rects
-caravel_00020021_fill_pattern_1_1: 650000 rects
-caravel_00020021_fill_pattern_1_1: 660000 rects
-caravel_00020021_fill_pattern_1_1: 670000 rects
-caravel_00020021_fill_pattern_1_1: 680000 rects
-caravel_00020021_fill_pattern_1_1: 690000 rects
-caravel_00020021_fill_pattern_1_1: 700000 rects
-caravel_00020021_fill_pattern_1_1: 710000 rects
-caravel_00020021_fill_pattern_1_1: 720000 rects
-caravel_00020021_fill_pattern_1_1: 730000 rects
-caravel_00020021_fill_pattern_1_1: 740000 rects
-caravel_00020021_fill_pattern_1_1: 750000 rects
-caravel_00020021_fill_pattern_1_1: 760000 rects
-caravel_00020021_fill_pattern_1_1: 770000 rects
-caravel_00020021_fill_pattern_1_1: 780000 rects
-caravel_00020021_fill_pattern_1_1: 790000 rects
-caravel_00020021_fill_pattern_1_1: 800000 rects
-caravel_00020021_fill_pattern_1_1: 810000 rects
-caravel_00020021_fill_pattern_1_1: 820000 rects
-caravel_00020021_fill_pattern_1_1: 830000 rects
-caravel_00020021_fill_pattern_1_1: 840000 rects
-caravel_00020021_fill_pattern_1_1: 850000 rects
-caravel_00020021_fill_pattern_1_1: 860000 rects
-caravel_00020021_fill_pattern_1_1: 870000 rects
-caravel_00020021_fill_pattern_1_1: 880000 rects
-caravel_00020021_fill_pattern_1_1: 890000 rects
-caravel_00020021_fill_pattern_1_1: 900000 rects
-caravel_00020021_fill_pattern_1_1: 910000 rects
-caravel_00020021_fill_pattern_1_1: 920000 rects
-caravel_00020021_fill_pattern_1_1: 930000 rects
-caravel_00020021_fill_pattern_1_1: 940000 rects
-caravel_00020021_fill_pattern_1_1: 950000 rects
-caravel_00020021_fill_pattern_1_1: 960000 rects
-caravel_00020021_fill_pattern_1_1: 970000 rects
-caravel_00020021_fill_pattern_1_1: 980000 rects
-caravel_00020021_fill_pattern_1_1: 990000 rects
-caravel_00020021_fill_pattern_1_1: 1000000 rects
-caravel_00020021_fill_pattern_1_1: 1010000 rects
-caravel_00020021_fill_pattern_1_1: 1020000 rects
-caravel_00020021_fill_pattern_1_1: 1030000 rects
-caravel_00020021_fill_pattern_1_1: 1040000 rects
-caravel_00020021_fill_pattern_1_1: 1050000 rects
-caravel_00020021_fill_pattern_1_1: 1060000 rects
-caravel_00020021_fill_pattern_1_1: 1070000 rects
-caravel_00020021_fill_pattern_1_1: 1080000 rects
-caravel_00020021_fill_pattern_1_1: 1090000 rects
-caravel_00020021_fill_pattern_1_1: 1100000 rects
-caravel_00020021_fill_pattern_1_1: 1110000 rects
-caravel_00020021_fill_pattern_1_1: 1120000 rects
-caravel_00020021_fill_pattern_1_1: 1130000 rects
-caravel_00020021_fill_pattern_1_1: 1140000 rects
-caravel_00020021_fill_pattern_1_1: 1150000 rects
-caravel_00020021_fill_pattern_1_1: 1160000 rects
-caravel_00020021_fill_pattern_1_1: 1170000 rects
-caravel_00020021_fill_pattern_1_1: 1180000 rects
-caravel_00020021_fill_pattern_1_1: 1190000 rects
-caravel_00020021_fill_pattern_1_1: 1200000 rects
-caravel_00020021_fill_pattern_1_1: 1210000 rects
-caravel_00020021_fill_pattern_1_1: 1220000 rects
-caravel_00020021_fill_pattern_1_1: 1230000 rects
-caravel_00020021_fill_pattern_1_1: 1240000 rects
-caravel_00020021_fill_pattern_1_1: 1250000 rects
-caravel_00020021_fill_pattern_1_1: 1260000 rects
-caravel_00020021_fill_pattern_1_1: 1270000 rects
-caravel_00020021_fill_pattern_1_1: 1280000 rects
-caravel_00020021_fill_pattern_1_1: 1290000 rects
-caravel_00020021_fill_pattern_1_1: 1300000 rects
-caravel_00020021_fill_pattern_1_1: 1310000 rects
-caravel_00020021_fill_pattern_1_1: 1320000 rects
-caravel_00020021_fill_pattern_1_1: 1330000 rects
-caravel_00020021_fill_pattern_1_1: 1340000 rects
-caravel_00020021_fill_pattern_1_1: 1350000 rects
-caravel_00020021_fill_pattern_1_1: 1360000 rects
-caravel_00020021_fill_pattern_1_1: 1370000 rects
-caravel_00020021_fill_pattern_1_1: 1380000 rects
-caravel_00020021_fill_pattern_1_1: 1390000 rects
-caravel_00020021_fill_pattern_1_1: 1400000 rects
-caravel_00020021_fill_pattern_1_1: 1410000 rects
-caravel_00020021_fill_pattern_1_1: 1420000 rects
-caravel_00020021_fill_pattern_1_1: 1430000 rects
-caravel_00020021_fill_pattern_1_1: 1440000 rects
-caravel_00020021_fill_pattern_1_1: 1450000 rects
-caravel_00020021_fill_pattern_1_1: 1460000 rects
-caravel_00020021_fill_pattern_1_1: 1470000 rects
-caravel_00020021_fill_pattern_1_1: 1480000 rects
-caravel_00020021_fill_pattern_1_1: 1490000 rects
-caravel_00020021_fill_pattern_1_1: 1500000 rects
-caravel_00020021_fill_pattern_1_1: 1510000 rects
-caravel_00020021_fill_pattern_1_1: 1520000 rects
-caravel_00020021_fill_pattern_1_1: 1530000 rects
-caravel_00020021_fill_pattern_1_1: 1540000 rects
-caravel_00020021_fill_pattern_1_1: 1550000 rects
-caravel_00020021_fill_pattern_1_1: 1560000 rects
-caravel_00020021_fill_pattern_1_1: 1570000 rects
-caravel_00020021_fill_pattern_1_1: 1580000 rects
-caravel_00020021_fill_pattern_1_1: 1590000 rects
-caravel_00020021_fill_pattern_1_1: 1600000 rects
-caravel_00020021_fill_pattern_1_1: 1610000 rects
-caravel_00020021_fill_pattern_1_1: 1620000 rects
-caravel_00020021_fill_pattern_1_1: 1630000 rects
-caravel_00020021_fill_pattern_1_1: 1640000 rects
-caravel_00020021_fill_pattern_1_1: 1650000 rects
-caravel_00020021_fill_pattern_1_1: 1660000 rects
-caravel_00020021_fill_pattern_1_1: 1670000 rects
-caravel_00020021_fill_pattern_1_1: 1680000 rects
-caravel_00020021_fill_pattern_1_1: 1690000 rects
-caravel_00020021_fill_pattern_1_1: 1700000 rects
-caravel_00020021_fill_pattern_1_1: 1710000 rects
-caravel_00020021_fill_pattern_1_1: 1720000 rects
-caravel_00020021_fill_pattern_1_1: 1730000 rects
-caravel_00020021_fill_pattern_1_1: 1740000 rects
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-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
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 caravel_00020021_fill_pattern_0_0: 30000 rects
@@ -4022,6 +3684,343 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
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+caravel_00020021_fill_pattern_1_1: 3220000 rects
+caravel_00020021_fill_pattern_1_1: 3230000 rects
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_3_1: 10000 rects
 caravel_00020021_fill_pattern_3_1: 20000 rects
 caravel_00020021_fill_pattern_3_1: 30000 rects
@@ -6478,7 +6477,7 @@
    Generating output for cell caravel_00020021_fill_pattern_5_7
 Reading "caravel_00020021_fill_pattern_5_7".
    Generating output for cell caravel_00020021_fill_pattern
-Ended: 12/10/2021 00:42:18
+Ended: 12/27/2021 08:16:37
 Done!
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
@@ -6778,226 +6777,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_5_1: 10000 rects
-caravel_00020021_fill_pattern_5_1: 20000 rects
-caravel_00020021_fill_pattern_5_1: 30000 rects
-caravel_00020021_fill_pattern_5_1: 40000 rects
-caravel_00020021_fill_pattern_5_1: 50000 rects
-caravel_00020021_fill_pattern_5_1: 60000 rects
-caravel_00020021_fill_pattern_5_1: 70000 rects
-caravel_00020021_fill_pattern_5_1: 80000 rects
-caravel_00020021_fill_pattern_5_1: 90000 rects
-caravel_00020021_fill_pattern_5_1: 100000 rects
-caravel_00020021_fill_pattern_5_1: 110000 rects
-caravel_00020021_fill_pattern_5_1: 120000 rects
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-caravel_00020021_fill_pattern_5_1: 140000 rects
-caravel_00020021_fill_pattern_5_1: 150000 rects
-caravel_00020021_fill_pattern_5_1: 160000 rects
-caravel_00020021_fill_pattern_5_1: 170000 rects
-caravel_00020021_fill_pattern_5_1: 180000 rects
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-caravel_00020021_fill_pattern_5_1: 890000 rects
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-caravel_00020021_fill_pattern_5_1: 910000 rects
-caravel_00020021_fill_pattern_5_1: 920000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_5_1
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_5_2: 10000 rects
-caravel_00020021_fill_pattern_5_2: 20000 rects
-caravel_00020021_fill_pattern_5_2: 30000 rects
-caravel_00020021_fill_pattern_5_2: 40000 rects
-caravel_00020021_fill_pattern_5_2: 50000 rects
-caravel_00020021_fill_pattern_5_2: 60000 rects
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-caravel_00020021_fill_pattern_5_2: 80000 rects
-caravel_00020021_fill_pattern_5_2: 90000 rects
-caravel_00020021_fill_pattern_5_2: 100000 rects
-caravel_00020021_fill_pattern_5_2: 110000 rects
-caravel_00020021_fill_pattern_5_2: 120000 rects
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-caravel_00020021_fill_pattern_5_2: 140000 rects
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-caravel_00020021_fill_pattern_5_2: 720000 rects
-caravel_00020021_fill_pattern_5_2: 730000 rects
-caravel_00020021_fill_pattern_5_2: 740000 rects
-caravel_00020021_fill_pattern_5_2: 750000 rects
-caravel_00020021_fill_pattern_5_2: 760000 rects
-caravel_00020021_fill_pattern_5_2: 770000 rects
-caravel_00020021_fill_pattern_5_2: 780000 rects
-caravel_00020021_fill_pattern_5_2: 790000 rects
-caravel_00020021_fill_pattern_5_2: 800000 rects
-caravel_00020021_fill_pattern_5_2: 810000 rects
-caravel_00020021_fill_pattern_5_2: 820000 rects
-caravel_00020021_fill_pattern_5_2: 830000 rects
-caravel_00020021_fill_pattern_5_2: 840000 rects
-caravel_00020021_fill_pattern_5_2: 850000 rects
-caravel_00020021_fill_pattern_5_2: 860000 rects
-caravel_00020021_fill_pattern_5_2: 870000 rects
-caravel_00020021_fill_pattern_5_2: 880000 rects
-caravel_00020021_fill_pattern_5_2: 890000 rects
-caravel_00020021_fill_pattern_5_2: 900000 rects
-caravel_00020021_fill_pattern_5_2: 910000 rects
-caravel_00020021_fill_pattern_5_2: 920000 rects
-caravel_00020021_fill_pattern_5_2: 930000 rects
-caravel_00020021_fill_pattern_5_2: 940000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_5_2
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_5_4: 10000 rects
 caravel_00020021_fill_pattern_5_4: 20000 rects
 caravel_00020021_fill_pattern_5_4: 30000 rects
@@ -7114,6 +6893,227 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_5_2: 10000 rects
+caravel_00020021_fill_pattern_5_2: 20000 rects
+caravel_00020021_fill_pattern_5_2: 30000 rects
+caravel_00020021_fill_pattern_5_2: 40000 rects
+caravel_00020021_fill_pattern_5_2: 50000 rects
+caravel_00020021_fill_pattern_5_2: 60000 rects
+caravel_00020021_fill_pattern_5_2: 70000 rects
+caravel_00020021_fill_pattern_5_2: 80000 rects
+caravel_00020021_fill_pattern_5_2: 90000 rects
+caravel_00020021_fill_pattern_5_2: 100000 rects
+caravel_00020021_fill_pattern_5_2: 110000 rects
+caravel_00020021_fill_pattern_5_2: 120000 rects
+caravel_00020021_fill_pattern_5_2: 130000 rects
+caravel_00020021_fill_pattern_5_2: 140000 rects
+caravel_00020021_fill_pattern_5_2: 150000 rects
+caravel_00020021_fill_pattern_5_2: 160000 rects
+caravel_00020021_fill_pattern_5_2: 170000 rects
+caravel_00020021_fill_pattern_5_2: 180000 rects
+caravel_00020021_fill_pattern_5_2: 190000 rects
+caravel_00020021_fill_pattern_5_2: 200000 rects
+caravel_00020021_fill_pattern_5_2: 210000 rects
+caravel_00020021_fill_pattern_5_2: 220000 rects
+caravel_00020021_fill_pattern_5_2: 230000 rects
+caravel_00020021_fill_pattern_5_2: 240000 rects
+caravel_00020021_fill_pattern_5_2: 250000 rects
+caravel_00020021_fill_pattern_5_2: 260000 rects
+caravel_00020021_fill_pattern_5_2: 270000 rects
+caravel_00020021_fill_pattern_5_2: 280000 rects
+caravel_00020021_fill_pattern_5_2: 290000 rects
+caravel_00020021_fill_pattern_5_2: 300000 rects
+caravel_00020021_fill_pattern_5_2: 310000 rects
+caravel_00020021_fill_pattern_5_2: 320000 rects
+caravel_00020021_fill_pattern_5_2: 330000 rects
+caravel_00020021_fill_pattern_5_2: 340000 rects
+caravel_00020021_fill_pattern_5_2: 350000 rects
+caravel_00020021_fill_pattern_5_2: 360000 rects
+caravel_00020021_fill_pattern_5_2: 370000 rects
+caravel_00020021_fill_pattern_5_2: 380000 rects
+caravel_00020021_fill_pattern_5_2: 390000 rects
+caravel_00020021_fill_pattern_5_2: 400000 rects
+caravel_00020021_fill_pattern_5_2: 410000 rects
+caravel_00020021_fill_pattern_5_2: 420000 rects
+caravel_00020021_fill_pattern_5_2: 430000 rects
+caravel_00020021_fill_pattern_5_2: 440000 rects
+caravel_00020021_fill_pattern_5_2: 450000 rects
+caravel_00020021_fill_pattern_5_2: 460000 rects
+caravel_00020021_fill_pattern_5_2: 470000 rects
+caravel_00020021_fill_pattern_5_2: 480000 rects
+caravel_00020021_fill_pattern_5_2: 490000 rects
+caravel_00020021_fill_pattern_5_2: 500000 rects
+caravel_00020021_fill_pattern_5_2: 510000 rects
+caravel_00020021_fill_pattern_5_2: 520000 rects
+caravel_00020021_fill_pattern_5_2: 530000 rects
+caravel_00020021_fill_pattern_5_2: 540000 rects
+caravel_00020021_fill_pattern_5_2: 550000 rects
+caravel_00020021_fill_pattern_5_2: 560000 rects
+caravel_00020021_fill_pattern_5_2: 570000 rects
+caravel_00020021_fill_pattern_5_2: 580000 rects
+caravel_00020021_fill_pattern_5_2: 590000 rects
+caravel_00020021_fill_pattern_5_2: 600000 rects
+caravel_00020021_fill_pattern_5_2: 610000 rects
+caravel_00020021_fill_pattern_5_2: 620000 rects
+caravel_00020021_fill_pattern_5_2: 630000 rects
+caravel_00020021_fill_pattern_5_2: 640000 rects
+caravel_00020021_fill_pattern_5_2: 650000 rects
+caravel_00020021_fill_pattern_5_2: 660000 rects
+caravel_00020021_fill_pattern_5_2: 670000 rects
+caravel_00020021_fill_pattern_5_2: 680000 rects
+caravel_00020021_fill_pattern_5_2: 690000 rects
+caravel_00020021_fill_pattern_5_2: 700000 rects
+caravel_00020021_fill_pattern_5_2: 710000 rects
+caravel_00020021_fill_pattern_5_2: 720000 rects
+caravel_00020021_fill_pattern_5_2: 730000 rects
+caravel_00020021_fill_pattern_5_2: 740000 rects
+caravel_00020021_fill_pattern_5_2: 750000 rects
+caravel_00020021_fill_pattern_5_2: 760000 rects
+caravel_00020021_fill_pattern_5_2: 770000 rects
+caravel_00020021_fill_pattern_5_2: 780000 rects
+caravel_00020021_fill_pattern_5_2: 790000 rects
+caravel_00020021_fill_pattern_5_2: 800000 rects
+caravel_00020021_fill_pattern_5_2: 810000 rects
+caravel_00020021_fill_pattern_5_2: 820000 rects
+caravel_00020021_fill_pattern_5_2: 830000 rects
+caravel_00020021_fill_pattern_5_2: 840000 rects
+caravel_00020021_fill_pattern_5_2: 850000 rects
+caravel_00020021_fill_pattern_5_2: 860000 rects
+caravel_00020021_fill_pattern_5_2: 870000 rects
+caravel_00020021_fill_pattern_5_2: 880000 rects
+caravel_00020021_fill_pattern_5_2: 890000 rects
+caravel_00020021_fill_pattern_5_2: 900000 rects
+caravel_00020021_fill_pattern_5_2: 910000 rects
+caravel_00020021_fill_pattern_5_2: 920000 rects
+caravel_00020021_fill_pattern_5_2: 930000 rects
+caravel_00020021_fill_pattern_5_2: 940000 rects
+caravel_00020021_fill_pattern_5_2: 950000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_5_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_5_1: 10000 rects
+caravel_00020021_fill_pattern_5_1: 20000 rects
+caravel_00020021_fill_pattern_5_1: 30000 rects
+caravel_00020021_fill_pattern_5_1: 40000 rects
+caravel_00020021_fill_pattern_5_1: 50000 rects
+caravel_00020021_fill_pattern_5_1: 60000 rects
+caravel_00020021_fill_pattern_5_1: 70000 rects
+caravel_00020021_fill_pattern_5_1: 80000 rects
+caravel_00020021_fill_pattern_5_1: 90000 rects
+caravel_00020021_fill_pattern_5_1: 100000 rects
+caravel_00020021_fill_pattern_5_1: 110000 rects
+caravel_00020021_fill_pattern_5_1: 120000 rects
+caravel_00020021_fill_pattern_5_1: 130000 rects
+caravel_00020021_fill_pattern_5_1: 140000 rects
+caravel_00020021_fill_pattern_5_1: 150000 rects
+caravel_00020021_fill_pattern_5_1: 160000 rects
+caravel_00020021_fill_pattern_5_1: 170000 rects
+caravel_00020021_fill_pattern_5_1: 180000 rects
+caravel_00020021_fill_pattern_5_1: 190000 rects
+caravel_00020021_fill_pattern_5_1: 200000 rects
+caravel_00020021_fill_pattern_5_1: 210000 rects
+caravel_00020021_fill_pattern_5_1: 220000 rects
+caravel_00020021_fill_pattern_5_1: 230000 rects
+caravel_00020021_fill_pattern_5_1: 240000 rects
+caravel_00020021_fill_pattern_5_1: 250000 rects
+caravel_00020021_fill_pattern_5_1: 260000 rects
+caravel_00020021_fill_pattern_5_1: 270000 rects
+caravel_00020021_fill_pattern_5_1: 280000 rects
+caravel_00020021_fill_pattern_5_1: 290000 rects
+caravel_00020021_fill_pattern_5_1: 300000 rects
+caravel_00020021_fill_pattern_5_1: 310000 rects
+caravel_00020021_fill_pattern_5_1: 320000 rects
+caravel_00020021_fill_pattern_5_1: 330000 rects
+caravel_00020021_fill_pattern_5_1: 340000 rects
+caravel_00020021_fill_pattern_5_1: 350000 rects
+caravel_00020021_fill_pattern_5_1: 360000 rects
+caravel_00020021_fill_pattern_5_1: 370000 rects
+caravel_00020021_fill_pattern_5_1: 380000 rects
+caravel_00020021_fill_pattern_5_1: 390000 rects
+caravel_00020021_fill_pattern_5_1: 400000 rects
+caravel_00020021_fill_pattern_5_1: 410000 rects
+caravel_00020021_fill_pattern_5_1: 420000 rects
+caravel_00020021_fill_pattern_5_1: 430000 rects
+caravel_00020021_fill_pattern_5_1: 440000 rects
+caravel_00020021_fill_pattern_5_1: 450000 rects
+caravel_00020021_fill_pattern_5_1: 460000 rects
+caravel_00020021_fill_pattern_5_1: 470000 rects
+caravel_00020021_fill_pattern_5_1: 480000 rects
+caravel_00020021_fill_pattern_5_1: 490000 rects
+caravel_00020021_fill_pattern_5_1: 500000 rects
+caravel_00020021_fill_pattern_5_1: 510000 rects
+caravel_00020021_fill_pattern_5_1: 520000 rects
+caravel_00020021_fill_pattern_5_1: 530000 rects
+caravel_00020021_fill_pattern_5_1: 540000 rects
+caravel_00020021_fill_pattern_5_1: 550000 rects
+caravel_00020021_fill_pattern_5_1: 560000 rects
+caravel_00020021_fill_pattern_5_1: 570000 rects
+caravel_00020021_fill_pattern_5_1: 580000 rects
+caravel_00020021_fill_pattern_5_1: 590000 rects
+caravel_00020021_fill_pattern_5_1: 600000 rects
+caravel_00020021_fill_pattern_5_1: 610000 rects
+caravel_00020021_fill_pattern_5_1: 620000 rects
+caravel_00020021_fill_pattern_5_1: 630000 rects
+caravel_00020021_fill_pattern_5_1: 640000 rects
+caravel_00020021_fill_pattern_5_1: 650000 rects
+caravel_00020021_fill_pattern_5_1: 660000 rects
+caravel_00020021_fill_pattern_5_1: 670000 rects
+caravel_00020021_fill_pattern_5_1: 680000 rects
+caravel_00020021_fill_pattern_5_1: 690000 rects
+caravel_00020021_fill_pattern_5_1: 700000 rects
+caravel_00020021_fill_pattern_5_1: 710000 rects
+caravel_00020021_fill_pattern_5_1: 720000 rects
+caravel_00020021_fill_pattern_5_1: 730000 rects
+caravel_00020021_fill_pattern_5_1: 740000 rects
+caravel_00020021_fill_pattern_5_1: 750000 rects
+caravel_00020021_fill_pattern_5_1: 760000 rects
+caravel_00020021_fill_pattern_5_1: 770000 rects
+caravel_00020021_fill_pattern_5_1: 780000 rects
+caravel_00020021_fill_pattern_5_1: 790000 rects
+caravel_00020021_fill_pattern_5_1: 800000 rects
+caravel_00020021_fill_pattern_5_1: 810000 rects
+caravel_00020021_fill_pattern_5_1: 820000 rects
+caravel_00020021_fill_pattern_5_1: 830000 rects
+caravel_00020021_fill_pattern_5_1: 840000 rects
+caravel_00020021_fill_pattern_5_1: 850000 rects
+caravel_00020021_fill_pattern_5_1: 860000 rects
+caravel_00020021_fill_pattern_5_1: 870000 rects
+caravel_00020021_fill_pattern_5_1: 880000 rects
+caravel_00020021_fill_pattern_5_1: 890000 rects
+caravel_00020021_fill_pattern_5_1: 900000 rects
+caravel_00020021_fill_pattern_5_1: 910000 rects
+caravel_00020021_fill_pattern_5_1: 920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_5_1
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_3_7: 10000 rects
 caravel_00020021_fill_pattern_3_7: 20000 rects
 caravel_00020021_fill_pattern_3_7: 30000 rects
@@ -7186,36 +7186,13 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_7: 10000 rects
-caravel_00020021_fill_pattern_4_7: 20000 rects
-caravel_00020021_fill_pattern_4_7: 30000 rects
-caravel_00020021_fill_pattern_4_7: 40000 rects
-caravel_00020021_fill_pattern_4_7: 50000 rects
-caravel_00020021_fill_pattern_4_7: 60000 rects
-caravel_00020021_fill_pattern_4_7: 70000 rects
-caravel_00020021_fill_pattern_4_7: 80000 rects
-caravel_00020021_fill_pattern_4_7: 90000 rects
-caravel_00020021_fill_pattern_4_7: 100000 rects
-caravel_00020021_fill_pattern_4_7: 110000 rects
-caravel_00020021_fill_pattern_4_7: 120000 rects
-caravel_00020021_fill_pattern_4_7: 130000 rects
-caravel_00020021_fill_pattern_4_7: 140000 rects
-caravel_00020021_fill_pattern_4_7: 150000 rects
-caravel_00020021_fill_pattern_4_7: 160000 rects
-caravel_00020021_fill_pattern_4_7: 170000 rects
-caravel_00020021_fill_pattern_4_7: 180000 rects
-caravel_00020021_fill_pattern_4_7: 190000 rects
-caravel_00020021_fill_pattern_4_7: 200000 rects
-caravel_00020021_fill_pattern_4_7: 210000 rects
-caravel_00020021_fill_pattern_4_7: 220000 rects
-caravel_00020021_fill_pattern_4_7: 230000 rects
-caravel_00020021_fill_pattern_4_7: 240000 rects
-caravel_00020021_fill_pattern_4_7: 250000 rects
-caravel_00020021_fill_pattern_4_7: 260000 rects
-caravel_00020021_fill_pattern_4_7: 270000 rects
-caravel_00020021_fill_pattern_4_7: 280000 rects
+caravel_00020021_fill_pattern_0_7: 10000 rects
+caravel_00020021_fill_pattern_0_7: 20000 rects
+caravel_00020021_fill_pattern_0_7: 30000 rects
+caravel_00020021_fill_pattern_0_7: 40000 rects
+caravel_00020021_fill_pattern_0_7: 50000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_7
+   Generating output for cell caravel_00020021_fill_pattern_0_7
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7334,46 +7311,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_0_7: 10000 rects
-caravel_00020021_fill_pattern_0_7: 20000 rects
-caravel_00020021_fill_pattern_0_7: 30000 rects
-caravel_00020021_fill_pattern_0_7: 40000 rects
-caravel_00020021_fill_pattern_0_7: 50000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_7
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-Scaled magic input cell caravel_00020021_fill_pattern_2_3 geometry by factor of 2
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_2_3
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_2_2
 
@@ -7391,71 +7328,36 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_0_6: 10000 rects
-caravel_00020021_fill_pattern_0_6: 20000 rects
-caravel_00020021_fill_pattern_0_6: 30000 rects
-caravel_00020021_fill_pattern_0_6: 40000 rects
-caravel_00020021_fill_pattern_0_6: 50000 rects
-caravel_00020021_fill_pattern_0_6: 60000 rects
-caravel_00020021_fill_pattern_0_6: 70000 rects
-caravel_00020021_fill_pattern_0_6: 80000 rects
-caravel_00020021_fill_pattern_0_6: 90000 rects
-caravel_00020021_fill_pattern_0_6: 100000 rects
-caravel_00020021_fill_pattern_0_6: 110000 rects
-caravel_00020021_fill_pattern_0_6: 120000 rects
-caravel_00020021_fill_pattern_0_6: 130000 rects
-caravel_00020021_fill_pattern_0_6: 140000 rects
-caravel_00020021_fill_pattern_0_6: 150000 rects
-caravel_00020021_fill_pattern_0_6: 160000 rects
-caravel_00020021_fill_pattern_0_6: 170000 rects
-caravel_00020021_fill_pattern_0_6: 180000 rects
-caravel_00020021_fill_pattern_0_6: 190000 rects
-caravel_00020021_fill_pattern_0_6: 200000 rects
-caravel_00020021_fill_pattern_0_6: 210000 rects
-caravel_00020021_fill_pattern_0_6: 220000 rects
-caravel_00020021_fill_pattern_0_6: 230000 rects
-caravel_00020021_fill_pattern_0_6: 240000 rects
-caravel_00020021_fill_pattern_0_6: 250000 rects
-caravel_00020021_fill_pattern_0_6: 260000 rects
-caravel_00020021_fill_pattern_0_6: 270000 rects
-caravel_00020021_fill_pattern_0_6: 280000 rects
-caravel_00020021_fill_pattern_0_6: 290000 rects
-caravel_00020021_fill_pattern_0_6: 300000 rects
-caravel_00020021_fill_pattern_0_6: 310000 rects
-caravel_00020021_fill_pattern_0_6: 320000 rects
-caravel_00020021_fill_pattern_0_6: 330000 rects
-caravel_00020021_fill_pattern_0_6: 340000 rects
-caravel_00020021_fill_pattern_0_6: 350000 rects
-caravel_00020021_fill_pattern_0_6: 360000 rects
-caravel_00020021_fill_pattern_0_6: 370000 rects
-caravel_00020021_fill_pattern_0_6: 380000 rects
-caravel_00020021_fill_pattern_0_6: 390000 rects
-caravel_00020021_fill_pattern_0_6: 400000 rects
-caravel_00020021_fill_pattern_0_6: 410000 rects
-caravel_00020021_fill_pattern_0_6: 420000 rects
-caravel_00020021_fill_pattern_0_6: 430000 rects
-caravel_00020021_fill_pattern_0_6: 440000 rects
-caravel_00020021_fill_pattern_0_6: 450000 rects
-caravel_00020021_fill_pattern_0_6: 460000 rects
-caravel_00020021_fill_pattern_0_6: 470000 rects
-caravel_00020021_fill_pattern_0_6: 480000 rects
-caravel_00020021_fill_pattern_0_6: 490000 rects
-caravel_00020021_fill_pattern_0_6: 500000 rects
-caravel_00020021_fill_pattern_0_6: 510000 rects
-caravel_00020021_fill_pattern_0_6: 520000 rects
-caravel_00020021_fill_pattern_0_6: 530000 rects
-caravel_00020021_fill_pattern_0_6: 540000 rects
-caravel_00020021_fill_pattern_0_6: 550000 rects
-caravel_00020021_fill_pattern_0_6: 560000 rects
-caravel_00020021_fill_pattern_0_6: 570000 rects
-caravel_00020021_fill_pattern_0_6: 580000 rects
-caravel_00020021_fill_pattern_0_6: 590000 rects
-caravel_00020021_fill_pattern_0_6: 600000 rects
-caravel_00020021_fill_pattern_0_6: 610000 rects
-caravel_00020021_fill_pattern_0_6: 620000 rects
-caravel_00020021_fill_pattern_0_6: 630000 rects
+caravel_00020021_fill_pattern_4_7: 10000 rects
+caravel_00020021_fill_pattern_4_7: 20000 rects
+caravel_00020021_fill_pattern_4_7: 30000 rects
+caravel_00020021_fill_pattern_4_7: 40000 rects
+caravel_00020021_fill_pattern_4_7: 50000 rects
+caravel_00020021_fill_pattern_4_7: 60000 rects
+caravel_00020021_fill_pattern_4_7: 70000 rects
+caravel_00020021_fill_pattern_4_7: 80000 rects
+caravel_00020021_fill_pattern_4_7: 90000 rects
+caravel_00020021_fill_pattern_4_7: 100000 rects
+caravel_00020021_fill_pattern_4_7: 110000 rects
+caravel_00020021_fill_pattern_4_7: 120000 rects
+caravel_00020021_fill_pattern_4_7: 130000 rects
+caravel_00020021_fill_pattern_4_7: 140000 rects
+caravel_00020021_fill_pattern_4_7: 150000 rects
+caravel_00020021_fill_pattern_4_7: 160000 rects
+caravel_00020021_fill_pattern_4_7: 170000 rects
+caravel_00020021_fill_pattern_4_7: 180000 rects
+caravel_00020021_fill_pattern_4_7: 190000 rects
+caravel_00020021_fill_pattern_4_7: 200000 rects
+caravel_00020021_fill_pattern_4_7: 210000 rects
+caravel_00020021_fill_pattern_4_7: 220000 rects
+caravel_00020021_fill_pattern_4_7: 230000 rects
+caravel_00020021_fill_pattern_4_7: 240000 rects
+caravel_00020021_fill_pattern_4_7: 250000 rects
+caravel_00020021_fill_pattern_4_7: 260000 rects
+caravel_00020021_fill_pattern_4_7: 270000 rects
+caravel_00020021_fill_pattern_4_7: 280000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_6
+   Generating output for cell caravel_00020021_fill_pattern_4_7
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7494,84 +7396,27 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_4: 10000 rects
-caravel_00020021_fill_pattern_3_4: 20000 rects
-caravel_00020021_fill_pattern_3_4: 30000 rects
-caravel_00020021_fill_pattern_3_4: 40000 rects
-caravel_00020021_fill_pattern_3_4: 50000 rects
-caravel_00020021_fill_pattern_3_4: 60000 rects
-caravel_00020021_fill_pattern_3_4: 70000 rects
-caravel_00020021_fill_pattern_3_4: 80000 rects
-caravel_00020021_fill_pattern_3_4: 90000 rects
-caravel_00020021_fill_pattern_3_4: 100000 rects
-caravel_00020021_fill_pattern_3_4: 110000 rects
-caravel_00020021_fill_pattern_3_4: 120000 rects
-caravel_00020021_fill_pattern_3_4: 130000 rects
-caravel_00020021_fill_pattern_3_4: 140000 rects
-caravel_00020021_fill_pattern_3_4: 150000 rects
-caravel_00020021_fill_pattern_3_4: 160000 rects
-caravel_00020021_fill_pattern_3_4: 170000 rects
-caravel_00020021_fill_pattern_3_4: 180000 rects
-caravel_00020021_fill_pattern_3_4: 190000 rects
-caravel_00020021_fill_pattern_3_4: 200000 rects
-caravel_00020021_fill_pattern_3_4: 210000 rects
-caravel_00020021_fill_pattern_3_4: 220000 rects
-caravel_00020021_fill_pattern_3_4: 230000 rects
-caravel_00020021_fill_pattern_3_4: 240000 rects
-caravel_00020021_fill_pattern_3_4: 250000 rects
-caravel_00020021_fill_pattern_3_4: 260000 rects
-caravel_00020021_fill_pattern_3_4: 270000 rects
-caravel_00020021_fill_pattern_3_4: 280000 rects
-caravel_00020021_fill_pattern_3_4: 290000 rects
-caravel_00020021_fill_pattern_3_4: 300000 rects
-caravel_00020021_fill_pattern_3_4: 310000 rects
-caravel_00020021_fill_pattern_3_4: 320000 rects
-caravel_00020021_fill_pattern_3_4: 330000 rects
-caravel_00020021_fill_pattern_3_4: 340000 rects
-caravel_00020021_fill_pattern_3_4: 350000 rects
-caravel_00020021_fill_pattern_3_4: 360000 rects
-caravel_00020021_fill_pattern_3_4: 370000 rects
-caravel_00020021_fill_pattern_3_4: 380000 rects
-caravel_00020021_fill_pattern_3_4: 390000 rects
-caravel_00020021_fill_pattern_3_4: 400000 rects
-caravel_00020021_fill_pattern_3_4: 410000 rects
-caravel_00020021_fill_pattern_3_4: 420000 rects
-caravel_00020021_fill_pattern_3_4: 430000 rects
-caravel_00020021_fill_pattern_3_4: 440000 rects
-caravel_00020021_fill_pattern_3_4: 450000 rects
-caravel_00020021_fill_pattern_3_4: 460000 rects
-caravel_00020021_fill_pattern_3_4: 470000 rects
-caravel_00020021_fill_pattern_3_4: 480000 rects
-caravel_00020021_fill_pattern_3_4: 490000 rects
-caravel_00020021_fill_pattern_3_4: 500000 rects
-caravel_00020021_fill_pattern_3_4: 510000 rects
-caravel_00020021_fill_pattern_3_4: 520000 rects
-caravel_00020021_fill_pattern_3_4: 530000 rects
-caravel_00020021_fill_pattern_3_4: 540000 rects
-caravel_00020021_fill_pattern_3_4: 550000 rects
-caravel_00020021_fill_pattern_3_4: 560000 rects
-caravel_00020021_fill_pattern_3_4: 570000 rects
-caravel_00020021_fill_pattern_3_4: 580000 rects
-caravel_00020021_fill_pattern_3_4: 590000 rects
-caravel_00020021_fill_pattern_3_4: 600000 rects
-caravel_00020021_fill_pattern_3_4: 610000 rects
-caravel_00020021_fill_pattern_3_4: 620000 rects
-caravel_00020021_fill_pattern_3_4: 630000 rects
-caravel_00020021_fill_pattern_3_4: 640000 rects
-caravel_00020021_fill_pattern_3_4: 650000 rects
-caravel_00020021_fill_pattern_3_4: 660000 rects
-caravel_00020021_fill_pattern_3_4: 670000 rects
-caravel_00020021_fill_pattern_3_4: 680000 rects
-caravel_00020021_fill_pattern_3_4: 690000 rects
-caravel_00020021_fill_pattern_3_4: 700000 rects
-caravel_00020021_fill_pattern_3_4: 710000 rects
-caravel_00020021_fill_pattern_3_4: 720000 rects
-caravel_00020021_fill_pattern_3_4: 730000 rects
-caravel_00020021_fill_pattern_3_4: 740000 rects
-caravel_00020021_fill_pattern_3_4: 750000 rects
-caravel_00020021_fill_pattern_3_4: 760000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_4
+   Generating output for cell caravel_00020021_fill_pattern_1_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_1_3: 10000 rects
+caravel_00020021_fill_pattern_1_3: 20000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_1_3
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7604,42 +7449,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_2_6
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-Scaled magic input cell caravel_00020021_fill_pattern_3_3 geometry by factor of 2
-caravel_00020021_fill_pattern_3_3: 10000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_3
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_1_4: 10000 rects
 caravel_00020021_fill_pattern_1_4: 20000 rects
 caravel_00020021_fill_pattern_1_4: 30000 rects
@@ -7666,21 +7475,52 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_6: 10000 rects
-caravel_00020021_fill_pattern_3_6: 20000 rects
-caravel_00020021_fill_pattern_3_6: 30000 rects
-caravel_00020021_fill_pattern_3_6: 40000 rects
-caravel_00020021_fill_pattern_3_6: 50000 rects
-caravel_00020021_fill_pattern_3_6: 60000 rects
-caravel_00020021_fill_pattern_3_6: 70000 rects
-caravel_00020021_fill_pattern_3_6: 80000 rects
-caravel_00020021_fill_pattern_3_6: 90000 rects
-caravel_00020021_fill_pattern_3_6: 100000 rects
-caravel_00020021_fill_pattern_3_6: 110000 rects
-caravel_00020021_fill_pattern_3_6: 120000 rects
-caravel_00020021_fill_pattern_3_6: 130000 rects
+caravel_00020021_fill_pattern_4_6: 10000 rects
+caravel_00020021_fill_pattern_4_6: 20000 rects
+caravel_00020021_fill_pattern_4_6: 30000 rects
+caravel_00020021_fill_pattern_4_6: 40000 rects
+caravel_00020021_fill_pattern_4_6: 50000 rects
+caravel_00020021_fill_pattern_4_6: 60000 rects
+caravel_00020021_fill_pattern_4_6: 70000 rects
+caravel_00020021_fill_pattern_4_6: 80000 rects
+caravel_00020021_fill_pattern_4_6: 90000 rects
+caravel_00020021_fill_pattern_4_6: 100000 rects
+caravel_00020021_fill_pattern_4_6: 110000 rects
+caravel_00020021_fill_pattern_4_6: 120000 rects
+caravel_00020021_fill_pattern_4_6: 130000 rects
+caravel_00020021_fill_pattern_4_6: 140000 rects
+caravel_00020021_fill_pattern_4_6: 150000 rects
+caravel_00020021_fill_pattern_4_6: 160000 rects
+caravel_00020021_fill_pattern_4_6: 170000 rects
+caravel_00020021_fill_pattern_4_6: 180000 rects
+caravel_00020021_fill_pattern_4_6: 190000 rects
+caravel_00020021_fill_pattern_4_6: 200000 rects
+caravel_00020021_fill_pattern_4_6: 210000 rects
+caravel_00020021_fill_pattern_4_6: 220000 rects
+caravel_00020021_fill_pattern_4_6: 230000 rects
+caravel_00020021_fill_pattern_4_6: 240000 rects
+caravel_00020021_fill_pattern_4_6: 250000 rects
+caravel_00020021_fill_pattern_4_6: 260000 rects
+caravel_00020021_fill_pattern_4_6: 270000 rects
+caravel_00020021_fill_pattern_4_6: 280000 rects
+caravel_00020021_fill_pattern_4_6: 290000 rects
+caravel_00020021_fill_pattern_4_6: 300000 rects
+caravel_00020021_fill_pattern_4_6: 310000 rects
+caravel_00020021_fill_pattern_4_6: 320000 rects
+caravel_00020021_fill_pattern_4_6: 330000 rects
+caravel_00020021_fill_pattern_4_6: 340000 rects
+caravel_00020021_fill_pattern_4_6: 350000 rects
+caravel_00020021_fill_pattern_4_6: 360000 rects
+caravel_00020021_fill_pattern_4_6: 370000 rects
+caravel_00020021_fill_pattern_4_6: 380000 rects
+caravel_00020021_fill_pattern_4_6: 390000 rects
+caravel_00020021_fill_pattern_4_6: 400000 rects
+caravel_00020021_fill_pattern_4_6: 410000 rects
+caravel_00020021_fill_pattern_4_6: 420000 rects
+caravel_00020021_fill_pattern_4_6: 430000 rects
+caravel_00020021_fill_pattern_4_6: 440000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_6
+   Generating output for cell caravel_00020021_fill_pattern_4_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7697,7 +7537,119 @@
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_2
+   Generating output for cell caravel_00020021_fill_pattern_2_6
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_3_5: 10000 rects
+caravel_00020021_fill_pattern_3_5: 20000 rects
+caravel_00020021_fill_pattern_3_5: 30000 rects
+caravel_00020021_fill_pattern_3_5: 40000 rects
+caravel_00020021_fill_pattern_3_5: 50000 rects
+caravel_00020021_fill_pattern_3_5: 60000 rects
+caravel_00020021_fill_pattern_3_5: 70000 rects
+caravel_00020021_fill_pattern_3_5: 80000 rects
+caravel_00020021_fill_pattern_3_5: 90000 rects
+caravel_00020021_fill_pattern_3_5: 100000 rects
+caravel_00020021_fill_pattern_3_5: 110000 rects
+caravel_00020021_fill_pattern_3_5: 120000 rects
+caravel_00020021_fill_pattern_3_5: 130000 rects
+caravel_00020021_fill_pattern_3_5: 140000 rects
+caravel_00020021_fill_pattern_3_5: 150000 rects
+caravel_00020021_fill_pattern_3_5: 160000 rects
+caravel_00020021_fill_pattern_3_5: 170000 rects
+caravel_00020021_fill_pattern_3_5: 180000 rects
+caravel_00020021_fill_pattern_3_5: 190000 rects
+caravel_00020021_fill_pattern_3_5: 200000 rects
+caravel_00020021_fill_pattern_3_5: 210000 rects
+caravel_00020021_fill_pattern_3_5: 220000 rects
+caravel_00020021_fill_pattern_3_5: 230000 rects
+caravel_00020021_fill_pattern_3_5: 240000 rects
+caravel_00020021_fill_pattern_3_5: 250000 rects
+caravel_00020021_fill_pattern_3_5: 260000 rects
+caravel_00020021_fill_pattern_3_5: 270000 rects
+caravel_00020021_fill_pattern_3_5: 280000 rects
+caravel_00020021_fill_pattern_3_5: 290000 rects
+caravel_00020021_fill_pattern_3_5: 300000 rects
+caravel_00020021_fill_pattern_3_5: 310000 rects
+caravel_00020021_fill_pattern_3_5: 320000 rects
+caravel_00020021_fill_pattern_3_5: 330000 rects
+caravel_00020021_fill_pattern_3_5: 340000 rects
+caravel_00020021_fill_pattern_3_5: 350000 rects
+caravel_00020021_fill_pattern_3_5: 360000 rects
+caravel_00020021_fill_pattern_3_5: 370000 rects
+caravel_00020021_fill_pattern_3_5: 380000 rects
+caravel_00020021_fill_pattern_3_5: 390000 rects
+caravel_00020021_fill_pattern_3_5: 400000 rects
+caravel_00020021_fill_pattern_3_5: 410000 rects
+caravel_00020021_fill_pattern_3_5: 420000 rects
+caravel_00020021_fill_pattern_3_5: 430000 rects
+caravel_00020021_fill_pattern_3_5: 440000 rects
+caravel_00020021_fill_pattern_3_5: 450000 rects
+caravel_00020021_fill_pattern_3_5: 460000 rects
+caravel_00020021_fill_pattern_3_5: 470000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_3_5
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+Scaled magic input cell caravel_00020021_fill_pattern_2_3 geometry by factor of 2
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_2_3
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_3_6: 10000 rects
+caravel_00020021_fill_pattern_3_6: 20000 rects
+caravel_00020021_fill_pattern_3_6: 30000 rects
+caravel_00020021_fill_pattern_3_6: 40000 rects
+caravel_00020021_fill_pattern_3_6: 50000 rects
+caravel_00020021_fill_pattern_3_6: 60000 rects
+caravel_00020021_fill_pattern_3_6: 70000 rects
+caravel_00020021_fill_pattern_3_6: 80000 rects
+caravel_00020021_fill_pattern_3_6: 90000 rects
+caravel_00020021_fill_pattern_3_6: 100000 rects
+caravel_00020021_fill_pattern_3_6: 110000 rects
+caravel_00020021_fill_pattern_3_6: 120000 rects
+caravel_00020021_fill_pattern_3_6: 130000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_3_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7846,10 +7798,10 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_1_3: 10000 rects
-caravel_00020021_fill_pattern_1_3: 20000 rects
+Scaled magic input cell caravel_00020021_fill_pattern_3_3 geometry by factor of 2
+caravel_00020021_fill_pattern_3_3: 10000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_3
+   Generating output for cell caravel_00020021_fill_pattern_3_3
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -7892,55 +7844,84 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_5: 10000 rects
-caravel_00020021_fill_pattern_3_5: 20000 rects
-caravel_00020021_fill_pattern_3_5: 30000 rects
-caravel_00020021_fill_pattern_3_5: 40000 rects
-caravel_00020021_fill_pattern_3_5: 50000 rects
-caravel_00020021_fill_pattern_3_5: 60000 rects
-caravel_00020021_fill_pattern_3_5: 70000 rects
-caravel_00020021_fill_pattern_3_5: 80000 rects
-caravel_00020021_fill_pattern_3_5: 90000 rects
-caravel_00020021_fill_pattern_3_5: 100000 rects
-caravel_00020021_fill_pattern_3_5: 110000 rects
-caravel_00020021_fill_pattern_3_5: 120000 rects
-caravel_00020021_fill_pattern_3_5: 130000 rects
-caravel_00020021_fill_pattern_3_5: 140000 rects
-caravel_00020021_fill_pattern_3_5: 150000 rects
-caravel_00020021_fill_pattern_3_5: 160000 rects
-caravel_00020021_fill_pattern_3_5: 170000 rects
-caravel_00020021_fill_pattern_3_5: 180000 rects
-caravel_00020021_fill_pattern_3_5: 190000 rects
-caravel_00020021_fill_pattern_3_5: 200000 rects
-caravel_00020021_fill_pattern_3_5: 210000 rects
-caravel_00020021_fill_pattern_3_5: 220000 rects
-caravel_00020021_fill_pattern_3_5: 230000 rects
-caravel_00020021_fill_pattern_3_5: 240000 rects
-caravel_00020021_fill_pattern_3_5: 250000 rects
-caravel_00020021_fill_pattern_3_5: 260000 rects
-caravel_00020021_fill_pattern_3_5: 270000 rects
-caravel_00020021_fill_pattern_3_5: 280000 rects
-caravel_00020021_fill_pattern_3_5: 290000 rects
-caravel_00020021_fill_pattern_3_5: 300000 rects
-caravel_00020021_fill_pattern_3_5: 310000 rects
-caravel_00020021_fill_pattern_3_5: 320000 rects
-caravel_00020021_fill_pattern_3_5: 330000 rects
-caravel_00020021_fill_pattern_3_5: 340000 rects
-caravel_00020021_fill_pattern_3_5: 350000 rects
-caravel_00020021_fill_pattern_3_5: 360000 rects
-caravel_00020021_fill_pattern_3_5: 370000 rects
-caravel_00020021_fill_pattern_3_5: 380000 rects
-caravel_00020021_fill_pattern_3_5: 390000 rects
-caravel_00020021_fill_pattern_3_5: 400000 rects
-caravel_00020021_fill_pattern_3_5: 410000 rects
-caravel_00020021_fill_pattern_3_5: 420000 rects
-caravel_00020021_fill_pattern_3_5: 430000 rects
-caravel_00020021_fill_pattern_3_5: 440000 rects
-caravel_00020021_fill_pattern_3_5: 450000 rects
-caravel_00020021_fill_pattern_3_5: 460000 rects
-caravel_00020021_fill_pattern_3_5: 470000 rects
+caravel_00020021_fill_pattern_3_4: 10000 rects
+caravel_00020021_fill_pattern_3_4: 20000 rects
+caravel_00020021_fill_pattern_3_4: 30000 rects
+caravel_00020021_fill_pattern_3_4: 40000 rects
+caravel_00020021_fill_pattern_3_4: 50000 rects
+caravel_00020021_fill_pattern_3_4: 60000 rects
+caravel_00020021_fill_pattern_3_4: 70000 rects
+caravel_00020021_fill_pattern_3_4: 80000 rects
+caravel_00020021_fill_pattern_3_4: 90000 rects
+caravel_00020021_fill_pattern_3_4: 100000 rects
+caravel_00020021_fill_pattern_3_4: 110000 rects
+caravel_00020021_fill_pattern_3_4: 120000 rects
+caravel_00020021_fill_pattern_3_4: 130000 rects
+caravel_00020021_fill_pattern_3_4: 140000 rects
+caravel_00020021_fill_pattern_3_4: 150000 rects
+caravel_00020021_fill_pattern_3_4: 160000 rects
+caravel_00020021_fill_pattern_3_4: 170000 rects
+caravel_00020021_fill_pattern_3_4: 180000 rects
+caravel_00020021_fill_pattern_3_4: 190000 rects
+caravel_00020021_fill_pattern_3_4: 200000 rects
+caravel_00020021_fill_pattern_3_4: 210000 rects
+caravel_00020021_fill_pattern_3_4: 220000 rects
+caravel_00020021_fill_pattern_3_4: 230000 rects
+caravel_00020021_fill_pattern_3_4: 240000 rects
+caravel_00020021_fill_pattern_3_4: 250000 rects
+caravel_00020021_fill_pattern_3_4: 260000 rects
+caravel_00020021_fill_pattern_3_4: 270000 rects
+caravel_00020021_fill_pattern_3_4: 280000 rects
+caravel_00020021_fill_pattern_3_4: 290000 rects
+caravel_00020021_fill_pattern_3_4: 300000 rects
+caravel_00020021_fill_pattern_3_4: 310000 rects
+caravel_00020021_fill_pattern_3_4: 320000 rects
+caravel_00020021_fill_pattern_3_4: 330000 rects
+caravel_00020021_fill_pattern_3_4: 340000 rects
+caravel_00020021_fill_pattern_3_4: 350000 rects
+caravel_00020021_fill_pattern_3_4: 360000 rects
+caravel_00020021_fill_pattern_3_4: 370000 rects
+caravel_00020021_fill_pattern_3_4: 380000 rects
+caravel_00020021_fill_pattern_3_4: 390000 rects
+caravel_00020021_fill_pattern_3_4: 400000 rects
+caravel_00020021_fill_pattern_3_4: 410000 rects
+caravel_00020021_fill_pattern_3_4: 420000 rects
+caravel_00020021_fill_pattern_3_4: 430000 rects
+caravel_00020021_fill_pattern_3_4: 440000 rects
+caravel_00020021_fill_pattern_3_4: 450000 rects
+caravel_00020021_fill_pattern_3_4: 460000 rects
+caravel_00020021_fill_pattern_3_4: 470000 rects
+caravel_00020021_fill_pattern_3_4: 480000 rects
+caravel_00020021_fill_pattern_3_4: 490000 rects
+caravel_00020021_fill_pattern_3_4: 500000 rects
+caravel_00020021_fill_pattern_3_4: 510000 rects
+caravel_00020021_fill_pattern_3_4: 520000 rects
+caravel_00020021_fill_pattern_3_4: 530000 rects
+caravel_00020021_fill_pattern_3_4: 540000 rects
+caravel_00020021_fill_pattern_3_4: 550000 rects
+caravel_00020021_fill_pattern_3_4: 560000 rects
+caravel_00020021_fill_pattern_3_4: 570000 rects
+caravel_00020021_fill_pattern_3_4: 580000 rects
+caravel_00020021_fill_pattern_3_4: 590000 rects
+caravel_00020021_fill_pattern_3_4: 600000 rects
+caravel_00020021_fill_pattern_3_4: 610000 rects
+caravel_00020021_fill_pattern_3_4: 620000 rects
+caravel_00020021_fill_pattern_3_4: 630000 rects
+caravel_00020021_fill_pattern_3_4: 640000 rects
+caravel_00020021_fill_pattern_3_4: 650000 rects
+caravel_00020021_fill_pattern_3_4: 660000 rects
+caravel_00020021_fill_pattern_3_4: 670000 rects
+caravel_00020021_fill_pattern_3_4: 680000 rects
+caravel_00020021_fill_pattern_3_4: 690000 rects
+caravel_00020021_fill_pattern_3_4: 700000 rects
+caravel_00020021_fill_pattern_3_4: 710000 rects
+caravel_00020021_fill_pattern_3_4: 720000 rects
+caravel_00020021_fill_pattern_3_4: 730000 rects
+caravel_00020021_fill_pattern_3_4: 740000 rects
+caravel_00020021_fill_pattern_3_4: 750000 rects
+caravel_00020021_fill_pattern_3_4: 760000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_5
+   Generating output for cell caravel_00020021_fill_pattern_3_4
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -8061,82 +8042,71 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_6: 10000 rects
-caravel_00020021_fill_pattern_4_6: 20000 rects
-caravel_00020021_fill_pattern_4_6: 30000 rects
-caravel_00020021_fill_pattern_4_6: 40000 rects
-caravel_00020021_fill_pattern_4_6: 50000 rects
-caravel_00020021_fill_pattern_4_6: 60000 rects
-caravel_00020021_fill_pattern_4_6: 70000 rects
-caravel_00020021_fill_pattern_4_6: 80000 rects
-caravel_00020021_fill_pattern_4_6: 90000 rects
-caravel_00020021_fill_pattern_4_6: 100000 rects
-caravel_00020021_fill_pattern_4_6: 110000 rects
-caravel_00020021_fill_pattern_4_6: 120000 rects
-caravel_00020021_fill_pattern_4_6: 130000 rects
-caravel_00020021_fill_pattern_4_6: 140000 rects
-caravel_00020021_fill_pattern_4_6: 150000 rects
-caravel_00020021_fill_pattern_4_6: 160000 rects
-caravel_00020021_fill_pattern_4_6: 170000 rects
-caravel_00020021_fill_pattern_4_6: 180000 rects
-caravel_00020021_fill_pattern_4_6: 190000 rects
-caravel_00020021_fill_pattern_4_6: 200000 rects
-caravel_00020021_fill_pattern_4_6: 210000 rects
-caravel_00020021_fill_pattern_4_6: 220000 rects
-caravel_00020021_fill_pattern_4_6: 230000 rects
-caravel_00020021_fill_pattern_4_6: 240000 rects
-caravel_00020021_fill_pattern_4_6: 250000 rects
-caravel_00020021_fill_pattern_4_6: 260000 rects
-caravel_00020021_fill_pattern_4_6: 270000 rects
-caravel_00020021_fill_pattern_4_6: 280000 rects
-caravel_00020021_fill_pattern_4_6: 290000 rects
-caravel_00020021_fill_pattern_4_6: 300000 rects
-caravel_00020021_fill_pattern_4_6: 310000 rects
-caravel_00020021_fill_pattern_4_6: 320000 rects
-caravel_00020021_fill_pattern_4_6: 330000 rects
-caravel_00020021_fill_pattern_4_6: 340000 rects
-caravel_00020021_fill_pattern_4_6: 350000 rects
-caravel_00020021_fill_pattern_4_6: 360000 rects
-caravel_00020021_fill_pattern_4_6: 370000 rects
-caravel_00020021_fill_pattern_4_6: 380000 rects
-caravel_00020021_fill_pattern_4_6: 390000 rects
-caravel_00020021_fill_pattern_4_6: 400000 rects
-caravel_00020021_fill_pattern_4_6: 410000 rects
-caravel_00020021_fill_pattern_4_6: 420000 rects
-caravel_00020021_fill_pattern_4_6: 430000 rects
-caravel_00020021_fill_pattern_4_6: 440000 rects
+caravel_00020021_fill_pattern_0_6: 10000 rects
+caravel_00020021_fill_pattern_0_6: 20000 rects
+caravel_00020021_fill_pattern_0_6: 30000 rects
+caravel_00020021_fill_pattern_0_6: 40000 rects
+caravel_00020021_fill_pattern_0_6: 50000 rects
+caravel_00020021_fill_pattern_0_6: 60000 rects
+caravel_00020021_fill_pattern_0_6: 70000 rects
+caravel_00020021_fill_pattern_0_6: 80000 rects
+caravel_00020021_fill_pattern_0_6: 90000 rects
+caravel_00020021_fill_pattern_0_6: 100000 rects
+caravel_00020021_fill_pattern_0_6: 110000 rects
+caravel_00020021_fill_pattern_0_6: 120000 rects
+caravel_00020021_fill_pattern_0_6: 130000 rects
+caravel_00020021_fill_pattern_0_6: 140000 rects
+caravel_00020021_fill_pattern_0_6: 150000 rects
+caravel_00020021_fill_pattern_0_6: 160000 rects
+caravel_00020021_fill_pattern_0_6: 170000 rects
+caravel_00020021_fill_pattern_0_6: 180000 rects
+caravel_00020021_fill_pattern_0_6: 190000 rects
+caravel_00020021_fill_pattern_0_6: 200000 rects
+caravel_00020021_fill_pattern_0_6: 210000 rects
+caravel_00020021_fill_pattern_0_6: 220000 rects
+caravel_00020021_fill_pattern_0_6: 230000 rects
+caravel_00020021_fill_pattern_0_6: 240000 rects
+caravel_00020021_fill_pattern_0_6: 250000 rects
+caravel_00020021_fill_pattern_0_6: 260000 rects
+caravel_00020021_fill_pattern_0_6: 270000 rects
+caravel_00020021_fill_pattern_0_6: 280000 rects
+caravel_00020021_fill_pattern_0_6: 290000 rects
+caravel_00020021_fill_pattern_0_6: 300000 rects
+caravel_00020021_fill_pattern_0_6: 310000 rects
+caravel_00020021_fill_pattern_0_6: 320000 rects
+caravel_00020021_fill_pattern_0_6: 330000 rects
+caravel_00020021_fill_pattern_0_6: 340000 rects
+caravel_00020021_fill_pattern_0_6: 350000 rects
+caravel_00020021_fill_pattern_0_6: 360000 rects
+caravel_00020021_fill_pattern_0_6: 370000 rects
+caravel_00020021_fill_pattern_0_6: 380000 rects
+caravel_00020021_fill_pattern_0_6: 390000 rects
+caravel_00020021_fill_pattern_0_6: 400000 rects
+caravel_00020021_fill_pattern_0_6: 410000 rects
+caravel_00020021_fill_pattern_0_6: 420000 rects
+caravel_00020021_fill_pattern_0_6: 430000 rects
+caravel_00020021_fill_pattern_0_6: 440000 rects
+caravel_00020021_fill_pattern_0_6: 450000 rects
+caravel_00020021_fill_pattern_0_6: 460000 rects
+caravel_00020021_fill_pattern_0_6: 470000 rects
+caravel_00020021_fill_pattern_0_6: 480000 rects
+caravel_00020021_fill_pattern_0_6: 490000 rects
+caravel_00020021_fill_pattern_0_6: 500000 rects
+caravel_00020021_fill_pattern_0_6: 510000 rects
+caravel_00020021_fill_pattern_0_6: 520000 rects
+caravel_00020021_fill_pattern_0_6: 530000 rects
+caravel_00020021_fill_pattern_0_6: 540000 rects
+caravel_00020021_fill_pattern_0_6: 550000 rects
+caravel_00020021_fill_pattern_0_6: 560000 rects
+caravel_00020021_fill_pattern_0_6: 570000 rects
+caravel_00020021_fill_pattern_0_6: 580000 rects
+caravel_00020021_fill_pattern_0_6: 590000 rects
+caravel_00020021_fill_pattern_0_6: 600000 rects
+caravel_00020021_fill_pattern_0_6: 610000 rects
+caravel_00020021_fill_pattern_0_6: 620000 rects
+caravel_00020021_fill_pattern_0_6: 630000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_6
-
-caravel_00020021_fill_pattern_0_2: 1560000 rects
-caravel_00020021_fill_pattern_0_2: 1570000 rects
-caravel_00020021_fill_pattern_0_2: 1580000 rects
-caravel_00020021_fill_pattern_0_2: 1590000 rects
-caravel_00020021_fill_pattern_0_2: 1600000 rects
-caravel_00020021_fill_pattern_0_2: 1610000 rects
-caravel_00020021_fill_pattern_0_2: 1620000 rects
-caravel_00020021_fill_pattern_0_2: 1630000 rects
-caravel_00020021_fill_pattern_0_2: 1640000 rects
-caravel_00020021_fill_pattern_0_2: 1650000 rects
-caravel_00020021_fill_pattern_0_2: 1660000 rects
-caravel_00020021_fill_pattern_0_2: 1670000 rects
-caravel_00020021_fill_pattern_0_2: 1680000 rects
-caravel_00020021_fill_pattern_0_2: 1690000 rects
-caravel_00020021_fill_pattern_0_2: 1700000 rects
-caravel_00020021_fill_pattern_0_2: 1710000 rects
-caravel_00020021_fill_pattern_0_2: 1720000 rects
-caravel_00020021_fill_pattern_0_2: 1730000 rects
-caravel_00020021_fill_pattern_0_2: 1740000 rects
-caravel_00020021_fill_pattern_0_2: 1750000 rects
-caravel_00020021_fill_pattern_0_2: 1760000 rects
-caravel_00020021_fill_pattern_0_2: 1770000 rects
-caravel_00020021_fill_pattern_0_2: 1780000 rects
-caravel_00020021_fill_pattern_0_2: 1790000 rects
-caravel_00020021_fill_pattern_0_2: 1800000 rects
-caravel_00020021_fill_pattern_0_2: 1810000 rects
-caravel_00020021_fill_pattern_0_2: 1820000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_2
+   Generating output for cell caravel_00020021_fill_pattern_0_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -8231,94 +8201,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_5: 10000 rects
-caravel_00020021_fill_pattern_4_5: 20000 rects
-caravel_00020021_fill_pattern_4_5: 30000 rects
-caravel_00020021_fill_pattern_4_5: 40000 rects
-caravel_00020021_fill_pattern_4_5: 50000 rects
-caravel_00020021_fill_pattern_4_5: 60000 rects
-caravel_00020021_fill_pattern_4_5: 70000 rects
-caravel_00020021_fill_pattern_4_5: 80000 rects
-caravel_00020021_fill_pattern_4_5: 90000 rects
-caravel_00020021_fill_pattern_4_5: 100000 rects
-caravel_00020021_fill_pattern_4_5: 110000 rects
-caravel_00020021_fill_pattern_4_5: 120000 rects
-caravel_00020021_fill_pattern_4_5: 130000 rects
-caravel_00020021_fill_pattern_4_5: 140000 rects
-caravel_00020021_fill_pattern_4_5: 150000 rects
-caravel_00020021_fill_pattern_4_5: 160000 rects
-caravel_00020021_fill_pattern_4_5: 170000 rects
-caravel_00020021_fill_pattern_4_5: 180000 rects
-caravel_00020021_fill_pattern_4_5: 190000 rects
-caravel_00020021_fill_pattern_4_5: 200000 rects
-caravel_00020021_fill_pattern_4_5: 210000 rects
-caravel_00020021_fill_pattern_4_5: 220000 rects
-caravel_00020021_fill_pattern_4_5: 230000 rects
-caravel_00020021_fill_pattern_4_5: 240000 rects
-caravel_00020021_fill_pattern_4_5: 250000 rects
-caravel_00020021_fill_pattern_4_5: 260000 rects
-caravel_00020021_fill_pattern_4_5: 270000 rects
-caravel_00020021_fill_pattern_4_5: 280000 rects
-caravel_00020021_fill_pattern_4_5: 290000 rects
-caravel_00020021_fill_pattern_4_5: 300000 rects
-caravel_00020021_fill_pattern_4_5: 310000 rects
-caravel_00020021_fill_pattern_4_5: 320000 rects
-caravel_00020021_fill_pattern_4_5: 330000 rects
-caravel_00020021_fill_pattern_4_5: 340000 rects
-caravel_00020021_fill_pattern_4_5: 350000 rects
-caravel_00020021_fill_pattern_4_5: 360000 rects
-caravel_00020021_fill_pattern_4_5: 370000 rects
-caravel_00020021_fill_pattern_4_5: 380000 rects
-caravel_00020021_fill_pattern_4_5: 390000 rects
-caravel_00020021_fill_pattern_4_5: 400000 rects
-caravel_00020021_fill_pattern_4_5: 410000 rects
-caravel_00020021_fill_pattern_4_5: 420000 rects
-caravel_00020021_fill_pattern_4_5: 430000 rects
-caravel_00020021_fill_pattern_4_5: 440000 rects
-caravel_00020021_fill_pattern_4_5: 450000 rects
-caravel_00020021_fill_pattern_4_5: 460000 rects
-caravel_00020021_fill_pattern_4_5: 470000 rects
-caravel_00020021_fill_pattern_4_5: 480000 rects
-caravel_00020021_fill_pattern_4_5: 490000 rects
-caravel_00020021_fill_pattern_4_5: 500000 rects
-caravel_00020021_fill_pattern_4_5: 510000 rects
-caravel_00020021_fill_pattern_4_5: 520000 rects
-caravel_00020021_fill_pattern_4_5: 530000 rects
-caravel_00020021_fill_pattern_4_5: 540000 rects
-caravel_00020021_fill_pattern_4_5: 550000 rects
-caravel_00020021_fill_pattern_4_5: 560000 rects
-caravel_00020021_fill_pattern_4_5: 570000 rects
-caravel_00020021_fill_pattern_4_5: 580000 rects
-caravel_00020021_fill_pattern_4_5: 590000 rects
-caravel_00020021_fill_pattern_4_5: 600000 rects
-caravel_00020021_fill_pattern_4_5: 610000 rects
-caravel_00020021_fill_pattern_4_5: 620000 rects
-caravel_00020021_fill_pattern_4_5: 630000 rects
-caravel_00020021_fill_pattern_4_5: 640000 rects
-caravel_00020021_fill_pattern_4_5: 650000 rects
-caravel_00020021_fill_pattern_4_5: 660000 rects
-caravel_00020021_fill_pattern_4_5: 670000 rects
-caravel_00020021_fill_pattern_4_5: 680000 rects
-caravel_00020021_fill_pattern_4_5: 690000 rects
-caravel_00020021_fill_pattern_4_5: 700000 rects
-caravel_00020021_fill_pattern_4_5: 710000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_5
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_4_2: 10000 rects
 caravel_00020021_fill_pattern_4_2: 20000 rects
 caravel_00020021_fill_pattern_4_2: 30000 rects
@@ -8406,6 +8288,124 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_4_2
 
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_4_5: 10000 rects
+caravel_00020021_fill_pattern_4_5: 20000 rects
+caravel_00020021_fill_pattern_4_5: 30000 rects
+caravel_00020021_fill_pattern_4_5: 40000 rects
+caravel_00020021_fill_pattern_4_5: 50000 rects
+caravel_00020021_fill_pattern_4_5: 60000 rects
+caravel_00020021_fill_pattern_4_5: 70000 rects
+caravel_00020021_fill_pattern_4_5: 80000 rects
+caravel_00020021_fill_pattern_4_5: 90000 rects
+caravel_00020021_fill_pattern_4_5: 100000 rects
+caravel_00020021_fill_pattern_4_5: 110000 rects
+caravel_00020021_fill_pattern_4_5: 120000 rects
+caravel_00020021_fill_pattern_4_5: 130000 rects
+caravel_00020021_fill_pattern_4_5: 140000 rects
+caravel_00020021_fill_pattern_4_5: 150000 rects
+caravel_00020021_fill_pattern_4_5: 160000 rects
+caravel_00020021_fill_pattern_4_5: 170000 rects
+caravel_00020021_fill_pattern_4_5: 180000 rects
+caravel_00020021_fill_pattern_4_5: 190000 rects
+caravel_00020021_fill_pattern_4_5: 200000 rects
+caravel_00020021_fill_pattern_4_5: 210000 rects
+caravel_00020021_fill_pattern_4_5: 220000 rects
+caravel_00020021_fill_pattern_4_5: 230000 rects
+caravel_00020021_fill_pattern_4_5: 240000 rects
+caravel_00020021_fill_pattern_4_5: 250000 rects
+caravel_00020021_fill_pattern_4_5: 260000 rects
+caravel_00020021_fill_pattern_4_5: 270000 rects
+caravel_00020021_fill_pattern_4_5: 280000 rects
+caravel_00020021_fill_pattern_4_5: 290000 rects
+caravel_00020021_fill_pattern_4_5: 300000 rects
+caravel_00020021_fill_pattern_4_5: 310000 rects
+caravel_00020021_fill_pattern_4_5: 320000 rects
+caravel_00020021_fill_pattern_4_5: 330000 rects
+caravel_00020021_fill_pattern_4_5: 340000 rects
+caravel_00020021_fill_pattern_4_5: 350000 rects
+caravel_00020021_fill_pattern_4_5: 360000 rects
+caravel_00020021_fill_pattern_4_5: 370000 rects
+caravel_00020021_fill_pattern_4_5: 380000 rects
+caravel_00020021_fill_pattern_4_5: 390000 rects
+caravel_00020021_fill_pattern_4_5: 400000 rects
+caravel_00020021_fill_pattern_4_5: 410000 rects
+caravel_00020021_fill_pattern_4_5: 420000 rects
+caravel_00020021_fill_pattern_4_5: 430000 rects
+caravel_00020021_fill_pattern_4_5: 440000 rects
+caravel_00020021_fill_pattern_4_5: 450000 rects
+caravel_00020021_fill_pattern_4_5: 460000 rects
+caravel_00020021_fill_pattern_4_5: 470000 rects
+caravel_00020021_fill_pattern_4_5: 480000 rects
+caravel_00020021_fill_pattern_4_5: 490000 rects
+caravel_00020021_fill_pattern_4_5: 500000 rects
+caravel_00020021_fill_pattern_4_5: 510000 rects
+caravel_00020021_fill_pattern_4_5: 520000 rects
+caravel_00020021_fill_pattern_4_5: 530000 rects
+caravel_00020021_fill_pattern_4_5: 540000 rects
+caravel_00020021_fill_pattern_4_5: 550000 rects
+caravel_00020021_fill_pattern_4_5: 560000 rects
+caravel_00020021_fill_pattern_4_5: 570000 rects
+caravel_00020021_fill_pattern_4_5: 580000 rects
+caravel_00020021_fill_pattern_4_5: 590000 rects
+caravel_00020021_fill_pattern_4_5: 600000 rects
+caravel_00020021_fill_pattern_4_5: 610000 rects
+caravel_00020021_fill_pattern_4_5: 620000 rects
+caravel_00020021_fill_pattern_4_5: 630000 rects
+caravel_00020021_fill_pattern_4_5: 640000 rects
+caravel_00020021_fill_pattern_4_5: 650000 rects
+caravel_00020021_fill_pattern_4_5: 660000 rects
+caravel_00020021_fill_pattern_4_5: 670000 rects
+caravel_00020021_fill_pattern_4_5: 680000 rects
+caravel_00020021_fill_pattern_4_5: 690000 rects
+caravel_00020021_fill_pattern_4_5: 700000 rects
+caravel_00020021_fill_pattern_4_5: 710000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_4_5
+
+caravel_00020021_fill_pattern_0_2: 1560000 rects
+caravel_00020021_fill_pattern_0_2: 1570000 rects
+caravel_00020021_fill_pattern_0_2: 1580000 rects
+caravel_00020021_fill_pattern_0_2: 1590000 rects
+caravel_00020021_fill_pattern_0_2: 1600000 rects
+caravel_00020021_fill_pattern_0_2: 1610000 rects
+caravel_00020021_fill_pattern_0_2: 1620000 rects
+caravel_00020021_fill_pattern_0_2: 1630000 rects
+caravel_00020021_fill_pattern_0_2: 1640000 rects
+caravel_00020021_fill_pattern_0_2: 1650000 rects
+caravel_00020021_fill_pattern_0_2: 1660000 rects
+caravel_00020021_fill_pattern_0_2: 1670000 rects
+caravel_00020021_fill_pattern_0_2: 1680000 rects
+caravel_00020021_fill_pattern_0_2: 1690000 rects
+caravel_00020021_fill_pattern_0_2: 1700000 rects
+caravel_00020021_fill_pattern_0_2: 1710000 rects
+caravel_00020021_fill_pattern_0_2: 1720000 rects
+caravel_00020021_fill_pattern_0_2: 1730000 rects
+caravel_00020021_fill_pattern_0_2: 1740000 rects
+caravel_00020021_fill_pattern_0_2: 1750000 rects
+caravel_00020021_fill_pattern_0_2: 1760000 rects
+caravel_00020021_fill_pattern_0_2: 1770000 rects
+caravel_00020021_fill_pattern_0_2: 1780000 rects
+caravel_00020021_fill_pattern_0_2: 1790000 rects
+caravel_00020021_fill_pattern_0_2: 1800000 rects
+caravel_00020021_fill_pattern_0_2: 1810000 rects
+caravel_00020021_fill_pattern_0_2: 1820000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_0_2
+
 caravel_00020021_fill_pattern_0_5: 1560000 rects
 caravel_00020021_fill_pattern_0_5: 1570000 rects
 caravel_00020021_fill_pattern_0_5: 1580000 rects
@@ -8435,6 +8435,7 @@
 caravel_00020021_fill_pattern_0_5: 1820000 rects
 caravel_00020021_fill_pattern_0_5: 1830000 rects
 caravel_00020021_fill_pattern_0_5: 1840000 rects
+caravel_00020021_fill_pattern_0_5: 1850000 rects
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_5
 
@@ -8465,110 +8466,6 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_4
 
-caravel_00020021_fill_pattern_4_0: 1560000 rects
-caravel_00020021_fill_pattern_4_0: 1570000 rects
-caravel_00020021_fill_pattern_4_0: 1580000 rects
-caravel_00020021_fill_pattern_4_0: 1590000 rects
-caravel_00020021_fill_pattern_4_0: 1600000 rects
-caravel_00020021_fill_pattern_4_0: 1610000 rects
-caravel_00020021_fill_pattern_4_0: 1620000 rects
-caravel_00020021_fill_pattern_4_0: 1630000 rects
-caravel_00020021_fill_pattern_4_0: 1640000 rects
-caravel_00020021_fill_pattern_4_0: 1650000 rects
-caravel_00020021_fill_pattern_4_0: 1660000 rects
-caravel_00020021_fill_pattern_4_0: 1670000 rects
-caravel_00020021_fill_pattern_4_0: 1680000 rects
-caravel_00020021_fill_pattern_4_0: 1690000 rects
-caravel_00020021_fill_pattern_4_0: 1700000 rects
-caravel_00020021_fill_pattern_4_0: 1710000 rects
-caravel_00020021_fill_pattern_4_0: 1720000 rects
-caravel_00020021_fill_pattern_4_0: 1730000 rects
-caravel_00020021_fill_pattern_4_0: 1740000 rects
-caravel_00020021_fill_pattern_4_0: 1750000 rects
-caravel_00020021_fill_pattern_4_0: 1760000 rects
-caravel_00020021_fill_pattern_4_0: 1770000 rects
-caravel_00020021_fill_pattern_4_0: 1780000 rects
-caravel_00020021_fill_pattern_4_0: 1790000 rects
-caravel_00020021_fill_pattern_4_0: 1800000 rects
-caravel_00020021_fill_pattern_4_0: 1810000 rects
-caravel_00020021_fill_pattern_4_0: 1820000 rects
-caravel_00020021_fill_pattern_4_0: 1830000 rects
-caravel_00020021_fill_pattern_4_0: 1840000 rects
-caravel_00020021_fill_pattern_4_0: 1850000 rects
-caravel_00020021_fill_pattern_4_0: 1860000 rects
-caravel_00020021_fill_pattern_4_0: 1870000 rects
-caravel_00020021_fill_pattern_4_0: 1880000 rects
-caravel_00020021_fill_pattern_4_0: 1890000 rects
-caravel_00020021_fill_pattern_4_0: 1900000 rects
-caravel_00020021_fill_pattern_4_0: 1910000 rects
-caravel_00020021_fill_pattern_4_0: 1920000 rects
-caravel_00020021_fill_pattern_4_0: 1930000 rects
-caravel_00020021_fill_pattern_4_0: 1940000 rects
-caravel_00020021_fill_pattern_4_0: 1950000 rects
-caravel_00020021_fill_pattern_4_0: 1960000 rects
-caravel_00020021_fill_pattern_4_0: 1970000 rects
-caravel_00020021_fill_pattern_4_0: 1980000 rects
-caravel_00020021_fill_pattern_4_0: 1990000 rects
-caravel_00020021_fill_pattern_4_0: 2000000 rects
-caravel_00020021_fill_pattern_4_0: 2010000 rects
-caravel_00020021_fill_pattern_4_0: 2020000 rects
-caravel_00020021_fill_pattern_4_0: 2030000 rects
-caravel_00020021_fill_pattern_4_0: 2040000 rects
-caravel_00020021_fill_pattern_4_0: 2050000 rects
-caravel_00020021_fill_pattern_4_0: 2060000 rects
-caravel_00020021_fill_pattern_4_0: 2070000 rects
-caravel_00020021_fill_pattern_4_0: 2080000 rects
-caravel_00020021_fill_pattern_4_0: 2090000 rects
-caravel_00020021_fill_pattern_4_0: 2100000 rects
-caravel_00020021_fill_pattern_4_0: 2110000 rects
-caravel_00020021_fill_pattern_4_0: 2120000 rects
-caravel_00020021_fill_pattern_4_0: 2130000 rects
-caravel_00020021_fill_pattern_4_0: 2140000 rects
-caravel_00020021_fill_pattern_4_0: 2150000 rects
-caravel_00020021_fill_pattern_4_0: 2160000 rects
-caravel_00020021_fill_pattern_4_0: 2170000 rects
-caravel_00020021_fill_pattern_4_0: 2180000 rects
-caravel_00020021_fill_pattern_4_0: 2190000 rects
-caravel_00020021_fill_pattern_4_0: 2200000 rects
-caravel_00020021_fill_pattern_4_0: 2210000 rects
-caravel_00020021_fill_pattern_4_0: 2220000 rects
-caravel_00020021_fill_pattern_4_0: 2230000 rects
-caravel_00020021_fill_pattern_4_0: 2240000 rects
-caravel_00020021_fill_pattern_4_0: 2250000 rects
-caravel_00020021_fill_pattern_4_0: 2260000 rects
-caravel_00020021_fill_pattern_4_0: 2270000 rects
-caravel_00020021_fill_pattern_4_0: 2280000 rects
-caravel_00020021_fill_pattern_4_0: 2290000 rects
-caravel_00020021_fill_pattern_4_0: 2300000 rects
-caravel_00020021_fill_pattern_4_0: 2310000 rects
-caravel_00020021_fill_pattern_4_0: 2320000 rects
-caravel_00020021_fill_pattern_4_0: 2330000 rects
-caravel_00020021_fill_pattern_4_0: 2340000 rects
-caravel_00020021_fill_pattern_4_0: 2350000 rects
-caravel_00020021_fill_pattern_4_0: 2360000 rects
-caravel_00020021_fill_pattern_4_0: 2370000 rects
-caravel_00020021_fill_pattern_4_0: 2380000 rects
-caravel_00020021_fill_pattern_4_0: 2390000 rects
-caravel_00020021_fill_pattern_4_0: 2400000 rects
-caravel_00020021_fill_pattern_4_0: 2410000 rects
-caravel_00020021_fill_pattern_4_0: 2420000 rects
-caravel_00020021_fill_pattern_4_0: 2430000 rects
-caravel_00020021_fill_pattern_4_0: 2440000 rects
-caravel_00020021_fill_pattern_4_0: 2450000 rects
-caravel_00020021_fill_pattern_4_0: 2460000 rects
-caravel_00020021_fill_pattern_4_0: 2470000 rects
-caravel_00020021_fill_pattern_4_0: 2480000 rects
-caravel_00020021_fill_pattern_4_0: 2490000 rects
-caravel_00020021_fill_pattern_4_0: 2500000 rects
-caravel_00020021_fill_pattern_4_0: 2510000 rects
-caravel_00020021_fill_pattern_4_0: 2520000 rects
-caravel_00020021_fill_pattern_4_0: 2530000 rects
-caravel_00020021_fill_pattern_4_0: 2540000 rects
-caravel_00020021_fill_pattern_4_0: 2550000 rects
-caravel_00020021_fill_pattern_4_0: 2560000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_0
-
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
@@ -8698,6 +8595,110 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_2_5
 
+caravel_00020021_fill_pattern_4_0: 1560000 rects
+caravel_00020021_fill_pattern_4_0: 1570000 rects
+caravel_00020021_fill_pattern_4_0: 1580000 rects
+caravel_00020021_fill_pattern_4_0: 1590000 rects
+caravel_00020021_fill_pattern_4_0: 1600000 rects
+caravel_00020021_fill_pattern_4_0: 1610000 rects
+caravel_00020021_fill_pattern_4_0: 1620000 rects
+caravel_00020021_fill_pattern_4_0: 1630000 rects
+caravel_00020021_fill_pattern_4_0: 1640000 rects
+caravel_00020021_fill_pattern_4_0: 1650000 rects
+caravel_00020021_fill_pattern_4_0: 1660000 rects
+caravel_00020021_fill_pattern_4_0: 1670000 rects
+caravel_00020021_fill_pattern_4_0: 1680000 rects
+caravel_00020021_fill_pattern_4_0: 1690000 rects
+caravel_00020021_fill_pattern_4_0: 1700000 rects
+caravel_00020021_fill_pattern_4_0: 1710000 rects
+caravel_00020021_fill_pattern_4_0: 1720000 rects
+caravel_00020021_fill_pattern_4_0: 1730000 rects
+caravel_00020021_fill_pattern_4_0: 1740000 rects
+caravel_00020021_fill_pattern_4_0: 1750000 rects
+caravel_00020021_fill_pattern_4_0: 1760000 rects
+caravel_00020021_fill_pattern_4_0: 1770000 rects
+caravel_00020021_fill_pattern_4_0: 1780000 rects
+caravel_00020021_fill_pattern_4_0: 1790000 rects
+caravel_00020021_fill_pattern_4_0: 1800000 rects
+caravel_00020021_fill_pattern_4_0: 1810000 rects
+caravel_00020021_fill_pattern_4_0: 1820000 rects
+caravel_00020021_fill_pattern_4_0: 1830000 rects
+caravel_00020021_fill_pattern_4_0: 1840000 rects
+caravel_00020021_fill_pattern_4_0: 1850000 rects
+caravel_00020021_fill_pattern_4_0: 1860000 rects
+caravel_00020021_fill_pattern_4_0: 1870000 rects
+caravel_00020021_fill_pattern_4_0: 1880000 rects
+caravel_00020021_fill_pattern_4_0: 1890000 rects
+caravel_00020021_fill_pattern_4_0: 1900000 rects
+caravel_00020021_fill_pattern_4_0: 1910000 rects
+caravel_00020021_fill_pattern_4_0: 1920000 rects
+caravel_00020021_fill_pattern_4_0: 1930000 rects
+caravel_00020021_fill_pattern_4_0: 1940000 rects
+caravel_00020021_fill_pattern_4_0: 1950000 rects
+caravel_00020021_fill_pattern_4_0: 1960000 rects
+caravel_00020021_fill_pattern_4_0: 1970000 rects
+caravel_00020021_fill_pattern_4_0: 1980000 rects
+caravel_00020021_fill_pattern_4_0: 1990000 rects
+caravel_00020021_fill_pattern_4_0: 2000000 rects
+caravel_00020021_fill_pattern_4_0: 2010000 rects
+caravel_00020021_fill_pattern_4_0: 2020000 rects
+caravel_00020021_fill_pattern_4_0: 2030000 rects
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+caravel_00020021_fill_pattern_4_0: 2050000 rects
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+caravel_00020021_fill_pattern_4_0: 2080000 rects
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+caravel_00020021_fill_pattern_4_0: 2100000 rects
+caravel_00020021_fill_pattern_4_0: 2110000 rects
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+caravel_00020021_fill_pattern_4_0: 2130000 rects
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+caravel_00020021_fill_pattern_4_0: 2160000 rects
+caravel_00020021_fill_pattern_4_0: 2170000 rects
+caravel_00020021_fill_pattern_4_0: 2180000 rects
+caravel_00020021_fill_pattern_4_0: 2190000 rects
+caravel_00020021_fill_pattern_4_0: 2200000 rects
+caravel_00020021_fill_pattern_4_0: 2210000 rects
+caravel_00020021_fill_pattern_4_0: 2220000 rects
+caravel_00020021_fill_pattern_4_0: 2230000 rects
+caravel_00020021_fill_pattern_4_0: 2240000 rects
+caravel_00020021_fill_pattern_4_0: 2250000 rects
+caravel_00020021_fill_pattern_4_0: 2260000 rects
+caravel_00020021_fill_pattern_4_0: 2270000 rects
+caravel_00020021_fill_pattern_4_0: 2280000 rects
+caravel_00020021_fill_pattern_4_0: 2290000 rects
+caravel_00020021_fill_pattern_4_0: 2300000 rects
+caravel_00020021_fill_pattern_4_0: 2310000 rects
+caravel_00020021_fill_pattern_4_0: 2320000 rects
+caravel_00020021_fill_pattern_4_0: 2330000 rects
+caravel_00020021_fill_pattern_4_0: 2340000 rects
+caravel_00020021_fill_pattern_4_0: 2350000 rects
+caravel_00020021_fill_pattern_4_0: 2360000 rects
+caravel_00020021_fill_pattern_4_0: 2370000 rects
+caravel_00020021_fill_pattern_4_0: 2380000 rects
+caravel_00020021_fill_pattern_4_0: 2390000 rects
+caravel_00020021_fill_pattern_4_0: 2400000 rects
+caravel_00020021_fill_pattern_4_0: 2410000 rects
+caravel_00020021_fill_pattern_4_0: 2420000 rects
+caravel_00020021_fill_pattern_4_0: 2430000 rects
+caravel_00020021_fill_pattern_4_0: 2440000 rects
+caravel_00020021_fill_pattern_4_0: 2450000 rects
+caravel_00020021_fill_pattern_4_0: 2460000 rects
+caravel_00020021_fill_pattern_4_0: 2470000 rects
+caravel_00020021_fill_pattern_4_0: 2480000 rects
+caravel_00020021_fill_pattern_4_0: 2490000 rects
+caravel_00020021_fill_pattern_4_0: 2500000 rects
+caravel_00020021_fill_pattern_4_0: 2510000 rects
+caravel_00020021_fill_pattern_4_0: 2520000 rects
+caravel_00020021_fill_pattern_4_0: 2530000 rects
+caravel_00020021_fill_pattern_4_0: 2540000 rects
+caravel_00020021_fill_pattern_4_0: 2550000 rects
+caravel_00020021_fill_pattern_4_0: 2560000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_4_0
+
 caravel_00020021_fill_pattern_4_1: 1560000 rects
 caravel_00020021_fill_pattern_4_1: 1570000 rects
 caravel_00020021_fill_pattern_4_1: 1580000 rects
@@ -9003,91 +9004,6 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_1
 
-caravel_00020021_fill_pattern_1_1: 3240000 rects
-caravel_00020021_fill_pattern_1_1: 3250000 rects
-caravel_00020021_fill_pattern_1_1: 3260000 rects
-caravel_00020021_fill_pattern_1_1: 3270000 rects
-caravel_00020021_fill_pattern_1_1: 3280000 rects
-caravel_00020021_fill_pattern_1_1: 3290000 rects
-caravel_00020021_fill_pattern_1_1: 3300000 rects
-caravel_00020021_fill_pattern_1_1: 3310000 rects
-caravel_00020021_fill_pattern_1_1: 3320000 rects
-caravel_00020021_fill_pattern_1_1: 3330000 rects
-caravel_00020021_fill_pattern_1_1: 3340000 rects
-caravel_00020021_fill_pattern_1_1: 3350000 rects
-caravel_00020021_fill_pattern_1_1: 3360000 rects
-caravel_00020021_fill_pattern_1_1: 3370000 rects
-caravel_00020021_fill_pattern_1_1: 3380000 rects
-caravel_00020021_fill_pattern_1_1: 3390000 rects
-caravel_00020021_fill_pattern_1_1: 3400000 rects
-caravel_00020021_fill_pattern_1_1: 3410000 rects
-caravel_00020021_fill_pattern_1_1: 3420000 rects
-caravel_00020021_fill_pattern_1_1: 3430000 rects
-caravel_00020021_fill_pattern_1_1: 3440000 rects
-caravel_00020021_fill_pattern_1_1: 3450000 rects
-caravel_00020021_fill_pattern_1_1: 3460000 rects
-caravel_00020021_fill_pattern_1_1: 3470000 rects
-caravel_00020021_fill_pattern_1_1: 3480000 rects
-caravel_00020021_fill_pattern_1_1: 3490000 rects
-caravel_00020021_fill_pattern_1_1: 3500000 rects
-caravel_00020021_fill_pattern_1_1: 3510000 rects
-caravel_00020021_fill_pattern_1_1: 3520000 rects
-caravel_00020021_fill_pattern_1_1: 3530000 rects
-caravel_00020021_fill_pattern_1_1: 3540000 rects
-caravel_00020021_fill_pattern_1_1: 3550000 rects
-caravel_00020021_fill_pattern_1_1: 3560000 rects
-caravel_00020021_fill_pattern_1_1: 3570000 rects
-caravel_00020021_fill_pattern_1_1: 3580000 rects
-caravel_00020021_fill_pattern_1_1: 3590000 rects
-caravel_00020021_fill_pattern_1_1: 3600000 rects
-caravel_00020021_fill_pattern_1_1: 3610000 rects
-caravel_00020021_fill_pattern_1_1: 3620000 rects
-caravel_00020021_fill_pattern_1_1: 3630000 rects
-caravel_00020021_fill_pattern_1_1: 3640000 rects
-caravel_00020021_fill_pattern_1_1: 3650000 rects
-caravel_00020021_fill_pattern_1_1: 3660000 rects
-caravel_00020021_fill_pattern_1_1: 3670000 rects
-caravel_00020021_fill_pattern_1_1: 3680000 rects
-caravel_00020021_fill_pattern_1_1: 3690000 rects
-caravel_00020021_fill_pattern_1_1: 3700000 rects
-caravel_00020021_fill_pattern_1_1: 3710000 rects
-caravel_00020021_fill_pattern_1_1: 3720000 rects
-caravel_00020021_fill_pattern_1_1: 3730000 rects
-caravel_00020021_fill_pattern_1_1: 3740000 rects
-caravel_00020021_fill_pattern_1_1: 3750000 rects
-caravel_00020021_fill_pattern_1_1: 3760000 rects
-caravel_00020021_fill_pattern_1_1: 3770000 rects
-caravel_00020021_fill_pattern_1_1: 3780000 rects
-caravel_00020021_fill_pattern_1_1: 3790000 rects
-caravel_00020021_fill_pattern_1_1: 3800000 rects
-caravel_00020021_fill_pattern_1_1: 3810000 rects
-caravel_00020021_fill_pattern_1_1: 3820000 rects
-caravel_00020021_fill_pattern_1_1: 3830000 rects
-caravel_00020021_fill_pattern_1_1: 3840000 rects
-caravel_00020021_fill_pattern_1_1: 3850000 rects
-caravel_00020021_fill_pattern_1_1: 3860000 rects
-caravel_00020021_fill_pattern_1_1: 3870000 rects
-caravel_00020021_fill_pattern_1_1: 3880000 rects
-caravel_00020021_fill_pattern_1_1: 3890000 rects
-caravel_00020021_fill_pattern_1_1: 3900000 rects
-caravel_00020021_fill_pattern_1_1: 3910000 rects
-caravel_00020021_fill_pattern_1_1: 3920000 rects
-caravel_00020021_fill_pattern_1_1: 3930000 rects
-caravel_00020021_fill_pattern_1_1: 3940000 rects
-caravel_00020021_fill_pattern_1_1: 3950000 rects
-caravel_00020021_fill_pattern_1_1: 3960000 rects
-caravel_00020021_fill_pattern_1_1: 3970000 rects
-caravel_00020021_fill_pattern_1_1: 3980000 rects
-caravel_00020021_fill_pattern_1_1: 3990000 rects
-caravel_00020021_fill_pattern_1_1: 4000000 rects
-caravel_00020021_fill_pattern_1_1: 4010000 rects
-caravel_00020021_fill_pattern_1_1: 4020000 rects
-caravel_00020021_fill_pattern_1_1: 4030000 rects
-caravel_00020021_fill_pattern_1_1: 4040000 rects
-caravel_00020021_fill_pattern_1_1: 4050000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_1
-
 caravel_00020021_fill_pattern_0_0: 4920000 rects
 caravel_00020021_fill_pattern_0_0: 4930000 rects
 caravel_00020021_fill_pattern_0_0: 4940000 rects
@@ -9222,6 +9138,90 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_0
 
+caravel_00020021_fill_pattern_1_1: 3240000 rects
+caravel_00020021_fill_pattern_1_1: 3250000 rects
+caravel_00020021_fill_pattern_1_1: 3260000 rects
+caravel_00020021_fill_pattern_1_1: 3270000 rects
+caravel_00020021_fill_pattern_1_1: 3280000 rects
+caravel_00020021_fill_pattern_1_1: 3290000 rects
+caravel_00020021_fill_pattern_1_1: 3300000 rects
+caravel_00020021_fill_pattern_1_1: 3310000 rects
+caravel_00020021_fill_pattern_1_1: 3320000 rects
+caravel_00020021_fill_pattern_1_1: 3330000 rects
+caravel_00020021_fill_pattern_1_1: 3340000 rects
+caravel_00020021_fill_pattern_1_1: 3350000 rects
+caravel_00020021_fill_pattern_1_1: 3360000 rects
+caravel_00020021_fill_pattern_1_1: 3370000 rects
+caravel_00020021_fill_pattern_1_1: 3380000 rects
+caravel_00020021_fill_pattern_1_1: 3390000 rects
+caravel_00020021_fill_pattern_1_1: 3400000 rects
+caravel_00020021_fill_pattern_1_1: 3410000 rects
+caravel_00020021_fill_pattern_1_1: 3420000 rects
+caravel_00020021_fill_pattern_1_1: 3430000 rects
+caravel_00020021_fill_pattern_1_1: 3440000 rects
+caravel_00020021_fill_pattern_1_1: 3450000 rects
+caravel_00020021_fill_pattern_1_1: 3460000 rects
+caravel_00020021_fill_pattern_1_1: 3470000 rects
+caravel_00020021_fill_pattern_1_1: 3480000 rects
+caravel_00020021_fill_pattern_1_1: 3490000 rects
+caravel_00020021_fill_pattern_1_1: 3500000 rects
+caravel_00020021_fill_pattern_1_1: 3510000 rects
+caravel_00020021_fill_pattern_1_1: 3520000 rects
+caravel_00020021_fill_pattern_1_1: 3530000 rects
+caravel_00020021_fill_pattern_1_1: 3540000 rects
+caravel_00020021_fill_pattern_1_1: 3550000 rects
+caravel_00020021_fill_pattern_1_1: 3560000 rects
+caravel_00020021_fill_pattern_1_1: 3570000 rects
+caravel_00020021_fill_pattern_1_1: 3580000 rects
+caravel_00020021_fill_pattern_1_1: 3590000 rects
+caravel_00020021_fill_pattern_1_1: 3600000 rects
+caravel_00020021_fill_pattern_1_1: 3610000 rects
+caravel_00020021_fill_pattern_1_1: 3620000 rects
+caravel_00020021_fill_pattern_1_1: 3630000 rects
+caravel_00020021_fill_pattern_1_1: 3640000 rects
+caravel_00020021_fill_pattern_1_1: 3650000 rects
+caravel_00020021_fill_pattern_1_1: 3660000 rects
+caravel_00020021_fill_pattern_1_1: 3670000 rects
+caravel_00020021_fill_pattern_1_1: 3680000 rects
+caravel_00020021_fill_pattern_1_1: 3690000 rects
+caravel_00020021_fill_pattern_1_1: 3700000 rects
+caravel_00020021_fill_pattern_1_1: 3710000 rects
+caravel_00020021_fill_pattern_1_1: 3720000 rects
+caravel_00020021_fill_pattern_1_1: 3730000 rects
+caravel_00020021_fill_pattern_1_1: 3740000 rects
+caravel_00020021_fill_pattern_1_1: 3750000 rects
+caravel_00020021_fill_pattern_1_1: 3760000 rects
+caravel_00020021_fill_pattern_1_1: 3770000 rects
+caravel_00020021_fill_pattern_1_1: 3780000 rects
+caravel_00020021_fill_pattern_1_1: 3790000 rects
+caravel_00020021_fill_pattern_1_1: 3800000 rects
+caravel_00020021_fill_pattern_1_1: 3810000 rects
+caravel_00020021_fill_pattern_1_1: 3820000 rects
+caravel_00020021_fill_pattern_1_1: 3830000 rects
+caravel_00020021_fill_pattern_1_1: 3840000 rects
+caravel_00020021_fill_pattern_1_1: 3850000 rects
+caravel_00020021_fill_pattern_1_1: 3860000 rects
+caravel_00020021_fill_pattern_1_1: 3870000 rects
+caravel_00020021_fill_pattern_1_1: 3880000 rects
+caravel_00020021_fill_pattern_1_1: 3890000 rects
+caravel_00020021_fill_pattern_1_1: 3900000 rects
+caravel_00020021_fill_pattern_1_1: 3910000 rects
+caravel_00020021_fill_pattern_1_1: 3920000 rects
+caravel_00020021_fill_pattern_1_1: 3930000 rects
+caravel_00020021_fill_pattern_1_1: 3940000 rects
+caravel_00020021_fill_pattern_1_1: 3950000 rects
+caravel_00020021_fill_pattern_1_1: 3960000 rects
+caravel_00020021_fill_pattern_1_1: 3970000 rects
+caravel_00020021_fill_pattern_1_1: 3980000 rects
+caravel_00020021_fill_pattern_1_1: 3990000 rects
+caravel_00020021_fill_pattern_1_1: 4000000 rects
+caravel_00020021_fill_pattern_1_1: 4010000 rects
+caravel_00020021_fill_pattern_1_1: 4020000 rects
+caravel_00020021_fill_pattern_1_1: 4030000 rects
+caravel_00020021_fill_pattern_1_1: 4040000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_1_1
+
 caravel_00020021_fill_pattern_3_1: 3240000 rects
 caravel_00020021_fill_pattern_3_1: 3250000 rects
 caravel_00020021_fill_pattern_3_1: 3260000 rects
diff --git a/signoff/build/gpio_defaults.out b/signoff/build/gpio_defaults.out
index 689cfdd..e8cf007 100644
--- a/signoff/build/gpio_defaults.out
+++ b/signoff/build/gpio_defaults.out
@@ -1,69 +1,69 @@
 Step 1:  Create new cells for new GPIO default vectors.
-Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
 Step 2:  Modify top-level layouts to use the specified defaults.
 Done.
diff --git a/signoff/build/make_truck.out b/signoff/build/make_truck.out
index 186a07c..bd7e59e 100644
--- a/signoff/build/make_truck.out
+++ b/signoff/build/make_truck.out
@@ -20,6 +20,7 @@
 caravan: 30000 rects
 caravan: 40000 rects
 caravan: 50000 rects
+Processing timestamp mismatches: gpio_defaults_block_0403, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_6.
 Warning:  Parent cell lists instance of "xres_buf" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/xres_buf.mag.
 The cell exists in the search paths at ../mag/xres_buf.mag.
 The discovered version will be used.
@@ -795,8 +796,8 @@
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbn_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbn_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbn_1.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_1" at bad file path ../mag/sky130_fd_sc_hd__ebufn_1.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_1.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "mgmt_protect" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/mgmt_protect.mag.
 The cell exists in the search paths at ../mag/mgmt_protect.mag.
@@ -817,12 +818,11 @@
 mgmt_protect: 140000 rects
 mgmt_protect: 150000 rects
 mgmt_protect: 160000 rects
-mgmt_protect: 170000 rects
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_4" at bad file path ../mag/sky130_fd_sc_hd__einvp_4.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_4.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2b_2" at bad file path ../mag/sky130_fd_sc_hd__and2b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_2.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_16" at bad file path ../mag/sky130_fd_sc_hd__clkinv_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_16.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_4" at bad file path ../mag/sky130_fd_sc_hd__and2_4.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag.
@@ -830,15 +830,15 @@
 Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__conb_1" at bad file path ../mag/sky130_fd_sc_hvl__conb_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__conb_1.mag.
 The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_16" at bad file path ../mag/sky130_fd_sc_hd__inv_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_16.mag.
+The discovered version will be used.
 Warning:  Parent cell lists instance of "spare_logic_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/spare_logic_block.mag.
 The cell exists in the search paths at ../mag/spare_logic_block.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbp_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbp_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbp_1.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "gpio_defaults_block_0403" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag.
-The cell exists in the search paths at ../mag/gpio_defaults_block_0403.mag.
-The discovered version will be used.
 Warning:  Parent cell lists instance of "chip_io_alt" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/chip_io_alt.mag.
 The cell exists in the search paths at ../mag/chip_io_alt.mag.
 The discovered version will be used.
@@ -1280,7 +1280,7 @@
 Warning:  Parent cell lists instance of "caravan_power_routing" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/caravan_power_routing.mag.
 The cell exists in the search paths at ../mag/caravan_power_routing.mag.
 The discovered version will be used.
-Processing timestamp mismatches: sky130_ef_io__top_power_hvc, sky130_ef_io__analog_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, chip_io_alt, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__einvp_4, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__ebufn_1, sky130_fd_sc_hd__dfbbn_1, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__ebufn_8, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_1, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8.
+Processing timestamp mismatches: sky130_ef_io__top_power_hvc, sky130_ef_io__analog_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, chip_io_alt, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, sky130_fd_sc_hd__inv_16, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__clkinv_16, sky130_fd_sc_hd__and2b_2, mgmt_protect, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__dfbbn_1, gpio_control_block, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__ebufn_8, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_2, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_1, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8.
    Generating output for cell sky130_fd_sc_hvl__decap_8
    Generating output for cell sky130_fd_sc_hvl__diode_2
    Generating output for cell sky130_fd_sc_hvl__decap_4
@@ -1360,35 +1360,35 @@
    Generating output for cell sky130_fd_sc_hd__o2bb2ai_2
    Generating output for cell sky130_fd_sc_hd__dfrtp_2
    Generating output for cell sky130_fd_sc_hd__mux2_1
-   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
-   Generating output for cell sky130_fd_sc_hd__buf_1
    Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__buf_1
    Generating output for cell sky130_fd_sc_hd__or2b_1
+   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
    Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
    Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
    Generating output for cell sky130_fd_sc_hd__clkinv_2
    Generating output for cell sky130_fd_sc_hd__clkinv_4
-   Generating output for cell sky130_fd_sc_hd__buf_12
-   Generating output for cell sky130_fd_sc_hd__clkbuf_16
-   Generating output for cell sky130_fd_sc_hd__clkbuf_2
-   Generating output for cell sky130_fd_sc_hd__nand2_1
    Generating output for cell sky130_fd_sc_hd__and2_1
-   Generating output for cell sky130_fd_sc_hd__clkbuf_1
-   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__nand2_1
    Generating output for cell sky130_fd_sc_hd__diode_2
    Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
    Generating output for cell sky130_fd_sc_hd__mux2_2
    Generating output for cell sky130_fd_sc_hd__decap_8
-   Generating output for cell sky130_fd_sc_hd__nand2_2
-   Generating output for cell sky130_fd_sc_hd__inv_2
-   Generating output for cell sky130_fd_sc_hd__decap_6
-   Generating output for cell sky130_fd_sc_hd__conb_1
    Generating output for cell sky130_fd_sc_hd__fill_2
-   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__conb_1
    Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__decap_4
    Generating output for cell sky130_fd_sc_hd__decap_3
    Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
-   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__inv_2
    Generating output for cell caravel_clocking
    Generating output for cell sky130_fd_sc_hd__o2111ai_2
    Generating output for cell sky130_fd_sc_hd__and4_2
@@ -1410,6 +1410,7 @@
    Generating output for cell sky130_fd_sc_hd__or3_2
    Generating output for cell sky130_fd_sc_hd__or2_2
    Generating output for cell sky130_fd_sc_hd__o311a_2
+   Generating output for cell sky130_fd_sc_hd__einvp_2
    Generating output for cell sky130_fd_sc_hd__clkinv_1
    Generating output for cell sky130_fd_sc_hd__einvn_8
    Generating output for cell sky130_fd_sc_hd__einvn_4
@@ -1423,11 +1424,16 @@
    Generating output for cell sky130_fd_sc_hd__a311o_2
    Generating output for cell sky130_fd_sc_hd__a21oi_2
    Generating output for cell sky130_fd_sc_hd__a22oi_2
-   Generating output for cell sky130_fd_sc_hd__einvp_2
    Generating output for cell sky130_fd_sc_hd__clkinv_8
    Generating output for cell sky130_fd_sc_hd__nor2_2
    Generating output for cell digital_pll
    Generating output for cell sky130_fd_sc_hd__ebufn_8
+   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__dfbbn_1
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
    Generating output for cell sky130_fd_sc_hd__a221o_1
    Generating output for cell sky130_fd_sc_hd__or4bb_1
    Generating output for cell sky130_fd_sc_hd__or4b_1
@@ -1465,7 +1471,6 @@
    Generating output for cell sky130_fd_sc_hd__a32o_1
    Generating output for cell sky130_fd_sc_hd__ebufn_2
    Generating output for cell sky130_fd_sc_hd__or3b_2
-   Generating output for cell sky130_fd_sc_hd__clkbuf_8
    Generating output for cell sky130_fd_sc_hd__a22oi_1
    Generating output for cell sky130_fd_sc_hd__mux2_4
    Generating output for cell sky130_fd_sc_hd__a41o_1
@@ -1504,15 +1509,14 @@
    Generating output for cell sky130_fd_sc_hd__o21ai_4
    Generating output for cell sky130_fd_sc_hd__nor2_8
    Generating output for cell sky130_fd_sc_hd__a31oi_1
-   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
    Generating output for cell sky130_fd_sc_hd__inv_12
    Generating output for cell sky130_fd_sc_hd__and2b_1
    Generating output for cell sky130_fd_sc_hd__buf_8
-   Generating output for cell sky130_fd_sc_hd__buf_6
    Generating output for cell sky130_fd_sc_hd__nand2_8
    Generating output for cell sky130_fd_sc_hd__nand2_4
-   Generating output for cell sky130_fd_sc_hd__inv_6
    Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
    Generating output for cell sky130_fd_sc_hd__inv_8
    Generating output for cell housekeeping
    Generating output for cell user_id_programming
@@ -1527,10 +1531,6 @@
 Reading "sky130_fd_sc_hd__decap_12".
 Reading "user_id_programming".
    Generating output for cell gpio_defaults_block_1803
-   Generating output for cell sky130_fd_sc_hd__dfbbn_1
-   Generating output for cell sky130_fd_sc_hd__ebufn_1
-   Generating output for cell gpio_logic_high
-   Generating output for cell gpio_control_block
    Generating output for cell simple_por
 Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
@@ -1930,10 +1930,10 @@
 Reading "sky130_fd_sc_hd__o211a_4".
 Reading "mgmt_core".
 Reading "mgmt_core_wrapper".
-   Generating output for cell gpio_defaults_block_1800
-   Generating output for cell sky130_fd_sc_hd__einvp_4
-   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell sky130_fd_sc_hd__and2b_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_16
    Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hd__inv_16
    Generating output for cell sky130_fd_sc_hvl__conb_1
    Generating output for cell mgmt_protect_hv
    Generating output for cell mprj_logic_high
diff --git a/signoff/caravel_layout.png b/signoff/caravel_layout.png
new file mode 100644
index 0000000..79d9902
--- /dev/null
+++ b/signoff/caravel_layout.png
Binary files differ
diff --git a/signoff/cdrc.log b/signoff/cdrc.log
index 34a1502..51aef24 100644
--- a/signoff/cdrc.log
+++ b/signoff/cdrc.log
@@ -1,2 +1,2 @@
-caldrc-put: caravel_00020021.oas 744d9b95f2636bd62bb805796679d0b19bc9d9a9 2021-12-07.05:26:39.UTC md5=5854ca93f567a790a6cff9da4216aacc /mnt/shuttles/mpw-two/slot-033/digital_pll/gds/caravel_00020021.oas [no-git-push]
-caldrc-post: caravel_00020021.gds put=744d9b95 2021-12-07.06:49:27.UTC md5=(no-gds-file) output2295_pdk87-g445b81c13_drc2208-gf4ea9309_prj2201-g744d9b95_caravel_00020021
+caldrc-put: caravel_00020021.oas 7490772bd47d9f7412a97ef2f1a6425fefb0e8a1 2021-12-10.17:02:09.UTC md5=71adb565dd475f6bbe5caa256284bde2 /mnt/shuttles/mpw-two/slot-033/digital_pll/gds/caravel_00020021.oas [no-git-push]
+caldrc-post: caravel_00020021.gds put=7490772b 2021-12-10.19:16:27.UTC md5=(no-gds-file) output2437_pdk87-g445b81c13_drc2350-geb07bf26_prj2343-g7490772b_caravel_00020021
diff --git a/signoff/cdrcpost/caravel_00020021/caravel_00020021.drcmr_runset.log b/signoff/cdrcpost/caravel_00020021/caravel_00020021.drcmr_runset.log
index 613beb6..2344205 100644
--- a/signoff/cdrcpost/caravel_00020021/caravel_00020021.drcmr_runset.log
+++ b/signoff/cdrcpost/caravel_00020021/caravel_00020021.drcmr_runset.log
@@ -14,7 +14,7 @@
 //  Running on Linux tansell-u.c.googlers.com 5.10.46-5rodete1-amd64 #1 SMP Debian 5.10.46-5rodete1 (2021-09-28) x86_64
 //  64 bit virtual addressing enabled
 //
-//  Starting time: Tue Dec  7 01:34:13 2021
+//  Starting time: Fri ... XX XX:XX:XX 2...
 //
 //  calinteractive license acquired.
 //  Calibre Interactive authorized.
@@ -43,43 +43,43 @@
 //  Entries in /proc/meminfo:
 //
 //  MemTotal:       131922156 kB
-//  MemFree:        91136796 kB
-//  MemAvailable:   127254836 kB
-//  Buffers:         2896104 kB
-//  Cached:         30020728 kB
+//  MemFree:        86654120 kB
+//  MemAvailable:   127402044 kB
+//  Buffers:         2908136 kB
+//  Cached:         34403044 kB
 //  SwapCached:            0 kB
-//  Active:         15181192 kB
-//  Inactive:       20340520 kB
-//  Active(anon):        828 kB
-//  Inactive(anon):  2641016 kB
-//  Active(file):   15180364 kB
-//  Inactive(file): 17699504 kB
-//  Unevictable:       62552 kB
-//  Mlocked:           62552 kB
+//  Active:         17429260 kB
+//  Inactive:       22322804 kB
+//  Active(anon):        820 kB
+//  Inactive(anon):  2470280 kB
+//  Active(file):   17428440 kB
+//  Inactive(file): 19852524 kB
+//  Unevictable:       63668 kB
+//  Mlocked:           63668 kB
 //  SwapTotal:      70155256 kB
 //  SwapFree:       70155256 kB
-//  Dirty:             67368 kB
+//  Dirty:               960 kB
 //  Writeback:             0 kB
-//  AnonPages:       2488432 kB
-//  Mapped:           972912 kB
-//  Shmem:               848 kB
-//  KReclaimable:    4487464 kB
-//  Slab:            4828408 kB
-//  SReclaimable:    4487464 kB
-//  SUnreclaim:       340944 kB
-//  KernelStack:       35120 kB
-//  PageTables:        21912 kB
+//  AnonPages:       2339716 kB
+//  Mapped:           903820 kB
+//  Shmem:               856 kB
+//  KReclaimable:    4716252 kB
+//  Slab:            5080468 kB
+//  SReclaimable:    4716252 kB
+//  SUnreclaim:       364216 kB
+//  KernelStack:       35168 kB
+//  PageTables:        20756 kB
 //  NFS_Unstable:          0 kB
 //  Bounce:                0 kB
 //  WritebackTmp:          0 kB
 //  CommitLimit:    136116332 kB
-//  Committed_AS:    7826192 kB
+//  Committed_AS:    7604592 kB
 //  VmallocTotal:   34359738367 kB
-//  VmallocUsed:       72908 kB
+//  VmallocUsed:       73680 kB
 //  VmallocChunk:          0 kB
-//  Percpu:            66432 kB
+//  Percpu:            67584 kB
 //  HardwareCorrupted:     0 kB
-//  AnonHugePages:   1533952 kB
+//  AnonHugePages:   1480704 kB
 //  ShmemHugePages:        0 kB
 //  ShmemPmdMapped:        0 kB
 //  FileHugePages:         0 kB
@@ -90,9 +90,9 @@
 //  HugePages_Surp:        0
 //  Hugepagesize:       2048 kB
 //  Hugetlb:               0 kB
-//  DirectMap4k:     1116144 kB
-//  DirectMap2M:    39778304 kB
-//  DirectMap1G:    95420416 kB
+//  DirectMap4k:     1189872 kB
+//  DirectMap2M:    43898880 kB
+//  DirectMap1G:    91226112 kB
 //
 //  User limits:
 //
@@ -108,15 +108,15 @@
 //  Max file descriptors: 131072
 //  64 bit virtual addressing enabled
 //  Running aoj_cal_2018.4_34.26//pkgs/icv/pvt/calibre -drc -hier -nowait /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
-//  Process ID: 2663892
+//  Process ID: 3454441
 //
-//  Starting time: Tue Dec  7 01:34:17 2021
+//  Starting time: Fri ... XX XX:XX:XX 2...
 //
 //  Running on 1 CPU (pending licensing) 
 //
 //
 
---- CALIBRE::DRC-H - Tue Dec  7 01:34:17 2021
+--- CALIBRE::DRC-H - Fri ... XX XX:XX:XX 2...
 
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -127,7 +127,7 @@
 --- RULE FILE = /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 
 //
-//  Rule file generated on Tue Dec 07 01:34:16 EST 2021
+//  Rule file generated on Fri Dec 10 14:01:28 EST 2021
 //     by Calibre Interactive - DRC (v2018.4_34.26)
 //
 //      *** PLEASE DO NOT MODIFY THIS FILE ***
@@ -2280,181 +2280,198 @@
 DN_sky130_fd_io__corner_bus_overlay
                                          0        0       4050        0       64
 DN_sky130_fd_sc_hvl__conb_1              0        0         84        0       18
-DN_RO_sky130_fd_sc_hd__a211oi_2          0        0        104        2       21
-DN_RO_sky130_fd_sc_hd__o221ai_4          0        0        163        2       11
-DN_RO_sky130_fd_sc_hd__or2b_4            0        0         82        2        8
+DN_RO_sky130_fd_sc_hd__o211a_4           0        0        108        2       10
+DN_RO_sky130_fd_sc_hd__o41ai_2           0        0        135        2       18
+DN_RO_sky130_fd_sc_hd__o31ai_2           0        0        105        2       20
+DN_RO_sky130_fd_sc_hd__a21bo_2           0        0         75        2        9
+DN_RO_sky130_fd_sc_hd__o32ai_2           0        0        121        2       17
 DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8
                                         12        8      22897        0      131
-DN_RO_sky130_fd_sc_hd__o22ai_4           0        0        126        2       10
-DN_RO_sky130_fd_sc_hd__o22a_4            0        0        117        2       10
-DN_RO_sky130_fd_sc_hd__o2bb2ai_2         0        0        103        2       10
-DN_RO_sky130_fd_sc_hd__a21boi_4          0        0        114        2        9
-DN_RO_sky130_fd_sc_hd__o21a_2            0        0         67        2        9
-DN_RO_sky130_fd_sc_hd__xnor2_2           0        0        107        2        8
-DN_RO_sky130_fd_sc_hd__nand3b_2          0        0         84        2       11
-DN_RO_sky130_fd_sc_hd__nor3_4            0        0        112        2        9
-DN_RO_sky130_fd_sc_hd__a2111oi_2         0        0         99        2       11
-DN_RO_sky130_fd_sc_hd__a2111oi_1         0        0         86        2       27
-DN_RO_sky130_fd_sc_hd__a2111o_2          0        0        103        2       26
-DN_RO_sky130_fd_sc_hd__o31ai_4           0        0        165        2       34
-DN_RO_sky130_fd_sc_hd__o21bai_2          0        0         87        2        9
-DN_RO_sky130_fd_sc_hd__a211o_4           0        0        108        2       10
-DN_RO_sky130_fd_sc_hd__o31ai_2           0        0        105        2       20
-DN_RO_sky130_fd_sc_hd__xor2_2            0        0        110        2        8
-DN_RO_sky130_fd_sc_hd__a311o_2           0        0         87        2       16
 DN_RO_sky130_fd_sc_hd__a31o_4            0        0        114        2       16
-DN_RO_sky130_fd_sc_hd__a21oi_2           0        0         70        2       10
-DN_RO_sky130_fd_sc_hd__o41a_2            0        0        107        2       23
-DN_RO_sky130_fd_sc_hd__o31a_2            0        0         83        2       18
-DN_RO_sky130_fd_sc_hd__o221a_2           0        0         89        3       13
-DN_RO_sky130_fd_sc_hd__o2111a_4          0        0        131        2       13
-DN_RO_sky130_fd_sc_hd__o221a_4           0        0        131        2       11
+DN_RO_sky130_fd_sc_hd__o221ai_2          0        0        106        2       11
+DN_RO_sky130_fd_sc_hd__or2b_2            0        0         65        2        8
+DN_RO_sky130_fd_sc_hd__o32ai_4           0        0        192        2       23
+DN_RO_sky130_fd_sc_hd__and3b_2           0        0         77        0       11
+DN_RO_sky130_fd_sc_hd__a32o_4            0        0        141        2       23
+DN_RO_sky130_fd_sc_hd__or4b_1            0        0         81        2       17
+DN_RO_sky130_fd_sc_hd__a21o_4            0        0         99        2        9
+DN_RO_sky130_fd_sc_hd__o311a_1           0        0         89        2       20
+DN_RO_sky130_fd_sc_hd__a32oi_4           0        0        190        0       33
+DN_RO_sky130_fd_sc_hd__a22o_4            0        0        117        2       10
+DN_RO_sky130_fd_sc_hd__or3_4             0        0         85        2       10
+DN_RO_sky130_fd_sc_hd__dlymetal6s4s_1
+                                         0        0         89        2       15
+DN_RO_sky130_fd_sc_hd__a2bb2oi_2         0        0        109        2       10
+DN_RO_sky130_fd_sc_hd__a2bb2oi_4         0        0        175        2       10
 DN_RO_sky130_fd_sc_hd__o2111a_2          0        0        101        2       14
-DN_RO_sky130_fd_sc_hd__a22oi_1           0        0         65        2       13
+DN_RO_sky130_fd_sc_hd__nand2b_1          0        0         51        2       12
+DN_RO_sky130_fd_sc_hd__and4b_1           0        0         84        2       21
+DN_RO_sky130_fd_sc_hd__o22a_2            0        0         81        2       10
+DN_RO_sky130_fd_sc_hd__o2bb2ai_4         0        0        185        2       10
+DN_RO_sky130_fd_sc_hd__o2bb2ai_2         0        0        103        2       10
+DN_RO_sky130_fd_sc_hd__and2b_4           0        0         65        2        8
+DN_RO_sky130_fd_sc_hd__a311oi_4          0        0        179        2       31
+DN_RO_sky130_fd_sc_hd__o21ba_2           0        0         75        2        9
+DN_RO_sky130_fd_sc_hd__o31a_4            0        0        128        2       23
+DN_RO_sky130_fd_sc_hd__or3_2             0        0         63        2       12
+DN_RO_sky130_fd_sc_hd__o41ai_4           0        0        213        2       31
+DN_RO_sky130_fd_sc_hd__o311a_2           0        0         97        2       21
+DN_RO_sky130_fd_sc_hd__a31oi_2           0        0        104        2       23
+DN_RO_sky130_fd_sc_hd__a311oi_2          0        0        121        2       21
+DN_RO_sky130_fd_sc_hd__o31ai_4           0        0        165        2       34
+DN_RO_sky130_fd_sc_hd__o311ai_2          0        0        122        2       22
+DN_RO_sky130_fd_sc_hd__o211ai_2          0        0         90        2       10
+DN_RO_sky130_fd_sc_hd__a221oi_1          0        0         77        2       15
 DN_RO_sky130_fd_sc_hd__a221oi_2          0        0        111        2       13
 DN_RO_sky130_fd_sc_hd__o22ai_2           0        0         98        2       10
-DN_RO_sky130_fd_sc_hd__xor2_4            0        0        174        2        8
-DN_RO_sky130_fd_sc_hd__xnor2_4           0        0        175        2        8
-DN_RO_sky130_fd_sc_hd__or2b_2            0        0         65        2        8
-DN_RO_sky130_fd_sc_hd__nand2b_4          0        0        110        2       13
-DN_RO_sky130_fd_sc_hd__o21bai_4          0        0        135        2        9
-DN_RO_sky130_fd_sc_hd__a32oi_4           0        0        190        0       33
-DN_RO_sky130_fd_sc_hd__o32ai_1           0        0         78        2       18
-DN_RO_sky130_fd_sc_hd__o211a_4           0        0        108        2       10
-DN_RO_sky130_fd_sc_hd__o21a_4            0        0         96        2        9
-DN_RO_sky130_fd_sc_hd__o41a_1            0        0         95        2       22
-DN_RO_sky130_fd_sc_hd__a31o_2            0        0         73        2       15
-DN_RO_sky130_fd_sc_hd__a221o_2           0        0         91        2       16
-DN_RO_sky130_fd_sc_hd__a211o_2           0        0         83        2       10
-DN_RO_sky130_fd_sc_hd__a22o_2            0        0         81        2       13
-DN_RO_sky130_fd_sc_hd__nor2b_4           0        0        106        2        8
-DN_RO_sky130_fd_sc_hd__o2111ai_1         0        0         75        2       11
-DN_RO_sky130_fd_sc_hd__or4b_1            0        0         81        2       17
-DN_RO_sky130_fd_sc_hd__a2bb2oi_4         0        0        175        2       10
-DN_RO_sky130_fd_sc_hd__a2111o_4          0        0        147        2       19
-DN_RO_sky130_fd_sc_hd__or3b_2            0        0         65        2        9
-DN_RO_sky130_fd_sc_hd__a22oi_4           0        0        150        2       10
-DN_RO_sky130_fd_sc_hd__a21bo_1           0        0         88        2       19
+DN_RO_sky130_fd_sc_hd__or3_1             0        0         56        2       12
 DN_RO_sky130_fd_sc_hd__and2_4            0        0         68        2        8
-DN_RO_sky130_fd_sc_hd__a22oi_2           0        0        100        2       19
-DN_RO_sky130_fd_sc_hd__or2_4             0        0         68        2        8
-DN_RO_sky130_fd_sc_hd__mux4_2            0        0        159        2       20
-DN_RO_sky130_fd_sc_hd__o21ba_4           0        0        109        2        9
-DN_RO_sky130_fd_sc_hd__or3_4             0        0         85        2       10
-DN_RO_sky130_fd_sc_hd__o2bb2ai_1         0        0         76        2       10
-DN_RO_sky130_fd_sc_hd__a41oi_4           0        0        194        0       33
-DN_RO_sky130_fd_sc_hd__a32o_1            0        0         85        2       20
-DN_RO_sky130_fd_sc_hd__o22ai_1           0        0         57        2       10
-DN_RO_sky130_fd_sc_hd__o2111ai_4         0        0        176        2       28
-DN_RO_sky130_fd_sc_hd__xor2_1            0        0         65        2        8
-DN_RO_sky130_fd_sc_hd__a22o_4            0        0        117        2       10
-DN_RO_sky130_fd_sc_hd__o21ai_4           0        0         97        2        9
-DN_RO_sky130_fd_sc_hd__nor3b_1           0        0         56        2        9
-DN_RO_sky130_fd_sc_hd__o2111a_1          0        0        101        2       19
-DN_RO_sky130_fd_sc_hd__o2111ai_2         0        0        114        2       17
-DN_RO_sky130_fd_sc_hd__a31oi_4           0        0        148        2       27
-DN_RO_sky130_fd_sc_hd__a311o_1           0        0         76        2       14
-DN_RO_sky130_fd_sc_hd__o211ai_4          0        0        120        2       10
-DN_RO_sky130_fd_sc_hd__o211ai_1          0        0         67        2       10
-DN_RO_sky130_fd_sc_hd__a211oi_1          0        0         72        2       24
-DN_RO_sky130_fd_sc_hd__or3b_4            0        0         74        2        9
-DN_RO_sky130_fd_sc_hd__nand2b_1          0        0         51        2       12
-DN_RO_sky130_fd_sc_hd__a311oi_1          0        0         70        2       15
-DN_RO_sky130_fd_sc_hd__a221oi_1          0        0         77        2       15
-DN_RO_sky130_fd_sc_hd__o31a_4            0        0        128        2       23
-DN_RO_sky130_fd_sc_hd__and4b_1           0        0         84        2       21
+DN_RO_sky130_fd_sc_hd__o221a_1           0        0         88        2       13
+DN_RO_sky130_fd_sc_hd__o221a_2           0        0         89        3       13
+DN_RO_sky130_fd_sc_hd__and3_2            0        0         65        0       13
+DN_RO_sky130_fd_sc_hd__a22oi_1           0        0         65        2       13
+DN_RO_sky130_fd_sc_hd__o41a_1            0        0         95        2       22
 DN_RO_sky130_fd_sc_hd__o32a_1            0        0         82        2       17
 DN_RO_sky130_fd_sc_hd__o221ai_1          0        0         78        3       12
-DN_RO_sky130_fd_sc_hd__o22a_2            0        0         81        2       10
-DN_RO_sky130_fd_sc_hd__xnor2_1           0        0         63        2        8
-DN_RO_sky130_fd_sc_hd__o221ai_2          0        0        106        2       11
-DN_RO_sky130_fd_sc_hd__a2bb2o_1          0        0         79        2       17
-DN_RO_sky130_fd_sc_hd__a2111o_1          0        0         98        2       27
-DN_RO_sky130_fd_sc_hd__and4_4            0        0         87        2       12
-DN_RO_sky130_fd_sc_hd__o31ai_1           0        0         72        2       19
-DN_RO_sky130_fd_sc_hd__a31oi_1           0        0         61        2       13
-DN_RO_sky130_fd_sc_hd__o311a_1           0        0         89        2       20
-DN_RO_sky130_fd_sc_hd__clkbuf_8          0        0         86        4       13
-DN_RO_sky130_fd_sc_hd__a31o_1            0        0         76        2       16
-DN_RO_sky130_fd_sc_hd__a31oi_2           0        0        104        2       23
-DN_RO_sky130_fd_sc_hd__a221o_4           0        0        148        2       13
-DN_RO_sky130_fd_sc_hd__a2111oi_4         0        0        172        2       11
-DN_RO_sky130_fd_sc_hd__nor3_2            0        0         82        2        9
+DN_RO_sky130_fd_sc_hd__xor2_2            0        0        110        2        8
 DN_RO_sky130_fd_sc_hd__a41o_1            0        0         90        2       22
-DN_RO_sky130_fd_sc_hd__nand3b_1          0        0         64        2       14
-DN_RO_sky130_fd_sc_hd__o31a_1            0        0         75        2       17
-DN_RO_sky130_fd_sc_hd__and2b_1           0        0         61        2       13
-DN_RO_sky130_fd_sc_hd__a21boi_2          0        0         80        2        9
-DN_RO_sky130_fd_sc_hd__a211o_1           0        0         75        2       15
-DN_RO_sky130_fd_sc_hd__nand3_1           0        0         53        2        9
-DN_RO_sky130_fd_sc_hd__and3_2            0        0         65        0       13
-DN_RO_sky130_fd_sc_hd__mux2_4            0        0         99        2       12
-DN_RO_sky130_fd_sc_hd__and4_1            0        0         72        2       18
-DN_RO_sky130_fd_sc_hd__or4_2             0        0         73        2       16
-DN_RO_sky130_fd_sc_hd__or3_2             0        0         63        2       12
-DN_RO_sky130_fd_sc_hd__nand3_2           0        0         87        2       15
-DN_RO_sky130_fd_sc_hd__or4_4             0        0         85        2       12
-DN_RO_sky130_fd_sc_hd__o2bb2a_1          0        0         73        2       10
-DN_RO_sky130_fd_sc_hd__a21boi_1          0        0         71        2       16
-DN_RO_sky130_fd_sc_hd__or3b_1            0        0         70        2       13
-DN_RO_sky130_fd_sc_hd__o2bb2a_2          0        0         82        2       10
-DN_RO_sky130_fd_sc_hd__o22a_1            0        0         74        2       10
-DN_RO_sky130_fd_sc_hd__nand3_4           0        0        133        2       20
-DN_RO_sky130_fd_sc_hd__or2b_1            0        0         58        2        8
+DN_RO_sky130_fd_sc_hd__o32ai_1           0        0         78        2       18
+DN_RO_sky130_fd_sc_hd__or4_1             0        0         66        2       16
+DN_RO_sky130_fd_sc_hd__a21boi_4          0        0        114        2        9
+DN_RO_sky130_fd_sc_hd__inv_8             0        0         86        2       13
+DN_RO_sky130_fd_sc_hd__a32oi_1           0        0         70        2       13
+DN_RO_sky130_fd_sc_hd__o2bb2ai_1         0        0         76        2       10
+DN_RO_sky130_fd_sc_hd__o22ai_1           0        0         57        2       10
+DN_RO_sky130_fd_sc_hd__or2_2             0        0         51        2        8
+DN_RO_sky130_fd_sc_hd__o2111ai_4         0        0        176        2       28
+DN_RO_sky130_fd_sc_hd__and4b_4           0        0         87        2       16
+DN_RO_sky130_fd_sc_hd__o21a_4            0        0         96        2        9
+DN_RO_sky130_fd_sc_hd__or2b_4            0        0         82        2        8
+DN_RO_sky130_fd_sc_hd__mux4_2            0        0        159        2       20
+DN_RO_sky130_fd_sc_hd__a2111oi_4         0        0        172        2       11
+DN_RO_sky130_fd_sc_hd__o311ai_4          0        0        183        2       30
+DN_RO_sky130_fd_sc_hd__a211oi_4          0        0        126        2       10
+DN_RO_sky130_fd_sc_hd__a2111oi_1         0        0         86        2       27
 DN_RO_sky130_fd_sc_hd__o21ai_2           0        0         75        2       14
-DN_RO_sky130_fd_sc_hd__and3b_1           0        0         73        2       12
-DN_RO_sky130_fd_sc_hd__clkinv_2          0        0         48        2       11
-DN_RO_sky130_fd_sc_hd__o221a_1           0        0         88        2       13
-DN_RO_sky130_fd_sc_hd__o21ba_1           0        0         76        2        9
-DN_RO_sky130_fd_sc_hd__o21ai_1           0        0         54        2       13
-DN_RO_sky130_fd_sc_hd__mux2_2            0        0         80        2       16
-DN_RO_sky130_fd_sc_hd__inv_16            0        0        135        2       11
-DN_RO_sky130_fd_sc_hd__mux2_8            0        0        154        2        9
+DN_RO_sky130_fd_sc_hd__or4_4             0        0         85        2       12
+DN_RO_sky130_fd_sc_hd__a2111o_4          0        0        147        2       19
+DN_RO_sky130_fd_sc_hd__a311oi_1          0        0         70        2       15
+DN_RO_sky130_fd_sc_hd__a32o_1            0        0         85        2       20
+DN_RO_sky130_fd_sc_hd__o2111ai_1         0        0         75        2       11
+DN_RO_sky130_fd_sc_hd__o2111ai_2         0        0        114        2       17
+DN_RO_sky130_fd_sc_hd__o21ba_4           0        0        109        2        9
+DN_RO_sky130_fd_sc_hd__o211ai_4          0        0        120        2       10
+DN_RO_sky130_fd_sc_hd__clkinv_16         0        0        153        2        7
+DN_RO_sky130_fd_sc_hd__or3b_4            0        0         74        2        9
+DN_RO_sky130_fd_sc_hd__a41oi_2           0        0        122        2       17
+DN_RO_sky130_fd_sc_hd__o311ai_1          0        0         79        2       20
 DN_RO_sky130_fd_sc_hd__nor2_4            0        0         86        2        8
+DN_RO_sky130_fd_sc_hd__a21boi_2          0        0         80        2        9
+DN_RO_sky130_fd_sc_hd__nand3b_2          0        0         84        2       11
+DN_RO_sky130_fd_sc_hd__a31oi_4           0        0        148        2       27
+DN_RO_sky130_fd_sc_hd__a2bb2oi_1         0        0         79        2       18
+DN_RO_sky130_fd_sc_hd__clkinv_4          0        0         65        2       13
+DN_RO_sky130_fd_sc_hd__a211oi_2          0        0        104        2       21
+DN_RO_sky130_fd_sc_hd__or4_2             0        0         73        2       16
+DN_RO_sky130_fd_sc_hd__nor2b_4           0        0        106        2        8
+DN_RO_sky130_fd_sc_hd__a221oi_4          0        0        162        2       11
+DN_RO_sky130_fd_sc_hd__a32oi_2           0        0        128        2       27
+DN_RO_sky130_fd_sc_hd__nor2_8            0        0        138        2        8
+DN_RO_sky130_fd_sc_hd__nand2_2           0        0         60        2       10
+DN_RO_sky130_fd_sc_hd__o41a_2            0        0        107        2       23
+DN_RO_sky130_fd_sc_hd__a22oi_2           0        0        100        2       19
+DN_RO_sky130_fd_sc_hd__and4_4            0        0         87        2       12
+DN_RO_sky130_fd_sc_hd__a31o_1            0        0         76        2       16
+DN_RO_sky130_fd_sc_hd__o22a_1            0        0         74        2       10
+DN_RO_sky130_fd_sc_hd__o2111a_4          0        0        131        2       13
+DN_RO_sky130_fd_sc_hd__a22oi_4           0        0        150        2       10
+DN_RO_sky130_fd_sc_hd__a311o_1           0        0         76        2       14
+DN_RO_sky130_fd_sc_hd__a211o_1           0        0         75        2       15
+DN_RO_sky130_fd_sc_hd__o21bai_4          0        0        135        2        9
+DN_RO_sky130_fd_sc_hd__a21o_2            0        0         66        2       10
+DN_RO_sky130_fd_sc_hd__a21oi_2           0        0         70        2       10
+DN_RO_sky130_fd_sc_hd__mux2_4            0        0         99        2       12
+DN_RO_sky130_fd_sc_hd__mux2_8            0        0        154        2        9
+DN_RO_sky130_fd_sc_hd__o31a_1            0        0         75        2       17
+DN_RO_sky130_fd_sc_hd__o211a_2           0        0         76        2       10
+DN_RO_sky130_fd_sc_hd__nor2b_2           0        0         73        2        8
+DN_RO_sky130_fd_sc_hd__xor2_1            0        0         65        2        8
 DN_RO_sky130_fd_sc_hd__nand2_8           0        0        145        2       18
+DN_RO_sky130_fd_sc_hd__xnor2_1           0        0         63        2        8
+DN_RO_sky130_fd_sc_hd__nand2_4           0        0         90        2       13
+DN_RO_sky130_fd_sc_hd__or3b_1            0        0         70        2       13
+DN_RO_sky130_fd_sc_hd__xnor2_2           0        0        107        2        8
+DN_RO_sky130_fd_sc_hd__a41oi_4           0        0        194        0       33
+DN_RO_sky130_fd_sc_hd__clkbuf_8          0        0         86        4       13
+DN_RO_sky130_fd_sc_hd__xnor2_4           0        0        175        2        8
+DN_RO_sky130_fd_sc_hd__o21bai_2          0        0         87        2        9
+DN_RO_sky130_fd_sc_hd__o41ai_1           0        0         83        2       21
+DN_RO_sky130_fd_sc_hd__nor3_2            0        0         82        2        9
+DN_RO_sky130_fd_sc_hd__a41oi_1           0        0         77        2       19
+DN_RO_sky130_fd_sc_hd__o21ba_1           0        0         76        2        9
+DN_RO_sky130_fd_sc_hd__nand3_2           0        0         87        2       15
+DN_RO_sky130_fd_sc_hd__xor2_4            0        0        174        2        8
+DN_RO_sky130_fd_sc_hd__nor2_1            0        0         43        2        8
+DN_RO_sky130_fd_sc_hd__o31ai_1           0        0         72        2       19
+DN_RO_sky130_fd_sc_hd__o211ai_1          0        0         67        2       10
+DN_RO_sky130_fd_sc_hd__o21bai_1          0        0         68        2        9
+DN_RO_sky130_fd_sc_hd__o21a_2            0        0         67        2        9
+DN_RO_sky130_fd_sc_hd__a21o_1            0        0         70        2       16
+DN_RO_sky130_fd_sc_hd__a31oi_1           0        0         61        2       13
+DN_RO_sky130_fd_sc_hd__nor2_2            0        0         58        2        8
+DN_RO_sky130_fd_sc_hd__nor3_1            0        0         49        2        9
+DN_RO_sky130_fd_sc_hd__a21boi_1          0        0         71        2       16
+DN_RO_sky130_fd_sc_hd__o21ai_1           0        0         54        2       13
+DN_RO_sky130_fd_sc_hd__a21oi_4           0        0        102        2        9
+DN_RO_sky130_fd_sc_hd__or2b_1            0        0         58        2        8
+DN_RO_sky130_fd_sc_hd__a211o_2           0        0         83        2       10
+DN_RO_sky130_fd_sc_hd__o21a_1            0        0         67        2        9
+DN_RO_sky130_fd_sc_hd__a21bo_1           0        0         88        2       19
+DN_RO_sky130_fd_sc_hd__clkinv_2          0        0         48        2       11
+DN_RO_sky130_fd_sc_hd__inv_4             0        0         56        2       12
+DN_RO_sky130_fd_sc_hd__mux2_2            0        0         80        2       16
+DN_RO_sky130_fd_sc_hd__o21ai_4           0        0         97        2        9
+DN_RO_sky130_fd_sc_hd__a21oi_1           0        0         53        2       13
+DN_RO_sky130_fd_sc_hd__o2111a_1          0        0        101        2       19
+DN_RO_sky130_fd_sc_hd__inv_16            0        0        135        2       11
+DN_RO_sky130_fd_sc_hd__nand3_1           0        0         53        2        9
+DN_RO_sky130_fd_sc_hd__nand3b_4          0        0        145        2       16
+DN_RO_sky130_fd_sc_hd__nand2_1           0        0         46        2       10
+DN_RO_sky130_fd_sc_hd__inv_6             0        0         67        2       12
+DN_RO_sky130_fd_sc_hd__a211oi_1          0        0         72        2       24
+DN_RO_sky130_fd_sc_hd__buf_4             0        0         61        2       11
+DN_RO_sky130_fd_sc_hd__or2_1             0        0         50        2        8
+DN_RO_sky130_fd_sc_hd__nor3b_2           0        0        100        2        9
+DN_RO_sky130_fd_sc_hd__and3b_1           0        0         73        2       12
+DN_RO_sky130_fd_sc_hd__inv_12            0        0        118        2       17
+DN_RO_sky130_fd_sc_hd__clkinv_8          0        0        104        2       17
+DN_RO_sky130_fd_sc_hd__nor3_4            0        0        112        2        9
+DN_RO_sky130_fd_sc_hd__nor3b_1           0        0         56        2        9
+DN_RO_sky130_fd_sc_hd__a221o_4           0        0        148        2       13
+DN_RO_sky130_fd_sc_hd__a22o_2            0        0         81        2       13
+DN_RO_sky130_fd_sc_hd__a2111oi_2         0        0         99        2       11
+DN_RO_sky130_fd_sc_hd__nand3b_1          0        0         64        2       14
+DN_RO_sky130_fd_sc_hd__and2b_1           0        0         61        2       13
+DN_RO_sky130_fd_sc_hd__inv_2             0        0         44        2        9
+DN_RO_sky130_fd_sc_hd__and3_1            0        0         89        2       10
+DN_RO_sky130_fd_sc_hd__o211a_1           0        0         84        2       12
+DN_RO_sky130_fd_sc_hd__a2111o_2          0        0        103        2       26
+DN_RO_sky130_fd_sc_hd__and4_1            0        0         72        2       18
+DN_RO_sky130_fd_sc_hd__a2111o_1          0        0         98        2       27
+DN_RO_sky130_fd_sc_hd__buf_12            0        0        127        2       14
 DN_RO_sky130_fd_sc_hd__dlymetal6s2s_1
                                          0        0         89        2       15
-DN_RO_sky130_fd_sc_hd__clkinv_16         0        0        153        2        7
-DN_RO_sky130_fd_sc_hd__nor2_2            0        0         58        2        8
-DN_RO_sky130_fd_sc_hd__nand2_2           0        0         60        2       10
-DN_RO_sky130_fd_sc_hd__nand2_4           0        0         90        2       13
-DN_RO_sky130_fd_sc_hd__nor2_8            0        0        138        2        8
-DN_RO_sky130_fd_sc_hd__or2_2             0        0         51        2        8
-DN_RO_sky130_fd_sc_hd__a21o_1            0        0         70        2       16
-DN_RO_sky130_fd_sc_hd__or3_1             0        0         56        2       12
-DN_RO_sky130_fd_sc_hd__nor3_1            0        0         49        2        9
-DN_RO_sky130_fd_sc_hd__o21a_1            0        0         67        2        9
-DN_RO_sky130_fd_sc_hd__or4_1             0        0         66        2       16
-DN_RO_sky130_fd_sc_hd__a21oi_1           0        0         53        2       13
-DN_RO_sky130_fd_sc_hd__o21bai_1          0        0         68        2        9
-DN_RO_sky130_fd_sc_hd__nor2_1            0        0         43        2        8
-DN_RO_sky130_fd_sc_hd__or2_1             0        0         50        2        8
-DN_RO_sky130_fd_sc_hd__inv_2             0        0         44        2        9
-DN_RO_sky130_fd_sc_hd__o211a_1           0        0         84        2       12
-DN_RO_sky130_fd_sc_hd__inv_6             0        0         67        2       12
-DN_RO_sky130_fd_sc_hd__nand2_1           0        0         46        2       10
-DN_RO_sky130_fd_sc_hd__inv_12            0        0        118        2       17
-DN_RO_sky130_fd_sc_hd__inv_4             0        0         56        2       12
-DN_RO_sky130_fd_sc_hd__clkinv_8          0        0        104        2       17
-DN_RO_sky130_fd_sc_hd__inv_8             0        0         86        2       13
-DN_RO_sky130_fd_sc_hd__a21oi_4           0        0        102        2        9
+DN_RO_sky130_fd_sc_hd__a221o_2           0        0         91        2       16
+DN_RO_sky130_fd_sc_hd__nand3_4           0        0        133        2       20
 DN_RO_sky130_fd_sc_hd__dfxtp_4           0        0        167        1       14
-DN_RO_sky130_fd_sc_hd__a221o_1           0        0         84        2       16
 DN_RO_sky130_fd_sc_hd__a22o_1            0        0         74        2       13
-DN_RO_sky130_fd_sc_hd__and3_1            0        0         89        2       10
-DN_RO_sky130_fd_sc_hd__clkinv_4          0        0         65        2       13
-DN_RO_sky130_fd_sc_hd__clkdlybuf4s50_1
-                                         0        0         73        2       12
+DN_RO_sky130_fd_sc_hd__buf_2             0        0         50        2       11
+DN_RO_sky130_fd_sc_hd__a221o_1           0        0         84        2       16
 DN_RO_sky130_fd_sc_hd__dfxtp_2           0        0        149        0       10
-DN_RO_sky130_fd_sc_hd__clkdlybuf4s25_1
-                                         0        0         72        2       12
 DN_RO_sky130_fd_sc_hd__buf_6             0        0         80        2       12
-DN_RO_sky130_fd_sc_hd__buf_4             0        0         61        2       11
-DN_RO_sky130_fd_sc_hd__buf_12            0        0        127        2       14
 DN_RO_sky130_fd_sc_hd__buf_8             0        0        102        2       13
 DN_RO_sky130_fd_sc_hd__dlygate4sd3_1
                                          0        0         68        2       15
-DN_RO_sky130_fd_sc_hd__buf_2             0        0         50        2       11
 DN_RO_sky130_fd_sc_hd__clkbuf_4          0        0         58        2       10
 DN_RO_sky130_fd_sc_hd__and2b_2           0        0         61        2       13
 DN_RO_sky130_fd_sc_hd__and4_2            0        0         83        2       18
@@ -2486,15 +2503,15 @@
 DN_RO_sky130_fd_sc_hd__tapvpwrvgnd_1
                                          0        0         22        0        3
 DN_RO_sky130_fd_sc_hd__decap_3           0        0         31        2        5
-DN_sky130_fd_sc_hd__decap_6              0        0         39        2        5
+DN_sky130_fd_sc_hd__decap_4              0        0         33        2        5
 DN_sky130_fd_sc_hd__tapvpwrvgnd_1
                                          0        0         22        0        3
 DN_sky130_fd_sc_hd__decap_3              0        0         31        2        5
-DN_sky130_fd_sc_hd__decap_4              0        0         33        2        5
-DN_sky130_fd_sc_hd__decap_12             0        0         55        2        5
 DN_sky130_fd_sc_hd__fill_1               0        0         11        4        5
-DN_sky130_fd_sc_hd__conb_1               0        0         36        2       11
+DN_sky130_fd_sc_hd__decap_12             0        0         55        2        5
 DN_sky130_fd_sc_hd__fill_2               0        0         13        4        5
+DN_sky130_fd_sc_hd__conb_1               0        0         36        2       11
+DN_sky130_fd_sc_hd__decap_6              0        0         39        2        5
 DN_sky130_fd_sc_hd__decap_8              0        0         45        2        5
 DN_sky130_fd_sc_hvl__lsbufhv2lv_1
                                          0        0        258        0       18
@@ -2583,94 +2600,58 @@
 DN_sky130_fd_sc_hd__and2_4               0        0         68        2        8
 DN_sky130_fd_sc_hd__einvp_8              0        0        144        2       21
 DN_sky130_fd_sc_hd__einvp_4              0        0         92        2       14
-DN_RO_mgmt_core                     146684        0    1380724        0      944
+DN_RO_mgmt_core                     148311        0    1477392        0      944
 DN_RO_DFFRAM                         50974        0     822821        0      104
-DN_DN_sky130_fd_sc_hd__decap_12          0        0         55        2        5
-DN_DN_sky130_fd_sc_hd__decap_4           0        0         33        2        5
-DN_DN_sky130_fd_sc_hd__tapvpwrvgnd_1
-                                         0        0         22        0        3
-DN_DN_sky130_fd_sc_hd__decap_6           0        0         39        2        5
-DN_DN_sky130_fd_sc_hd__fill_2            0        0         13        4        5
-DN_DN_sky130_fd_sc_hd__decap_8           0        0         45        2        5
-DN_DN_sky130_fd_sc_hd__fill_1            0        0         11        4        5
-DN_DN_sky130_fd_sc_hd__conb_1            0        0         36        2       11
-DN_DN_sky130_fd_sc_hd__decap_3           0        0         31        2        5
-DN_R2_sky130_fd_pr__cap_mim_m3_1_WRT4AW
+DN_DN_sky130_fd_pr__cap_mim_m3_1_WRT4AW
                                          0        0        600        0        0
-DN_R2_sky130_fd_pr__cap_mim_m3_2_W5U4AW
+DN_DN_sky130_fd_pr__cap_mim_m3_2_W5U4AW
                                          0        0        312        0        0
-DN_R2_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
+DN_DN_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3
                                          0        0       1011        0        0
-DN_R2_sky130_fd_sc_hvl__inv_8            0        0        234        0       16
-DN_R2_sky130_fd_sc_hvl__fill_4           0        0         48        0        7
-DN_R2_sky130_fd_sc_hvl__buf_8            0        0        273        0       18
-DN_R2_sky130_fd_sc_hvl__schmittbuf_1
+DN_DN_sky130_fd_sc_hvl__inv_8            0        0        234        0       16
+DN_DN_sky130_fd_sc_hvl__fill_4           0        0         48        0        7
+DN_DN_sky130_fd_sc_hvl__buf_8            0        0        273        0       18
+DN_DN_sky130_fd_sc_hvl__schmittbuf_1
                                          0        0        147        0       19
-DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
+DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE
                                          0        0        100        0        0
-DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
+DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV
                                          0        0        299        0        0
-DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
+DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG
                                          0        0        100        0        0
-DN_R2_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
+DN_DN_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM
                                          0        0         83        0        0
-DN_R2_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
+DN_DN_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB
                                          0        0         94        0        0
-DN_R2_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
+DN_DN_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ
                                          0        0        333        0        0
-DN_R2_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
+DN_DN_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC
                                          0        0         77        0        0
-DN_R2_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
+DN_DN_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS
                                          0        0        276        0        0
 DN_gpio_logic_high                      26        0        101        0        3
 DN_sky130_fd_sc_hd__ebufn_1              0        0         75        2       21
 DN_sky130_fd_sc_hd__dfbbn_1              0        0        237        0       21
-DN_sky130_fd_sc_hd__einvp_2              0        0         71        2       14
-DN_sky130_fd_sc_hd__a22oi_2              0        0        100        2       19
-DN_sky130_fd_sc_hd__a21oi_2              0        0         70        2       10
-DN_sky130_fd_sc_hd__a311o_2              0        0         87        2       16
-DN_sky130_fd_sc_hd__a2bb2o_2             0        0         87        2       17
-DN_sky130_fd_sc_hd__einvp_1              0        0         52        2       12
-DN_sky130_fd_sc_hd__a31o_2               0        0         73        2       15
-DN_sky130_fd_sc_hd__o41a_2               0        0        107        2       23
-DN_sky130_fd_sc_hd__o31a_2               0        0         83        2       18
-DN_sky130_fd_sc_hd__and2_2               0        0         61        2       14
-DN_sky130_fd_sc_hd__o21a_2               0        0         67        2        9
-DN_sky130_fd_sc_hd__einvn_4              0        0         91        2       12
-DN_sky130_fd_sc_hd__einvn_8              0        0        142        2       17
-DN_sky130_fd_sc_hd__clkinv_1             0        0         41        2       13
+DN_R2_sky130_fd_sc_hd__decap_12          0        0         55        2        5
+DN_R2_sky130_fd_sc_hd__decap_4           0        0         33        2        5
+DN_R2_sky130_fd_sc_hd__tapvpwrvgnd_1
+                                         0        0         22        0        3
+DN_R2_sky130_fd_sc_hd__decap_6           0        0         39        2        5
+DN_R2_sky130_fd_sc_hd__fill_2            0        0         13        4        5
+DN_R2_sky130_fd_sc_hd__decap_8           0        0         45        2        5
+DN_R2_sky130_fd_sc_hd__fill_1            0        0         11        4        5
+DN_R2_sky130_fd_sc_hd__conb_1            0        0         36        2       11
+DN_R2_sky130_fd_sc_hd__decap_3           0        0         31        2        5
 DN_sky130_fd_sc_hd__inv_8                0        0         86        2       13
-DN_sky130_fd_sc_hd__clkbuf_4             0        0         58        2       10
 DN_sky130_fd_sc_hd__buf_4                0        0         61        2       11
 DN_sky130_fd_sc_hd__inv_6                0        0         67        2       12
 DN_sky130_fd_sc_hd__nand2_4              0        0         90        2       13
-DN_sky130_fd_sc_hd__clkinv_8             0        0        104        2       17
 DN_sky130_fd_sc_hd__nand2_8              0        0        145        2       18
 DN_sky130_fd_sc_hd__buf_6                0        0         80        2       12
 DN_sky130_fd_sc_hd__buf_8                0        0        102        2       13
+DN_sky130_fd_sc_hd__and2b_1              0        0         61        2       13
 DN_sky130_fd_sc_hd__inv_12               0        0        118        2       17
-DN_sky130_fd_sc_hd__dlymetal6s2s_1
-                                         0        0         89        2       15
 DN_sky130_fd_sc_hd__or2_1                0        0         50        2        8
-DN_sky130_fd_sc_hd__o311a_2              0        0         97        2       21
-DN_sky130_fd_sc_hd__or2_2                0        0         51        2        8
-DN_sky130_fd_sc_hd__or3_2                0        0         63        2       12
-DN_sky130_fd_sc_hd__or4_2                0        0         73        2       16
-DN_sky130_fd_sc_hd__and3_2               0        0         65        0       13
-DN_sky130_fd_sc_hd__o32a_2               0        0         93        2       16
-DN_sky130_fd_sc_hd__a32o_2               0        0         98        2       20
-DN_sky130_fd_sc_hd__a22o_2               0        0         81        2       13
-DN_sky130_fd_sc_hd__o2bb2a_2             0        0         82        2       10
-DN_sky130_fd_sc_hd__o211a_2              0        0         76        2       10
-DN_sky130_fd_sc_hd__a221o_2              0        0         91        2       16
-DN_sky130_fd_sc_hd__o22a_2               0        0         81        2       10
-DN_sky130_fd_sc_hd__o221ai_2             0        0        106        2       11
-DN_sky130_fd_sc_hd__o22ai_2              0        0         98        2       10
-DN_sky130_fd_sc_hd__o221a_2              0        0         89        3       13
-DN_sky130_fd_sc_hd__a21bo_2              0        0         75        2        9
-DN_sky130_fd_sc_hd__a21o_2               0        0         66        2       10
-DN_sky130_fd_sc_hd__and4_2               0        0         83        2       18
-DN_sky130_fd_sc_hd__o2111ai_2            0        0        114        2       17
 DN_sky130_fd_sc_hd__a31oi_1              0        0         61        2       13
 DN_sky130_fd_sc_hd__nor2_8               0        0        138        2        8
 DN_sky130_fd_sc_hd__o21ai_4              0        0         97        2        9
@@ -2685,6 +2666,7 @@
 DN_sky130_fd_sc_hd__nand4b_4             0        0        182        2       21
 DN_sky130_fd_sc_hd__nand4_4              0        0        162        2       21
 DN_sky130_fd_sc_hd__o2111a_2             0        0        101        2       14
+DN_sky130_fd_sc_hd__o211ai_2             0        0         90        2       10
 DN_sky130_fd_sc_hd__and4bb_1             0        0         90        2       20
 DN_sky130_fd_sc_hd__and3_4               0        0         83        2        9
 DN_sky130_fd_sc_hd__a2111o_2             0        0        103        2       26
@@ -2706,6 +2688,7 @@
 DN_sky130_fd_sc_hd__a41o_2               0        0         96        2       20
 DN_sky130_fd_sc_hd__o22ai_4              0        0        126        2       10
 DN_sky130_fd_sc_hd__a41o_1               0        0         90        2       22
+DN_sky130_fd_sc_hd__mux2_4               0        0         99        2       12
 DN_sky130_fd_sc_hd__a22oi_1              0        0         65        2       13
 DN_sky130_fd_sc_hd__clkbuf_8             0        0         86        4       13
 DN_sky130_fd_sc_hd__or3b_2               0        0         65        2        9
@@ -2738,6 +2721,7 @@
 DN_sky130_fd_sc_hd__o2bb2a_1             0        0         73        2       10
 DN_sky130_fd_sc_hd__o22a_1               0        0         74        2       10
 DN_sky130_fd_sc_hd__or3_1                0        0         56        2       12
+DN_sky130_fd_sc_hd__a22o_1               0        0         74        2       13
 DN_sky130_fd_sc_hd__nand4bb_1            0        0         86        2       14
 DN_sky130_fd_sc_hd__nand4_1              0        0         63        2       10
 DN_sky130_fd_sc_hd__or4_1                0        0         66        2       16
@@ -2745,10 +2729,46 @@
 DN_sky130_fd_sc_hd__or4bb_1              0        0         81        2       10
 DN_sky130_fd_sc_hd__a221o_1              0        0         84        2       16
 DN_sky130_fd_sc_hd__ebufn_8              0        0        160        0       26
+DN_sky130_fd_sc_hd__nor2_2               0        0         58        2        8
+DN_sky130_fd_sc_hd__clkinv_8             0        0        104        2       17
+DN_sky130_fd_sc_hd__einvp_2              0        0         71        2       14
+DN_sky130_fd_sc_hd__a22oi_2              0        0        100        2       19
+DN_sky130_fd_sc_hd__a21oi_2              0        0         70        2       10
+DN_sky130_fd_sc_hd__a311o_2              0        0         87        2       16
+DN_sky130_fd_sc_hd__a2bb2o_2             0        0         87        2       17
+DN_sky130_fd_sc_hd__einvp_1              0        0         52        2       12
+DN_sky130_fd_sc_hd__a31o_2               0        0         73        2       15
+DN_sky130_fd_sc_hd__o41a_2               0        0        107        2       23
+DN_sky130_fd_sc_hd__o31a_2               0        0         83        2       18
+DN_sky130_fd_sc_hd__and2_2               0        0         61        2       14
+DN_sky130_fd_sc_hd__o21a_2               0        0         67        2        9
+DN_sky130_fd_sc_hd__einvn_4              0        0         91        2       12
+DN_sky130_fd_sc_hd__einvn_8              0        0        142        2       17
+DN_sky130_fd_sc_hd__clkinv_1             0        0         41        2       13
+DN_sky130_fd_sc_hd__o311a_2              0        0         97        2       21
+DN_sky130_fd_sc_hd__or2_2                0        0         51        2        8
+DN_sky130_fd_sc_hd__or3_2                0        0         63        2       12
+DN_sky130_fd_sc_hd__or4_2                0        0         73        2       16
+DN_sky130_fd_sc_hd__and3_2               0        0         65        0       13
+DN_sky130_fd_sc_hd__o21ai_2              0        0         75        2       14
+DN_sky130_fd_sc_hd__o32a_2               0        0         93        2       16
+DN_sky130_fd_sc_hd__a32o_2               0        0         98        2       20
+DN_sky130_fd_sc_hd__a22o_2               0        0         81        2       13
+DN_sky130_fd_sc_hd__o2bb2a_2             0        0         82        2       10
+DN_sky130_fd_sc_hd__o211a_2              0        0         76        2       10
+DN_sky130_fd_sc_hd__a221o_2              0        0         91        2       16
+DN_sky130_fd_sc_hd__o22a_2               0        0         81        2       10
+DN_sky130_fd_sc_hd__o221ai_2             0        0        106        2       11
+DN_sky130_fd_sc_hd__o22ai_2              0        0         98        2       10
+DN_sky130_fd_sc_hd__o221a_2              0        0         89        3       13
+DN_sky130_fd_sc_hd__a21bo_2              0        0         75        2        9
+DN_sky130_fd_sc_hd__a21o_2               0        0         66        2       10
+DN_sky130_fd_sc_hd__and4_2               0        0         83        2       18
+DN_sky130_fd_sc_hd__o2111ai_2            0        0        114        2       17
 DN_sky130_fd_sc_hd__inv_2                0        0         44        2        9
 DN_sky130_fd_sc_hd__nand2_2              0        0         60        2       10
-DN_sky130_fd_sc_hd__nor2_2               0        0         58        2        8
 DN_sky130_fd_sc_hd__mux2_2               0        0         80        2       16
+DN_sky130_fd_sc_hd__clkbuf_4             0        0         58        2       10
 DN_sky130_fd_sc_hd__diode_2              0        0         33        4       17
 DN_sky130_fd_sc_hd__buf_2                0        0         50        2       11
 DN_sky130_fd_sc_hd__clkbuf_1             0        0         41        2        9
@@ -2758,20 +2778,19 @@
 DN_sky130_fd_sc_hd__clkbuf_16            0        0        144        0       15
 DN_sky130_fd_sc_hd__buf_12               0        0        127        2       14
 DN_sky130_fd_sc_hd__clkinv_4             0        0         65        2       13
-DN_sky130_fd_sc_hd__and2b_1              0        0         61        2       13
 DN_sky130_fd_sc_hd__clkinv_2             0        0         48        2       11
 DN_sky130_fd_sc_hd__inv_4                0        0         56        2       12
+DN_sky130_fd_sc_hd__dlymetal6s2s_1
+                                         0        0         89        2       15
 DN_sky130_fd_sc_hd__or2b_1               0        0         58        2        8
 DN_sky130_fd_sc_hd__dfrtp_1              0        0        188        2       14
 DN_sky130_fd_sc_hd__buf_1                0        0         43        2       11
 DN_sky130_fd_sc_hd__clkdlybuf4s25_1
                                          0        0         72        2       12
 DN_sky130_fd_sc_hd__mux2_1               0        0         77        2       13
-DN_sky130_fd_sc_hd__o21ai_2              0        0         75        2       14
 DN_sky130_fd_sc_hd__dfrtp_2              0        0        197        6       14
 DN_sky130_fd_sc_hd__o2bb2ai_2            0        0        103        2       10
 DN_sky130_fd_sc_hd__dfstp_1              0        0        189        0       17
-DN_sky130_fd_sc_hd__a22o_1               0        0         74        2       13
 DN_sky130_fd_sc_hd__dfrtp_4              0        0        217       14       12
 DN_sky130_fd_sc_hd__dfxtp_1              0        0        144        0       10
 DN_sky130_fd_sc_hd__o21a_1               0        0         67        2        9
@@ -2782,23 +2801,17 @@
 DN_sky130_fd_sc_hd__nand3b_1             0        0         64        2       14
 DN_sky130_fd_sc_hd__o21bai_1             0        0         68        2        9
 DN_sky130_fd_sc_hd__a21o_1               0        0         70        2       16
-DN_sky130_fd_sc_hd__mux2_4               0        0         99        2       12
 DN_sky130_fd_sc_hd__o211ai_4             0        0        120        2       10
-DN_sky130_fd_sc_hd__o211ai_2             0        0         90        2       10
 DN_sky130_fd_sc_hd__o211a_1              0        0         84        2       12
 DN_sky130_fd_sc_hd__dfrtn_1              0        0        187        2       13
 DN_sky130_fd_sc_hd__dfstp_2              0        0        186        0       20
 DN_sky130_fd_sc_hd__dfstp_4              0        0        203        0       23
-DN_sky130_fd_sc_hd__o2bb2ai_1            0        0         76        2       10
-DN_sky130_fd_sc_hd__nor3b_4              0        0        121        2       11
 DN_sky130_fd_sc_hd__dlygate4sd1_1
                                          0        0         62        2       10
-DN_sky130_fd_sc_hd__o21bai_2             0        0         87        2        9
-DN_sky130_fd_sc_hd__and2b_2              0        0         61        2       13
 DN_sky130_fd_sc_hd__nor3b_1              0        0         56        2        9
 DN_sky130_fd_sc_hd__xnor2_1              0        0         63        2        8
-DN_sky130_fd_sc_hd__nand3_1              0        0         53        2        9
 DN_sky130_fd_sc_hd__nor3b_2              0        0        100        2        9
+DN_sky130_fd_sc_hd__nand3_1              0        0         53        2        9
 DN_sky130_fd_sc_hd__xor2_1               0        0         65        2        8
 DN_alpha_0                               0        0          5        0        0
 DN_alpha_1                               0        0          5        0        0
@@ -2866,18 +2879,19 @@
 
 DN_user_analog_project_wrapper          11       12       2093       11     1356
 DN_caravan_power_routing                 0        2      36270        0       31
-DN_chip_io_alt                         784        2      24234        0      557
+DN_chip_io_alt                         784        2      24232        0      557
+DN_gpio_defaults_block_0403             49        0        399        0       23
 DN_spare_logic_block                   178        0       1361        0       49
 DN_mgmt_protect                      20189        0     115138        0     1175
-DN_gpio_defaults_block_0403             49        0        399        0       23
-DN_mgmt_core_wrapper                     2        0      17127        0      774
-DN_user_id_programming                 113        0        991        0       34
+DN_gpio_defaults_block_1800             49        0        399        0       23
+DN_mgmt_core_wrapper                     2        0      16876        0      774
 DN_simple_por                           13        2       1905        0        6
 DN_gpio_control_block                  333        0       6527        0       61
 DN_gpio_defaults_block_1803             49        0        399        0       23
-DN_digital_pll                         631        0      10946        0       43
+DN_user_id_programming                 113        0        991        0       34
 DN_housekeeping                      19452        0     298527        0      405
-DN_caravel_clocking                    867        0      11030        0       30
+DN_digital_pll                         631        0      10885        0       43
+DN_caravel_clocking                    871        0      11561        0       30
 DN_user_id_textblock                     8        0          4        0        0
 DN_copyright_block_a                    20       12         12        0        0
 DN_caravan_logo                          0        0        188        0        0
@@ -2961,28 +2975,28 @@
 R2_caravel_00020021_fill_pattern_5_0
                                          0        0     109752        0        0
 R2_caravel_00020021_fill_pattern_4_1
-                                         0        0    1002860        0        0
+                                         0        0    1005305        0        0
 R2_caravel_00020021_fill_pattern_4_0
-                                         0        0    1001226        0        0
+                                         0        0    1004000        0        0
 R2_caravel_00020021_fill_pattern_3_1
-                                         0        0    1073752        0        0
+                                         0        0    1080819        0        0
 R2_caravel_00020021_fill_pattern_3_0
-                                         0        0    1046749        0        0
+                                         0        0    1034885        0        0
 R2_caravel_00020021_fill_pattern_2_1
-                                         0        0    1058137        0        0
+                                         0        0    1042950        0        0
 R2_caravel_00020021_fill_pattern_2_0
-                                         0        0    1016377        0        0
+                                         0        0    1033633        0        0
 R2_caravel_00020021_fill_pattern_1_1
-                                         0        0    1185953        0        0
+                                         0        0    1161631        0        0
 R2_caravel_00020021_fill_pattern_0_1
-                                         0        0    1018143        0        0
+                                         0        0    1016833        0        0
 R2_caravel_00020021_fill_pattern_1_0
-                                         0        0     938548        0        0
+                                         0        0     941971        0        0
 R2_caravel_00020021_fill_pattern_0_0
-                                         0        0     871371        0        0
+                                         0        0     870709        0        0
 seal_ring_corner                        15        0          2        0        0
 seal_ring_slots_array                    0        2          0        0        0
-caravan                                 70        1      61817        0       73
+caravan                                 70        1      61794        0       73
 caravel_00020021_fill_pattern           48        0          0        0        0
 advSeal_6um_gen                          6        0          0        0        0
 caravel_00020021                         3        0          1        0        0
@@ -3174,12 +3188,12 @@
     1087
     1088
 
---- LAYOUT DATABASE CONSTRUCTOR COMPLETED.  CPU TIME = 5  REAL TIME = 5  LVHEAP = 79/81/81
+--- LAYOUT DATABASE CONSTRUCTOR COMPLETED.  CPU TIME = 4  REAL TIME = 5  LVHEAP = 80/81/81
 
 CONSTRUCTING HIERARCHICAL DATABASE
     COPYING LAYOUT DATABASE
     COPY COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
-    (P=325105 A=26(53312) AX=3(152) AY=2(269) D=268)
+    (P=326785 A=26(53312) AX=3(152) AY=2(269) D=268)
     LITHO HEURISTICS OFF
     MDP HEURISTICS OFF
     CLONE STATE: LCTP(Y/N/U) = U LCRP(Y/N/U) = U LITHO(0/1/2) = 0 DFM(0/1/2) = 0
@@ -3215,263 +3229,6 @@
         sr_polygon00036
         sr_polygon00039
         nikon_sealring_shape
-        DN_UP_via2$1
-        DN_UP_via3
-        DN_UP_via4
-        DN_UP_via_new$19
-        DN_UP_via2$3
-        DN_UP_via_new$16
-        DN_UP_via2$2
-        DN_UP_via_new$17
-        DN_UP_via2$4
-        DN_UP_via_new$15
-        DN_UP_via2$5
-        DN_UP_via_new$14
-        DN_UP_via2$6
-        DN_UP_via_new$12
-        DN_UP_via3$1
-        DN_UP_via_new$10
-        DN_UP_via2$7
-        DN_UP_via3$2
-        DN_UP_via4$1
-        DN_UP_via_new$13
-        DN_UP_via2$8
-        DN_UP_via_new$11
-        DN_UP_via2$9
-        DN_UP_via_new$9
-        DN_UP_via2$10
-        DN_UP_via_new$8
-        DN_UP_via2$13
-        DN_UP_via_new$3
-        DN_UP_via4$3
-        DN_UP_via_new$1
-        DN_UP_via2$14
-        DN_UP_via_new$5
-        DN_UP_via2$16
-        DN_UP_via_new$2
-        DN_UP_via2$15
-        DN_UP_via3$3
-        DN_UP_via4$2
-        DN_UP_via_new
-        DN_UP_via2$12
-        DN_UP_via_new$4
-        DN_UP_via2$11
-        DN_UP_via_new$7
-        DN_UP_via2
-        DN_UP_via_new$18
-        DN_R2_sky130_fd_pr__cap_mim_m3_2_W5U4AW
-        DN_R2_sky130_fd_pr__cap_mim_m3_1_WRT4AW
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4
-        DN_RO_sky130_fd_bd_sram__openram_dp_cell_cap_col
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3
-        DN_sky130_ef_io__com_bus_slice_1um
-        DN_sky130_ef_io__com_bus_slice_20um
-        DN_sky130_ef_io__com_bus_slice_10um
-        DN_sky130_ef_io__disconnect_vdda_slice_5um
-        DN_sky130_ef_io__com_bus_slice_5um
-        DN_sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
-        DN_sky130_fd_pr__genrivetdlring__example_559591418082
-        DN_sky130_fd_pr__padplhp__example_559591418080
-        DN_sky130_fd_io__pad_esd
-        DN_sky130_fd_io__com_bus_slice
-        DN_sky130_fd_io__com_bus_hookup
-        DN_sky130_fd_io__com_busses_esd
-        DN_sky130_fd_io__com_bus_slice_m4
-        DN_sky130_fd_io__top_gpio_pad
-        DN_sky130_fd_io__overlay_gpiov2_m4
-        DN_sky130_fd_pr__via_l1m1__example_559591418084
-        DN_sky130_fd_pr__via_l1m1__example_55959141808154
-        DN_sky130_fd_pr__via_l1m1__example_55959141808153
-        DN_sky130_fd_pr__via_l1m1__example_55959141808152
-        DN_sky130_fd_pr__via_l1m1__example_55959141808157
-        DN_sky130_fd_pr__via_l1m1__example_55959141808156
-        DN_sky130_fd_pr__via_l1m1__example_55959141808155
-        DN_sky130_fd_pr__via_l1m1__example_55959141808290
-        DN_sky130_fd_pr__via_m1m2__example_55959141808260
-        DN_sky130_fd_pr__via_l1m1__example_5595914180878
-        DN_sky130_fd_pr__via_l1m1__example_55959141808440
-        DN_sky130_fd_pr__via_l1m1__example_5595914180858
-        DN_sky130_fd_pr__via_l1m1__example_55959141808372
-        DN_sky130_fd_pr__via_l1m1__example_5595914180897
-        DN_sky130_fd_pr__via_m1m2__example_55959141808261
-        DN_sky130_fd_io__tk_em2s_cdns_55959141808438
-        DN_sky130_fd_io__tk_em2o_cdns_55959141808439
-        DN_sky130_fd_io__tk_em1o_cdns_5595914180880
-        DN_sky130_fd_io__tk_em1o_cdns_5595914180879
-        DN_sky130_fd_io__tk_em1s_cdns_5595914180882
-        DN_sky130_fd_io__tk_em1s_cdns_5595914180881
-        DN_sky130_fd_pr__via_l1m1__example_55959141808264
-        DN_sky130_fd_pr__via_l1m1__example_5595914180857
-        DN_sky130_fd_pr__via_m1m2__example_55959141808271
-        DN_sky130_fd_pr__via_l1m1__example_55959141808127
-        DN_sky130_fd_pr__via_l1m1__example_55959141808400
-        DN_sky130_fd_pr__via_l1m1__example_55959141808325
-        DN_sky130_fd_pr__via_l1m1__example_55959141808399
-        DN_sky130_fd_pr__via_m1m2__example_55959141808402
-        DN_sky130_fd_pr__via_l1m1__example_55959141808269
-        DN_sky130_fd_pr__via_l1m1__example_55959141808401
-        DN_sky130_fd_pr__via_m1m2__example_55959141808350
-        DN_sky130_fd_pr__via_l1m1__example_55959141808292
-        DN_sky130_fd_pr__via_l1m1__example_55959141808368
-        DN_sky130_fd_pr__via_l1m1__example_55959141808267
-        DN_sky130_fd_pr__via_l1m1__example_55959141808266
-        DN_sky130_fd_pr__via_l1m1__example_55959141808128
-        DN_sky130_fd_pr__via_l1m1__example_55959141808270
-        DN_sky130_fd_io__tk_em1s_cdns_55959141808301
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808302
-        DN_sky130_fd_pr__via_l1m1__example_55959141808293
-        DN_sky130_fd_pr__via_l1m1__example_55959141808291
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808289
-        DN_sky130_fd_pr__via_m1m2__example_55959141808276
-        DN_sky130_fd_io__tk_em1s_cdns_55959141808288
-        DN_sky130_fd_pr__via_l1m1__example_55959141808324
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808327
-        DN_sky130_fd_pr__via_l1m1__example_55959141808326
-        DN_sky130_fd_pr__via_l1m1__example_55959141808323
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808328
-        DN_sky130_fd_io__tk_em1s_cdns_5595914180852
-        DN_sky130_fd_io__tk_em1s_cdns_5595914180859
-        DN_sky130_fd_io__tk_em1o_cdns_5595914180860
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418085
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418084
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418086
-        DN_sky130_fd_io__tk_em2o_cdns_55959141808653
-        DN_sky130_fd_io__tk_em2s_cdns_55959141808652
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418083
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418082
-        DN_sky130_fd_pr__via_l1m1__example_5595914180832
-        DN_sky130_fd_io__overlay_gpiov2
-        DN_sky130_fd_pr__via_l1m1__example_55959141808683
-        DN_sky130_fd_io__gnd2gnd_strap
-        DN_sky130_fd_pr__via_l1m1__example_55959141808684
-        DN_sky130_ef_io__lvc_vccdy_overlay
-        DN_sky130_fd_io__overlay_vssa_hvc
-        DN_sky130_fd_pr__via_l1m1__example_55959141808660
-        DN_sky130_fd_pr__via_l1m1__example_55959141808661
-        DN_sky130_ef_io__hvc_vdda_overlay
-        DN_sky130_fd_io__corner_bus_overlay
-        DN_sky130_ef_io__corner_pad
-        DN_sky130_fd_io__overlay_vdda_hvc
-        DN_sky130_fd_io__overlay_vddio_hvc
-        DN_sky130_ef_io__hvc_vddio_overlay
-        DN_sky130_fd_io__overlay_vssio_hvc
-        DN_sky130_ef_io__hvc_vssio_overlay
-        DN_sky130_fd_io__com_busses
-        DN_sky130_fd_pr__via_m2m3__example_55959141808714
-        DN_sky130_fd_pr__via_m1m2__example_55959141808552
-        DN_sky130_fd_pr__via_m1m2__example_55959141808551
-        DN_sky130_fd_pr__via_m1m2__example_55959141808259
-        DN_sky130_fd_pr__via_m1m2__example_55959141808727
-        DN_sky130_fd_pr__via_m1m2__example_55959141808728
-        DN_sky130_fd_pr__via_m1m2__example_55959141808724
-        DN_sky130_fd_pr__via_m1m2__example_55959141808553
-        DN_sky130_fd_pr__via_m1m2__example_55959141808725
-        DN_sky130_fd_pr__via_m1m2__example_55959141808554
-        DN_sky130_fd_pr__via_m1m2__example_55959141808726
-        DN_sky130_fd_pr__via_l1m1_centered__example_5595914180811
-        DN_sky130_fd_pr__via_l1m1_centered__example_5595914180812
-        DN_sky130_fd_pr__via_m1m2__example_55959141808737
-        DN_sky130_fd_pr__via_l1m1__example_55959141808747
-        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
-        DN_sky130_fd_pr__via_m1m2__example_55959141808733
-        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
-        DN_sky130_fd_io__xres_p_em1c_cdns_55959141808753
-        DN_sky130_fd_pr__via_m1m2__example_55959141808730
-        DN_sky130_fd_pr__via_l1m1__example_55959141808741
-        DN_sky130_fd_pr__via_m1m2__example_55959141808734
-        DN_sky130_fd_pr__via_m1m2__example_55959141808732
-        DN_sky130_fd_pr__via_l1m1__example_55959141808743
-        DN_sky130_fd_pr__via_m1m2__example_55959141808739
-        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
-        DN_sky130_fd_pr__via_m1m2__example_55959141808735
-        DN_sky130_fd_pr__via_m1m2__example_55959141808731
-        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
-        DN_sky130_fd_pr__via_l1m1__example_55959141808744
-        DN_sky130_fd_pr__via_m1m2__example_55959141808736
-        DN_sky130_fd_pr__via_m1m2__example_55959141808738
-        DN_sky130_fd_pr__via_l1m1__example_55959141808746
-        DN_sky130_fd_pr__via_l1m1__example_55959141808745
-        DN_sky130_fd_pr__via_l1m1__example_55959141808748
-        DN_sky130_fd_pr__via_l1m1__example_55959141808752
-        DN_sky130_fd_pr__via_m1m2__example_55959141808740
-        DN_sky130_fd_pr__via_l1m1__example_55959141808749
-        DN_sky130_fd_pr__via_l1m1__example_55959141808751
-        DN_sky130_fd_pr__via_l1m1__example_55959141808750
-        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
-        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
-        DN_sky130_fd_pr__via_l1m1__example_55959141808742
-        DN_sky130_fd_io__overlay_vccd_lvc
-        DN_sky130_ef_io__lvc_vccdx_overlay
-        DN_sky130_fd_io__overlay_vssd_lvc
-        DN_open_source
-        DN_font_68
-        DN_font_4F
-        DN_font_70
-        DN_font_65
-        DN_font_6E
-        DN_font_44
-        DN_font_52
-        DN_font_72
-        DN_font_6F
-        DN_font_76
-        DN_font_61
-        DN_font_64
-        DN_font_22
-        DN_font_54
-        DN_font_67
-        DN_font_69
-        DN_caravan_motto
-        DN_gpio_control_power_routing_right
-        DN_gpio_control_power_routing
-        DN_caravan_power_routing
-        DN_caravan_logo
-        DN_font_2D
-        DN_font_32
-        DN_font_56
-        DN_font_73
-        DN_font_4B
-        DN_font_6C
-        DN_font_50
-        DN_font_62
-        DN_font_74
-        DN_font_66
-        DN_font_29
-        DN_font_43
-        DN_font_28
-        DN_font_57
-        DN_font_6B
-        DN_font_79
-        DN_font_53
-        DN_font_47
-        DN_font_31
-        DN_font_30
-        DN_font_6D
-        DN_font_4E
-        DN_copyright_block_a
-        DN_alpha_2
-        DN_alpha_1
-        DN_alpha_0
-        DN_user_id_textblock
         R2_caravel_00020021_fill_pattern_3_7
         R2_caravel_00020021_fill_pattern_2_7
         R2_caravel_00020021_fill_pattern_1_6
@@ -3521,6 +3278,263 @@
         R2_caravel_00020021_fill_pattern_4_7
         R2_caravel_00020021_fill_pattern_5_7
         caravel_00020021_fill_pattern
+        DN_DN_sky130_fd_pr__cap_mim_m3_1_WRT4AW
+        DN_DN_sky130_fd_pr__cap_mim_m3_2_W5U4AW
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8
+        DN_RO_sky130_fd_bd_sram__openram_dp_cell_cap_col
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5
+        DN_UP_via2$1
+        DN_UP_via3
+        DN_UP_via4
+        DN_UP_via_new$19
+        DN_UP_via2$2
+        DN_UP_via_new$17
+        DN_UP_via2$3
+        DN_UP_via_new$16
+        DN_UP_via2$4
+        DN_UP_via_new$15
+        DN_UP_via2$5
+        DN_UP_via_new$14
+        DN_UP_via2$6
+        DN_UP_via_new$12
+        DN_UP_via3$1
+        DN_UP_via_new$10
+        DN_UP_via2$7
+        DN_UP_via3$2
+        DN_UP_via4$1
+        DN_UP_via_new$13
+        DN_UP_via2$8
+        DN_UP_via_new$11
+        DN_UP_via2$9
+        DN_UP_via_new$9
+        DN_UP_via2$10
+        DN_UP_via_new$8
+        DN_UP_via2$12
+        DN_UP_via_new$4
+        DN_UP_via2$15
+        DN_UP_via3$3
+        DN_UP_via4$2
+        DN_UP_via_new
+        DN_UP_via2$14
+        DN_UP_via_new$5
+        DN_UP_via2$13
+        DN_UP_via_new$3
+        DN_UP_via4$3
+        DN_UP_via_new$1
+        DN_UP_via2$11
+        DN_UP_via_new$7
+        DN_UP_via2$16
+        DN_UP_via_new$2
+        DN_UP_via2
+        DN_UP_via_new$18
+        DN_sky130_ef_io__com_bus_slice_20um
+        DN_sky130_ef_io__com_bus_slice_1um
+        DN_sky130_ef_io__com_bus_slice_10um
+        DN_sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+        DN_sky130_ef_io__com_bus_slice_5um
+        DN_sky130_fd_io__com_bus_slice_m4
+        DN_sky130_fd_pr__genrivetdlring__example_559591418082
+        DN_sky130_fd_pr__padplhp__example_559591418080
+        DN_sky130_fd_io__top_gpio_pad
+        DN_sky130_fd_io__overlay_gpiov2_m4
+        DN_sky130_fd_pr__via_l1m1__example_559591418084
+        DN_sky130_fd_pr__via_l1m1__example_55959141808155
+        DN_sky130_fd_pr__via_l1m1__example_55959141808154
+        DN_sky130_fd_pr__via_l1m1__example_55959141808153
+        DN_sky130_fd_pr__via_l1m1__example_55959141808152
+        DN_sky130_fd_pr__via_l1m1__example_55959141808156
+        DN_sky130_fd_pr__via_l1m1__example_55959141808157
+        DN_sky130_fd_pr__via_l1m1__example_55959141808290
+        DN_sky130_fd_pr__via_m1m2__example_55959141808260
+        DN_sky130_fd_pr__via_l1m1__example_55959141808440
+        DN_sky130_fd_pr__via_l1m1__example_5595914180858
+        DN_sky130_fd_pr__via_l1m1__example_5595914180897
+        DN_sky130_fd_pr__via_l1m1__example_5595914180878
+        DN_sky130_fd_pr__via_l1m1__example_55959141808372
+        DN_sky130_fd_pr__via_m1m2__example_55959141808261
+        DN_sky130_fd_io__tk_em2s_cdns_55959141808438
+        DN_sky130_fd_io__tk_em2o_cdns_55959141808439
+        DN_sky130_fd_io__tk_em1o_cdns_5595914180880
+        DN_sky130_fd_io__tk_em1o_cdns_5595914180879
+        DN_sky130_fd_io__tk_em1s_cdns_5595914180882
+        DN_sky130_fd_io__tk_em1s_cdns_5595914180881
+        DN_sky130_fd_pr__via_l1m1__example_55959141808264
+        DN_sky130_fd_pr__via_m1m2__example_55959141808271
+        DN_sky130_fd_pr__via_l1m1__example_5595914180857
+        DN_sky130_fd_pr__via_m1m2__example_55959141808350
+        DN_sky130_fd_pr__via_l1m1__example_55959141808399
+        DN_sky130_fd_pr__via_l1m1__example_55959141808127
+        DN_sky130_fd_pr__via_m1m2__example_55959141808402
+        DN_sky130_fd_pr__via_l1m1__example_55959141808400
+        DN_sky130_fd_pr__via_l1m1__example_55959141808401
+        DN_sky130_fd_pr__via_l1m1__example_55959141808325
+        DN_sky130_fd_pr__via_l1m1__example_55959141808269
+        DN_sky130_fd_pr__via_l1m1__example_55959141808292
+        DN_sky130_fd_pr__via_l1m1__example_55959141808368
+        DN_sky130_fd_pr__via_l1m1__example_55959141808270
+        DN_sky130_fd_pr__via_m1m2__example_55959141808276
+        DN_sky130_fd_pr__via_l1m1__example_55959141808128
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808289
+        DN_sky130_fd_io__tk_em1s_cdns_55959141808288
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808302
+        DN_sky130_fd_pr__via_l1m1__example_55959141808291
+        DN_sky130_fd_io__tk_em1s_cdns_55959141808301
+        DN_sky130_fd_pr__via_l1m1__example_55959141808293
+        DN_sky130_fd_pr__via_l1m1__example_55959141808324
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808327
+        DN_sky130_fd_pr__via_l1m1__example_55959141808323
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808328
+        DN_sky130_fd_pr__via_l1m1__example_55959141808326
+        DN_sky130_fd_pr__via_l1m1__example_55959141808267
+        DN_sky130_fd_pr__via_l1m1__example_55959141808266
+        DN_sky130_fd_pr__via_l1m1__example_5595914180832
+        DN_sky130_fd_io__tk_em1s_cdns_5595914180852
+        DN_sky130_fd_io__tk_em1o_cdns_5595914180860
+        DN_sky130_fd_io__tk_em1s_cdns_5595914180859
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418086
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418085
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418084
+        DN_sky130_fd_io__tk_em2o_cdns_55959141808653
+        DN_sky130_fd_io__tk_em2s_cdns_55959141808652
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418083
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418082
+        DN_sky130_fd_io__overlay_gpiov2
+        DN_sky130_fd_io__com_bus_slice
+        DN_sky130_fd_io__com_bus_hookup
+        DN_sky130_fd_io__overlay_vddio_hvc
+        DN_sky130_fd_io__pad_esd
+        DN_sky130_fd_io__com_busses_esd
+        DN_sky130_fd_pr__via_l1m1__example_55959141808660
+        DN_sky130_fd_pr__via_l1m1__example_55959141808661
+        DN_sky130_ef_io__hvc_vddio_overlay
+        DN_sky130_fd_io__overlay_vssa_hvc
+        DN_sky130_ef_io__hvc_vdda_overlay
+        DN_sky130_fd_pr__via_l1m1__example_55959141808683
+        DN_sky130_fd_io__gnd2gnd_strap
+        DN_sky130_fd_pr__via_l1m1__example_55959141808684
+        DN_sky130_ef_io__lvc_vccdy_overlay
+        DN_sky130_fd_io__corner_bus_overlay
+        DN_sky130_ef_io__corner_pad
+        DN_sky130_fd_io__overlay_vssio_hvc
+        DN_sky130_ef_io__hvc_vssio_overlay
+        DN_sky130_ef_io__disconnect_vdda_slice_5um
+        DN_sky130_fd_io__overlay_vccd_lvc
+        DN_sky130_ef_io__lvc_vccdx_overlay
+        DN_sky130_fd_io__overlay_vdda_hvc
+        DN_sky130_fd_io__com_busses
+        DN_sky130_fd_pr__via_l1m1_centered__example_5595914180811
+        DN_sky130_fd_pr__via_l1m1_centered__example_5595914180812
+        DN_sky130_fd_pr__via_m2m3__example_55959141808714
+        DN_sky130_fd_pr__via_m1m2__example_55959141808725
+        DN_sky130_fd_pr__via_m1m2__example_55959141808552
+        DN_sky130_fd_pr__via_m1m2__example_55959141808259
+        DN_sky130_fd_pr__via_m1m2__example_55959141808551
+        DN_sky130_fd_pr__via_m1m2__example_55959141808727
+        DN_sky130_fd_pr__via_m1m2__example_55959141808728
+        DN_sky130_fd_pr__via_m1m2__example_55959141808724
+        DN_sky130_fd_pr__via_m1m2__example_55959141808553
+        DN_sky130_fd_pr__via_m1m2__example_55959141808554
+        DN_sky130_fd_pr__via_m1m2__example_55959141808726
+        DN_sky130_fd_pr__via_m1m2__example_55959141808737
+        DN_sky130_fd_pr__via_m1m2__example_55959141808738
+        DN_sky130_fd_pr__via_l1m1__example_55959141808746
+        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+        DN_sky130_fd_io__xres_p_em1c_cdns_55959141808753
+        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+        DN_sky130_fd_pr__via_l1m1__example_55959141808741
+        DN_sky130_fd_pr__via_l1m1__example_55959141808752
+        DN_sky130_fd_pr__via_m1m2__example_55959141808730
+        DN_sky130_fd_pr__via_m1m2__example_55959141808733
+        DN_sky130_fd_pr__via_m1m2__example_55959141808732
+        DN_sky130_fd_pr__via_l1m1__example_55959141808743
+        DN_sky130_fd_pr__via_m1m2__example_55959141808739
+        DN_sky130_fd_pr__via_l1m1__example_55959141808747
+        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+        DN_sky130_fd_pr__via_m1m2__example_55959141808735
+        DN_sky130_fd_pr__via_m1m2__example_55959141808731
+        DN_sky130_fd_pr__via_m1m2__example_55959141808736
+        DN_sky130_fd_pr__via_l1m1__example_55959141808744
+        DN_sky130_fd_pr__via_l1m1__example_55959141808745
+        DN_sky130_fd_pr__via_l1m1__example_55959141808748
+        DN_sky130_fd_pr__via_m1m2__example_55959141808740
+        DN_sky130_fd_pr__via_m1m2__example_55959141808734
+        DN_sky130_fd_pr__via_l1m1__example_55959141808749
+        DN_sky130_fd_pr__via_l1m1__example_55959141808751
+        DN_sky130_fd_pr__via_l1m1__example_55959141808750
+        DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+        DN_sky130_fd_pr__via_l1m1__example_55959141808742
+        DN_sky130_fd_io__overlay_vssd_lvc
+        DN_open_source
+        DN_font_68
+        DN_font_4F
+        DN_font_70
+        DN_font_65
+        DN_font_6E
+        DN_font_44
+        DN_font_52
+        DN_font_72
+        DN_font_6F
+        DN_font_76
+        DN_font_61
+        DN_font_64
+        DN_font_22
+        DN_font_54
+        DN_font_67
+        DN_font_69
+        DN_caravan_motto
+        DN_caravan_logo
+        DN_font_2D
+        DN_font_32
+        DN_font_56
+        DN_font_73
+        DN_font_4B
+        DN_font_6C
+        DN_font_50
+        DN_font_62
+        DN_font_74
+        DN_font_66
+        DN_font_29
+        DN_font_43
+        DN_font_28
+        DN_font_57
+        DN_font_6B
+        DN_font_79
+        DN_font_53
+        DN_font_47
+        DN_font_31
+        DN_font_30
+        DN_font_6D
+        DN_font_4E
+        DN_copyright_block_a
+        DN_alpha_2
+        DN_alpha_1
+        DN_alpha_0
+        DN_user_id_textblock
+        DN_gpio_control_power_routing_right
+        DN_gpio_control_power_routing
+        DN_caravan_power_routing
         sr_polygon00031 (ADDITIONAL 45 45)
         sr_polygon00023 (ADDITIONAL 48 48)
         sr_polygon00027 (ADDITIONAL 47 47)
@@ -3534,42 +3548,12 @@
     TOP LAYER CELL IDENTIFICATION COMPLETE CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
     IDENTIFYING VERY SMALL CELLS
         DN_sky130_fd_sc_hd__fill_1
-        DN_UP_via2$1
-        DN_UP_via3
-        DN_UP_via4
-        DN_UP_via2$3
-        DN_UP_via2$2
-        DN_UP_via2$4
-        DN_UP_via2$5
-        DN_UP_via2$6
-        DN_UP_via3$1
-        DN_UP_via2$7
-        DN_UP_via3$2
-        DN_UP_via4$1
-        DN_UP_via2$8
-        DN_UP_via2$9
-        DN_UP_via2$10
-        DN_UP_sky130_fd_sc_hd__fill_1
-        DN_UP_via2$13
-        DN_UP_via_new$3
-        DN_UP_via4$3
-        DN_UP_via2$14
-        DN_UP_via_new$5
-        DN_UP_via2$16
-        DN_UP_via2$15
-        DN_UP_via3$3
-        DN_UP_via4$2
-        DN_UP_via2$12
-        DN_UP_via_new$4
-        DN_UP_via2$11
-        DN_UP_via_new$7
-        DN_UP_via2
-        DN_DN_sky130_fd_sc_hd__fill_1
         DN_RO_sky130_fd_sc_hd__fill_1
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11
@@ -3577,7 +3561,6 @@
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23
@@ -3591,6 +3574,37 @@
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39
+        DN_R2_sky130_fd_sc_hd__fill_1
+        DN_UP_via2$1
+        DN_UP_via3
+        DN_UP_via4
+        DN_UP_via2$2
+        DN_UP_via2$3
+        DN_UP_via2$4
+        DN_UP_via2$5
+        DN_UP_via2$6
+        DN_UP_via3$1
+        DN_UP_via2$7
+        DN_UP_via3$2
+        DN_UP_via4$1
+        DN_UP_via2$8
+        DN_UP_via2$9
+        DN_UP_via2$10
+        DN_UP_sky130_fd_sc_hd__fill_1
+        DN_UP_via2$12
+        DN_UP_via_new$4
+        DN_UP_via2$15
+        DN_UP_via3$3
+        DN_UP_via4$2
+        DN_UP_via2$14
+        DN_UP_via_new$5
+        DN_UP_via2$13
+        DN_UP_via_new$3
+        DN_UP_via4$3
+        DN_UP_via2$11
+        DN_UP_via_new$7
+        DN_UP_via2$16
+        DN_UP_via2
         DN_sky130_fd_pr__hvdfl1sd2__example_55959141808488
         DN_sky130_fd_pr__dfl1sd__example_5595914180868
         DN_sky130_fd_pr__dfl1sd2__example_5595914180869
@@ -3598,6 +3612,8 @@
         DN_sky130_fd_pr__dfl1sd2__example_5595914180875
         DN_sky130_fd_pr__via_pol1__example_5595914180833
         DN_sky130_fd_pr__dfl1sd__example_5595914180815
+        DN_sky130_fd_pr__dfl1sd__example_55959141808106
+        DN_sky130_fd_pr__dfl1sd__example_55959141808510
         DN_sky130_fd_pr__dfl1sd__example_5595914180823
         DN_sky130_fd_pr__hvdfm1sd__example_55959141808581
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808418
@@ -3606,14 +3622,12 @@
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808137
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808122
         DN_sky130_fd_pr__dfl1sd__example_55959141808123
-        DN_sky130_fd_pr__dfl1sd__example_55959141808106
-        DN_sky130_fd_pr__dfl1sd__example_55959141808510
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808370
+        DN_sky130_fd_pr__via_l1m1__example_559591418084
+        DN_sky130_fd_pr__via_pol1__example_559591418083
         DN_sky130_fd_pr__hvdfl1sd2__example_55959141808385
         DN_sky130_fd_pr__dfl1sd__example_559591418088
         DN_sky130_fd_pr__hvdfl1sd2__example_55959141808316
-        DN_sky130_fd_pr__via_l1m1__example_559591418084
-        DN_sky130_fd_pr__via_pol1__example_559591418083
         DN_sky130_fd_pr__dfm1sd__example_55959141808258
         DN_sky130_fd_pr__hvdfl1sd__example_5595914180894
         DN_sky130_fd_pr__hvdfm1sd__example_55959141808200
@@ -3621,22 +3635,22 @@
         DN_sky130_fd_pr__hvdfm1sd__example_55959141808452
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808476
         DN_sky130_fd_pr__dfl1sd2__example_5595914180816
-        DN_sky130_fd_pr__via_pol1__example_55959141808147
         DN_sky130_fd_pr__via_l1m1__example_55959141808152
-        DN_sky130_fd_pr__via_l1m1__example_55959141808157
         DN_sky130_fd_pr__via_l1m1__example_55959141808156
+        DN_sky130_fd_pr__via_pol1__example_55959141808147
+        DN_sky130_fd_pr__via_l1m1__example_55959141808157
         DN_sky130_fd_pr__via_pol1__example_55959141808274
         DN_sky130_fd_pr__via_l1m1__example_55959141808290
         DN_sky130_fd_pr__via_m1m2__example_55959141808260
         DN_sky130_fd_pr__via_pol1__example_55959141808612
-        DN_sky130_fd_pr__via_l1m1__example_5595914180878
         DN_sky130_fd_pr__via_l1m1__example_5595914180858
-        DN_sky130_fd_pr__via_l1m1__example_55959141808372
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808434
         DN_sky130_fd_pr__via_pol1__example_55959141808298
+        DN_sky130_fd_pr__via_l1m1__example_5595914180897
+        DN_sky130_fd_pr__via_l1m1__example_5595914180878
+        DN_sky130_fd_pr__via_l1m1__example_55959141808372
         DN_sky130_fd_pr__hvdfl1sd__example_55959141808280
         DN_sky130_fd_pr__hvdfl1sd2__example_55959141808425
-        DN_sky130_fd_pr__via_l1m1__example_5595914180897
         DN_sky130_fd_pr__via_m1m2__example_55959141808261
         DN_sky130_fd_io__tk_em2s_cdns_55959141808438
         DN_sky130_fd_io__tk_em2o_cdns_55959141808439
@@ -3644,35 +3658,35 @@
         DN_sky130_fd_io__tk_em1o_cdns_5595914180879
         DN_sky130_fd_io__tk_em1s_cdns_5595914180882
         DN_sky130_fd_io__tk_em1s_cdns_5595914180881
-        DN_sky130_fd_pr__via_pol1__example_55959141808373
         DN_sky130_fd_pr__via_l1m1__example_55959141808264
-        DN_sky130_fd_pr__via_l1m1__example_5595914180857
         DN_sky130_fd_pr__via_m1m2__example_55959141808271
-        DN_sky130_fd_pr__via_pol1__example_55959141808396
+        DN_sky130_fd_pr__via_pol1__example_55959141808373
+        DN_sky130_fd_pr__via_l1m1__example_5595914180857
+        DN_sky130_fd_pr__via_m1m2__example_55959141808350
         DN_sky130_fd_pr__via_l1m1__example_55959141808127
-        DN_sky130_fd_pr__via_pol1__example_55959141808395
         DN_sky130_fd_pr__via_m1m2__example_55959141808402
         DN_sky130_fd_pr__via_l1m1__example_55959141808401
-        DN_sky130_fd_pr__via_m1m2__example_55959141808350
-        DN_sky130_fd_pr__via_l1m1__example_55959141808128
+        DN_sky130_fd_pr__via_pol1__example_55959141808395
+        DN_sky130_fd_pr__via_pol1__example_55959141808396
         DN_sky130_fd_pr__via_l1m1__example_55959141808270
-        DN_sky130_fd_io__tk_em1s_cdns_55959141808301
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808302
-        DN_sky130_fd_pr__via_l1m1__example_55959141808291
-        DN_sky130_fd_io__tk_em1o_cdns_55959141808289
         DN_sky130_fd_pr__via_pol1__example_5595914180839
         DN_sky130_fd_pr__via_m1m2__example_55959141808276
+        DN_sky130_fd_pr__via_l1m1__example_55959141808128
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808289
         DN_sky130_fd_io__tk_em1s_cdns_55959141808288
+        DN_sky130_fd_io__tk_em1o_cdns_55959141808302
+        DN_sky130_fd_pr__via_l1m1__example_55959141808291
+        DN_sky130_fd_io__tk_em1s_cdns_55959141808301
         DN_sky130_fd_io__tk_em1o_cdns_55959141808327
         DN_sky130_fd_pr__via_l1m1__example_55959141808323
         DN_sky130_fd_io__tk_em1o_cdns_55959141808328
         DN_sky130_fd_pr__dfl1sd2__example_55959141808633
         DN_sky130_fd_io__tk_em1s_cdns_5595914180852
+        DN_sky130_fd_io__tk_em1o_cdns_5595914180860
         DN_sky130_fd_pr__res_generic_po__example_5595914180864
         DN_sky130_fd_io__tk_em1s_cdns_5595914180859
-        DN_sky130_fd_io__tk_em1o_cdns_5595914180860
-        DN_sky130_fd_pr__via_l1m1_centered__example_559591418084
         DN_sky130_fd_pr__via_l1m1_centered__example_559591418086
+        DN_sky130_fd_pr__via_l1m1_centered__example_559591418084
         DN_sky130_fd_io__tk_em2o_cdns_55959141808653
         DN_sky130_fd_io__tk_em2s_cdns_55959141808652
         DN_sky130_fd_pr__via_pol1_centered__example_559591418081
@@ -3680,8 +3694,8 @@
         DN_sky130_fd_pr__hvdfm1sd2__example_55959141808717
         DN_sky130_fd_pr__hvdfm1sd2__example_5595914180890
         DN_sky130_fd_pr__via_m1m2__example_55959141808552
-        DN_sky130_fd_pr__via_m1m2__example_55959141808551
         DN_sky130_fd_pr__via_m1m2__example_55959141808259
+        DN_sky130_fd_pr__via_m1m2__example_55959141808551
         DN_sky130_fd_pr__via_m1m2__example_55959141808728
         DN_sky130_fd_pr__via_m1m2__example_55959141808553
         DN_sky130_fd_pr__dfl1__example_55959141808729
@@ -3689,11 +3703,11 @@
         DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
         DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
         DN_sky130_fd_io__xres_p_em1c_cdns_55959141808753
-        DN_sky130_fd_pr__via_m1m2__example_55959141808734
+        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
         DN_sky130_fd_pr__via_m1m2__example_55959141808739
         DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
         DN_sky130_fd_pr__via_m1m2__example_55959141808735
-        DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+        DN_sky130_fd_pr__via_m1m2__example_55959141808734
         DN_sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
         DN_sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
         DN_font_6E
@@ -3707,7 +3721,7 @@
     CHECKING ACUTE/SKEW/ANGLED/OFFGRID
     REMOVING EXCLUSIVE INSIDE/EXTENT CELL INPUT LAYERS
     ELIMINATING DUPLICATE PLACEMENTS
-    DUPLICATE PLACEMENT ELIMINATION COMPLETE (325024 -> 325024 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    DUPLICATE PLACEMENT ELIMINATION COMPLETE (326704 -> 326704 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
     FLATTENING SELECTED LAYERS
     EXPANDING UNIQUE ICV PLACEMENTS
     COMPUTING RECTILINEAR EXTENTS
@@ -3715,13 +3729,12 @@
     SORTING PLACEMENTS VERTICALLY
     SORT COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
     ELIMINATING DUPLICATE PLACEMENTS
-    DUPLICATE PLACEMENT ELIMINATION COMPLETE (325024 -> 325024 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    DUPLICATE PLACEMENT ELIMINATION COMPLETE (326704 -> 326704 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
     EXPANDING UNIQUE TRANSPARENT CELL PLACEMENTS
-        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5 at (-0.18,-0.085)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1 at (-0.18,-0.085)
+        DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5 at (-0.18,-0.085)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver at (-0.18,-0.085)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4 at (-0.18,-0.085)
-        DN_sky130_fd_io__simple_pad_and_busses in DN_sky130_ef_io__analog_pad at (0,0)
         DN_sky130_fd_io__res250_sub_small in DN_sky130_fd_io__res250only_small at (0,0)
         DN_sky130_fd_io__com_res_weak_bentbigres in DN_sky130_fd_io__com_res_weak at (-0.79,5.07)
         DN_sky130_fd_io__gpio_odrvr_subv2 in DN_sky130_fd_io__gpio_odrvrv2 at (-4.99,-68.065)
@@ -3729,6 +3742,7 @@
         DN_sky130_ef_io__gpiov2_pad in DN_sky130_ef_io__gpiov2_pad_wrapped at (-0.715,10.965)
         DN_sky130_fd_pr__model__nfet_highvoltage__example_55959141808680 in DN_sky130_fd_io__esd_rcclamp_nfetcap at (0.45,0.45)
         DN_sky130_fd_io__hvc_clampv2 in DN_sky130_fd_io__top_power_hvc_wpadv2 at (0,0)
+        DN_sky130_fd_io__simple_pad_and_busses in DN_sky130_ef_io__analog_pad at (0,0)
         caravan in caravel_00020021 at (6,6)
     EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
     EXPANDING UNIQUE LIGHT-WEIGHT CELL PLACEMENTS
@@ -4006,27 +4020,28 @@
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8 at (96.19,15.1)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8 at (90.81,11.735)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3 in DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8 at (84.725,15.215)
-        DN_RO_sky130_fd_sc_hd__a41oi_4 in DN_RO_mgmt_core at (1931.81,494.8)
-        DN_RO_sky130_fd_sc_hd__a2bb2oi_4 in DN_RO_mgmt_core at (1751.95,424.08)
-        DN_RO_sky130_fd_sc_hd__a32oi_4 in DN_RO_mgmt_core at (1720.21,307.12)
-        DN_RO_sky130_fd_sc_hd__or4b_1 in DN_RO_mgmt_core at (1718.83,407.76)
-        DN_RO_sky130_fd_sc_hd__o211a_4 in DN_RO_mgmt_core at (1718.83,337.04)
-        DN_RO_sky130_fd_sc_hd__nand2b_1 in DN_RO_mgmt_core at (1692.61,560.08)
-        DN_RO_sky130_fd_sc_hd__a31o_2 in DN_RO_mgmt_core at (1646.15,364.24)
-        DN_RO_sky130_fd_sc_hd__o21ba_4 in DN_RO_mgmt_core at (1545.41,489.36)
-        DN_RO_sky130_fd_sc_hd__o31a_4 in DN_RO_mgmt_core at (1530.23,568.24)
-        DN_RO_sky130_fd_sc_hd__nand2b_4 in DN_RO_mgmt_core at (1499.41,277.2)
-        DN_RO_sky130_fd_sc_hd__xnor2_4 in DN_RO_mgmt_core at (1424.43,266.32)
-        DN_RO_sky130_fd_sc_hd__a2111oi_1 in DN_RO_mgmt_core at (1356.35,492.08)
-        DN_RO_sky130_fd_sc_hd__a311o_2 in DN_RO_mgmt_core at (1326.45,551.92)
-        DN_RO_sky130_fd_sc_hd__o31ai_4 in DN_RO_mgmt_core at (1306.67,500.24)
-        DN_RO_sky130_fd_sc_hd__a2111o_2 in DN_RO_mgmt_core at (1255.15,500.24)
-        DN_RO_sky130_fd_sc_hd__a31o_4 in DN_RO_mgmt_core at (1159.93,579.12)
-        DN_RO_sky130_fd_sc_hd__o21a_2 in DN_RO_mgmt_core at (1153.95,293.52)
-        DN_RO_sky130_fd_sc_hd__o31a_2 in DN_RO_mgmt_core at (841.61,600.88)
-        DN_RO_sky130_fd_sc_hd__o31ai_2 in DN_RO_mgmt_core at (816.77,519.28)
-        DN_RO_sky130_fd_sc_hd__a211oi_2 in DN_RO_mgmt_core at (537.09,535.6)
-        DN_RO_sky130_fd_sc_hd__o221ai_4 in DN_RO_mgmt_core at (494.77,549.2)
+        DN_RO_sky130_fd_sc_hd__a211o_2 in DN_RO_mgmt_core at (1878.91,668.88)
+        DN_RO_sky130_fd_sc_hd__a311oi_2 in DN_RO_mgmt_core at (1860.51,459.44)
+        DN_RO_sky130_fd_sc_hd__o41a_2 in DN_RO_mgmt_core at (1763.91,619.92)
+        DN_RO_sky130_fd_sc_hd__or3b_1 in DN_RO_mgmt_core at (1751.95,644.4)
+        DN_RO_sky130_fd_sc_hd__o221a_2 in DN_RO_mgmt_core at (1672.83,486.64)
+        DN_RO_sky130_fd_sc_hd__or2b_4 in DN_RO_mgmt_core at (1655.35,581.84)
+        DN_RO_sky130_fd_sc_hd__o21ba_4 in DN_RO_mgmt_core at (1601.53,603.6)
+        DN_RO_sky130_fd_sc_hd__or3_2 in DN_RO_mgmt_core at (1578.99,440.4)
+        DN_RO_sky130_fd_sc_hd__o22a_2 in DN_RO_mgmt_core at (1564.27,328.88)
+        DN_RO_sky130_fd_sc_hd__o21ba_2 in DN_RO_mgmt_core at (1541.73,421.36)
+        DN_RO_sky130_fd_sc_hd__o211a_2 in DN_RO_mgmt_core at (1430.87,633.52)
+        DN_RO_sky130_fd_sc_hd__nand2b_1 in DN_RO_mgmt_core at (1406.49,211.92)
+        DN_RO_sky130_fd_sc_hd__a32o_4 in DN_RO_mgmt_core at (1371.07,301.68)
+        DN_RO_sky130_fd_sc_hd__or2b_2 in DN_RO_mgmt_core at (1191.67,195.6)
+        DN_RO_sky130_fd_sc_hd__or4b_1 in DN_RO_mgmt_core at (1139.23,323.44)
+        DN_RO_sky130_fd_sc_hd__a31o_4 in DN_RO_mgmt_core at (1014.11,179.28)
+        DN_RO_sky130_fd_sc_hd__o32ai_4 in DN_RO_mgmt_core at (955.69,211.92)
+        DN_RO_sky130_fd_sc_hd__a22o_4 in DN_RO_mgmt_core at (927.17,584.56)
+        DN_RO_sky130_fd_sc_hd__o211a_4 in DN_RO_mgmt_core at (679.23,532.88)
+        DN_RO_sky130_fd_sc_hd__o41ai_2 in DN_RO_mgmt_core at (648.41,549.2)
+        DN_RO_sky130_fd_sc_hd__a21bo_2 in DN_RO_mgmt_core at (360.91,568.24)
+        DN_RO_sky130_fd_sc_hd__o32ai_2 in DN_RO_mgmt_core at (221.99,638.96)
         DN_UP_sky130_fd_sc_hd__inv_4 in DN_UP_dpll at (805.73,366.96)
         DN_UP_sky130_fd_sc_hd__nand2_4 in DN_UP_dpll at (619.89,122.16)
         DN_UP_sky130_fd_sc_hd__o221ai_4 in DN_UP_dpll at (604.71,124.88)
@@ -4098,6 +4113,7 @@
         DN_sky130_fd_sc_hd__and3_4 in DN_housekeeping at (164.03,347.92)
         DN_sky130_fd_sc_hd__or3b_4 in DN_housekeeping at (99.63,122.16)
         DN_sky130_fd_sc_hd__nor2_8 in DN_housekeeping at (96.87,119.44)
+        DN_sky130_fd_sc_hd__o211ai_2 in DN_housekeeping at (70.19,337.04)
         DN_sky130_fd_sc_hd__o22ai_4 in DN_housekeeping at (65.59,415.92)
         DN_sky130_fd_sc_hd__o31ai_4 in DN_housekeeping at (61.91,478.48)
         DN_sky130_fd_sc_hd__or3b_2 in DN_housekeeping at (53.63,437.68)
@@ -4112,37 +4128,32 @@
         DN_sky130_fd_sc_hd__a31oi_1 in DN_housekeeping at (13.15,84.08)
         DN_sky130_fd_sc_hd__a311oi_2 in DN_housekeeping at (12.69,282.64)
         DN_sky130_fd_sc_hd__nor3_2 in DN_housekeeping at (9.47,252.72)
-        DN_sky130_fd_sc_hd__nor3b_4 in DN_caravel_clocking at (64.67,2.48)
-        DN_sky130_fd_sc_hd__o21bai_2 in DN_caravel_clocking at (55.47,13.36)
-        DN_sky130_fd_sc_hd__and2b_2 in DN_caravel_clocking at (54.09,16.08)
-        DN_sky130_fd_sc_hd__dlygate4sd1_1 in DN_caravel_clocking at (37.07,5.2)
-        DN_sky130_fd_sc_hd__o2bb2ai_1 in DN_caravel_clocking at (26.49,-0.24)
-        DN_sky130_fd_sc_hd__nor3b_1 in DN_caravel_clocking at (14.07,29.68)
+        DN_sky130_fd_sc_hd__nor3b_1 in DN_caravel_clocking at (22.35,21.52)
         DN_sky130_fd_sc_hd__and2_2 in DN_digital_pll at (54.09,54.16)
         DN_sky130_fd_sc_hd__o21a_2 in DN_digital_pll at (31.55,56.88)
         DN_sky130_fd_sc_hd__a311o_2 in DN_digital_pll at (24.19,21.52)
         DN_sky130_fd_sc_hd__einvp_1 in DN_digital_pll at (18.67,37.84)
         DN_sky130_fd_sc_hd__a22oi_2 in DN_digital_pll at (7.17,21.52)
-        DN_R2_sky130_fd_sc_hvl__fill_4 in DN_simple_por at (51.885,31.755)
-        DN_R2_sky130_fd_sc_hvl__inv_8 in DN_simple_por at (46.655,36.925)
-        DN_R2_sky130_fd_sc_hvl__schmittbuf_1 in DN_simple_por at (37.005,31.755)
-        DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in DN_simple_por at (29.1,36.72)
-        DN_R2_sky130_fd_pr__cap_mim_m3_2_W5U4AW in DN_simple_por at (23.955,0.25)
-        DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in DN_simple_por at (20.13,36.72)
-        DN_R2_sky130_fd_pr__cap_mim_m3_1_WRT4AW in DN_simple_por at (19.455,0.255)
-        DN_R2_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in DN_simple_por at (12.84,36.72)
-        DN_R2_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in DN_simple_por at (11.755,31.555)
-        DN_R2_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in DN_simple_por at (2.78,36.72)
-        DN_R2_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in DN_simple_por at (2.76,31.55)
-        DN_R2_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in DN_simple_por at (0.31,31.55)
-        DN_R2_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in DN_simple_por at (0.15,0.15)
+        DN_DN_sky130_fd_sc_hvl__fill_4 in DN_simple_por at (51.885,31.755)
+        DN_DN_sky130_fd_sc_hvl__inv_8 in DN_simple_por at (46.655,36.925)
+        DN_DN_sky130_fd_sc_hvl__schmittbuf_1 in DN_simple_por at (37.005,31.755)
+        DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE in DN_simple_por at (29.1,36.72)
+        DN_DN_sky130_fd_pr__cap_mim_m3_2_W5U4AW in DN_simple_por at (23.955,0.25)
+        DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV in DN_simple_por at (20.13,36.72)
+        DN_DN_sky130_fd_pr__cap_mim_m3_1_WRT4AW in DN_simple_por at (19.455,0.255)
+        DN_DN_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG in DN_simple_por at (12.84,36.72)
+        DN_DN_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM in DN_simple_por at (11.755,31.555)
+        DN_DN_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ in DN_simple_por at (2.78,36.72)
+        DN_DN_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS in DN_simple_por at (2.76,31.55)
+        DN_DN_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC in DN_simple_por at (0.31,31.55)
+        DN_DN_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 in DN_simple_por at (0.15,0.15)
         DN_caravan_motto in caravel_00020021 at (1574.92,58.49)
         DN_caravan_logo in caravel_00020021 at (1296.9,51.86)
         DN_open_source in caravel_00020021 at (1041.77,46.48)
         DN_copyright_block_a in caravel_00020021 at (753.91,40.785)
         DN_xres_buf in caravel_00020021 at (716.94,239.44)
         DN_user_id_textblock in caravel_00020021 at (487.36,51.25)
-    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 32/81/83
     EXPANDING TRIVIAL CELL PLACEMENTS
         DN_sky130_fd_io__tk_em1s_cdns_5595914180882 (simple=16 array=0 total=16)
         DN_sky130_fd_io__tk_em1o_cdns_5595914180880 (simple=13 array=0 total=13)
@@ -4200,19 +4211,19 @@
         DN_font_44 (simple=2 array=0 total=2)
         DN_font_22 (simple=2 array=0 total=2)
         DN_font_69 (simple=2 array=0 total=2)
-    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 32/81/83
     EXPANDING VERY SPARSE ARRAY PLACEMENTS
     EXPANDING LARGE CELL ARRAY PLACEMENTS
     EXPANDING VERY SPARSE CELL PLACEMENTS
         seal_ring_corner (simple=4 array=0 total=4)
         advSeal_6um_gen (simple=1 array=0 total=1)
         DN_chip_io_alt (simple=1 array=0 total=1)
-    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 32/81/83
     EXPANDING VERY SPARSE CELL PLACEMENTS
     ELIMINATING DUPLICATE SUPER-HIERARCHICAL PLACEMENTS
         DN_sky130_fd_io__overlay_gpiov2_m4 in DN_sky130_ef_io__gpiov2_pad_wrapped at (0,13)
         DN_sky130_fd_io__com_bus_hookup in DN_sky130_ef_io__vdda_hvc_clamped_pad at (0,0)
-    DUPLICATE SUPER-HIERARCHICAL PLACEMENT ELIMINATION COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    DUPLICATE SUPER-HIERARCHICAL PLACEMENT ELIMINATION COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 32/81/83
     EXPANDING DENSE OVERLAPS
         DN_sky130_fd_io__com_busses_esd in DN_sky130_fd_io__top_power_lvc_wpad at (0,0.035)
         DN_sky130_fd_io__com_busses_esd in DN_sky130_fd_io__top_power_hvc_wpadv2 at (0,2.035)
@@ -4277,7 +4288,7 @@
         DN_sky130_ef_io__corner_pad in caravel_00020021 at (6,6)
         DN_caravan_power_routing in caravel_00020021 at (36.11,175.5)
         caravel_00020021_fill_pattern in caravel_00020021 at (7.5,7.5)
-    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 31/81/83
+    EXPAND COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 32/81/83
     EXPANDING DENSE OVERLAPS
         DN_sky130_fd_io__overlay_gpiov2_m4 in DN_sky130_ef_io__gpiov2_pad_wrapped at (0,13)
         DN_sky130_fd_io__corner_bus_overlay in caravel_00020021 at (3394,4990.335)
@@ -4378,10 +4389,10 @@
             DN_mprj_logic_high (7581.2658)
         DN_UP_Error_amplifier (bin BC=8 FBC=0 F=8 A=5995.19205)
         DN_UP_LDO (bin BC=8 FBC=0 F=8 A=34163.8973)
-        DN_RO_mgmt_core (bin BC=9 FBC=1 F=8 A=1480054.8004) FAUX BINS:
+        DN_RO_mgmt_core (bin BC=10 FBC=1 F=8 A=1480054.8004) FAUX BINS:
             DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8 (284560.4672)
         DN_RO_DFFRAM (bin BC=10 FBC=0 F=8 A=407011)
-      BIN INJECTION COMPLETE CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83
+      BIN INJECTION COMPLETE CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
         DN_sky130_fd_io__top_power_lvc_wpad (priority8)
         DN_sky130_fd_io__top_power_hvc_wpadv2 (priority8)
         DN_sky130_fd_io__amux_switch_1v2b (priority4)
@@ -4395,12 +4406,13 @@
         DN_sky130_fd_io__com_cclat (priority4)
         DN_sky130_fd_io__top_ground_lvc_wpad (priority8)
         DN_sky130_fd_io__top_ground_hvc_wpad (priority8)
-        DN_gpio_defaults_block_0403 (priority4)
+        DN_gpio_defaults_block_1800 (priority4)
         DN_spare_logic_block (priority8)
         DN_sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2 (priority4)
         DN_sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2 (priority4)
         DN_user_id_programming (priority8)
         DN_gpio_defaults_block_1803 (priority4)
+        DN_gpio_defaults_block_0403 (priority4)
         DN_sky130_fd_pr__nfet_01v8__example_55959141808677 (priority4)
         DN_gpio_control_block (priority8)
         DN_RO_DFFRAM(BIN0) (priority16)
@@ -4421,27 +4433,28 @@
         DN_housekeeping(BIN4) (priority16)
         DN_housekeeping(BIN5) (priority16)
         DN_housekeeping(BIN7) (priority16)
-        DN_caravel_clocking (priority8)
         DN_digital_pll (priority8)
         DN_RO_DFFRAM(BIN9) (priority16)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain (priority4)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8 (priority4)
-        DN_RO_mgmt_core(BIN8) (priority16)
+        DN_RO_mgmt_core(BIN3) (priority16)
+        DN_RO_mgmt_core(BIN7) (priority16)
         DN_mgmt_protect(BIN0) (priority16)
         DN_mgmt_protect(BIN3) (priority16)
         DN_mgmt_protect(BIN5) (priority16)
         DN_mgmt_protect(BIN6) (priority16)
         DN_housekeeping(BIN6) (priority16)
+        DN_caravel_clocking (priority8)
         DN_sky130_fd_pr__pfet_01v8__example_55959141808665 (priority4)
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_port_data (priority8)
         DN_RO_mgmt_core(BIN0) (priority16)
         DN_RO_mgmt_core(BIN1) (priority16)
         DN_RO_mgmt_core(BIN2) (priority16)
-        DN_RO_mgmt_core(BIN3) (priority16)
         DN_RO_mgmt_core(BIN4) (priority16)
         DN_RO_mgmt_core(BIN5) (priority16)
         DN_RO_mgmt_core(BIN6) (priority16)
-        DN_RO_mgmt_core(BIN7) (priority16)
+        DN_RO_mgmt_core(BIN8) (priority16)
+        DN_RO_mgmt_core(BIN9) (priority16)
         DN_mgmt_protect(BIN1) (priority16)
         DN_mgmt_protect(BIN2) (priority16)
         DN_mgmt_protect(BIN7) (priority16)
@@ -4454,11 +4467,11 @@
         DN_RO_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array (priority4)
         DN_mgmt_protect(BIN8) (priority16)
         DN_UP_dpll (priority4)
-      PRIORITY INJECTION COMPLETE CPU TIME = 1  REAL TIME = 1  LVHEAP = 34/81/83
-    INJECTION POST COMPLETE (219 209). CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83
-    INJECTION COMPLETE. CPU TIME = 2  REAL TIME = 2  LVHEAP = 34/81/83
+      PRIORITY INJECTION COMPLETE CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83
+    INJECTION POST COMPLETE (218 209). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
+    INJECTION COMPLETE. CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83
     COMPUTING RECTANGULAR EXTENTS
-    RECTANGULAR EXTENTS COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83
+    RECTANGULAR EXTENTS COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     COMPUTING RECTILINEAR EXTENTS
     RECTILINEAR EXTENTS COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     SORTING PLACEMENTS VERTICALLY
@@ -4466,25 +4479,25 @@
     PUSHING VERY SMALL CELL PLACEMENTS
     PUSH COMPLETE (P=6440 PA1=0 PA2=0) CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     ELIMINATING DUPLICATE PLACEMENTS
-    DUPLICATE PLACEMENT ELIMINATION COMPLETE (177051 -> 177051 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
+    DUPLICATE PLACEMENT ELIMINATION COMPLETE (179701 -> 179701 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     PUSHING TOP LAYER CELL PLACEMENTS
     PUSH COMPLETE (P=14 PA1=0 PA2=0) CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     ELIMINATING DUPLICATE PLACEMENTS
-    DUPLICATE PLACEMENT ELIMINATION COMPLETE (177051 -> 177051 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
+    DUPLICATE PLACEMENT ELIMINATION COMPLETE (179701 -> 179701 = 0). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     COMPUTING CELL-TO-WORLD TRANSFORMS
     COMPUTE COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     SORTING PLACEMENTS BY CELL
     SORT COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
-    PACKING HIERARCHY. (C=28 CN=6 P1=479 P2=1 XF=0) LVHEAP = 35/81/83
-    PACKING COMPLETE. (C=26 CN=3 P=174 XF=0) CPU TIME = 0  REAL TIME = 0  LVHEAP = 30/81/83
+    PACKING HIERARCHY. (C=28 CN=6 P1=481 P2=1 XF=0) LVHEAP = 35/81/83
+    PACKING COMPLETE. (C=26 CN=3 P=177 XF=0) CPU TIME = 0  REAL TIME = 0  LVHEAP = 30/81/83
     COMPUTING PLACEMENT OVERLAPS
-    COMPUTE COMPLETE (OC=205688 V1=17022 V2=109 SC=228 FC=204017). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
+    COMPUTE COMPLETE (OC=209377 V1=17209 V2=109 SC=220 FC=207781). CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83
     COMPUTING CELL OVERLAP AREAS
-    COMPUTE COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 33/81/83
+    COMPUTE COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83
     COMPUTING PLACEMENT / OVERLAP AREA INTERSECTIONS
-    COMPUTE COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 33/81/83
-HIERARCHICAL DATABASE CONSTRUCTOR COMPLETE. CPU TIME = 12  REAL TIME = 12  LVHEAP = 34/81/83
-(C=26 CN=3 P=174 G=1526 GH=94 D=0 TXT=0 XF=0 PO=130)
+    COMPUTE COMPLETE. CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83
+HIERARCHICAL DATABASE CONSTRUCTOR COMPLETE. CPU TIME = 11  REAL TIME = 11  LVHEAP = 34/81/83
+(C=26 CN=3 P=177 G=1539 GH=96 D=0 TXT=0 XF=0 PO=132)
 
 --------------------------------------------------------------------------------
 -----               TEXT OBJECTS FOR CONNECTIVITY EXTRACTION               -----
@@ -4512,28 +4525,28 @@
 SIMPLE LAYER      GEOMETRIES                                                    
 --------------------------------------------------------------------------------
 
-  1000                1197
-  1001                4021
+  1000                1211
+  1001                4087
   1002                  27
   1003                 895
   1004                  38
-  1005                 518
+  1005                 533
   1006                 540
   1007                   0
-  1008                9422
-  1009                2683
-  1012              170970
-  1013              242977
-  1014              412989
-  1015             1236970
-  1016              621857
-  1017              582080
-  1019              274893
-  1020              137437
-  1021              321096
-  1022               14486
-  1023               26828
-  1024                2082
+  1008                9496
+  1009                2697
+  1012              171815
+  1013              250228
+  1014              420614
+  1015             1277795
+  1016              632044
+  1017              603193
+  1019              277394
+  1020              145134
+  1021              321359
+  1022               14813
+  1023               26903
+  1024                2067
   1026                   1
   1028                  24
   1032                   0
@@ -4554,14 +4567,14 @@
   1229                   1
   1230                   8
   1300                   4
-  1417              491173
-  1418             3809890
+  1417              491629
+  1418             3809899
   1419             2444432
-  1420            12023192
-  1421             9514811
-  1422             3984100
-  1423             3211261
-  1424              302352
+  1420            12004526
+  1421             9500224
+  1422             3992940
+  1423             3217774
+  1424              299407
 
 --------------------------------------------------------------------------------
 -----            LAYER READ SUMMARY (ORIGINAL LAYER GEOMETRIES)            -----
@@ -4571,50 +4584,50 @@
 
 COREID                     4 (17160)                        4 (17160)           
 ncm                        0 (0)                            0 (0)               
-diff                    4021 (922230)                    4612 (922230)          
+diff                    4087 (923535)                    4678 (923535)          
 tap                      895 (144433)                     895 (144433)          
-poly                    9422 (1209714)                   9422 (1209714)         
-licon1                170970 (7107683)                 170970 (7107683)         
-diffTap                 4916 (1066663)                   5507 (1066663)         
+poly                    9496 (1210072)                   9496 (1210072)         
+licon1                171815 (7141634)                 171815 (7141634)         
+diffTap                 4982 (1067968)                   5573 (1067968)         
 urpm                       4 (6)                            4 (6)               
 rpm                        0 (0)                            0 (0)               
-li1                   242977 (2426567)                 242977 (2426501)         
-mcon                  412989 (6485028)                 412989 (6484896)         
-nwell                   1197 (399247)                    1197 (399247)          
-npc                     2683 (321116)                    2683 (321116)          
+li1                   250228 (2444559)                 250228 (2444493)         
+mcon                  420614 (6492822)                 420614 (6492690)         
+nwell                   1211 (400878)                    1211 (400878)          
+npc                     2697 (319285)                    2697 (319285)          
 capm                       1 (1)                            1 (1)               
-via3                  321096 (892664)                  322570 (892664)          
+via3                  321359 (892879)                  322833 (892879)          
 cap2m                      8 (12)                           8 (12)              
-via4                   26828 (246000)                   39060 (231348)          
-met3                  137437 (178931)                  137437 (178931)          
-met4                   14486 (70628)                    15854 (60392)           
-met1                 1236970 (2894100)                1237387 (2894034)         
-via                   621857 (1583350)                 621857 (1583350)         
+via4                   26903 (246067)                   39135 (231415)          
+met3                  145134 (186612)                  145134 (186612)          
+met4                   14813 (70947)                    16181 (60711)           
+met1                 1277795 (2938372)                1278212 (2938306)         
+via                   632044 (1593460)                 632044 (1593460)         
 moduleCutAREA              0 (0)                            0 (0)               
-met2                  582080 (1195573)                 582351 (1195573)         
-via2                  274893 (987185)                  294301 (987185)          
-met5                    2082 (27417)                     3470 (26376)           
+met2                  603193 (1216629)                 603464 (1216629)         
+via2                  277394 (989638)                  296802 (989638)          
+met5                    2067 (27400)                     3455 (26359)           
 hvi                      540 (40380)                      540 (40380)           
 hvntm                     24 (45)                          24 (45)              
 SEALID                     6 (24)                          24 (24)              
-FOM_FILL              491173 (491173)                  491173 (491173)          
+FOM_FILL              491629 (491629)                  491629 (491629)          
 FOMmk                      3 (12)                          12 (12)              
 P1Mmk                      3 (12)                          12 (12)              
-P1M_FILL             3809890 (3809890)                3809890 (3809890)         
-MM1_FILL            12023192 (12023192)              12023192 (12023192)        
+P1M_FILL             3809899 (3809899)                3809899 (3809899)         
+MM1_FILL            12004526 (12004526)              12004526 (12004526)        
 MM1mk                      3 (12)                          12 (12)              
-MM2_FILL             9514811 (9514811)                9514811 (9514811)         
+MM2_FILL             9500224 (9500224)                9500224 (9500224)         
 MM2mk                      3 (12)                          12 (12)              
-MM3_FILL             3984100 (3984100)                3984100 (3984100)         
+MM3_FILL             3992940 (3992940)                3992940 (3992940)         
 MM3mk                      3 (12)                          12 (12)              
-MM4_FILL             3211261 (3211261)                3211261 (3211261)         
+MM4_FILL             3217774 (3217774)                3217774 (3217774)         
 MM4mk                      3 (12)                          12 (12)              
-MM5_FILL              302352 (302352)                  302352 (302352)          
+MM5_FILL              299407 (299407)                  299407 (299407)          
 MM5mk                      3 (12)                          12 (12)              
 LI1Mmk                     3 (12)                          12 (12)              
 LI1M_FILL            2444432 (2444432)                2444432 (2444432)         
 dnwell                    27 (424)                         27 (424)             
-hvtp                     518 (317981)                     518 (317981)          
+hvtp                     533 (318851)                     533 (318851)          
 hvtr                       0 (0)                            0 (0)               
 lvtn                      38 (4460)                        38 (4460)            
 tunm                       0 (0)                            0 (0)               
@@ -4655,20 +4668,20 @@
 CELL TYPE                 CELLS           PLACEMENTS       FLAT PLACEMENTS      
 --------------------------------------------------------------------------------
 
-USER                        987               146900                598521
- VERY SMALL                 107                72379                220267
+USER                       1005               148228                600155
+ VERY SMALL                 107                72490                220370
  TOP LAYER                  128                46898                125918
   VERY SMALL                 53                45571                121175
-PSEUDO                     1139                61208                156395
-TOTAL                      2126               208108                754916
+PSEUDO                     1141                62530                155427
+TOTAL                      2146               210758                755582
 
 --------------------------------------------------------------------------------
 -----                   LAYOUT DATA INPUT MODULE SUMMARY                   -----
 --------------------------------------------------------------------------------
 
---- TOTAL GEOMETRIES READ FROM SIMPLE LAYERS = 39845289
---- TOTAL GEOMETRIES READ FROM ORIGINAL LAYERS = 39850205 (64320425)
---- TOTAL GEOMETRIES WRITTEN TO ORIGINAL LAYERS = 39888035 (64294199)
+--- TOTAL GEOMETRIES READ FROM SIMPLE LAYERS = 39923786
+--- TOTAL GEOMETRIES READ FROM ORIGINAL LAYERS = 39928768 (64449576)
+--- TOTAL GEOMETRIES WRITTEN TO ORIGINAL LAYERS = 39966598 (64423350)
 --- LVHEAP = 34/81/83
 --- DATABASE EXTENT = [ 0 , 0 ] -> [ 3600 , 5200 ]
 --- GEOMETRIC DEPTH = ALL
@@ -4688,7 +4701,7 @@
                         metop5 metop6 metop7 metop8
 --- LAYOUT TOP LAYER = (NOT SPECIFIED)
 
---- CALIBRE LAYOUT DATA INPUT MODULE COMPLETED.  CPU TIME = 17  REAL TIME = 17
+--- CALIBRE LAYOUT DATA INPUT MODULE COMPLETED.  CPU TIME = 16  REAL TIME = 16
 
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -5064,14 +5077,14 @@
 dnwell = OR dnwell
 ------------------
 dnwell (HIER TYP=1 CFG=1 HGC=15 FGC=328 HEC=94 FEC=2092 IGC=438 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 1 OF 408  ELAPSED TIME = 21
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 1 OF 408  ELAPSED TIME = 20
 
 Original Layer dnwell DELETED -- LVHEAP = 34/81/83
 
 MR_dnwell.2::<1> = INT dnwell < 3 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 -------------------------------------------------------------------------
 MR_dnwell.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 2 OF 408  ELAPSED TIME = 21
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 2 OF 408  ELAPSED TIME = 20
 
 Layer MR_dnwell.2::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5079,8 +5092,8 @@
 
 nwell = OR nwell
 ----------------
-nwell (HIER TYP=1 CFG=1 HGC=810 FGC=380996 HEC=3665 FEC=1537984 IGC=2942 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 3 OF 408  ELAPSED TIME = 21
+nwell (HIER TYP=1 CFG=1 HGC=824 FGC=382627 HEC=3721 FEC=1544508 IGC=2937 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 3 OF 408  ELAPSED TIME = 20
 
 Original Layer nwell DELETED -- LVHEAP = 34/81/83
 
@@ -5089,7 +5102,7 @@
 --------------------------------------------------------------------------
 MR_nwell.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_nwell.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 5 OF 408  ELAPSED TIME = 21
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 5 OF 408  ELAPSED TIME = 20
 
 Layer MR_nwell.1::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5101,8 +5114,8 @@
 
 hvtp = OR hvtp
 --------------
-hvtp (HIER TYP=1 CFG=1 HGC=494 FGC=314237 HEC=2002 FEC=1257294 IGC=2375 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 6 OF 408  ELAPSED TIME = 21
+hvtp (HIER TYP=1 CFG=1 HGC=508 FGC=315868 HEC=2058 FEC=1263818 IGC=2370 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 6 OF 408  ELAPSED TIME = 20
 
 Original Layer hvtp DELETED -- LVHEAP = 34/81/83
 
@@ -5111,7 +5124,7 @@
 ------------------------------------------------------------------------
 MR_hvtp.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_hvtp.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 34/81/83  OPS COMPLETE = 8 OF 408  ELAPSED TIME = 22
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 34/81/83  OPS COMPLETE = 8 OF 408  ELAPSED TIME = 21
 
 Layer MR_hvtp.1::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5124,14 +5137,14 @@
 hvtr = OR hvtr
 --------------
 hvtr (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 9 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 9 OF 408  ELAPSED TIME = 21
 
 Original Layer hvtr DELETED -- LVHEAP = 34/81/83
 
 MR_hvtr.1::<1> = INT hvtr < 0.38 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ------------------------------------------------------------------------
 MR_hvtr.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 10 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 10 OF 408  ELAPSED TIME = 21
 
 Layer MR_hvtr.1::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5140,7 +5153,7 @@
 MR_hvtr.2::<1> = EXT hvtr hvtp < 0.38 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 -----------------------------------------------------------------------------
 MR_hvtr.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 11 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 11 OF 408  ELAPSED TIME = 21
 
 Layer MR_hvtr.2::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5149,7 +5162,7 @@
 MR_hvtr.2_a::<1> = hvtr AND hvtp
 --------------------------------
 MR_hvtr.2_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 12 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 12 OF 408  ELAPSED TIME = 21
 
 Layer hvtr DELETED -- LVHEAP = 34/81/83
 
@@ -5162,7 +5175,7 @@
 lvtn = OR lvtn
 --------------
 lvtn (HIER TYP=1 CFG=1 HGC=21 FGC=3798 HEC=138 FEC=17238 IGC=124 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 13 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 13 OF 408  ELAPSED TIME = 21
 
 Original Layer lvtn DELETED -- LVHEAP = 34/81/83
 
@@ -5171,7 +5184,7 @@
 -------------------------------------------------------------------------
 MR_lvtn.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_lvtn.1a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 15 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 15 OF 408  ELAPSED TIME = 21
 
 Layer lvtn DELETED -- LVHEAP = 34/81/83
 
@@ -5186,21 +5199,21 @@
 ncm = OR ncm
 ------------
 ncm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 16 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 16 OF 408  ELAPSED TIME = 21
 
 Original Layer ncm DELETED -- LVHEAP = 34/81/83
 
 COREID = OR COREID
 ------------------
 COREID (HIER TYP=1 CFG=1 HGC=4 FGC=17160 HEC=16 FEC=68640 IGC=37 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 17 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 17 OF 408  ELAPSED TIME = 21
 
 Original Layer COREID DELETED -- LVHEAP = 34/81/83
 
 ncmPeri_drc = ncm NOT COREID
 ----------------------------
 ncmPeri_drc (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 18 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 18 OF 408  ELAPSED TIME = 21
 
 Layer ncm DELETED -- LVHEAP = 34/81/83
 
@@ -5209,7 +5222,7 @@
 ------------------------------------------------------------------------------
 MR_ncm.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_ncm.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 20 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 20 OF 408  ELAPSED TIME = 21
 
 Layer ncmPeri_drc DELETED -- LVHEAP = 34/81/83
 
@@ -5223,27 +5236,27 @@
 
 diff = OR diff
 --------------
-diff (HIER TYP=1 CFG=1 HGC=3009 FGC=773298 HEC=13326 FEC=3601538 IGC=5453 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 21 OF 408  ELAPSED TIME = 22
+diff (HIER TYP=1 CFG=1 HGC=3075 FGC=775163 HEC=13578 FEC=3600578 IGC=5488 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 21 OF 408  ELAPSED TIME = 21
 
 Original Layer diff DELETED -- LVHEAP = 34/81/83
 
 q8diff = diff NOT COREID
 ------------------------
-q8diff (HIER TYP=1 CFG=1 HGC=2995 FGC=689056 HEC=13246 FEC=3129370 IGC=5453 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 22 OF 408  ELAPSED TIME = 22
+q8diff (HIER TYP=1 CFG=1 HGC=3061 FGC=690921 HEC=13498 FEC=3128410 IGC=5488 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 22 OF 408  ELAPSED TIME = 21
 
 q7diff = INT q8diff < 0.15 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ------------------------------------------------------------------
 q7diff (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 23 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 23 OF 408  ELAPSED TIME = 21
 
 Layer q8diff DELETED -- LVHEAP = 34/81/83
 
 q1diff = INT diff < 0.15 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ----------------------------------------------------------------
 q1diff (HIER TYP=1 CFG=1 HGC=2 FGC=16642 HEC=8 FEC=66568 IGC=64 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 24 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 24 OF 408  ELAPSED TIME = 21
 
 Layer diff DELETED -- LVHEAP = 34/81/83
 
@@ -5252,12 +5265,12 @@
 ------------------------------
 q4diff (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 TMP<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 26 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 26 OF 408  ELAPSED TIME = 21
 
 q2diff = q7diff INSIDE TMP<1>
 -----------------------------
 q2diff (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 27 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 27 OF 408  ELAPSED TIME = 21
 
 Layer q7diff DELETED -- LVHEAP = 34/81/83
 
@@ -5266,7 +5279,7 @@
 q3diff = SIZE q2diff BY 0.005 INSIDE OF q1diff STEP 0.15
 --------------------------------------------------------
 q3diff (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 28 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 28 OF 408  ELAPSED TIME = 21
 
 Layer q2diff DELETED -- LVHEAP = 34/81/83
 
@@ -5282,39 +5295,39 @@
 
 tap = OR tap
 ------------
-tap (HIER TYP=1 CFG=1 HGC=455 FGC=137890 HEC=3071 FEC=568312 IGC=2271 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 29 OF 408  ELAPSED TIME = 22
+tap (HIER TYP=1 CFG=1 HGC=455 FGC=137890 HEC=3071 FEC=568312 IGC=2355 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 29 OF 408  ELAPSED TIME = 21
 
 Original Layer tap DELETED -- LVHEAP = 34/81/83
 
 q7tap = tap NOT COREID
 ----------------------
-q7tap (HIER TYP=1 CFG=1 HGC=447 FGC=87448 HEC=3039 FEC=366544 IGC=2204 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 30 OF 408  ELAPSED TIME = 22
+q7tap (HIER TYP=1 CFG=1 HGC=447 FGC=87448 HEC=3039 FEC=366544 IGC=2288 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 30 OF 408  ELAPSED TIME = 21
 
 q6tap = INT q7tap < 0.15 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ----------------------------------------------------------------
 q6tap (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 31 OF 408  ELAPSED TIME = 22
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 31 OF 408  ELAPSED TIME = 21
 
 Layer q7tap DELETED -- LVHEAP = 34/81/83
 
 q0tap = INT tap < 0.15 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 --------------------------------------------------------------
 q0tap (HIER TYP=1 CFG=1 HGC=2 FGC=16642 HEC=8 FEC=66568 IGC=19 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 32 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 32 OF 408  ELAPSED TIME = 21
 
 q3tap = q0tap OUTSIDE COREID
 TMP<2> = q0tap CUT COREID
 ----------------------------
 q3tap (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 TMP<2> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 34 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 34 OF 408  ELAPSED TIME = 21
 
 q1tap = q6tap INSIDE TMP<2>
 ---------------------------
 q1tap (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 35 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 35 OF 408  ELAPSED TIME = 21
 
 Layer q6tap DELETED -- LVHEAP = 34/81/83
 
@@ -5323,7 +5336,7 @@
 q2tap = SIZE q1tap BY 0.005 INSIDE OF q0tap STEP 0.15
 -----------------------------------------------------
 q2tap (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 36 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 36 OF 408  ELAPSED TIME = 21
 
 Layer q1tap DELETED -- LVHEAP = 34/81/83
 
@@ -5339,15 +5352,15 @@
 
 diffTap = OR diffTap
 --------------------
-diffTap (HIER TYP=1 CFG=1 HGC=3429 FGC=835250 HEC=16257 FEC=3866098 IGC=5819 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 37 OF 408  ELAPSED TIME = 23
+diffTap (HIER TYP=1 CFG=1 HGC=3495 FGC=837115 HEC=16509 FEC=3865138 IGC=5849 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 37 OF 408  ELAPSED TIME = 22
 
 Original Layer diffTap DELETED -- LVHEAP = 34/81/83
 
 MR_difftap.3::<1> = EXT diffTap < 0.27 REGION ABUT < 90 SINGULAR
 ----------------------------------------------------------------
 MR_difftap.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 38 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 38 OF 408  ELAPSED TIME = 22
 
 Layer MR_difftap.3::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5356,7 +5369,7 @@
 tunm = OR tunm
 --------------
 tunm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 39 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 39 OF 408  ELAPSED TIME = 22
 
 Original Layer tunm DELETED -- LVHEAP = 34/81/83
 
@@ -5365,7 +5378,7 @@
 ------------------------------------------------------------------------
 MR_tunm.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_tunm.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 41 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 41 OF 408  ELAPSED TIME = 22
 
 Layer tunm DELETED -- LVHEAP = 34/81/83
 
@@ -5379,15 +5392,15 @@
 
 poly = OR poly
 --------------
-poly (HIER TYP=1 CFG=1 HGC=5491 FGC=831050 HEC=51253 FEC=7920187 IGC=5905 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 42 OF 408  ELAPSED TIME = 23
+poly (HIER TYP=1 CFG=1 HGC=5557 FGC=832813 HEC=52651 FEC=8008993 IGC=5921 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 42 OF 408  ELAPSED TIME = 22
 
 Original Layer poly DELETED -- LVHEAP = 34/81/83
 
 MR_poly.1a::<1> = INT poly < 0.15 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 -------------------------------------------------------------------------
 MR_poly.1a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 43 OF 408  ELAPSED TIME = 23
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 43 OF 408  ELAPSED TIME = 22
 
 Layer MR_poly.1a::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5395,13 +5408,13 @@
 
 poly_PERI = poly NOT COREID
 ---------------------------
-poly_PERI (HIER TYP=1 CFG=1 HGC=5473 FGC=745770 HEC=50985 FEC=6496427 IGC=5905 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 44 OF 408  ELAPSED TIME = 24
+poly_PERI (HIER TYP=1 CFG=1 HGC=5539 FGC=747533 HEC=52383 FEC=6585233 IGC=5921 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 44 OF 408  ELAPSED TIME = 22
 
 MR_poly.2::<1> = EXT poly_PERI < 0.21 REGION ABUT < 90 SINGULAR
 ---------------------------------------------------------------
 MR_poly.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 45 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 45 OF 408  ELAPSED TIME = 22
 
 Layer poly_PERI DELETED -- LVHEAP = 34/81/83
 
@@ -5412,7 +5425,7 @@
 rpm = OR rpm
 ------------
 rpm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 46 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 46 OF 408  ELAPSED TIME = 22
 
 Original Layer rpm DELETED -- LVHEAP = 34/81/83
 
@@ -5421,7 +5434,7 @@
 -----------------------------------------------------------------------
 MR_rpm.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_rpm.1a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 48 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 48 OF 408  ELAPSED TIME = 22
 
 Layer MR_rpm.1a::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5434,7 +5447,7 @@
 urpm = OR urpm
 --------------
 urpm (HIER TYP=1 CFG=1 HGC=4 FGC=6 HEC=16 FEC=24 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 49 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 49 OF 408  ELAPSED TIME = 22
 
 Original Layer urpm DELETED -- LVHEAP = 34/81/83
 
@@ -5443,7 +5456,7 @@
 -------------------------------------------------------------------------
 MR_urpm.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_urpm.1a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 51 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 51 OF 408  ELAPSED TIME = 22
 
 Layer MR_urpm.1a::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5455,8 +5468,8 @@
 
 npc = OR npc
 ------------
-npc (HIER TYP=1 CFG=1 HGC=2497 FGC=293113 HEC=11184 FEC=1857114 IGC=3632 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 52 OF 408  ELAPSED TIME = 24
+npc (HIER TYP=1 CFG=1 HGC=2511 FGC=291562 HEC=11208 FEC=1849878 IGC=3527 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 52 OF 408  ELAPSED TIME = 23
 
 Original Layer npc DELETED -- LVHEAP = 34/81/83
 
@@ -5465,7 +5478,7 @@
 ----------------------------------------------------------------------
 MR_npc.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_npc.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 54 OF 408  ELAPSED TIME = 24
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 54 OF 408  ELAPSED TIME = 23
 
 Layer MR_npc.1::<1> DELETED -- LVHEAP = 34/81/83
 
@@ -5477,36 +5490,36 @@
 
 licon1 = OR licon1
 ------------------
-licon1 (HIER TYP=1 CFG=1 HGC=170997 FGC=6822541 HEC=683988 FEC=27290164 IGC=51829 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 34/81/83  OPS COMPLETE = 55 OF 408  ELAPSED TIME = 25
+licon1 (HIER TYP=1 CFG=1 HGC=171842 FGC=6856492 HEC=687368 FEC=27425968 IGC=51916 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83  OPS COMPLETE = 55 OF 408  ELAPSED TIME = 24
 
-Original Layer licon1 DELETED -- LVHEAP = 34/81/83
+Original Layer licon1 DELETED -- LVHEAP = 35/81/83
 
 ringLCON1 = DONUT licon1
 ------------------------
 ringLCON1 (HIER-FMF TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 56 OF 408  ELAPSED TIME = 25
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 56 OF 408  ELAPSED TIME = 24
 
 rectLCON1 = licon1 NOT ringLCON1
 --------------------------------
-rectLCON1 (HIER TYP=1 CFG=0 HGC=170997 FGC=6822541 HEC=683988 FEC=27290164 IGC=51829 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 57 OF 408  ELAPSED TIME = 25
+rectLCON1 (HIER TYP=1 CFG=0 HGC=171842 FGC=6856492 HEC=687368 FEC=27425968 IGC=51916 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 57 OF 408  ELAPSED TIME = 24
 
-Layer ringLCON1 DELETED -- LVHEAP = 34/81/83
+Layer ringLCON1 DELETED -- LVHEAP = 35/81/83
 
 TMP<9> = rpm OR urpm
 --------------------
 TMP<9> (HIER TYP=1 CFG=0 HGC=4 FGC=6 HEC=16 FEC=24 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 58 OF 408  ELAPSED TIME = 25
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 58 OF 408  ELAPSED TIME = 24
 
-Layer rpm DELETED -- LVHEAP = 34/81/83
+Layer rpm DELETED -- LVHEAP = 35/81/83
 
-Layer urpm DELETED -- LVHEAP = 34/81/83
+Layer urpm DELETED -- LVHEAP = 35/81/83
 
 rectLCON1OutRpm = rectLCON1 NOT TMP<9>
 --------------------------------------
-rectLCON1OutRpm (HIER TYP=1 CFG=1 HGC=170609 FGC=6821857 HEC=682436 FEC=27287428 IGC=51829 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 59 OF 408  ELAPSED TIME = 25
+rectLCON1OutRpm (HIER TYP=1 CFG=1 HGC=171454 FGC=6855808 HEC=685816 FEC=27423232 IGC=51916 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 59 OF 408  ELAPSED TIME = 24
 
 Layer rectLCON1 DELETED -- LVHEAP = 35/81/83
 
@@ -5515,7 +5528,7 @@
 q0rectLCON1OutRpm = NOT RECTANGLE rectLCON1OutRpm ORTHOGONAL ONLY
 -----------------------------------------------------------------
 q0rectLCON1OutRpm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 60 OF 408  ELAPSED TIME = 25
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 60 OF 408  ELAPSED TIME = 24
 
 Layer q0rectLCON1OutRpm DELETED -- LVHEAP = 35/81/83
 
@@ -5524,7 +5537,7 @@
 q1rectLCON1OutRpm = INT rectLCON1OutRpm < 0.17 REGION
 -----------------------------------------------------
 q1rectLCON1OutRpm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 61 OF 408  ELAPSED TIME = 25
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 61 OF 408  ELAPSED TIME = 24
 
 Layer q1rectLCON1OutRpm DELETED -- LVHEAP = 35/81/83
 
@@ -5533,51 +5546,51 @@
 TMP<10> = LENGTH rectLCON1OutRpm > 0.17
 ---------------------------------------
 TMP<10> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 62 OF 408  ELAPSED TIME = 26
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 62 OF 408  ELAPSED TIME = 25
 
 q2rectLCON1OutRpm = rectLCON1OutRpm WITH EDGE TMP<10>
 -----------------------------------------------------
 q2rectLCON1OutRpm (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 63 OF 408  ELAPSED TIME = 26
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 63 OF 408  ELAPSED TIME = 25
 
-Layer rectLCON1OutRpm DELETED -- LVHEAP = 34/81/83
+Layer rectLCON1OutRpm DELETED -- LVHEAP = 35/81/83
 
-Layer TMP<10> DELETED -- LVHEAP = 34/81/83
+Layer TMP<10> DELETED -- LVHEAP = 35/81/83
 
-Layer q2rectLCON1OutRpm DELETED -- LVHEAP = 34/81/83
+Layer q2rectLCON1OutRpm DELETED -- LVHEAP = 35/81/83
 
 DRC RuleCheck MR_licon.1_b COMPLETED. Number of Results = 0 (0)
 
 xfom = diffTap NOT poly
 -----------------------
-xfom (HIER TYP=1 CFG=0 HGC=11572 FGC=2212746 HEC=48833 FEC=9376362 IGC=5819 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 64 OF 408  ELAPSED TIME = 26
+xfom (HIER TYP=1 CFG=0 HGC=11988 FGC=2239778 HEC=50485 FEC=9476070 IGC=5849 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 64 OF 408  ELAPSED TIME = 25
 
 TMP<3> = licon1 AND xfom
 ------------------------
-TMP<3> (HIER TYP=1 CFG=1 HGC=154674 FGC=5367835 HEC=618696 FEC=21471340 IGC=49903 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 65 OF 408  ELAPSED TIME = 26
+TMP<3> (HIER TYP=1 CFG=1 HGC=155353 FGC=5405435 HEC=621412 FEC=21621740 IGC=49984 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 65 OF 408  ELAPSED TIME = 25
 
 Layer xfom DELETED -- LVHEAP = 35/81/83
 
 licon1ToXfom = licon1 INTERACT TMP<3>
 -------------------------------------
-licon1ToXfom (HIER TYP=1 CFG=0 HGC=154502 FGC=5367835 HEC=618008 FEC=21471340 IGC=51829 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 66 OF 408  ELAPSED TIME = 26
+licon1ToXfom (HIER TYP=1 CFG=0 HGC=155181 FGC=5405435 HEC=620724 FEC=21621740 IGC=51916 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 66 OF 408  ELAPSED TIME = 25
 
 Layer TMP<3> DELETED -- LVHEAP = 35/81/83
 
 licon1ToXfom_PERI = licon1ToXfom NOT COREID
 -------------------------------------------
-licon1ToXfom_PERI (HIER TYP=1 CFG=1 HGC=154459 FGC=5082599 HEC=617836 FEC=20330396 IGC=51829 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 67 OF 408  ELAPSED TIME = 27
+licon1ToXfom_PERI (HIER TYP=1 CFG=1 HGC=155138 FGC=5120199 HEC=620552 FEC=20480796 IGC=51916 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 67 OF 408  ELAPSED TIME = 25
 
 Layer licon1ToXfom DELETED -- LVHEAP = 35/81/83
 
 MR_licon.13::<1> = EXT licon1ToXfom_PERI npc < 0.09 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 -------------------------------------------------------------------------------------------
 MR_licon.13::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 68 OF 408  ELAPSED TIME = 27
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 68 OF 408  ELAPSED TIME = 26
 
 Layer MR_licon.13::<1> DELETED -- LVHEAP = 35/81/83
 
@@ -5586,55 +5599,55 @@
 MR_licon.13_a::<1> = licon1ToXfom_PERI AND npc
 ----------------------------------------------
 MR_licon.13_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 69 OF 408  ELAPSED TIME = 27
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 69 OF 408  ELAPSED TIME = 26
 
-Layer licon1ToXfom_PERI DELETED -- LVHEAP = 34/81/83
+Layer licon1ToXfom_PERI DELETED -- LVHEAP = 35/81/83
 
-Layer MR_licon.13_a::<1> DELETED -- LVHEAP = 34/81/83
+Layer MR_licon.13_a::<1> DELETED -- LVHEAP = 35/81/83
 
 DRC RuleCheck MR_licon.13_a COMPLETED. Number of Results = 0 (0)
 
 TMP<11> = licon1 AND poly
 -------------------------
-TMP<11> (HIER TYP=1 CFG=1 HGC=16495 FGC=1454706 HEC=65992 FEC=5886424 IGC=5384 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 70 OF 408  ELAPSED TIME = 27
+TMP<11> (HIER TYP=1 CFG=1 HGC=16661 FGC=1451057 HEC=66656 FEC=5871828 IGC=5365 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 70 OF 408  ELAPSED TIME = 26
 
 liconOverPoly = licon1 INTERACT TMP<11>
 ---------------------------------------
-liconOverPoly (HIER TYP=1 CFG=0 HGC=16495 FGC=1454706 HEC=65980 FEC=5818824 IGC=5384 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 71 OF 408  ELAPSED TIME = 28
+liconOverPoly (HIER TYP=1 CFG=0 HGC=16661 FGC=1451057 HEC=66644 FEC=5804228 IGC=5365 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 71 OF 408  ELAPSED TIME = 27
 
 Layer TMP<11> DELETED -- LVHEAP = 35/81/83
 
 MR_licon.17::<1> = liconOverPoly AND diffTap
 --------------------------------------------
 MR_licon.17::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 34/81/83  OPS COMPLETE = 72 OF 408  ELAPSED TIME = 28
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 72 OF 408  ELAPSED TIME = 27
 
-Layer liconOverPoly DELETED -- LVHEAP = 34/81/83
+Layer liconOverPoly DELETED -- LVHEAP = 35/81/83
 
-Layer MR_licon.17::<1> DELETED -- LVHEAP = 34/81/83
+Layer MR_licon.17::<1> DELETED -- LVHEAP = 35/81/83
 
 DRC RuleCheck MR_licon.17 COMPLETED. Number of Results = 0 (0)
 
 li1 = OR li1
 ------------
-li1 (HIER TYP=1 CFG=1 HGC=234243 FGC=1890026 HEC=978001 FEC=14071493 IGC=9746 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83  OPS COMPLETE = 73 OF 408  ELAPSED TIME = 29
+li1 (HIER TYP=1 CFG=1 HGC=241496 FGC=1910538 HEC=1008177 FEC=14208383 IGC=10307 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83  OPS COMPLETE = 73 OF 408  ELAPSED TIME = 28
 
 Original Layer li1 DELETED -- LVHEAP = 35/81/83
 
 li1_PERI = li1 NOT COREID
 -------------------------
-li1_PERI (HIER TYP=1 CFG=1 HGC=234212 FGC=1688516 HEC=977765 FEC=12785029 IGC=9746 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 74 OF 408  ELAPSED TIME = 29
+li1_PERI (HIER TYP=1 CFG=1 HGC=241465 FGC=1709028 HEC=1007941 FEC=12921919 IGC=10307 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 74 OF 408  ELAPSED TIME = 28
 
 MR_li.3::<1> = EXT li1_PERI < 0.17 REGION ABUT < 90 SINGULAR
 MR_li.1::<1> = INT li1_PERI < 0.17 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 --------------------------------------------------------------------------
 MR_li.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_li.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 10  REAL TIME = 10  LVHEAP = 35/81/83  OPS COMPLETE = 76 OF 408  ELAPSED TIME = 39
+CPU TIME = 10  REAL TIME = 10  LVHEAP = 35/81/83  OPS COMPLETE = 76 OF 408  ELAPSED TIME = 37
 
 Layer li1_PERI DELETED -- LVHEAP = 35/81/83
 
@@ -5648,27 +5661,27 @@
 
 licon1_PERI = licon1 NOT COREID
 -------------------------------
-licon1_PERI (HIER TYP=1 CFG=1 HGC=170939 FGC=6452805 HEC=683756 FEC=25811220 IGC=51829 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 77 OF 408  ELAPSED TIME = 39
+licon1_PERI (HIER TYP=1 CFG=1 HGC=171784 FGC=6486756 HEC=687136 FEC=25947024 IGC=51916 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 77 OF 408  ELAPSED TIME = 37
 
 MR_li.5::q2li1enc = ENC [licon1_PERI] li1 < 0.08 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 ---------------------------------------------------------------------------------------------------
-MR_li.5::q2li1enc (HIER-PMF TYP=2 CFG=0 HGC=774995 FGC=5721233 HEC=774995 FEC=5721233 IGC=63255 VHC=F VPC=F)
-CPU TIME = 14  REAL TIME = 14  LVHEAP = 37/81/83  OPS COMPLETE = 78 OF 408  ELAPSED TIME = 52
+MR_li.5::q2li1enc (HIER-PMF TYP=2 CFG=0 HGC=766776 FGC=5788242 HEC=766776 FEC=5788242 IGC=63483 VHC=F VPC=F)
+CPU TIME = 14  REAL TIME = 14  LVHEAP = 37/81/83  OPS COMPLETE = 78 OF 408  ELAPSED TIME = 51
 
 Layer licon1_PERI DELETED -- LVHEAP = 37/81/83
 
 MR_li.5::TMP<12> = EXPAND EDGE MR_li.5::q2li1enc INSIDE BY 0.005
 ----------------------------------------------------------------
-MR_li.5::TMP<12> (HIER TYP=1 CFG=1 HGC=774479 FGC=5712018 HEC=3097916 FEC=22848072 IGC=62448 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 37/81/83  OPS COMPLETE = 79 OF 408  ELAPSED TIME = 54
+MR_li.5::TMP<12> (HIER TYP=1 CFG=1 HGC=766185 FGC=5778986 HEC=3064740 FEC=23115944 IGC=62599 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 37/81/83  OPS COMPLETE = 79 OF 408  ELAPSED TIME = 53
 
 Layer MR_li.5::q2li1enc DELETED -- LVHEAP = 37/81/83
 
 MR_li.5::<1> = NOT RECTANGLE MR_li.5::TMP<12> ORTHOGONAL ONLY
 -------------------------------------------------------------
 MR_li.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 80 OF 408  ELAPSED TIME = 54
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 80 OF 408  ELAPSED TIME = 53
 
 Layer MR_li.5::TMP<12> DELETED -- LVHEAP = 35/81/83
 
@@ -5679,7 +5692,7 @@
 MR_li.6::<1> = AREA li1 < 0.0561
 --------------------------------
 MR_li.6::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 35/81/83  OPS COMPLETE = 81 OF 408  ELAPSED TIME = 57
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 35/81/83  OPS COMPLETE = 81 OF 408  ELAPSED TIME = 56
 
 Layer MR_li.6::<1> DELETED -- LVHEAP = 35/81/83
 
@@ -5687,25 +5700,25 @@
 
 mcon = OR mcon
 --------------
-mcon (HIER TYP=1 CFG=1 HGC=403768 FGC=6247938 HEC=1615072 FEC=24991752 IGC=50168 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 35/81/83  OPS COMPLETE = 82 OF 408  ELAPSED TIME = 58
+mcon (HIER TYP=1 CFG=1 HGC=411397 FGC=6255736 HEC=1645588 FEC=25022944 IGC=50789 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 36/81/83  OPS COMPLETE = 82 OF 408  ELAPSED TIME = 57
 
-Original Layer mcon DELETED -- LVHEAP = 35/81/83
+Original Layer mcon DELETED -- LVHEAP = 36/81/83
 
 ringMCON = DONUT mcon
 ---------------------
 ringMCON (HIER-FMF TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 35/81/83  OPS COMPLETE = 83 OF 408  ELAPSED TIME = 60
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 36/81/83  OPS COMPLETE = 83 OF 408  ELAPSED TIME = 59
 
 rectMCON = mcon NOT ringMCON
 ----------------------------
-rectMCON (HIER TYP=1 CFG=1 HGC=403768 FGC=6247938 HEC=1615072 FEC=24991752 IGC=50168 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 84 OF 408  ELAPSED TIME = 60
+rectMCON (HIER TYP=1 CFG=1 HGC=411397 FGC=6255736 HEC=1645588 FEC=25022944 IGC=50789 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 84 OF 408  ELAPSED TIME = 59
 
 q0rectMCON = NOT RECTANGLE rectMCON ORTHOGONAL ONLY
 ---------------------------------------------------
 q0rectMCON (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 36/81/83  OPS COMPLETE = 85 OF 408  ELAPSED TIME = 62
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 36/81/83  OPS COMPLETE = 85 OF 408  ELAPSED TIME = 60
 
 Layer q0rectMCON DELETED -- LVHEAP = 36/81/83
 
@@ -5714,7 +5727,7 @@
 q1rectMCON = INT rectMCON < 0.17 REGION
 ---------------------------------------
 q1rectMCON (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 36/81/83  OPS COMPLETE = 86 OF 408  ELAPSED TIME = 64
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 36/81/83  OPS COMPLETE = 86 OF 408  ELAPSED TIME = 63
 
 Layer q1rectMCON DELETED -- LVHEAP = 36/81/83
 
@@ -5723,82 +5736,82 @@
 TMP<13> = LENGTH rectMCON > 0.17
 --------------------------------
 TMP<13> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 6  REAL TIME = 6  LVHEAP = 36/81/83  OPS COMPLETE = 87 OF 408  ELAPSED TIME = 71
+CPU TIME = 6  REAL TIME = 6  LVHEAP = 36/81/83  OPS COMPLETE = 87 OF 408  ELAPSED TIME = 69
 
 q2rectMCON = rectMCON WITH EDGE TMP<13>
 ---------------------------------------
 q2rectMCON (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 88 OF 408  ELAPSED TIME = 71
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 88 OF 408  ELAPSED TIME = 69
 
-Layer rectMCON DELETED -- LVHEAP = 35/81/83
+Layer rectMCON DELETED -- LVHEAP = 36/81/83
 
-Layer TMP<13> DELETED -- LVHEAP = 35/81/83
+Layer TMP<13> DELETED -- LVHEAP = 36/81/83
 
-Layer q2rectMCON DELETED -- LVHEAP = 35/81/83
+Layer q2rectMCON DELETED -- LVHEAP = 36/81/83
 
 DRC RuleCheck MR_ct.1_b COMPLETED. Number of Results = 0 (0)
 
 MR_ct.2::<1> = EXT mcon < 0.19 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------
 MR_ct.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 35/81/83  OPS COMPLETE = 89 OF 408  ELAPSED TIME = 73
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 36/81/83  OPS COMPLETE = 89 OF 408  ELAPSED TIME = 72
 
-Layer MR_ct.2::<1> DELETED -- LVHEAP = 35/81/83
+Layer MR_ct.2::<1> DELETED -- LVHEAP = 36/81/83
 
 DRC RuleCheck MR_ct.2 COMPLETED. Number of Results = 0 (0)
 
 MR_ct.3::<1> = INT ringMCON < 0.17 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 --------------------------------------------------------------------------
 MR_ct.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 90 OF 408  ELAPSED TIME = 73
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 90 OF 408  ELAPSED TIME = 72
 
-Layer MR_ct.3::<1> DELETED -- LVHEAP = 35/81/83
+Layer MR_ct.3::<1> DELETED -- LVHEAP = 36/81/83
 
 DRC RuleCheck MR_ct.3 COMPLETED. Number of Results = 0 (0)
 
 MR_ct.3_a::q0ringMCON = SIZE ringMCON BY -0.087
 -----------------------------------------------
 MR_ct.3_a::q0ringMCON (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 91 OF 408  ELAPSED TIME = 73
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 91 OF 408  ELAPSED TIME = 72
 
 MR_ct.3_a::<1> = SIZE MR_ct.3_a::q0ringMCON BY 0.087
 ----------------------------------------------------
 MR_ct.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 92 OF 408  ELAPSED TIME = 73
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 92 OF 408  ELAPSED TIME = 72
 
-Layer MR_ct.3_a::q0ringMCON DELETED -- LVHEAP = 35/81/83
+Layer MR_ct.3_a::q0ringMCON DELETED -- LVHEAP = 36/81/83
 
-Layer MR_ct.3_a::<1> DELETED -- LVHEAP = 35/81/83
+Layer MR_ct.3_a::<1> DELETED -- LVHEAP = 36/81/83
 
 DRC RuleCheck MR_ct.3_a COMPLETED. Number of Results = 0 (0)
 
 SEALID = OR SEALID
 ------------------
 SEALID (HIER TYP=1 CFG=1 HGC=126 FGC=126 HEC=516 FEC=516 IGC=296 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 93 OF 408  ELAPSED TIME = 73
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 93 OF 408  ELAPSED TIME = 72
 
-Original Layer SEALID DELETED -- LVHEAP = 35/81/83
+Original Layer SEALID DELETED -- LVHEAP = 36/81/83
 
 MR_ct.3_b::<1> = ringMCON NOT SEALID
 ------------------------------------
 MR_ct.3_b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 35/81/83  OPS COMPLETE = 94 OF 408  ELAPSED TIME = 73
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 94 OF 408  ELAPSED TIME = 72
 
-Layer ringMCON DELETED -- LVHEAP = 35/81/83
+Layer ringMCON DELETED -- LVHEAP = 36/81/83
 
-Layer MR_ct.3_b::<1> DELETED -- LVHEAP = 35/81/83
+Layer MR_ct.3_b::<1> DELETED -- LVHEAP = 36/81/83
 
 DRC RuleCheck MR_ct.3_b COMPLETED. Number of Results = 0 (0)
 
 mcon_PERI = mcon NOT COREID
 ---------------------------
-mcon_PERI (HIER TYP=1 CFG=1 HGC=403733 FGC=6045396 HEC=1614932 FEC=24181584 IGC=50168 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 95 OF 408  ELAPSED TIME = 74
+mcon_PERI (HIER TYP=1 CFG=1 HGC=411362 FGC=6053194 HEC=1645448 FEC=24212776 IGC=50789 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 95 OF 408  ELAPSED TIME = 72
 
 MR_ct.4::<1> = mcon_PERI NOT li1
 --------------------------------
 MR_ct.4::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 96 OF 408  ELAPSED TIME = 74
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 96 OF 408  ELAPSED TIME = 72
 
 Layer MR_ct.4::<1> DELETED -- LVHEAP = 36/81/83
 
@@ -5806,52 +5819,52 @@
 
 NTAP = tap AND nwell
 --------------------
-NTAP (HIER TYP=1 CFG=1 HGC=236 FGC=59391 HEC=1496 FEC=244936 IGC=1500 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 97 OF 408  ELAPSED TIME = 74
+NTAP (HIER TYP=1 CFG=1 HGC=236 FGC=59391 HEC=1496 FEC=244936 IGC=1550 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 97 OF 408  ELAPSED TIME = 73
 
 npccon = npc AND licon1
 -----------------------
-npccon (HIER TYP=1 CFG=1 HGC=16495 FGC=1454706 HEC=65980 FEC=5818824 IGC=5384 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 98 OF 408  ELAPSED TIME = 74
+npccon (HIER TYP=1 CFG=1 HGC=16661 FGC=1451057 HEC=66644 FEC=5804228 IGC=5365 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 36/81/83  OPS COMPLETE = 98 OF 408  ELAPSED TIME = 73
 
 Layer npc DELETED -- LVHEAP = 36/81/83
 
 met1 = OR met1
 --------------
-met1 (HIER TYP=1 CFG=1 HGC=234324 FGC=1200152 HEC=3173003 FEC=8206114 IGC=12251 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 36/81/83  OPS COMPLETE = 99 OF 408  ELAPSED TIME = 77
+met1 (HIER TYP=1 CFG=1 HGC=241083 FGC=1210424 HEC=3282213 FEC=8331556 IGC=12263 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 37/81/83  OPS COMPLETE = 99 OF 408  ELAPSED TIME = 75
 
-Original Layer met1 DELETED -- LVHEAP = 36/81/83
+Original Layer met1 DELETED -- LVHEAP = 37/81/83
 
 via = OR via
 ------------
-via (HIER TYP=1 CFG=1 HGC=440126 FGC=1225732 HEC=1760506 FEC=4902930 IGC=103967 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 37/81/83  OPS COMPLETE = 100 OF 408  ELAPSED TIME = 77
+via (HIER TYP=1 CFG=1 HGC=450311 FGC=1235840 HEC=1801246 FEC=4943362 IGC=104729 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 37/81/83  OPS COMPLETE = 100 OF 408  ELAPSED TIME = 76
 
 Original Layer via DELETED -- LVHEAP = 37/81/83
 
 met2 = OR met2
 --------------
-met2 (HIER TYP=1 CFG=1 HGC=197751 FGC=335659 HEC=2253201 FEC=3344547 IGC=29404 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 37/81/83  OPS COMPLETE = 101 OF 408  ELAPSED TIME = 79
+met2 (HIER TYP=1 CFG=1 HGC=203514 FGC=341393 HEC=2334255 FEC=3425379 IGC=29641 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 38/81/83  OPS COMPLETE = 101 OF 408  ELAPSED TIME = 78
 
-Original Layer met2 DELETED -- LVHEAP = 37/81/83
+Original Layer met2 DELETED -- LVHEAP = 38/81/83
 
 via2 = OR via2
 --------------
-via2 (HIER TYP=1 CFG=1 HGC=177946 FGC=812013 HEC=711784 FEC=3248052 IGC=108923 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 38/81/83  OPS COMPLETE = 102 OF 408  ELAPSED TIME = 80
+via2 (HIER TYP=1 CFG=1 HGC=180431 FGC=814450 HEC=721724 FEC=3257800 IGC=110354 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 38/81/83  OPS COMPLETE = 102 OF 408  ELAPSED TIME = 79
 
 Original Layer via2 DELETED -- LVHEAP = 38/81/83
 
 met3 = OR met3
 --------------
-met3 (HIER TYP=1 CFG=3 HGC=40136 FGC=59171 HEC=333040 FEC=443831 IGC=13019 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/81/83  OPS COMPLETE = 103 OF 408  ELAPSED TIME = 80
+met3 (HIER TYP=1 CFG=3 HGC=41491 FGC=60510 HEC=351362 FEC=462089 IGC=13087 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/81/83  OPS COMPLETE = 103 OF 408  ELAPSED TIME = 79
 
 Original Layer met3 DELETED -- LVHEAP = 38/81/83
 
-CONNECT started.  LVHEAP = 38/81/83  ELAPSED TIME = 80
+CONNECT started.  LVHEAP = 38/82/83  ELAPSED TIME = 79
 
 CONNECT dnwell nwell ...
 CONNECT nwell tap BY NTAP ...
@@ -5865,9 +5878,9 @@
 
 NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 46/82/83
 
-CONNECT completed.  CPU TIME = 15  REAL TIME = 15  LVHEAP = 45/81/83  ELAPSED TIME = 95
+CONNECT completed.  CPU TIME = 15  REAL TIME = 15  LVHEAP = 45/81/83  ELAPSED TIME = 94
 
-NETS = 156066 (7903922)  EPINS = 53953 (2625715)
+NETS = 158350 (7951766)  EPINS = 54702 (2636200)
 
 Layer dnwell DELETED -- LVHEAP = 45/81/83
 
@@ -5877,9 +5890,9 @@
 
 Layer licon1 DELETED -- LVHEAP = 45/81/83
 
-Layer tap DELETED -- LVHEAP = 44/81/83
+Layer tap DELETED -- LVHEAP = 45/81/83
 
-Layer npccon DELETED -- LVHEAP = 44/81/83
+Layer npccon DELETED -- LVHEAP = 45/81/83
 
 Layer mcon DELETED -- LVHEAP = 44/81/83
 
@@ -5887,36 +5900,36 @@
 
 via3 = OR via3
 --------------
-via3 (HIER TYP=1 CFG=1 HGC=211808 FGC=725951 HEC=847232 FEC=2903804 IGC=82941 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 104 OF 408  ELAPSED TIME = 96
+via3 (HIER TYP=1 CFG=1 HGC=212065 FGC=726160 HEC=848260 FEC=2904640 IGC=83441 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 104 OF 408  ELAPSED TIME = 95
 
 Original Layer via3 DELETED -- LVHEAP = 44/81/83
 
 capm = OR capm
 --------------
 capm (HIER TYP=1 CFG=1 HGC=1 FGC=1 HEC=4 FEC=4 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 105 OF 408  ELAPSED TIME = 96
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 105 OF 408  ELAPSED TIME = 95
 
 Original Layer capm DELETED -- LVHEAP = 44/81/83
 
 capm_via3 = via3 AND capm
 -------------------------
 capm_via3 (HIER TYP=1 CFG=1 HGC=518 FGC=518 HEC=2072 FEC=2072 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 106 OF 408  ELAPSED TIME = 96
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 106 OF 408  ELAPSED TIME = 95
 
 via3_notcapm = via3 NOT capm_via3
 ---------------------------------
-via3_notcapm (HIER TYP=1 CFG=1 HGC=211290 FGC=725433 HEC=845160 FEC=2901732 IGC=82941 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 107 OF 408  ELAPSED TIME = 96
+via3_notcapm (HIER TYP=1 CFG=1 HGC=211547 FGC=725642 HEC=846188 FEC=2902568 IGC=83441 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 107 OF 408  ELAPSED TIME = 95
 
 met4 = OR met4
 --------------
-met4 (HIER TYP=1 CFG=3 HGC=10760 FGC=50945 HEC=66220 FEC=236958 IGC=12327 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 108 OF 408  ELAPSED TIME = 96
+met4 (HIER TYP=1 CFG=3 HGC=11039 FGC=51216 HEC=68128 FEC=238834 IGC=12490 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 45/81/83  OPS COMPLETE = 108 OF 408  ELAPSED TIME = 95
 
-Original Layer met4 DELETED -- LVHEAP = 44/81/83
+Original Layer met4 DELETED -- LVHEAP = 45/81/83
 
-CONNECT started.  LVHEAP = 44/82/83  ELAPSED TIME = 96
+CONNECT started.  LVHEAP = 45/82/83  ELAPSED TIME = 95
 
 CONNECT met3 met4 BY via3_notcapm ...
 CONNECT capm met4 BY capm_via3 ...
@@ -5924,15 +5937,15 @@
 NODE UPDATE: met3
 NODE UPDATE: met4
 
-NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/82/83
+NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 45/82/83
 
-CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  ELAPSED TIME = 98
+CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  ELAPSED TIME = 96
 
-NETS = 153416 (7936215)  EPINS = 55622 (2664359)
+NETS = 155697 (7984133)  EPINS = 56448 (2674996)
 
-Layer via3_notcapm DELETED -- LVHEAP = 43/81/83
+Layer via3_notcapm DELETED -- LVHEAP = 44/81/83
 
-Layer capm_via3 DELETED -- LVHEAP = 43/81/83
+Layer capm_via3 DELETED -- LVHEAP = 44/81/83
 
 HIERARCHICAL CONNECTIVITY marked on layer met3
 
@@ -5940,50 +5953,50 @@
 
 via4 = OR via4
 --------------
-via4 (HIER TYP=1 CFG=1 HGC=32979 FGC=222131 HEC=131916 FEC=888524 IGC=17216 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 109 OF 408  ELAPSED TIME = 98
+via4 (HIER TYP=1 CFG=1 HGC=33054 FGC=222198 HEC=132216 FEC=888792 IGC=17314 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 109 OF 408  ELAPSED TIME = 96
 
-Original Layer via4 DELETED -- LVHEAP = 43/81/83
+Original Layer via4 DELETED -- LVHEAP = 44/81/83
 
 cap2m = OR cap2m
 ----------------
 cap2m (HIER TYP=1 CFG=1 HGC=21 FGC=31 HEC=84 FEC=124 IGC=26 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 110 OF 408  ELAPSED TIME = 98
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 110 OF 408  ELAPSED TIME = 96
 
-Original Layer cap2m DELETED -- LVHEAP = 43/81/83
+Original Layer cap2m DELETED -- LVHEAP = 44/81/83
 
 cap2m_via4 = via4 AND cap2m
 ---------------------------
 cap2m_via4 (HIER TYP=1 CFG=1 HGC=2052 FGC=3096 HEC=8208 FEC=12384 IGC=14 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 111 OF 408  ELAPSED TIME = 98
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 111 OF 408  ELAPSED TIME = 96
 
 via4_notcap2m = via4 NOT cap2m_via4
 -----------------------------------
-via4_notcap2m (HIER TYP=1 CFG=1 HGC=30927 FGC=219035 HEC=123708 FEC=876140 IGC=17216 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 112 OF 408  ELAPSED TIME = 98
+via4_notcap2m (HIER TYP=1 CFG=1 HGC=31002 FGC=219102 HEC=124008 FEC=876408 IGC=17314 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 112 OF 408  ELAPSED TIME = 96
 
 met5 = OR met5
 --------------
-met5 (HIER TYP=1 CFG=1 HGC=2386 FGC=21448 HEC=12220 FEC=90841 IGC=3780 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 113 OF 408  ELAPSED TIME = 98
+met5 (HIER TYP=1 CFG=1 HGC=2457 FGC=21517 HEC=12402 FEC=91015 IGC=4021 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 113 OF 408  ELAPSED TIME = 96
 
-Original Layer met5 DELETED -- LVHEAP = 43/81/83
+Original Layer met5 DELETED -- LVHEAP = 44/81/83
 
 pad = OR pad
 ------------
 pad (HIER TYP=1 CFG=1 HGC=1 FGC=63 HEC=8 FEC=504 IGC=86 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 114 OF 408  ELAPSED TIME = 98
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 114 OF 408  ELAPSED TIME = 96
 
-Original Layer pad DELETED -- LVHEAP = 43/81/83
+Original Layer pad DELETED -- LVHEAP = 44/81/83
 
 rdl = OR rdl
 ------------
 rdl (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 115 OF 408  ELAPSED TIME = 98
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 115 OF 408  ELAPSED TIME = 96
 
-Original Layer rdl DELETED -- LVHEAP = 43/81/83
+Original Layer rdl DELETED -- LVHEAP = 44/81/83
 
-CONNECT started.  LVHEAP = 44/82/83  ELAPSED TIME = 98
+CONNECT started.  LVHEAP = 44/82/83  ELAPSED TIME = 96
 
 CONNECT met4 met5 BY via4_notcap2m ...
 CONNECT cap2m met5 BY cap2m_via4 ...
@@ -5993,17 +6006,17 @@
 NODE UPDATE: met3
 NODE UPDATE: met4
 
-NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/82/83
+NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 45/82/83
 
-CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  ELAPSED TIME = 99
+CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  ELAPSED TIME = 98
 
-NETS = 153224 (7933862)  EPINS = 55599 (2662332)
+NETS = 155464 (7981739)  EPINS = 56418 (2672962)
 
-Layer via4_notcap2m DELETED -- LVHEAP = 43/81/83
+Layer via4_notcap2m DELETED -- LVHEAP = 44/81/83
 
-Layer cap2m_via4 DELETED -- LVHEAP = 43/81/83
+Layer cap2m_via4 DELETED -- LVHEAP = 44/81/83
 
-Layer rdl DELETED -- LVHEAP = 43/81/83
+Layer rdl DELETED -- LVHEAP = 44/81/83
 
 HIERARCHICAL CONNECTIVITY marked on layer met3
 
@@ -6012,28 +6025,28 @@
 TMP<14> = capm AND met3
 -----------------------
 TMP<14> (HIER TYP=1 CFG=1 HGC=1 FGC=1 HEC=4 FEC=4 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 116 OF 408  ELAPSED TIME = 99
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 116 OF 408  ELAPSED TIME = 98
 
 m3_bot_plate = SIZE TMP<14> BY 0.14
 -----------------------------------
 m3_bot_plate (HIER TYP=1 CFG=3 HGC=1 FGC=1 HEC=4 FEC=4 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 117 OF 408  ELAPSED TIME = 99
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 117 OF 408  ELAPSED TIME = 98
 
-Layer TMP<14> DELETED -- LVHEAP = 43/81/83
+Layer TMP<14> DELETED -- LVHEAP = 44/81/83
 
 TMP<15> = EXT m3_bot_plate < 1.2 REGION
 ---------------------------------------
 TMP<15> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 118 OF 408  ELAPSED TIME = 99
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 118 OF 408  ELAPSED TIME = 98
 
 m3_bot_plate_err = TMP<15> INTERACT met3 > 1 BY NET
 ---------------------------------------------------
 m3_bot_plate_err (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 119 OF 408  ELAPSED TIME = 99
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 119 OF 408  ELAPSED TIME = 98
 
-Layer TMP<15> DELETED -- LVHEAP = 43/81/83
+Layer TMP<15> DELETED -- LVHEAP = 44/81/83
 
-CONNECT started.  LVHEAP = 43/82/83  ELAPSED TIME = 99
+CONNECT started.  LVHEAP = 44/82/83  ELAPSED TIME = 98
 
 CONNECT m3_bot_plate met3 ...
 
@@ -6042,9 +6055,9 @@
 
 NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/82/83
 
-CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  ELAPSED TIME = 100
+CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  ELAPSED TIME = 98
 
-NETS = 153224 (7933862)  EPINS = 55599 (2662332)
+NETS = 155464 (7981739)  EPINS = 56418 (2672962)
 
 HIERARCHICAL CONNECTIVITY marked on layer met3
 
@@ -6057,106 +6070,106 @@
 -----------------------------------------------------------
 MR_capm.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_capm.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 121 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 121 OF 408  ELAPSED TIME = 98
 
-Layer MR_capm.1::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.1::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.1 COMPLETED. Number of Results = 0 (0)
 
-Layer MR_capm.2a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.2a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.2a COMPLETED. Number of Results = 0 (0)
 
 MR_capm.2b::<1> = COPY m3_bot_plate_err
 ---------------------------------------
 MR_capm.2b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 122 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 122 OF 408  ELAPSED TIME = 98
 
-Layer m3_bot_plate_err DELETED -- LVHEAP = 43/81/83
+Layer m3_bot_plate_err DELETED -- LVHEAP = 44/81/83
 
-Layer MR_capm.2b::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.2b::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.2b COMPLETED. Number of Results = 0 (0)
 
 MR_capm.2b_a::<1> = EXT m3_bot_plate < 1.2 REGION NOT CONNECTED ABUT < 90 SINGULAR
 ----------------------------------------------------------------------------------
 MR_capm.2b_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 123 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 123 OF 408  ELAPSED TIME = 98
 
-Layer m3_bot_plate DELETED -- LVHEAP = 43/81/83
+Layer m3_bot_plate DELETED -- LVHEAP = 44/81/83
 
-Layer MR_capm.2b_a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.2b_a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.2b_a COMPLETED. Number of Results = 0 (0)
 
 MR_capm.3::q1capmand = capm AND met3
 ------------------------------------
 MR_capm.3::q1capmand (HIER TYP=1 CFG=1 HGC=1 FGC=1 HEC=4 FEC=4 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 124 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 124 OF 408  ELAPSED TIME = 98
 
 MR_capm.3::<1> = ENC MR_capm.3::q1capmand met3 < 0.14 MEASURE ALL ABUT < 90 SINGULAR
 ------------------------------------------------------------------------------------
 MR_capm.3::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 125 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 125 OF 408  ELAPSED TIME = 98
 
-Layer MR_capm.3::q1capmand DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.3::q1capmand DELETED -- LVHEAP = 44/81/83
 
-Layer MR_capm.3::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.3::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.3 COMPLETED. Number of Results = 0 (0)
 
 MR_capm.4::q3via3and = via3 AND capm
 ------------------------------------
 MR_capm.4::q3via3and (HIER TYP=1 CFG=1 HGC=518 FGC=518 HEC=2072 FEC=2072 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 126 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 126 OF 408  ELAPSED TIME = 98
 
 MR_capm.4::<1> = ENC MR_capm.4::q3via3and capm < 0.14 MEASURE ALL ABUT < 90 SINGULAR
 ------------------------------------------------------------------------------------
 MR_capm.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 127 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 127 OF 408  ELAPSED TIME = 98
 
-Layer MR_capm.4::q3via3and DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.4::q3via3and DELETED -- LVHEAP = 44/81/83
 
-Layer MR_capm.4::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.4::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.4 COMPLETED. Number of Results = 0 (0)
 
 MR_capm.5::<1> = EXT capm via3 < 0.14 REGION ABUT < 90 SINGULAR
 ---------------------------------------------------------------
 MR_capm.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 128 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 128 OF 408  ELAPSED TIME = 98
 
-Layer capm DELETED -- LVHEAP = 43/81/83
+Layer capm DELETED -- LVHEAP = 44/81/83
 
-Layer MR_capm.5::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_capm.5::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_capm.5 COMPLETED. Number of Results = 0 (0)
 
 TMP<16> = cap2m AND met4
 ------------------------
 TMP<16> (HIER TYP=1 CFG=1 HGC=21 FGC=31 HEC=84 FEC=124 IGC=26 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 129 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 129 OF 408  ELAPSED TIME = 98
 
 m4_bot_plate = SIZE TMP<16> BY 0.14
 -----------------------------------
 m4_bot_plate (HIER TYP=1 CFG=3 HGC=28 FGC=38 HEC=112 FEC=152 IGC=26 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 130 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 130 OF 408  ELAPSED TIME = 98
 
-Layer TMP<16> DELETED -- LVHEAP = 43/81/83
+Layer TMP<16> DELETED -- LVHEAP = 44/81/83
 
 TMP<17> = EXT m4_bot_plate < 1.2 REGION
 ---------------------------------------
 TMP<17> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 131 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 131 OF 408  ELAPSED TIME = 98
 
 m4_bot_plate_err = TMP<17> INTERACT met4 > 1 BY NET
 ---------------------------------------------------
 m4_bot_plate_err (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 132 OF 408  ELAPSED TIME = 100
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 132 OF 408  ELAPSED TIME = 98
 
-Layer TMP<17> DELETED -- LVHEAP = 43/81/83
+Layer TMP<17> DELETED -- LVHEAP = 44/81/83
 
-CONNECT started.  LVHEAP = 43/82/83  ELAPSED TIME = 100
+CONNECT started.  LVHEAP = 44/82/83  ELAPSED TIME = 98
 
 CONNECT m4_bot_plate met4 ...
 
@@ -6165,9 +6178,9 @@
 
 NODE UPDATE completed. CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/82/83
 
-CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  ELAPSED TIME = 101
+CONNECT completed.  CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  ELAPSED TIME = 99
 
-NETS = 153224 (7933862)  EPINS = 55599 (2662332)
+NETS = 155464 (7981739)  EPINS = 56418 (2672962)
 
 HIERARCHICAL CONNECTIVITY marked on layer met3
 
@@ -6180,78 +6193,78 @@
 -------------------------------------------------------------
 MR_cap2m.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_cap2m.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 134 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 134 OF 408  ELAPSED TIME = 99
 
-Layer MR_cap2m.1::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.1::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.1 COMPLETED. Number of Results = 0 (0)
 
-Layer MR_cap2m.2a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.2a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.2a COMPLETED. Number of Results = 0 (0)
 
 MR_cap2m.2b::<1> = COPY m4_bot_plate_err
 ----------------------------------------
 MR_cap2m.2b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 135 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 135 OF 408  ELAPSED TIME = 99
 
-Layer m4_bot_plate_err DELETED -- LVHEAP = 43/81/83
+Layer m4_bot_plate_err DELETED -- LVHEAP = 44/81/83
 
-Layer MR_cap2m.2b::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.2b::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.2b COMPLETED. Number of Results = 0 (0)
 
 MR_cap2m.2b_a::<1> = EXT m4_bot_plate < 1.2 REGION NOT CONNECTED ABUT < 90 SINGULAR
 -----------------------------------------------------------------------------------
 MR_cap2m.2b_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 136 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 136 OF 408  ELAPSED TIME = 99
 
-Layer m4_bot_plate DELETED -- LVHEAP = 43/81/83
+Layer m4_bot_plate DELETED -- LVHEAP = 44/81/83
 
-Layer MR_cap2m.2b_a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.2b_a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.2b_a COMPLETED. Number of Results = 0 (0)
 
 MR_cap2m.3::q1cap2mand = cap2m AND met4
 ---------------------------------------
 MR_cap2m.3::q1cap2mand (HIER TYP=1 CFG=1 HGC=21 FGC=31 HEC=84 FEC=124 IGC=26 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 137 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 137 OF 408  ELAPSED TIME = 99
 
 MR_cap2m.3::<1> = ENC MR_cap2m.3::q1cap2mand met4 < 0.14 MEASURE ALL ABUT < 90 SINGULAR
 ---------------------------------------------------------------------------------------
 MR_cap2m.3::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 138 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 138 OF 408  ELAPSED TIME = 99
 
-Layer MR_cap2m.3::q1cap2mand DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.3::q1cap2mand DELETED -- LVHEAP = 44/81/83
 
-Layer MR_cap2m.3::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.3::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.3 COMPLETED. Number of Results = 0 (0)
 
 MR_cap2m.4::q3via4and = via4 AND cap2m
 --------------------------------------
 MR_cap2m.4::q3via4and (HIER TYP=1 CFG=1 HGC=2052 FGC=3096 HEC=8208 FEC=12384 IGC=14 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 139 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 139 OF 408  ELAPSED TIME = 99
 
 MR_cap2m.4::<1> = ENC MR_cap2m.4::q3via4and cap2m < 0.2 MEASURE ALL ABUT < 90 SINGULAR
 --------------------------------------------------------------------------------------
 MR_cap2m.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 140 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 140 OF 408  ELAPSED TIME = 99
 
-Layer MR_cap2m.4::q3via4and DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.4::q3via4and DELETED -- LVHEAP = 44/81/83
 
-Layer MR_cap2m.4::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.4::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.4 COMPLETED. Number of Results = 0 (0)
 
 MR_cap2m.5::<1> = EXT cap2m via4 < 0.2 REGION ABUT < 90 SINGULAR
 ----------------------------------------------------------------
 MR_cap2m.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 141 OF 408  ELAPSED TIME = 101
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 141 OF 408  ELAPSED TIME = 99
 
-Layer cap2m DELETED -- LVHEAP = 43/81/83
+Layer cap2m DELETED -- LVHEAP = 44/81/83
 
-Layer MR_cap2m.5::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_cap2m.5::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_cap2m.5 COMPLETED. Number of Results = 0 (0)
 
@@ -6260,122 +6273,122 @@
 ----------------------------------------------------------------------
 MR_m1.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_m1.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 4  REAL TIME = 4  LVHEAP = 43/81/83  OPS COMPLETE = 143 OF 408  ELAPSED TIME = 105
+CPU TIME = 4  REAL TIME = 4  LVHEAP = 44/81/83  OPS COMPLETE = 143 OF 408  ELAPSED TIME = 103
 
-Layer MR_m1.1::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.1::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.1 COMPLETED. Number of Results = 0 (0)
 
-Layer MR_m1.2::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.2::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.2 COMPLETED. Number of Results = 0 (0)
 
 q0Hugemet1 = met1 WITH WIDTH > 3
 --------------------------------
 q0Hugemet1 (HIER TYP=1 CFG=1 HGC=66 FGC=500 HEC=698 FEC=4244 IGC=173 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 43/81/83  OPS COMPLETE = 144 OF 408  ELAPSED TIME = 108
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 44/81/83  OPS COMPLETE = 144 OF 408  ELAPSED TIME = 107
 
 q1Hugemet1 = SIZE q0Hugemet1 BY 0.28 INSIDE OF met1 STEP 0.28
 -------------------------------------------------------------
 q1Hugemet1 (HIER TYP=1 CFG=0 HGC=74 FGC=587 HEC=1022 FEC=6114 IGC=184 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 145 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 145 OF 408  ELAPSED TIME = 107
 
 q2Hugemet1 = q1Hugemet1 NOT q0Hugemet1
 --------------------------------------
 q2Hugemet1 (HIER TYP=1 CFG=1 HGC=186 FGC=1317 HEC=813 FEC=5989 IGC=322 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 146 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 146 OF 408  ELAPSED TIME = 107
 
-Layer q1Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q1Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 TMP<18> = q2Hugemet1 COINCIDENT OUTSIDE EDGE q0Hugemet1
 -------------------------------------------------------
 TMP<18> (HIER-PMF TYP=2 CFG=1 HGC=206 FGC=1506 HEC=206 FEC=1506 IGC=111 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 147 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 147 OF 408  ELAPSED TIME = 107
 
 q3Hugemet1 = q2Hugemet1 WITH EDGE TMP<18>
 -----------------------------------------
 q3Hugemet1 (HIER TYP=1 CFG=0 HGC=178 FGC=1230 HEC=788 FEC=5695 IGC=322 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 148 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 148 OF 408  ELAPSED TIME = 107
 
-Layer q2Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q2Hugemet1 DELETED -- LVHEAP = 44/81/83
 
-Layer TMP<18> DELETED -- LVHEAP = 43/81/83
+Layer TMP<18> DELETED -- LVHEAP = 44/81/83
 
 q4Hugemet1 = q3Hugemet1 OR q0Hugemet1
 -------------------------------------
 q4Hugemet1 (HIER TYP=1 CFG=1 HGC=66 FGC=500 HEC=997 FEC=5820 IGC=183 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 149 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 149 OF 408  ELAPSED TIME = 107
 
-Layer q3Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q3Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 q5Hugemet1 = SNAP q4Hugemet1 1
 ------------------------------
 q5Hugemet1 (HIER TYP=1 CFG=1 HGC=92 FGC=1102 HEC=1111 FEC=8494 IGC=160 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 150 OF 408  ELAPSED TIME = 108
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 150 OF 408  ELAPSED TIME = 107
 
-Layer q4Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q4Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 q6Hugemet1 = met1 NOT q5Hugemet1
 --------------------------------
-q6Hugemet1 (HIER TYP=1 CFG=1 HGC=234398 FGC=1200712 HEC=3172810 FEC=8204265 IGC=12259 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 46/81/83  OPS COMPLETE = 151 OF 408  ELAPSED TIME = 110
+q6Hugemet1 (HIER TYP=1 CFG=1 HGC=241157 FGC=1210984 HEC=3282020 FEC=8329707 IGC=12271 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 47/81/83  OPS COMPLETE = 151 OF 408  ELAPSED TIME = 108
 
 q7Hugemet1 = EXT q0Hugemet1 q6Hugemet1 <= 0.275 REGION
 ------------------------------------------------------
 q7Hugemet1 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 152 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 152 OF 408  ELAPSED TIME = 108
 
-Layer q0Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q0Hugemet1 DELETED -- LVHEAP = 44/81/83
 
-Layer q6Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q6Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 TMP<19> = q7Hugemet1 INSIDE met1
 --------------------------------
 TMP<19> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 153 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 153 OF 408  ELAPSED TIME = 108
 
 q8Hugemet1 = q7Hugemet1 NOT TMP<19>
 -----------------------------------
 q8Hugemet1 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 154 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 154 OF 408  ELAPSED TIME = 108
 
-Layer q7Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q7Hugemet1 DELETED -- LVHEAP = 44/81/83
 
-Layer TMP<19> DELETED -- LVHEAP = 43/81/83
+Layer TMP<19> DELETED -- LVHEAP = 44/81/83
 
-Layer q8Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q8Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.3b COMPLETED. Number of Results = 0 (0)
 
 q9Hugemet1 = EXT q5Hugemet1 < 0.28 REGION ABUT < 90
 ---------------------------------------------------
 q9Hugemet1 (HIER TYP=1 CFG=1 HGC=1 FGC=33 HEC=3 FEC=99 IGC=7 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 155 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 155 OF 408  ELAPSED TIME = 108
 
-Layer q5Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q5Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 TMP<21> = q9Hugemet1 AND met1
 -----------------------------
 TMP<21> (HIER TYP=1 CFG=1 HGC=1 FGC=33 HEC=3 FEC=99 IGC=7 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 156 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 156 OF 408  ELAPSED TIME = 108
 
 TMP<20> = q9Hugemet1 INTERACT TMP<21>
 -------------------------------------
 TMP<20> (HIER TYP=1 CFG=0 HGC=1 FGC=33 HEC=3 FEC=99 IGC=7 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 157 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 157 OF 408  ELAPSED TIME = 108
 
-Layer TMP<21> DELETED -- LVHEAP = 43/81/83
+Layer TMP<21> DELETED -- LVHEAP = 44/81/83
 
 q10Hugemet1 = q9Hugemet1 NOT TMP<20>
 ------------------------------------
 q10Hugemet1 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 158 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 158 OF 408  ELAPSED TIME = 108
 
-Layer q9Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q9Hugemet1 DELETED -- LVHEAP = 44/81/83
 
-Layer TMP<20> DELETED -- LVHEAP = 43/81/83
+Layer TMP<20> DELETED -- LVHEAP = 44/81/83
 
-Layer q10Hugemet1 DELETED -- LVHEAP = 43/81/83
+Layer q10Hugemet1 DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.3a COMPLETED. Number of Results = 0 (0)
 
@@ -6383,29 +6396,29 @@
                    s8fs_cmux4_fm
 ---------------------------------------
 s8spf_cells_m1_4 (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 159 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 159 OF 408  ELAPSED TIME = 108
 
 mcon_PERI_4a = mcon_PERI AND s8spf_cells_m1_4
 ---------------------------------------------
 mcon_PERI_4a (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 160 OF 408  ELAPSED TIME = 110
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 160 OF 408  ELAPSED TIME = 108
 
-Layer s8spf_cells_m1_4 DELETED -- LVHEAP = 43/81/83
+Layer s8spf_cells_m1_4 DELETED -- LVHEAP = 44/81/83
 
 mcon_PERI_4 = mcon_PERI NOT mcon_PERI_4a
 ----------------------------------------
-mcon_PERI_4 (HIER TYP=1 CFG=0 HGC=403733 FGC=6045396 HEC=1614932 FEC=24181584 IGC=50168 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 161 OF 408  ELAPSED TIME = 110
+mcon_PERI_4 (HIER TYP=1 CFG=0 HGC=411362 FGC=6053194 HEC=1645448 FEC=24212776 IGC=50789 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 161 OF 408  ELAPSED TIME = 108
 
 MR_791_m1.4::q0mcon_PERI_4and = mcon_PERI_4 AND met1
 ----------------------------------------------------
-MR_791_m1.4::q0mcon_PERI_4and (HIER TYP=1 CFG=1 HGC=403733 FGC=6045396 HEC=1614932 FEC=24181584 IGC=50175 VHC=F VPC=F)
-CPU TIME = 4  REAL TIME = 4  LVHEAP = 44/81/83  OPS COMPLETE = 162 OF 408  ELAPSED TIME = 114
+MR_791_m1.4::q0mcon_PERI_4and (HIER TYP=1 CFG=1 HGC=411362 FGC=6053194 HEC=1645448 FEC=24212776 IGC=50796 VHC=F VPC=F)
+CPU TIME = 4  REAL TIME = 4  LVHEAP = 45/81/83  OPS COMPLETE = 162 OF 408  ELAPSED TIME = 112
 
 MR_791_m1.4::<1> = ENC MR_791_m1.4::q0mcon_PERI_4and met1 < 0.03 MEASURE ALL ABUT < 90 SINGULAR
 -----------------------------------------------------------------------------------------------
 MR_791_m1.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 163 OF 408  ELAPSED TIME = 114
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 163 OF 408  ELAPSED TIME = 113
 
 Layer MR_791_m1.4::q0mcon_PERI_4and DELETED -- LVHEAP = 44/81/83
 
@@ -6416,130 +6429,130 @@
 MR_m1.4::<1> = mcon_PERI_4 NOT met1
 -----------------------------------
 MR_m1.4::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 164 OF 408  ELAPSED TIME = 115
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 164 OF 408  ELAPSED TIME = 114
 
-Layer mcon_PERI_4 DELETED -- LVHEAP = 43/81/83
+Layer mcon_PERI_4 DELETED -- LVHEAP = 44/81/83
 
-Layer MR_m1.4::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.4::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.4 COMPLETED. Number of Results = 0 (0)
 
 MR_m1.4a::q0mcon_PERI_4aand = mcon_PERI_4a AND met1
 ---------------------------------------------------
 MR_m1.4a::q0mcon_PERI_4aand (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 165 OF 408  ELAPSED TIME = 115
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 165 OF 408  ELAPSED TIME = 114
 
 MR_m1.4a::<1> = ENC MR_m1.4a::q0mcon_PERI_4aand met1 < 0.005 MEASURE ALL ABUT < 90 SINGULAR
 -------------------------------------------------------------------------------------------
 MR_m1.4a::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 166 OF 408  ELAPSED TIME = 115
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 166 OF 408  ELAPSED TIME = 114
 
-Layer MR_m1.4a::q0mcon_PERI_4aand DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.4a::q0mcon_PERI_4aand DELETED -- LVHEAP = 44/81/83
 
-Layer MR_m1.4a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.4a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.4a COMPLETED. Number of Results = 0 (0)
 
 MR_m1.4a_a::<1> = mcon_PERI_4a NOT met1
 ---------------------------------------
 MR_m1.4a_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 167 OF 408  ELAPSED TIME = 115
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 167 OF 408  ELAPSED TIME = 114
 
-Layer mcon_PERI_4a DELETED -- LVHEAP = 43/81/83
+Layer mcon_PERI_4a DELETED -- LVHEAP = 44/81/83
 
-Layer MR_m1.4a_a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m1.4a_a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m1.4a_a COMPLETED. Number of Results = 0 (0)
 
 MR_m1.5::q0met1enc = ENC [mcon_PERI] met1 < 0.06 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 ---------------------------------------------------------------------------------------------------
-MR_m1.5::q0met1enc (HIER-PMF TYP=2 CFG=0 HGC=850768 FGC=2024092 HEC=850768 FEC=2024092 IGC=73995 VHC=F VPC=F)
-CPU TIME = 8  REAL TIME = 8  LVHEAP = 44/81/83  OPS COMPLETE = 168 OF 408  ELAPSED TIME = 123
+MR_m1.5::q0met1enc (HIER-PMF TYP=2 CFG=0 HGC=867230 FGC=2040526 HEC=867230 FEC=2040526 IGC=75100 VHC=F VPC=F)
+CPU TIME = 8  REAL TIME = 8  LVHEAP = 44/81/83  OPS COMPLETE = 168 OF 408  ELAPSED TIME = 122
 
 Layer mcon_PERI DELETED -- LVHEAP = 44/81/83
 
 MR_m1.5::TMP<22> = EXPAND EDGE MR_m1.5::q0met1enc INSIDE BY 0.005
 -----------------------------------------------------------------
-MR_m1.5::TMP<22> (HIER TYP=1 CFG=1 HGC=850768 FGC=2024092 HEC=3403072 FEC=8096368 IGC=73637 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 169 OF 408  ELAPSED TIME = 124
+MR_m1.5::TMP<22> (HIER TYP=1 CFG=1 HGC=867230 FGC=2040526 HEC=3468920 FEC=8162104 IGC=74737 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 169 OF 408  ELAPSED TIME = 123
 
 Layer MR_m1.5::q0met1enc DELETED -- LVHEAP = 44/81/83
 
 MR_m1.5::<1> = NOT RECTANGLE MR_m1.5::TMP<22> ORTHOGONAL ONLY
 -------------------------------------------------------------
 MR_m1.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 170 OF 408  ELAPSED TIME = 124
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 170 OF 408  ELAPSED TIME = 123
 
-Layer MR_m1.5::TMP<22> DELETED -- LVHEAP = 42/81/83
+Layer MR_m1.5::TMP<22> DELETED -- LVHEAP = 43/81/83
 
-Layer MR_m1.5::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m1.5::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m1.5 COMPLETED. Number of Results = 0 (0)
 
 MR_m1.6::<1> = AREA met1 < 0.083
 --------------------------------
 MR_m1.6::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 42/81/83  OPS COMPLETE = 171 OF 408  ELAPSED TIME = 126
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 171 OF 408  ELAPSED TIME = 124
 
-Layer MR_m1.6::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m1.6::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m1.6 COMPLETED. Number of Results = 0 (0)
 
 met1Hole = HOLES met1
 met1HoleEmpty = HOLES met1 INNER
 --------------------------------
-met1Hole (HIER TYP=1 CFG=1 HGC=147 FGC=2751 HEC=1292 FEC=20327 IGC=127 VHC=F VPC=F)
-met1HoleEmpty (HIER TYP=1 CFG=1 HGC=147 FGC=1451 HEC=1209 FEC=11933 IGC=160 VHC=F VPC=F)
-CPU TIME = 4  REAL TIME = 4  LVHEAP = 42/81/83  OPS COMPLETE = 173 OF 408  ELAPSED TIME = 129
+met1Hole (HIER TYP=1 CFG=1 HGC=147 FGC=2751 HEC=1284 FEC=20319 IGC=130 VHC=F VPC=F)
+met1HoleEmpty (HIER TYP=1 CFG=1 HGC=147 FGC=1451 HEC=1201 FEC=11925 IGC=163 VHC=F VPC=F)
+CPU TIME = 4  REAL TIME = 4  LVHEAP = 43/81/83  OPS COMPLETE = 173 OF 408  ELAPSED TIME = 128
 
 MR_m1.7::<1> = AREA met1Hole < 0.14
 -----------------------------------
 MR_m1.7::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 174 OF 408  ELAPSED TIME = 129
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 174 OF 408  ELAPSED TIME = 128
 
-Layer met1Hole DELETED -- LVHEAP = 42/81/83
+Layer met1Hole DELETED -- LVHEAP = 43/81/83
 
-Layer MR_m1.7::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m1.7::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m1.7 COMPLETED. Number of Results = 0 (0)
 
 MR_m1.7_a::<1> = AREA met1HoleEmpty < 0.14
 ------------------------------------------
 MR_m1.7_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 175 OF 408  ELAPSED TIME = 129
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 175 OF 408  ELAPSED TIME = 128
 
-Layer met1HoleEmpty DELETED -- LVHEAP = 42/81/83
+Layer met1HoleEmpty DELETED -- LVHEAP = 43/81/83
 
-Layer MR_m1.7_a::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m1.7_a::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m1.7_a COMPLETED. Number of Results = 0 (0)
 
 ringVIA = DONUT via
 -------------------
 ringVIA (HIER-FMF TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 176 OF 408  ELAPSED TIME = 129
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 176 OF 408  ELAPSED TIME = 128
 
 rectVIA = via NOT ringVIA
 -------------------------
-rectVIA (HIER TYP=1 CFG=1 HGC=440126 FGC=1225732 HEC=1760506 FEC=4902930 IGC=103967 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 177 OF 408  ELAPSED TIME = 129
+rectVIA (HIER TYP=1 CFG=1 HGC=450311 FGC=1235840 HEC=1801246 FEC=4943362 IGC=104729 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 177 OF 408  ELAPSED TIME = 128
 
 moduleCutAREA = OR moduleCutAREA
 --------------------------------
 moduleCutAREA (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 178 OF 408  ELAPSED TIME = 129
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 178 OF 408  ELAPSED TIME = 128
 
-Original Layer moduleCutAREA DELETED -- LVHEAP = 43/81/83
+Original Layer moduleCutAREA DELETED -- LVHEAP = 44/81/83
 
 rectVIAnoMT = rectVIA NOT moduleCutAREA
 ---------------------------------------
-rectVIAnoMT (HIER TYP=1 CFG=1 HGC=440126 FGC=1225732 HEC=1760506 FEC=4902930 IGC=103967 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 179 OF 408  ELAPSED TIME = 130
+rectVIAnoMT (HIER TYP=1 CFG=1 HGC=450311 FGC=1235840 HEC=1801246 FEC=4943362 IGC=104729 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 179 OF 408  ELAPSED TIME = 128
 
 q0rectVIAnoMT = NOT RECTANGLE rectVIAnoMT ORTHOGONAL ONLY
 ---------------------------------------------------------
 q0rectVIAnoMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 180 OF 408  ELAPSED TIME = 130
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 180 OF 408  ELAPSED TIME = 128
 
 Layer q0rectVIAnoMT DELETED -- LVHEAP = 44/81/83
 
@@ -6548,7 +6561,7 @@
 q1rectVIAnoMT = INT rectVIAnoMT < 0.15 REGION
 ---------------------------------------------
 q1rectVIAnoMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 181 OF 408  ELAPSED TIME = 130
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 181 OF 408  ELAPSED TIME = 129
 
 Layer q1rectVIAnoMT DELETED -- LVHEAP = 44/81/83
 
@@ -6557,120 +6570,120 @@
 TMP<25> = LENGTH rectVIAnoMT > 0.15
 -----------------------------------
 TMP<25> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 182 OF 408  ELAPSED TIME = 130
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 182 OF 408  ELAPSED TIME = 129
 
 q2rectVIAnoMT = rectVIAnoMT WITH EDGE TMP<25>
 ---------------------------------------------
 q2rectVIAnoMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 183 OF 408  ELAPSED TIME = 130
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 183 OF 408  ELAPSED TIME = 129
 
-Layer rectVIAnoMT DELETED -- LVHEAP = 43/81/83
+Layer rectVIAnoMT DELETED -- LVHEAP = 44/81/83
 
-Layer TMP<25> DELETED -- LVHEAP = 43/81/83
+Layer TMP<25> DELETED -- LVHEAP = 44/81/83
 
-Layer q2rectVIAnoMT DELETED -- LVHEAP = 43/81/83
+Layer q2rectVIAnoMT DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.1a_b COMPLETED. Number of Results = 0 (0)
 
 MR_via.2::<1> = EXT via < 0.17 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------
 MR_via.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 184 OF 408  ELAPSED TIME = 131
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 184 OF 408  ELAPSED TIME = 130
 
-Layer MR_via.2::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.2::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.2 COMPLETED. Number of Results = 0 (0)
 
 MR_via.3::<1> = INT ringVIA < 0.2 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 -------------------------------------------------------------------------
 MR_via.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 185 OF 408  ELAPSED TIME = 131
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 185 OF 408  ELAPSED TIME = 130
 
-Layer MR_via.3::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.3::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.3 COMPLETED. Number of Results = 0 (0)
 
 MR_via.3_a::q0ringVIA = SIZE ringVIA BY -0.102
 ----------------------------------------------
 MR_via.3_a::q0ringVIA (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 186 OF 408  ELAPSED TIME = 131
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 186 OF 408  ELAPSED TIME = 130
 
 MR_via.3_a::<1> = SIZE MR_via.3_a::q0ringVIA BY 0.102
 -----------------------------------------------------
 MR_via.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 187 OF 408  ELAPSED TIME = 131
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 187 OF 408  ELAPSED TIME = 130
 
-Layer MR_via.3_a::q0ringVIA DELETED -- LVHEAP = 43/81/83
+Layer MR_via.3_a::q0ringVIA DELETED -- LVHEAP = 44/81/83
 
-Layer MR_via.3_a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.3_a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.3_a COMPLETED. Number of Results = 0 (0)
 
 MR_via.3_b::<1> = ringVIA NOT SEALID
 ------------------------------------
 MR_via.3_b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 188 OF 408  ELAPSED TIME = 131
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 188 OF 408  ELAPSED TIME = 130
 
-Layer ringVIA DELETED -- LVHEAP = 43/81/83
+Layer ringVIA DELETED -- LVHEAP = 44/81/83
 
-Layer MR_via.3_b::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.3_b::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.3_b COMPLETED. Number of Results = 0 (0)
 
 rectVIAa = RECTANGLE rectVIA == 0.15 BY == 0.15 ORTHOGONAL ONLY
 ---------------------------------------------------------------
-rectVIAa (HIER TYP=1 CFG=1 HGC=440126 FGC=1225732 HEC=1760506 FEC=4902930 IGC=103967 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 189 OF 408  ELAPSED TIME = 131
+rectVIAa (HIER TYP=1 CFG=1 HGC=450311 FGC=1235840 HEC=1801246 FEC=4943362 IGC=104729 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 189 OF 408  ELAPSED TIME = 130
 
-Layer rectVIA DELETED -- LVHEAP = 43/81/83
+Layer rectVIA DELETED -- LVHEAP = 44/81/83
 
 MR_via.4a::q0rectVIAaand = rectVIAa AND met1
 --------------------------------------------
-MR_via.4a::q0rectVIAaand (HIER TYP=1 CFG=1 HGC=440136 FGC=1225742 HEC=1760546 FEC=4902970 IGC=103974 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 44/81/83  OPS COMPLETE = 190 OF 408  ELAPSED TIME = 134
+MR_via.4a::q0rectVIAaand (HIER TYP=1 CFG=1 HGC=450321 FGC=1235850 HEC=1801286 FEC=4943402 IGC=104736 VHC=F VPC=F)
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 44/81/83  OPS COMPLETE = 190 OF 408  ELAPSED TIME = 133
 
 MR_via.4a::<1> = ENC MR_via.4a::q0rectVIAaand met1 < 0.055 MEASURE ALL ABUT < 90 SINGULAR
 -----------------------------------------------------------------------------------------
 MR_via.4a::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 191 OF 408  ELAPSED TIME = 135
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 191 OF 408  ELAPSED TIME = 134
 
-Layer MR_via.4a::q0rectVIAaand DELETED -- LVHEAP = 43/81/83
+Layer MR_via.4a::q0rectVIAaand DELETED -- LVHEAP = 44/81/83
 
-Layer MR_via.4a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.4a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.4a COMPLETED. Number of Results = 0 (0)
 
 MR_via.4a_a::<1> = rectVIAa NOT met1
 ------------------------------------
 MR_via.4a_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 192 OF 408  ELAPSED TIME = 136
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 192 OF 408  ELAPSED TIME = 135
 
-Layer MR_via.4a_a::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_via.4a_a::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_via.4a_a COMPLETED. Number of Results = 0 (0)
 
 MR_via.5a::q1met1enc = ENC [rectVIAa] met1 < 0.085 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 -----------------------------------------------------------------------------------------------------
-MR_via.5a::q1met1enc (HIER-PMF TYP=2 CFG=0 HGC=604131 FGC=1047462 HEC=604131 FEC=1047462 IGC=110638 VHC=F VPC=F)
-CPU TIME = 7  REAL TIME = 7  LVHEAP = 43/81/83  OPS COMPLETE = 193 OF 408  ELAPSED TIME = 143
+MR_via.5a::q1met1enc (HIER-PMF TYP=2 CFG=0 HGC=624802 FGC=1068107 HEC=624802 FEC=1068107 IGC=111931 VHC=F VPC=F)
+CPU TIME = 7  REAL TIME = 7  LVHEAP = 44/81/83  OPS COMPLETE = 193 OF 408  ELAPSED TIME = 142
 
-Layer rectVIAa DELETED -- LVHEAP = 43/81/83
+Layer rectVIAa DELETED -- LVHEAP = 44/81/83
 
 MR_via.5a::TMP<26> = EXPAND EDGE MR_via.5a::q1met1enc INSIDE BY 0.005
 ---------------------------------------------------------------------
-MR_via.5a::TMP<26> (HIER TYP=1 CFG=1 HGC=604131 FGC=1047462 HEC=2416524 FEC=4189848 IGC=110198 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 194 OF 408  ELAPSED TIME = 144
+MR_via.5a::TMP<26> (HIER TYP=1 CFG=1 HGC=624802 FGC=1068107 HEC=2499208 FEC=4272428 IGC=111491 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 194 OF 408  ELAPSED TIME = 143
 
-Layer MR_via.5a::q1met1enc DELETED -- LVHEAP = 43/81/83
+Layer MR_via.5a::q1met1enc DELETED -- LVHEAP = 44/81/83
 
 MR_via.5a::<1> = NOT RECTANGLE MR_via.5a::TMP<26> ORTHOGONAL ONLY
 -----------------------------------------------------------------
 MR_via.5a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 195 OF 408  ELAPSED TIME = 144
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 195 OF 408  ELAPSED TIME = 143
 
-Layer MR_via.5a::TMP<26> DELETED -- LVHEAP = 42/81/83
+Layer MR_via.5a::TMP<26> DELETED -- LVHEAP = 43/81/83
 
-Layer MR_via.5a::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_via.5a::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_via.5a COMPLETED. Number of Results = 0 (0)
 
@@ -6679,175 +6692,175 @@
 ----------------------------------------------------------------------
 MR_m2.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_m2.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 42/81/83  OPS COMPLETE = 197 OF 408  ELAPSED TIME = 146
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 43/81/83  OPS COMPLETE = 197 OF 408  ELAPSED TIME = 145
 
-Layer MR_m2.1::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m2.1::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m2.1 COMPLETED. Number of Results = 0 (0)
 
-Layer MR_m2.2::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m2.2::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m2.2 COMPLETED. Number of Results = 0 (0)
 
 q0Hugemet2 = met2 WITH WIDTH > 3
 --------------------------------
 q0Hugemet2 (HIER TYP=1 CFG=1 HGC=112 FGC=741 HEC=1047 FEC=6808 IGC=377 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 42/81/83  OPS COMPLETE = 198 OF 408  ELAPSED TIME = 147
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 198 OF 408  ELAPSED TIME = 146
 
 q1Hugemet2 = SIZE q0Hugemet2 BY 0.28 INSIDE OF met2 STEP 0.28
 -------------------------------------------------------------
 q1Hugemet2 (HIER TYP=1 CFG=0 HGC=112 FGC=773 HEC=1143 FEC=7467 IGC=383 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 199 OF 408  ELAPSED TIME = 147
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 199 OF 408  ELAPSED TIME = 146
 
 q2Hugemet2 = q1Hugemet2 NOT q0Hugemet2
 --------------------------------------
 q2Hugemet2 (HIER TYP=1 CFG=1 HGC=65 FGC=492 HEC=286 FEC=2190 IGC=201 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 200 OF 408  ELAPSED TIME = 147
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 200 OF 408  ELAPSED TIME = 146
 
-Layer q1Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q1Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 TMP<27> = q2Hugemet2 COINCIDENT OUTSIDE EDGE q0Hugemet2
 -------------------------------------------------------
 TMP<27> (HIER-PMF TYP=2 CFG=1 HGC=73 FGC=493 HEC=73 FEC=493 IGC=104 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 201 OF 408  ELAPSED TIME = 147
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 201 OF 408  ELAPSED TIME = 146
 
 q3Hugemet2 = q2Hugemet2 WITH EDGE TMP<27>
 -----------------------------------------
 q3Hugemet2 (HIER TYP=1 CFG=0 HGC=64 FGC=459 HEC=283 FEC=2091 IGC=201 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 202 OF 408  ELAPSED TIME = 147
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 202 OF 408  ELAPSED TIME = 146
 
-Layer q2Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q2Hugemet2 DELETED -- LVHEAP = 43/81/83
 
-Layer TMP<27> DELETED -- LVHEAP = 42/81/83
+Layer TMP<27> DELETED -- LVHEAP = 43/81/83
 
 q4Hugemet2 = q3Hugemet2 OR q0Hugemet2
 -------------------------------------
 q4Hugemet2 (HIER TYP=1 CFG=1 HGC=112 FGC=741 HEC=1122 FEC=7350 IGC=389 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 203 OF 408  ELAPSED TIME = 147
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 203 OF 408  ELAPSED TIME = 146
 
-Layer q3Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q3Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 q5Hugemet2 = SNAP q4Hugemet2 1
 ------------------------------
 q5Hugemet2 (HIER TYP=1 CFG=1 HGC=125 FGC=722 HEC=1144 FEC=6668 IGC=349 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 204 OF 408  ELAPSED TIME = 148
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 204 OF 408  ELAPSED TIME = 146
 
-Layer q4Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q4Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 q6Hugemet2 = met2 NOT q5Hugemet2
 --------------------------------
-q6Hugemet2 (HIER TYP=1 CFG=1 HGC=197684 FGC=335000 HEC=2252440 FEC=3338312 IGC=29412 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 205 OF 408  ELAPSED TIME = 148
+q6Hugemet2 (HIER TYP=1 CFG=1 HGC=203447 FGC=340734 HEC=2333494 FEC=3419144 IGC=29649 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 45/81/83  OPS COMPLETE = 205 OF 408  ELAPSED TIME = 147
 
 q7Hugemet2 = EXT q0Hugemet2 q6Hugemet2 <= 0.275 REGION
 ------------------------------------------------------
 q7Hugemet2 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 206 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 206 OF 408  ELAPSED TIME = 147
 
-Layer q0Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q0Hugemet2 DELETED -- LVHEAP = 43/81/83
 
-Layer q6Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q6Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 TMP<28> = q7Hugemet2 INSIDE met2
 --------------------------------
 TMP<28> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 207 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 207 OF 408  ELAPSED TIME = 147
 
 q8Hugemet2 = q7Hugemet2 NOT TMP<28>
 -----------------------------------
 q8Hugemet2 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 208 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 208 OF 408  ELAPSED TIME = 147
 
-Layer q7Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q7Hugemet2 DELETED -- LVHEAP = 43/81/83
 
-Layer TMP<28> DELETED -- LVHEAP = 42/81/83
+Layer TMP<28> DELETED -- LVHEAP = 43/81/83
 
-Layer q8Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q8Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m2.3b COMPLETED. Number of Results = 0 (0)
 
 q9Hugemet2 = EXT q5Hugemet2 < 0.28 REGION ABUT < 90
 ---------------------------------------------------
 q9Hugemet2 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 209 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 209 OF 408  ELAPSED TIME = 147
 
-Layer q5Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q5Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 TMP<30> = q9Hugemet2 AND met2
 -----------------------------
 TMP<30> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 210 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 210 OF 408  ELAPSED TIME = 147
 
 TMP<29> = q9Hugemet2 INTERACT TMP<30>
 -------------------------------------
 TMP<29> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 211 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 211 OF 408  ELAPSED TIME = 147
 
-Layer TMP<30> DELETED -- LVHEAP = 42/81/83
+Layer TMP<30> DELETED -- LVHEAP = 43/81/83
 
 q10Hugemet2 = q9Hugemet2 NOT TMP<29>
 ------------------------------------
 q10Hugemet2 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 212 OF 408  ELAPSED TIME = 149
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 212 OF 408  ELAPSED TIME = 147
 
-Layer q9Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q9Hugemet2 DELETED -- LVHEAP = 43/81/83
 
-Layer TMP<29> DELETED -- LVHEAP = 42/81/83
+Layer TMP<29> DELETED -- LVHEAP = 43/81/83
 
-Layer q10Hugemet2 DELETED -- LVHEAP = 42/81/83
+Layer q10Hugemet2 DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m2.3a COMPLETED. Number of Results = 0 (0)
 
 via_PERI = via NOT COREID
 -------------------------
-via_PERI (HIER TYP=1 CFG=0 HGC=440105 FGC=1107432 HEC=1760422 FEC=4429730 IGC=103967 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 213 OF 408  ELAPSED TIME = 149
+via_PERI (HIER TYP=1 CFG=0 HGC=450290 FGC=1117540 HEC=1801162 FEC=4470162 IGC=104729 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 44/81/83  OPS COMPLETE = 213 OF 408  ELAPSED TIME = 148
 
 MR_m2.4::q0via_PERIand = via_PERI AND met2
 ------------------------------------------
-MR_m2.4::q0via_PERIand (HIER TYP=1 CFG=1 HGC=440105 FGC=1107432 HEC=1760422 FEC=4429730 IGC=103968 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 214 OF 408  ELAPSED TIME = 150
+MR_m2.4::q0via_PERIand (HIER TYP=1 CFG=1 HGC=450290 FGC=1117540 HEC=1801162 FEC=4470162 IGC=104730 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 214 OF 408  ELAPSED TIME = 148
 
 MR_m2.4::<1> = ENC MR_m2.4::q0via_PERIand met2 < 0.055 MEASURE ALL ABUT < 90 SINGULAR
 -------------------------------------------------------------------------------------
 MR_m2.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 215 OF 408  ELAPSED TIME = 150
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 44/81/83  OPS COMPLETE = 215 OF 408  ELAPSED TIME = 149
 
-Layer MR_m2.4::q0via_PERIand DELETED -- LVHEAP = 43/81/83
+Layer MR_m2.4::q0via_PERIand DELETED -- LVHEAP = 44/81/83
 
-Layer MR_m2.4::<1> DELETED -- LVHEAP = 43/81/83
+Layer MR_m2.4::<1> DELETED -- LVHEAP = 44/81/83
 
 DRC RuleCheck MR_m2.4 COMPLETED. Number of Results = 0 (0)
 
 MR_m2.4_a::<1> = via_PERI NOT met2
 ----------------------------------
 MR_m2.4_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 216 OF 408  ELAPSED TIME = 150
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/81/83  OPS COMPLETE = 216 OF 408  ELAPSED TIME = 149
 
-Layer via_PERI DELETED -- LVHEAP = 42/81/83
+Layer via_PERI DELETED -- LVHEAP = 43/81/83
 
-Layer MR_m2.4_a::<1> DELETED -- LVHEAP = 42/81/83
+Layer MR_m2.4_a::<1> DELETED -- LVHEAP = 43/81/83
 
 DRC RuleCheck MR_m2.4_a COMPLETED. Number of Results = 0 (0)
 
 MR_m2.5::q0met2enc = ENC [via] met2 < 0.085 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 ----------------------------------------------------------------------------------------------
-MR_m2.5::q0met2enc (HIER-PMF TYP=2 CFG=0 HGC=659713 FGC=930044 HEC=659713 FEC=930044 IGC=134883 VHC=F VPC=F)
-CPU TIME = 4  REAL TIME = 4  LVHEAP = 43/81/83  OPS COMPLETE = 217 OF 408  ELAPSED TIME = 154
+MR_m2.5::q0met2enc (HIER-PMF TYP=2 CFG=0 HGC=680428 FGC=950700 HEC=680428 FEC=950700 IGC=134031 VHC=F VPC=F)
+CPU TIME = 4  REAL TIME = 4  LVHEAP = 43/81/83  OPS COMPLETE = 217 OF 408  ELAPSED TIME = 153
 
 Layer via DELETED -- LVHEAP = 43/81/83
 
 MR_m2.5::TMP<31> = EXPAND EDGE MR_m2.5::q0met2enc INSIDE BY 0.005
 -----------------------------------------------------------------
-MR_m2.5::TMP<31> (HIER TYP=1 CFG=1 HGC=659713 FGC=930044 HEC=2638852 FEC=3720176 IGC=133741 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 218 OF 408  ELAPSED TIME = 155
+MR_m2.5::TMP<31> (HIER TYP=1 CFG=1 HGC=680428 FGC=950700 HEC=2721712 FEC=3802800 IGC=133117 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 43/81/83  OPS COMPLETE = 218 OF 408  ELAPSED TIME = 154
 
 Layer MR_m2.5::q0met2enc DELETED -- LVHEAP = 43/81/83
 
 MR_m2.5::<1> = NOT RECTANGLE MR_m2.5::TMP<31> ORTHOGONAL ONLY
 -------------------------------------------------------------
 MR_m2.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 219 OF 408  ELAPSED TIME = 156
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 219 OF 408  ELAPSED TIME = 155
 
 Layer MR_m2.5::TMP<31> DELETED -- LVHEAP = 42/81/83
 
@@ -6858,7 +6871,7 @@
 MR_m2.6::<1> = AREA met2 < 0.0676
 ---------------------------------
 MR_m2.6::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 220 OF 408  ELAPSED TIME = 156
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 220 OF 408  ELAPSED TIME = 155
 
 Layer MR_m2.6::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -6869,12 +6882,12 @@
 --------------------------------
 met2Hole (HIER TYP=1 CFG=1 HGC=2 FGC=6 HEC=16 FEC=48 IGC=4 VHC=F VPC=F)
 met2HoleEmpty (HIER TYP=1 CFG=1 HGC=2 FGC=6 HEC=16 FEC=48 IGC=4 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 42/81/83  OPS COMPLETE = 222 OF 408  ELAPSED TIME = 158
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 42/81/83  OPS COMPLETE = 222 OF 408  ELAPSED TIME = 157
 
 MR_m2.7::<1> = AREA met2Hole < 0.14
 -----------------------------------
 MR_m2.7::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 223 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 223 OF 408  ELAPSED TIME = 157
 
 Layer met2Hole DELETED -- LVHEAP = 42/81/83
 
@@ -6885,7 +6898,7 @@
 MR_m2.7_a::<1> = AREA met2HoleEmpty < 0.14
 ------------------------------------------
 MR_m2.7_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 224 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 224 OF 408  ELAPSED TIME = 157
 
 Layer met2HoleEmpty DELETED -- LVHEAP = 42/81/83
 
@@ -6896,24 +6909,24 @@
 ringVIA2 = DONUT via2
 ---------------------
 ringVIA2 (HIER-FMF TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 225 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 225 OF 408  ELAPSED TIME = 157
 
 rectVIA2 = via2 NOT ringVIA2
 ----------------------------
-rectVIA2 (HIER TYP=1 CFG=0 HGC=177946 FGC=812013 HEC=711784 FEC=3248052 IGC=108923 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 226 OF 408  ELAPSED TIME = 158
+rectVIA2 (HIER TYP=1 CFG=0 HGC=180431 FGC=814450 HEC=721724 FEC=3257800 IGC=110354 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 226 OF 408  ELAPSED TIME = 157
 
 rectVIA2noMT = rectVIA2 NOT moduleCutAREA
 -----------------------------------------
-rectVIA2noMT (HIER TYP=1 CFG=1 HGC=177946 FGC=812013 HEC=711784 FEC=3248052 IGC=108923 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 227 OF 408  ELAPSED TIME = 158
+rectVIA2noMT (HIER TYP=1 CFG=1 HGC=180431 FGC=814450 HEC=721724 FEC=3257800 IGC=110354 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 227 OF 408  ELAPSED TIME = 157
 
 Layer rectVIA2 DELETED -- LVHEAP = 42/81/83
 
 q0rectVIA2noMT = NOT RECTANGLE rectVIA2noMT ORTHOGONAL ONLY
 -----------------------------------------------------------
 q0rectVIA2noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 228 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 228 OF 408  ELAPSED TIME = 157
 
 Layer q0rectVIA2noMT DELETED -- LVHEAP = 42/81/83
 
@@ -6922,7 +6935,7 @@
 q1rectVIA2noMT = INT rectVIA2noMT < 0.2 REGION
 ----------------------------------------------
 q1rectVIA2noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 229 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 229 OF 408  ELAPSED TIME = 157
 
 Layer q1rectVIA2noMT DELETED -- LVHEAP = 42/81/83
 
@@ -6931,12 +6944,12 @@
 TMP<35> = LENGTH rectVIA2noMT > 0.2
 -----------------------------------
 TMP<35> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 230 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 230 OF 408  ELAPSED TIME = 157
 
 q2rectVIA2noMT = rectVIA2noMT WITH EDGE TMP<35>
 -----------------------------------------------
 q2rectVIA2noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 231 OF 408  ELAPSED TIME = 158
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 231 OF 408  ELAPSED TIME = 157
 
 Layer rectVIA2noMT DELETED -- LVHEAP = 42/81/83
 
@@ -6949,7 +6962,7 @@
 MR_via2.2::<1> = EXT via2 < 0.2 REGION ABUT < 90 SINGULAR
 ---------------------------------------------------------
 MR_via2.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 232 OF 408  ELAPSED TIME = 159
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 232 OF 408  ELAPSED TIME = 158
 
 Layer MR_via2.2::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -6958,7 +6971,7 @@
 MR_via2.3::<1> = INT ringVIA2 < 0.2 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ---------------------------------------------------------------------------
 MR_via2.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 233 OF 408  ELAPSED TIME = 159
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 233 OF 408  ELAPSED TIME = 158
 
 Layer MR_via2.3::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -6967,12 +6980,12 @@
 MR_via2.3_a::q0ringVIA2 = SIZE ringVIA2 BY -0.102
 -------------------------------------------------
 MR_via2.3_a::q0ringVIA2 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 234 OF 408  ELAPSED TIME = 159
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 234 OF 408  ELAPSED TIME = 158
 
 MR_via2.3_a::<1> = SIZE MR_via2.3_a::q0ringVIA2 BY 0.102
 --------------------------------------------------------
 MR_via2.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 235 OF 408  ELAPSED TIME = 159
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 235 OF 408  ELAPSED TIME = 158
 
 Layer MR_via2.3_a::q0ringVIA2 DELETED -- LVHEAP = 42/81/83
 
@@ -6983,7 +6996,7 @@
 MR_via2.3_b::<1> = ringVIA2 NOT SEALID
 --------------------------------------
 MR_via2.3_b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 236 OF 408  ELAPSED TIME = 159
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 236 OF 408  ELAPSED TIME = 158
 
 Layer ringVIA2 DELETED -- LVHEAP = 42/81/83
 
@@ -6993,13 +7006,13 @@
 
 MR_via2.4::q0via2and = via2 AND met2
 ------------------------------------
-MR_via2.4::q0via2and (HIER TYP=1 CFG=1 HGC=193445 FGC=812013 HEC=773780 FEC=3248052 IGC=108926 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 42/81/83  OPS COMPLETE = 237 OF 408  ELAPSED TIME = 159
+MR_via2.4::q0via2and (HIER TYP=1 CFG=1 HGC=195930 FGC=814450 HEC=783720 FEC=3257800 IGC=110357 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 42/81/83  OPS COMPLETE = 237 OF 408  ELAPSED TIME = 158
 
 MR_via2.4::<1> = ENC MR_via2.4::q0via2and met2 < 0.04 MEASURE ALL ABUT < 90 SINGULAR
 ------------------------------------------------------------------------------------
 MR_via2.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 238 OF 408  ELAPSED TIME = 160
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 238 OF 408  ELAPSED TIME = 159
 
 Layer MR_via2.4::q0via2and DELETED -- LVHEAP = 42/81/83
 
@@ -7010,7 +7023,7 @@
 MR_via2.4_a::<1> = via2 NOT met2
 --------------------------------
 MR_via2.4_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 239 OF 408  ELAPSED TIME = 160
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 239 OF 408  ELAPSED TIME = 159
 
 Layer MR_via2.4_a::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -7018,20 +7031,20 @@
 
 MR_via2.5::q1met2enc = ENC [via2] met2 < 0.085 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 -------------------------------------------------------------------------------------------------
-MR_via2.5::q1met2enc (HIER-PMF TYP=2 CFG=0 HGC=97752 FGC=175250 HEC=97752 FEC=175250 IGC=89597 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 42/81/83  OPS COMPLETE = 240 OF 408  ELAPSED TIME = 162
+MR_via2.5::q1met2enc (HIER-PMF TYP=2 CFG=0 HGC=102710 FGC=180208 HEC=102710 FEC=180208 IGC=90392 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 42/81/83  OPS COMPLETE = 240 OF 408  ELAPSED TIME = 161
 
 MR_via2.5::TMP<36> = EXPAND EDGE MR_via2.5::q1met2enc INSIDE BY 0.005
 ---------------------------------------------------------------------
-MR_via2.5::TMP<36> (HIER TYP=1 CFG=1 HGC=97752 FGC=175250 HEC=391008 FEC=701000 IGC=89556 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 241 OF 408  ELAPSED TIME = 162
+MR_via2.5::TMP<36> (HIER TYP=1 CFG=1 HGC=102710 FGC=180208 HEC=410840 FEC=720832 IGC=90353 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 241 OF 408  ELAPSED TIME = 161
 
 Layer MR_via2.5::q1met2enc DELETED -- LVHEAP = 42/81/83
 
 MR_via2.5::<1> = NOT RECTANGLE MR_via2.5::TMP<36> ORTHOGONAL ONLY
 -----------------------------------------------------------------
 MR_via2.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 242 OF 408  ELAPSED TIME = 162
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 242 OF 408  ELAPSED TIME = 161
 
 Layer MR_via2.5::TMP<36> DELETED -- LVHEAP = 42/81/83
 
@@ -7044,7 +7057,7 @@
 ---------------------------------------------------------------------
 MR_m3.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_m3.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 244 OF 408  ELAPSED TIME = 162
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 244 OF 408  ELAPSED TIME = 161
 
 Layer MR_m3.1::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -7056,13 +7069,13 @@
 
 MR_m3.4::q1via2and = via2 AND met3
 ----------------------------------
-MR_m3.4::q1via2and (HIER TYP=1 CFG=1 HGC=193446 FGC=812014 HEC=773784 FEC=3248056 IGC=108947 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 245 OF 408  ELAPSED TIME = 163
+MR_m3.4::q1via2and (HIER TYP=1 CFG=1 HGC=195931 FGC=814451 HEC=783724 FEC=3257804 IGC=110378 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 245 OF 408  ELAPSED TIME = 162
 
 MR_m3.4::<1> = ENC MR_m3.4::q1via2and met3 < 0.065 MEASURE ALL ABUT < 90 SINGULAR
 ---------------------------------------------------------------------------------
 MR_m3.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 246 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 246 OF 408  ELAPSED TIME = 162
 
 Layer MR_m3.4::q1via2and DELETED -- LVHEAP = 42/81/83
 
@@ -7073,146 +7086,146 @@
 MR_m3.4_a::<1> = via2 NOT met3
 ------------------------------
 MR_m3.4_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 247 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 247 OF 408  ELAPSED TIME = 162
 
-Layer via2 DELETED -- LVHEAP = 41/81/83
+Layer via2 DELETED -- LVHEAP = 42/81/83
 
-Layer MR_m3.4_a::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_m3.4_a::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m3.4_a COMPLETED. Number of Results = 0 (0)
 
 q0Hugemet3 = met3 WITH WIDTH > 3
 --------------------------------
 q0Hugemet3 (HIER TYP=1 CFG=1 HGC=424 FGC=1852 HEC=2863 FEC=12930 IGC=1135 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 248 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 248 OF 408  ELAPSED TIME = 162
 
 q1Hugemet3 = SIZE q0Hugemet3 BY 0.4 INSIDE OF met3 STEP 0.4
 -----------------------------------------------------------
 q1Hugemet3 (HIER TYP=1 CFG=0 HGC=375 FGC=1835 HEC=2721 FEC=13092 IGC=1137 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 249 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 249 OF 408  ELAPSED TIME = 162
 
 q2Hugemet3 = q1Hugemet3 NOT q0Hugemet3
 --------------------------------------
 q2Hugemet3 (HIER TYP=1 CFG=1 HGC=35 FGC=425 HEC=151 FEC=1935 IGC=186 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 250 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 250 OF 408  ELAPSED TIME = 162
 
-Layer q1Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q1Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 TMP<37> = q2Hugemet3 COINCIDENT OUTSIDE EDGE q0Hugemet3
 -------------------------------------------------------
 TMP<37> (HIER-PMF TYP=2 CFG=1 HGC=38 FGC=492 HEC=38 FEC=492 IGC=123 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 251 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 251 OF 408  ELAPSED TIME = 162
 
 q3Hugemet3 = q2Hugemet3 WITH EDGE TMP<37>
 -----------------------------------------
 q3Hugemet3 (HIER TYP=1 CFG=0 HGC=33 FGC=391 HEC=145 FEC=1833 IGC=186 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 252 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 252 OF 408  ELAPSED TIME = 162
 
-Layer q2Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q2Hugemet3 DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<37> DELETED -- LVHEAP = 41/81/83
+Layer TMP<37> DELETED -- LVHEAP = 42/81/83
 
 q4Hugemet3 = q3Hugemet3 OR q0Hugemet3
 -------------------------------------
 q4Hugemet3 (HIER TYP=1 CFG=1 HGC=427 FGC=1855 HEC=2913 FEC=13246 IGC=1151 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 253 OF 408  ELAPSED TIME = 163
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 253 OF 408  ELAPSED TIME = 162
 
-Layer q3Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q3Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 q5Hugemet3 = SNAP q4Hugemet3 1
 ------------------------------
 q5Hugemet3 (HIER TYP=1 CFG=1 HGC=485 FGC=4827 HEC=2758 FEC=25163 IGC=962 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 254 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 254 OF 408  ELAPSED TIME = 162
 
-Layer q4Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q4Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 q6Hugemet3 = met3 NOT q5Hugemet3
 --------------------------------
-q6Hugemet3 (HIER TYP=1 CFG=1 HGC=39809 FGC=57447 HEC=331159 FEC=432749 IGC=13016 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 255 OF 408  ELAPSED TIME = 164
+q6Hugemet3 (HIER TYP=1 CFG=1 HGC=41164 FGC=58786 HEC=349481 FEC=451007 IGC=13084 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 255 OF 408  ELAPSED TIME = 163
 
 q7Hugemet3 = EXT q0Hugemet3 q6Hugemet3 <= 0.395 REGION
 ------------------------------------------------------
 q7Hugemet3 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 256 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 256 OF 408  ELAPSED TIME = 163
 
-Layer q0Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q0Hugemet3 DELETED -- LVHEAP = 42/81/83
 
-Layer q6Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q6Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 TMP<38> = q7Hugemet3 INSIDE met3
 --------------------------------
 TMP<38> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 257 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 257 OF 408  ELAPSED TIME = 163
 
 q8Hugemet3 = q7Hugemet3 NOT TMP<38>
 -----------------------------------
 q8Hugemet3 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 258 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 258 OF 408  ELAPSED TIME = 163
 
-Layer q7Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q7Hugemet3 DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<38> DELETED -- LVHEAP = 41/81/83
+Layer TMP<38> DELETED -- LVHEAP = 42/81/83
 
-Layer q8Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q8Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m3.3d COMPLETED. Number of Results = 0 (0)
 
 q9Hugemet3 = EXT q5Hugemet3 < 0.4 REGION ABUT < 90
 --------------------------------------------------
 q9Hugemet3 (HIER TYP=1 CFG=1 HGC=1 FGC=33 HEC=4 FEC=132 IGC=14 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 259 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 259 OF 408  ELAPSED TIME = 163
 
-Layer q5Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q5Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 TMP<40> = q9Hugemet3 AND met3
 -----------------------------
 TMP<40> (HIER TYP=1 CFG=1 HGC=1 FGC=33 HEC=4 FEC=132 IGC=14 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 260 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 260 OF 408  ELAPSED TIME = 163
 
 TMP<39> = q9Hugemet3 INTERACT TMP<40>
 -------------------------------------
 TMP<39> (HIER TYP=1 CFG=0 HGC=1 FGC=33 HEC=4 FEC=132 IGC=14 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 261 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 261 OF 408  ELAPSED TIME = 163
 
-Layer TMP<40> DELETED -- LVHEAP = 41/81/83
+Layer TMP<40> DELETED -- LVHEAP = 42/81/83
 
 q10Hugemet3 = q9Hugemet3 NOT TMP<39>
 ------------------------------------
 q10Hugemet3 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 262 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 262 OF 408  ELAPSED TIME = 163
 
-Layer q9Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q9Hugemet3 DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<39> DELETED -- LVHEAP = 41/81/83
+Layer TMP<39> DELETED -- LVHEAP = 42/81/83
 
-Layer q10Hugemet3 DELETED -- LVHEAP = 41/81/83
+Layer q10Hugemet3 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m3.3c COMPLETED. Number of Results = 0 (0)
 
 ringVIA3 = DONUT via3
 ---------------------
 ringVIA3 (HIER-FMF TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 263 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 263 OF 408  ELAPSED TIME = 163
 
 rectVIA3 = via3 NOT ringVIA3
 ----------------------------
-rectVIA3 (HIER TYP=1 CFG=0 HGC=211808 FGC=725951 HEC=847232 FEC=2903804 IGC=82941 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 264 OF 408  ELAPSED TIME = 164
+rectVIA3 (HIER TYP=1 CFG=0 HGC=212065 FGC=726160 HEC=848260 FEC=2904640 IGC=83441 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 264 OF 408  ELAPSED TIME = 163
 
-Layer ringVIA3 DELETED -- LVHEAP = 41/81/83
+Layer ringVIA3 DELETED -- LVHEAP = 42/81/83
 
 rectVIA3noMT = rectVIA3 NOT moduleCutAREA
 -----------------------------------------
-rectVIA3noMT (HIER TYP=1 CFG=1 HGC=211808 FGC=725951 HEC=847232 FEC=2903804 IGC=82941 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 265 OF 408  ELAPSED TIME = 164
+rectVIA3noMT (HIER TYP=1 CFG=1 HGC=212065 FGC=726160 HEC=848260 FEC=2904640 IGC=83441 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 265 OF 408  ELAPSED TIME = 163
 
 Layer moduleCutAREA DELETED -- LVHEAP = 42/81/83
 
 q0rectVIA3noMT = NOT RECTANGLE rectVIA3noMT ORTHOGONAL ONLY
 -----------------------------------------------------------
 q0rectVIA3noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 266 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 266 OF 408  ELAPSED TIME = 163
 
 Layer q0rectVIA3noMT DELETED -- LVHEAP = 42/81/83
 
@@ -7221,7 +7234,7 @@
 q1rectVIA3noMT = INT rectVIA3noMT < 0.2 REGION
 ----------------------------------------------
 q1rectVIA3noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 267 OF 408  ELAPSED TIME = 164
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 267 OF 408  ELAPSED TIME = 163
 
 Layer q1rectVIA3noMT DELETED -- LVHEAP = 42/81/83
 
@@ -7230,77 +7243,77 @@
 TMP<43> = LENGTH rectVIA3noMT > 0.2
 -----------------------------------
 TMP<43> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 268 OF 408  ELAPSED TIME = 165
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 268 OF 408  ELAPSED TIME = 163
 
 q2rectVIA3noMT = rectVIA3noMT WITH EDGE TMP<43>
 -----------------------------------------------
 q2rectVIA3noMT (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 269 OF 408  ELAPSED TIME = 165
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 269 OF 408  ELAPSED TIME = 163
 
-Layer rectVIA3noMT DELETED -- LVHEAP = 41/81/83
+Layer rectVIA3noMT DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<43> DELETED -- LVHEAP = 41/81/83
+Layer TMP<43> DELETED -- LVHEAP = 42/81/83
 
-Layer q2rectVIA3noMT DELETED -- LVHEAP = 41/81/83
+Layer q2rectVIA3noMT DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via3.1_b COMPLETED. Number of Results = 0 (0)
 
 MR_via3.2::<1> = EXT via3 < 0.2 REGION ABUT < 90 SINGULAR
 ---------------------------------------------------------
 MR_via3.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 270 OF 408  ELAPSED TIME = 165
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 270 OF 408  ELAPSED TIME = 164
 
-Layer MR_via3.2::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.2::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via3.2 COMPLETED. Number of Results = 0 (0)
 
 MR_via3.4::q0rectVIA3and = rectVIA3 AND met3
 --------------------------------------------
-MR_via3.4::q0rectVIA3and (HIER TYP=1 CFG=1 HGC=227308 FGC=725952 HEC=909232 FEC=2903808 IGC=82945 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 271 OF 408  ELAPSED TIME = 165
+MR_via3.4::q0rectVIA3and (HIER TYP=1 CFG=1 HGC=227565 FGC=726161 HEC=910260 FEC=2904644 IGC=83445 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 271 OF 408  ELAPSED TIME = 164
 
 MR_via3.4::<1> = ENC MR_via3.4::q0rectVIA3and met3 < 0.06 MEASURE ALL ABUT < 90 SINGULAR
 ----------------------------------------------------------------------------------------
 MR_via3.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 272 OF 408  ELAPSED TIME = 165
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 272 OF 408  ELAPSED TIME = 164
 
-Layer MR_via3.4::q0rectVIA3and DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.4::q0rectVIA3and DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via3.4::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.4::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via3.4 COMPLETED. Number of Results = 0 (0)
 
 MR_via3.4_a::<1> = rectVIA3 NOT met3
 ------------------------------------
 MR_via3.4_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 273 OF 408  ELAPSED TIME = 165
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 273 OF 408  ELAPSED TIME = 164
 
-Layer rectVIA3 DELETED -- LVHEAP = 41/81/83
+Layer rectVIA3 DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via3.4_a::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.4_a::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via3.4_a COMPLETED. Number of Results = 0 (0)
 
 MR_via3.5::q0met3enc = ENC [via3] met3 < 0.09 MEASURE ALL PROJECTING > 0 ABUT < 90 PARALLEL ONLY
 ------------------------------------------------------------------------------------------------
-MR_via3.5::q0met3enc (HIER-PMF TYP=2 CFG=0 HGC=105225 FGC=155822 HEC=105225 FEC=155822 IGC=52525 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 41/81/83  OPS COMPLETE = 274 OF 408  ELAPSED TIME = 166
+MR_via3.5::q0met3enc (HIER-PMF TYP=2 CFG=0 HGC=105747 FGC=156248 HEC=105747 FEC=156248 IGC=53407 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 42/81/83  OPS COMPLETE = 274 OF 408  ELAPSED TIME = 165
 
 MR_via3.5::TMP<44> = EXPAND EDGE MR_via3.5::q0met3enc INSIDE BY 0.005
 ---------------------------------------------------------------------
-MR_via3.5::TMP<44> (HIER TYP=1 CFG=1 HGC=105225 FGC=155822 HEC=420900 FEC=623288 IGC=52437 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 275 OF 408  ELAPSED TIME = 167
+MR_via3.5::TMP<44> (HIER TYP=1 CFG=1 HGC=105747 FGC=156248 HEC=422988 FEC=624992 IGC=53319 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 275 OF 408  ELAPSED TIME = 165
 
-Layer MR_via3.5::q0met3enc DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.5::q0met3enc DELETED -- LVHEAP = 42/81/83
 
 MR_via3.5::<1> = NOT RECTANGLE MR_via3.5::TMP<44> ORTHOGONAL ONLY
 -----------------------------------------------------------------
 MR_via3.5::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 276 OF 408  ELAPSED TIME = 167
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 276 OF 408  ELAPSED TIME = 165
 
-Layer MR_via3.5::TMP<44> DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.5::TMP<44> DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via3.5::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via3.5::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via3.5 COMPLETED. Number of Results = 0 (0)
 
@@ -7309,36 +7322,36 @@
 ---------------------------------------------------------------------
 MR_m4.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_m4.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 278 OF 408  ELAPSED TIME = 167
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 278 OF 408  ELAPSED TIME = 166
 
-Layer MR_m4.1::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_m4.1::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m4.1 COMPLETED. Number of Results = 0 (0)
 
-Layer MR_m4.2::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_m4.2::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m4.2 COMPLETED. Number of Results = 0 (0)
 
 MR_m4.3::q0via3and = via3 AND met4
 ----------------------------------
-MR_m4.3::q0via3and (HIER TYP=1 CFG=1 HGC=227307 FGC=725951 HEC=909228 FEC=2903804 IGC=84146 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 279 OF 408  ELAPSED TIME = 167
+MR_m4.3::q0via3and (HIER TYP=1 CFG=1 HGC=227565 FGC=726161 HEC=910260 FEC=2904644 IGC=84743 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 279 OF 408  ELAPSED TIME = 166
 
 MR_m4.3::<1> = ENC MR_m4.3::q0via3and met4 < 0.065 MEASURE ALL ABUT < 90 SINGULAR
 ---------------------------------------------------------------------------------
 MR_m4.3::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 280 OF 408  ELAPSED TIME = 167
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 280 OF 408  ELAPSED TIME = 166
 
-Layer MR_m4.3::q0via3and DELETED -- LVHEAP = 41/81/83
+Layer MR_m4.3::q0via3and DELETED -- LVHEAP = 42/81/83
 
-Layer MR_m4.3::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_m4.3::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m4.3 COMPLETED. Number of Results = 0 (0)
 
 MR_m4.3_a::<1> = via3 NOT met4
 ------------------------------
 MR_m4.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 281 OF 408  ELAPSED TIME = 167
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 281 OF 408  ELAPSED TIME = 166
 
 Layer via3 DELETED -- LVHEAP = 41/81/83
 
@@ -7349,7 +7362,7 @@
 MR_m4.4a::<1> = AREA met4 < 0.24
 --------------------------------
 MR_m4.4a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 282 OF 408  ELAPSED TIME = 167
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 282 OF 408  ELAPSED TIME = 166
 
 Layer MR_m4.4a::<1> DELETED -- LVHEAP = 41/81/83
 
@@ -7358,103 +7371,103 @@
 q0Hugemet4 = met4 WITH WIDTH > 3
 --------------------------------
 q0Hugemet4 (HIER TYP=1 CFG=1 HGC=6896 FGC=29099 HEC=27986 FEC=118730 IGC=1701 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 283 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 283 OF 408  ELAPSED TIME = 167
 
 q1Hugemet4 = SIZE q0Hugemet4 BY 0.4 INSIDE OF met4 STEP 0.4
 -----------------------------------------------------------
 q1Hugemet4 (HIER TYP=1 CFG=0 HGC=3078 FGC=25519 HEC=14276 FEC=115648 IGC=1722 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 284 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 284 OF 408  ELAPSED TIME = 167
 
 q2Hugemet4 = q1Hugemet4 NOT q0Hugemet4
 --------------------------------------
 q2Hugemet4 (HIER TYP=1 CFG=1 HGC=97 FGC=225 HEC=392 FEC=904 IGC=222 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 285 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 285 OF 408  ELAPSED TIME = 167
 
-Layer q1Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q1Hugemet4 DELETED -- LVHEAP = 42/81/83
 
 TMP<45> = q2Hugemet4 COINCIDENT OUTSIDE EDGE q0Hugemet4
 -------------------------------------------------------
 TMP<45> (HIER-PMF TYP=2 CFG=1 HGC=99 FGC=227 HEC=99 FEC=227 IGC=119 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 286 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 286 OF 408  ELAPSED TIME = 167
 
 q3Hugemet4 = q2Hugemet4 WITH EDGE TMP<45>
 -----------------------------------------
 q3Hugemet4 (HIER TYP=1 CFG=0 HGC=97 FGC=225 HEC=392 FEC=904 IGC=222 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 287 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 287 OF 408  ELAPSED TIME = 167
 
-Layer q2Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q2Hugemet4 DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<45> DELETED -- LVHEAP = 41/81/83
+Layer TMP<45> DELETED -- LVHEAP = 42/81/83
 
 q4Hugemet4 = q3Hugemet4 OR q0Hugemet4
 -------------------------------------
 q4Hugemet4 (HIER TYP=1 CFG=1 HGC=6897 FGC=29100 HEC=28316 FEC=119188 IGC=1706 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 288 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 288 OF 408  ELAPSED TIME = 167
 
-Layer q3Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q3Hugemet4 DELETED -- LVHEAP = 42/81/83
 
 q5Hugemet4 = SNAP q4Hugemet4 1
 ------------------------------
 q5Hugemet4 (HIER TYP=1 CFG=1 HGC=6988 FGC=32488 HEC=28645 FEC=134113 IGC=1674 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 289 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 289 OF 408  ELAPSED TIME = 167
 
-Layer q4Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q4Hugemet4 DELETED -- LVHEAP = 42/81/83
 
 q6Hugemet4 = met4 NOT q5Hugemet4
 --------------------------------
-q6Hugemet4 (HIER TYP=1 CFG=1 HGC=9405 FGC=25828 HEC=59975 FEC=127447 IGC=12325 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 290 OF 408  ELAPSED TIME = 168
+q6Hugemet4 (HIER TYP=1 CFG=1 HGC=9684 FGC=26099 HEC=61883 FEC=129323 IGC=12488 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 290 OF 408  ELAPSED TIME = 167
 
 q7Hugemet4 = EXT q0Hugemet4 q6Hugemet4 <= 0.395 REGION
 ------------------------------------------------------
 q7Hugemet4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 291 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 291 OF 408  ELAPSED TIME = 167
 
-Layer q0Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q0Hugemet4 DELETED -- LVHEAP = 42/81/83
 
-Layer q6Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q6Hugemet4 DELETED -- LVHEAP = 42/81/83
 
 TMP<46> = q7Hugemet4 INSIDE met4
 --------------------------------
 TMP<46> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 292 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 292 OF 408  ELAPSED TIME = 167
 
 q8Hugemet4 = q7Hugemet4 NOT TMP<46>
 -----------------------------------
 q8Hugemet4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 293 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 293 OF 408  ELAPSED TIME = 167
 
-Layer q7Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q7Hugemet4 DELETED -- LVHEAP = 42/81/83
 
-Layer TMP<46> DELETED -- LVHEAP = 41/81/83
+Layer TMP<46> DELETED -- LVHEAP = 42/81/83
 
-Layer q8Hugemet4 DELETED -- LVHEAP = 41/81/83
+Layer q8Hugemet4 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_m4.5b COMPLETED. Number of Results = 0 (0)
 
 q9Hugemet4 = EXT q5Hugemet4 < 0.4 REGION ABUT < 90
 --------------------------------------------------
 q9Hugemet4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 294 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 294 OF 408  ELAPSED TIME = 167
 
 Layer q5Hugemet4 DELETED -- LVHEAP = 41/81/83
 
 TMP<48> = q9Hugemet4 AND met4
 -----------------------------
 TMP<48> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 295 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 295 OF 408  ELAPSED TIME = 167
 
 TMP<47> = q9Hugemet4 INTERACT TMP<48>
 -------------------------------------
 TMP<47> (HIER TYP=1 CFG=0 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 296 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 296 OF 408  ELAPSED TIME = 167
 
 Layer TMP<48> DELETED -- LVHEAP = 41/81/83
 
 q10Hugemet4 = q9Hugemet4 NOT TMP<47>
 ------------------------------------
 q10Hugemet4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 297 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 297 OF 408  ELAPSED TIME = 167
 
 Layer q9Hugemet4 DELETED -- LVHEAP = 41/81/83
 
@@ -7467,112 +7480,112 @@
 ringVIA4 = DONUT via4
 ---------------------
 ringVIA4 (HIER-FMF TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 298 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 298 OF 408  ELAPSED TIME = 167
 
 rectVIA4 = via4 NOT ringVIA4
 ----------------------------
-rectVIA4 (HIER TYP=1 CFG=1 HGC=32979 FGC=222131 HEC=131916 FEC=888524 IGC=17216 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 299 OF 408  ELAPSED TIME = 168
+rectVIA4 (HIER TYP=1 CFG=1 HGC=33054 FGC=222198 HEC=132216 FEC=888792 IGC=17314 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 299 OF 408  ELAPSED TIME = 167
 
 q0rectVIA4 = NOT RECTANGLE rectVIA4 ORTHOGONAL ONLY
 ---------------------------------------------------
 q0rectVIA4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 300 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 300 OF 408  ELAPSED TIME = 167
 
-Layer q0rectVIA4 DELETED -- LVHEAP = 41/81/83
+Layer q0rectVIA4 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.1 COMPLETED. Number of Results = 0 (0)
 
 q1rectVIA4 = INT rectVIA4 < 0.8 REGION
 --------------------------------------
 q1rectVIA4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 301 OF 408  ELAPSED TIME = 168
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 301 OF 408  ELAPSED TIME = 167
 
-Layer q1rectVIA4 DELETED -- LVHEAP = 41/81/83
+Layer q1rectVIA4 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.1_a COMPLETED. Number of Results = 0 (0)
 
 TMP<50> = LENGTH rectVIA4 > 0.8
 -------------------------------
 TMP<50> (HIER-PMF TYP=2 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 302 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 302 OF 408  ELAPSED TIME = 168
 
 q2rectVIA4 = rectVIA4 WITH EDGE TMP<50>
 ---------------------------------------
 q2rectVIA4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 303 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 303 OF 408  ELAPSED TIME = 168
 
-Layer TMP<50> DELETED -- LVHEAP = 41/81/83
+Layer TMP<50> DELETED -- LVHEAP = 42/81/83
 
-Layer q2rectVIA4 DELETED -- LVHEAP = 41/81/83
+Layer q2rectVIA4 DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.1_b COMPLETED. Number of Results = 0 (0)
 
 MR_via4.2::<1> = EXT via4 < 0.8 REGION ABUT < 90 SINGULAR
 ---------------------------------------------------------
 MR_via4.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 304 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 304 OF 408  ELAPSED TIME = 168
 
-Layer MR_via4.2::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.2::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.2 COMPLETED. Number of Results = 0 (0)
 
 MR_via4.3::<1> = INT ringVIA4 < 0.8 REGION ABUT < 90 SINGULAR EXCLUDE FALSE
 ---------------------------------------------------------------------------
 MR_via4.3::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 305 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 305 OF 408  ELAPSED TIME = 168
 
-Layer MR_via4.3::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.3::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.3 COMPLETED. Number of Results = 0 (0)
 
 MR_via4.3_a::q0ringVIA4 = SIZE ringVIA4 BY -0.402
 -------------------------------------------------
 MR_via4.3_a::q0ringVIA4 (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 306 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 306 OF 408  ELAPSED TIME = 168
 
 MR_via4.3_a::<1> = SIZE MR_via4.3_a::q0ringVIA4 BY 0.402
 --------------------------------------------------------
 MR_via4.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 307 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 307 OF 408  ELAPSED TIME = 168
 
-Layer MR_via4.3_a::q0ringVIA4 DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.3_a::q0ringVIA4 DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via4.3_a::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.3_a::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.3_a COMPLETED. Number of Results = 0 (0)
 
 MR_via4.3_b::<1> = ringVIA4 NOT SEALID
 --------------------------------------
 MR_via4.3_b::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 308 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 308 OF 408  ELAPSED TIME = 168
 
-Layer ringVIA4 DELETED -- LVHEAP = 41/81/83
+Layer ringVIA4 DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via4.3_b::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.3_b::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.3_b COMPLETED. Number of Results = 0 (0)
 
 MR_via4.4::q0rectVIA4and = rectVIA4 AND met4
 --------------------------------------------
-MR_via4.4::q0rectVIA4and (HIER TYP=1 CFG=1 HGC=33054 FGC=222206 HEC=132274 FEC=888882 IGC=17274 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 309 OF 408  ELAPSED TIME = 169
+MR_via4.4::q0rectVIA4and (HIER TYP=1 CFG=1 HGC=33125 FGC=222269 HEC=132558 FEC=889134 IGC=17368 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 309 OF 408  ELAPSED TIME = 168
 
 MR_via4.4::<1> = ENC MR_via4.4::q0rectVIA4and met4 < 0.19 MEASURE ALL ABUT < 90 SINGULAR
 ----------------------------------------------------------------------------------------
 MR_via4.4::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 310 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 310 OF 408  ELAPSED TIME = 168
 
-Layer MR_via4.4::q0rectVIA4and DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.4::q0rectVIA4and DELETED -- LVHEAP = 42/81/83
 
-Layer MR_via4.4::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_via4.4::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_via4.4 COMPLETED. Number of Results = 0 (0)
 
 MR_via4.4_a::<1> = rectVIA4 NOT met4
 ------------------------------------
 MR_via4.4_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 311 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 311 OF 408  ELAPSED TIME = 168
 
 Layer rectVIA4 DELETED -- LVHEAP = 41/81/83
 
@@ -7585,7 +7598,7 @@
 ---------------------------------------------------------------------
 MR_m5.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_m5.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 313 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 313 OF 408  ELAPSED TIME = 168
 
 Layer MR_m5.1::<1> DELETED -- LVHEAP = 41/81/83
 
@@ -7597,13 +7610,13 @@
 
 MR_m5.3::q0via4and = via4 AND met5
 ----------------------------------
-MR_m5.3::q0via4and (HIER TYP=1 CFG=1 HGC=33059 FGC=222211 HEC=132236 FEC=888844 IGC=17285 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 314 OF 408  ELAPSED TIME = 169
+MR_m5.3::q0via4and (HIER TYP=1 CFG=1 HGC=33130 FGC=222274 HEC=132520 FEC=889096 IGC=17379 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 314 OF 408  ELAPSED TIME = 168
 
 MR_m5.3::<1> = ENC MR_m5.3::q0via4and met5 < 0.31 MEASURE ALL ABUT < 90 SINGULAR
 --------------------------------------------------------------------------------
 MR_m5.3::<1> (HIER TYP=3 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 315 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 315 OF 408  ELAPSED TIME = 168
 
 Layer MR_m5.3::q0via4and DELETED -- LVHEAP = 41/81/83
 
@@ -7614,7 +7627,7 @@
 MR_m5.3_a::<1> = via4 NOT met5
 ------------------------------
 MR_m5.3_a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 316 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 316 OF 408  ELAPSED TIME = 168
 
 Layer via4 DELETED -- LVHEAP = 41/81/83
 
@@ -7625,7 +7638,7 @@
 MR_m5.4::<1> = AREA met5 < 4
 ----------------------------
 MR_m5.4::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 317 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 317 OF 408  ELAPSED TIME = 168
 
 Layer MR_m5.4::<1> DELETED -- LVHEAP = 41/81/83
 
@@ -7634,7 +7647,7 @@
 MR_pad.2::<1> = EXT pad < 1.27 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------
 MR_pad.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 318 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 318 OF 408  ELAPSED TIME = 168
 
 Layer pad DELETED -- LVHEAP = 41/81/83
 
@@ -7645,14 +7658,14 @@
 hvi = OR hvi
 ------------
 hvi (HIER TYP=1 CFG=1 HGC=282 FGC=31309 HEC=1431 FEC=134587 IGC=608 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 319 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 319 OF 408  ELAPSED TIME = 168
 
 Original Layer hvi DELETED -- LVHEAP = 41/81/83
 
 hvi_peri = hvi NOT COREID
 -------------------------
 hvi_peri (HIER TYP=1 CFG=1 HGC=282 FGC=31309 HEC=1431 FEC=134587 IGC=608 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 320 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 320 OF 408  ELAPSED TIME = 168
 
 Layer hvi DELETED -- LVHEAP = 41/81/83
 
@@ -7661,7 +7674,7 @@
 --------------------------------------------------------------------------
 MR_hvi.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_hvi.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 322 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 322 OF 408  ELAPSED TIME = 168
 
 Layer hvi_peri DELETED -- LVHEAP = 41/81/83
 
@@ -7676,14 +7689,14 @@
 hvntm = OR hvntm
 ----------------
 hvntm (HIER TYP=1 CFG=1 HGC=22 FGC=43 HEC=104 FEC=200 IGC=15 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 323 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 323 OF 408  ELAPSED TIME = 168
 
 Original Layer hvntm DELETED -- LVHEAP = 41/81/83
 
 hvntm_peri = hvntm NOT COREID
 -----------------------------
 hvntm_peri (HIER TYP=1 CFG=1 HGC=22 FGC=43 HEC=104 FEC=200 IGC=15 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 324 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 324 OF 408  ELAPSED TIME = 168
 
 Layer hvntm DELETED -- LVHEAP = 41/81/83
 
@@ -7694,7 +7707,7 @@
 ------------------------------------------------------------------------------
 MR_hvntm.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 MR_hvntm.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 326 OF 408  ELAPSED TIME = 169
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 326 OF 408  ELAPSED TIME = 168
 
 Layer hvntm_peri DELETED -- LVHEAP = 41/81/83
 
@@ -7708,34 +7721,34 @@
 
 FOM_FILL = OR FOM_FILL
 ----------------------
-FOM_FILL (HIER TYP=1 CFG=1 HGC=510693 FGC=510693 HEC=2043233 FEC=2043233 IGC=19852 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 41/81/83  OPS COMPLETE = 327 OF 408  ELAPSED TIME = 170
+FOM_FILL (HIER TYP=1 CFG=1 HGC=511143 FGC=511143 HEC=2045035 FEC=2045035 IGC=19847 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 41/81/83  OPS COMPLETE = 327 OF 408  ELAPSED TIME = 169
 
 Original Layer FOM_FILL DELETED -- LVHEAP = 41/81/83
 
 FOMmk = OR FOMmk
 ----------------
 FOMmk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 328 OF 408  ELAPSED TIME = 170
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 328 OF 408  ELAPSED TIME = 169
 
 Original Layer FOMmk DELETED -- LVHEAP = 41/81/83
 
 TMP<51> = FOMmk OR FOM_FILL
 ---------------------------
-TMP<51> (HIER TYP=1 CFG=0 HGC=510697 FGC=510697 HEC=2043281 FEC=2043281 IGC=19852 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 329 OF 408  ELAPSED TIME = 170
+TMP<51> (HIER TYP=1 CFG=0 HGC=511147 FGC=511147 HEC=2045083 FEC=2045083 IGC=19847 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 329 OF 408  ELAPSED TIME = 169
 
 FOMpd = diffTap OR TMP<51>
 --------------------------
-FOMpd (HIER TYP=1 CFG=1 HGC=514126 FGC=1345947 HEC=2059538 FEC=5909379 IGC=24473 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 330 OF 408  ELAPSED TIME = 170
+FOMpd (HIER TYP=1 CFG=1 HGC=514642 FGC=1348262 HEC=2061592 FEC=5910221 IGC=24490 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 330 OF 408  ELAPSED TIME = 169
 
 Layer TMP<51> DELETED -- LVHEAP = 42/81/83
 
 MR_cfom.waffle.1::<1> = EXT FOM_FILL FOMpd < 0.4 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cfom.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 6  REAL TIME = 6  LVHEAP = 42/81/83  OPS COMPLETE = 331 OF 408  ELAPSED TIME = 176
+CPU TIME = 6  REAL TIME = 6  LVHEAP = 42/81/83  OPS COMPLETE = 331 OF 408  ELAPSED TIME = 175
 
 Layer MR_cfom.waffle.1::<1> DELETED -- LVHEAP = 42/81/83
 
@@ -7743,47 +7756,47 @@
 
 FOM_noFill = diffTap OR FOMmk
 -----------------------------
-FOM_noFill (HIER TYP=1 CFG=1 HGC=3433 FGC=835254 HEC=16305 FEC=3866146 IGC=5819 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 332 OF 408  ELAPSED TIME = 176
+FOM_noFill (HIER TYP=1 CFG=1 HGC=3499 FGC=837119 HEC=16557 FEC=3865186 IGC=5849 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 332 OF 408  ELAPSED TIME = 175
 
-Layer diffTap DELETED -- LVHEAP = 41/81/83
+Layer diffTap DELETED -- LVHEAP = 42/81/83
 
-Layer FOMmk DELETED -- LVHEAP = 41/81/83
+Layer FOMmk DELETED -- LVHEAP = 42/81/83
 
 MR_cfom.waffle.2::<1> = FOM_FILL INTERACT FOM_noFill
 ----------------------------------------------------
 MR_cfom.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 333 OF 408  ELAPSED TIME = 177
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 333 OF 408  ELAPSED TIME = 176
 
-Layer MR_cfom.waffle.2::<1> DELETED -- LVHEAP = 41/81/83
+Layer MR_cfom.waffle.2::<1> DELETED -- LVHEAP = 42/81/83
 
 DRC RuleCheck MR_cfom.waffle.2 COMPLETED. Number of Results = 0 (0)
 
 P1Mmk = OR P1Mmk
 ----------------
 P1Mmk (HIER TYP=1 CFG=0 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 41/81/83  OPS COMPLETE = 334 OF 408  ELAPSED TIME = 177
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 42/81/83  OPS COMPLETE = 334 OF 408  ELAPSED TIME = 176
 
-Original Layer P1Mmk DELETED -- LVHEAP = 41/81/83
+Original Layer P1Mmk DELETED -- LVHEAP = 42/81/83
 
 P1M_FILL = OR P1M_FILL
 ----------------------
-P1M_FILL (HIER TYP=1 CFG=1 HGC=3828516 FGC=3828516 HEC=15314166 FEC=15314166 IGC=33202 VHC=F VPC=F)
-CPU TIME = 10  REAL TIME = 10  LVHEAP = 46/81/83  OPS COMPLETE = 335 OF 408  ELAPSED TIME = 187
+P1M_FILL (HIER TYP=1 CFG=1 HGC=3828559 FGC=3828559 HEC=15314338 FEC=15314338 IGC=33235 VHC=F VPC=F)
+CPU TIME = 10  REAL TIME = 10  LVHEAP = 47/81/83  OPS COMPLETE = 335 OF 408  ELAPSED TIME = 186
 
-Original Layer P1M_FILL DELETED -- LVHEAP = 46/81/83
+Original Layer P1M_FILL DELETED -- LVHEAP = 47/81/83
 
 MR_cfom.waffle.2a::TMP<60> = P1Mmk OR P1M_FILL
 ----------------------------------------------
-MR_cfom.waffle.2a::TMP<60> (HIER TYP=1 CFG=0 HGC=3828520 FGC=3828520 HEC=15314214 FEC=15314214 IGC=33202 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 54/81/83  OPS COMPLETE = 336 OF 408  ELAPSED TIME = 188
+MR_cfom.waffle.2a::TMP<60> (HIER TYP=1 CFG=0 HGC=3828563 FGC=3828563 HEC=15314386 FEC=15314386 IGC=33235 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 55/81/83  OPS COMPLETE = 336 OF 408  ELAPSED TIME = 187
 
 MR_cfom.waffle.2a::TMP<59> = poly OR MR_cfom.waffle.2a::TMP<60>
 ---------------------------------------------------------------
-MR_cfom.waffle.2a::TMP<59> (HIER TYP=1 CFG=1 HGC=3834011 FGC=4659570 HEC=15365467 FEC=23234401 IGC=38726 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 54/81/83  OPS COMPLETE = 337 OF 408  ELAPSED TIME = 189
+MR_cfom.waffle.2a::TMP<59> (HIER TYP=1 CFG=1 HGC=3834120 FGC=4661376 HEC=15367037 FEC=23323379 IGC=38772 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 55/81/83  OPS COMPLETE = 337 OF 408  ELAPSED TIME = 188
 
-Layer MR_cfom.waffle.2a::TMP<60> DELETED -- LVHEAP = 54/81/83
+Layer MR_cfom.waffle.2a::TMP<60> DELETED -- LVHEAP = 55/81/83
 
 MR_cfom.waffle.2a::<1> = FOM_FILL INTERACT MR_cfom.waffle.2a::TMP<59>
 ---------------------------------------------------------------------
@@ -7800,7 +7813,7 @@
 
 p1m_noFill = poly OR P1Mmk
 --------------------------
-p1m_noFill (HIER TYP=1 CFG=0 HGC=5495 FGC=831054 HEC=51301 FEC=7920235 IGC=5905 VHC=F VPC=F)
+p1m_noFill (HIER TYP=1 CFG=0 HGC=5561 FGC=832817 HEC=52699 FEC=8009041 IGC=5921 VHC=F VPC=F)
 CPU TIME = 0  REAL TIME = 0  LVHEAP = 46/81/83  OPS COMPLETE = 339 OF 408  ELAPSED TIME = 192
 
 Layer poly DELETED -- LVHEAP = 46/81/83
@@ -7809,175 +7822,175 @@
 
 p1m_all = P1M_FILL OR p1m_noFill
 --------------------------------
-p1m_all (HIER TYP=1 CFG=1 HGC=3834011 FGC=4659570 HEC=15365467 FEC=23234401 IGC=38726 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 54/81/83  OPS COMPLETE = 340 OF 408  ELAPSED TIME = 193
+p1m_all (HIER TYP=1 CFG=1 HGC=3834120 FGC=4661376 HEC=15367037 FEC=23323379 IGC=38772 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 54/81/83  OPS COMPLETE = 340 OF 408  ELAPSED TIME = 192
 
 MR_cp1m.waffle.1::<1> = EXT P1M_FILL p1m_all < 0.36 REGION ABUT < 90 SINGULAR
 -----------------------------------------------------------------------------
 MR_cp1m.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 41  REAL TIME = 41  LVHEAP = 46/101/102  OPS COMPLETE = 341 OF 408  ELAPSED TIME = 234
+CPU TIME = 41  REAL TIME = 41  LVHEAP = 46/103/104  OPS COMPLETE = 341 OF 408  ELAPSED TIME = 234
 
-Layer p1m_all DELETED -- LVHEAP = 46/101/102
+Layer p1m_all DELETED -- LVHEAP = 46/103/104
 
-Layer MR_cp1m.waffle.1::<1> DELETED -- LVHEAP = 46/101/102
+Layer MR_cp1m.waffle.1::<1> DELETED -- LVHEAP = 46/103/104
 
 DRC RuleCheck MR_cp1m.waffle.1 COMPLETED. Number of Results = 0 (0)
 
 MR_cp1m.waffle.2a::<1> = P1M_FILL INTERACT FOMpd
 ------------------------------------------------
 MR_cp1m.waffle.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 6  REAL TIME = 6  LVHEAP = 37/101/102  OPS COMPLETE = 342 OF 408  ELAPSED TIME = 240
+CPU TIME = 6  REAL TIME = 6  LVHEAP = 38/103/104  OPS COMPLETE = 342 OF 408  ELAPSED TIME = 239
 
-Layer P1M_FILL DELETED -- LVHEAP = 37/101/102
+Layer P1M_FILL DELETED -- LVHEAP = 38/103/104
 
-Layer MR_cp1m.waffle.2a::<1> DELETED -- LVHEAP = 37/101/102
+Layer MR_cp1m.waffle.2a::<1> DELETED -- LVHEAP = 38/103/104
 
 DRC RuleCheck MR_cp1m.waffle.2a COMPLETED. Number of Results = 0 (0)
 
 LI1M_FILL = OR LI1M_FILL
 ------------------------
-LI1M_FILL (HIER TYP=1 CFG=1 HGC=1251899 FGC=1251899 HEC=5008125 FEC=5008125 IGC=17750 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 38/101/102  OPS COMPLETE = 343 OF 408  ELAPSED TIME = 242
+LI1M_FILL (HIER TYP=1 CFG=1 HGC=1251901 FGC=1251901 HEC=5008133 FEC=5008133 IGC=17758 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 38/103/104  OPS COMPLETE = 343 OF 408  ELAPSED TIME = 242
 
-Original Layer LI1M_FILL DELETED -- LVHEAP = 38/101/102
+Original Layer LI1M_FILL DELETED -- LVHEAP = 38/103/104
 
 LI1Mmk = OR LI1Mmk
 ------------------
 LI1Mmk (HIER TYP=1 CFG=0 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/101/102  OPS COMPLETE = 344 OF 408  ELAPSED TIME = 242
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/103/104  OPS COMPLETE = 344 OF 408  ELAPSED TIME = 242
 
-Original Layer LI1Mmk DELETED -- LVHEAP = 38/101/102
+Original Layer LI1Mmk DELETED -- LVHEAP = 38/103/104
 
 TMP<63> = li1 OR LI1Mmk
 -----------------------
-TMP<63> (HIER TYP=1 CFG=0 HGC=234247 FGC=1890030 HEC=978049 FEC=14071541 IGC=9746 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 39/101/102  OPS COMPLETE = 345 OF 408  ELAPSED TIME = 242
+TMP<63> (HIER TYP=1 CFG=0 HGC=241500 FGC=1910542 HEC=1008225 FEC=14208431 IGC=10307 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 39/103/104  OPS COMPLETE = 345 OF 408  ELAPSED TIME = 242
 
 li1m_all = LI1M_FILL OR TMP<63>
 -------------------------------
-li1m_all (HIER TYP=1 CFG=1 HGC=1486146 FGC=3141929 HEC=5986174 FEC=19079666 IGC=26344 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 40/101/102  OPS COMPLETE = 346 OF 408  ELAPSED TIME = 243
+li1m_all (HIER TYP=1 CFG=1 HGC=1493401 FGC=3162443 HEC=6016358 FEC=19216564 IGC=26913 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 40/103/104  OPS COMPLETE = 346 OF 408  ELAPSED TIME = 242
 
-Layer TMP<63> DELETED -- LVHEAP = 40/101/102
+Layer TMP<63> DELETED -- LVHEAP = 40/103/104
 
 MR_li1m.waffle.1::<1> = EXT LI1M_FILL li1m_all < 0.5 REGION ABUT < 90 SINGULAR
 ------------------------------------------------------------------------------
 MR_li1m.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 22  REAL TIME = 22  LVHEAP = 38/101/102  OPS COMPLETE = 347 OF 408  ELAPSED TIME = 265
+CPU TIME = 21  REAL TIME = 21  LVHEAP = 38/103/104  OPS COMPLETE = 347 OF 408  ELAPSED TIME = 263
 
-Layer li1m_all DELETED -- LVHEAP = 38/101/102
+Layer li1m_all DELETED -- LVHEAP = 38/103/104
 
-Layer MR_li1m.waffle.1::<1> DELETED -- LVHEAP = 38/101/102
+Layer MR_li1m.waffle.1::<1> DELETED -- LVHEAP = 38/103/104
 
 DRC RuleCheck MR_li1m.waffle.1 COMPLETED. Number of Results = 0 (0)
 
 li1_check = FOM_noFill OR p1m_noFill
 ------------------------------------
-li1_check (HIER TYP=1 CFG=1 HGC=4445 FGC=694552 HEC=103932 FEC=17807303 IGC=6720 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/101/102  OPS COMPLETE = 348 OF 408  ELAPSED TIME = 265
+li1_check (HIER TYP=1 CFG=1 HGC=4471 FGC=694762 HEC=107226 FEC=18017566 IGC=6754 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 38/103/104  OPS COMPLETE = 348 OF 408  ELAPSED TIME = 263
 
-Layer FOM_noFill DELETED -- LVHEAP = 38/101/102
+Layer FOM_noFill DELETED -- LVHEAP = 38/103/104
 
-Layer p1m_noFill DELETED -- LVHEAP = 38/101/102
+Layer p1m_noFill DELETED -- LVHEAP = 38/103/104
 
 MR_li1m.waffle.2a::<1> = LI1M_FILL INTERACT li1_check
 -----------------------------------------------------
 MR_li1m.waffle.2a::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 38/101/102  OPS COMPLETE = 349 OF 408  ELAPSED TIME = 267
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 38/103/104  OPS COMPLETE = 349 OF 408  ELAPSED TIME = 265
 
-Layer li1_check DELETED -- LVHEAP = 38/101/102
+Layer li1_check DELETED -- LVHEAP = 38/103/104
 
-Layer MR_li1m.waffle.2a::<1> DELETED -- LVHEAP = 38/101/102
+Layer MR_li1m.waffle.2a::<1> DELETED -- LVHEAP = 38/103/104
 
 DRC RuleCheck MR_li1m.waffle.2a COMPLETED. Number of Results = 0 (0)
 
 MM1_FILL = OR MM1_FILL
 ----------------------
-MM1_FILL (HIER TYP=1 CFG=1 HGC=12084072 FGC=12084072 HEC=48336918 FEC=48336918 IGC=68709 VHC=F VPC=F)
-CPU TIME = 16  REAL TIME = 16  LVHEAP = 43/101/102  OPS COMPLETE = 350 OF 408  ELAPSED TIME = 283
+MM1_FILL (HIER TYP=1 CFG=1 HGC=12065868 FGC=12065868 HEC=48264104 FEC=48264104 IGC=69795 VHC=F VPC=F)
+CPU TIME = 16  REAL TIME = 16  LVHEAP = 43/103/104  OPS COMPLETE = 350 OF 408  ELAPSED TIME = 280
 
-Original Layer MM1_FILL DELETED -- LVHEAP = 43/101/102
+Original Layer MM1_FILL DELETED -- LVHEAP = 43/103/104
 
 MM1mk = OR MM1mk
 ----------------
 MM1mk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/101/102  OPS COMPLETE = 351 OF 408  ELAPSED TIME = 283
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 43/103/104  OPS COMPLETE = 351 OF 408  ELAPSED TIME = 280
 
-Original Layer MM1mk DELETED -- LVHEAP = 43/101/102
+Original Layer MM1mk DELETED -- LVHEAP = 43/103/104
 
 TMP<53> = MM1mk OR MM1_FILL
 ---------------------------
-TMP<53> (HIER TYP=1 CFG=0 HGC=12084076 FGC=12084076 HEC=48336966 FEC=48336966 IGC=68709 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 52/101/102  OPS COMPLETE = 352 OF 408  ELAPSED TIME = 284
+TMP<53> (HIER TYP=1 CFG=0 HGC=12065872 FGC=12065872 HEC=48264152 FEC=48264152 IGC=69795 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 52/103/104  OPS COMPLETE = 352 OF 408  ELAPSED TIME = 282
 
 MM1pd = met1 OR TMP<53>
 -----------------------
-MM1pd (HIER TYP=1 CFG=1 HGC=12318400 FGC=13284228 HEC=51509969 FEC=56543080 IGC=68002 VHC=F VPC=F)
-CPU TIME = 4  REAL TIME = 4  LVHEAP = 55/101/102  OPS COMPLETE = 353 OF 408  ELAPSED TIME = 289
+MM1pd (HIER TYP=1 CFG=1 HGC=12306955 FGC=13276296 HEC=51546365 FEC=56595708 IGC=68759 VHC=F VPC=F)
+CPU TIME = 4  REAL TIME = 4  LVHEAP = 56/103/104  OPS COMPLETE = 353 OF 408  ELAPSED TIME = 286
 
-Layer TMP<53> DELETED -- LVHEAP = 55/101/102
+Layer TMP<53> DELETED -- LVHEAP = 56/103/104
 
 MR_cmm1.waffle.1::<1> = EXT MM1_FILL MM1pd < 0.2 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cmm1.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 92  REAL TIME = 92  LVHEAP = 55/185/186  OPS COMPLETE = 354 OF 408  ELAPSED TIME = 380
+CPU TIME = 91  REAL TIME = 91  LVHEAP = 56/185/186  OPS COMPLETE = 354 OF 408  ELAPSED TIME = 377
 
-Layer MR_cmm1.waffle.1::<1> DELETED -- LVHEAP = 55/185/186
+Layer MR_cmm1.waffle.1::<1> DELETED -- LVHEAP = 56/185/186
 
 DRC RuleCheck MR_cmm1.waffle.1 COMPLETED. Number of Results = 0 (0)
 
 MR_cmm1.waffle.2::TMP<64> = met1 OR MM1mk
 -----------------------------------------
-MR_cmm1.waffle.2::TMP<64> (HIER TYP=1 CFG=1 HGC=234328 FGC=1200156 HEC=3173051 FEC=8206162 IGC=12251 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 55/185/186  OPS COMPLETE = 355 OF 408  ELAPSED TIME = 381
+MR_cmm1.waffle.2::TMP<64> (HIER TYP=1 CFG=1 HGC=241087 FGC=1210428 HEC=3282261 FEC=8331604 IGC=12263 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 56/185/186  OPS COMPLETE = 355 OF 408  ELAPSED TIME = 378
 
-Layer met1 DELETED -- LVHEAP = 55/185/186
+Layer met1 DELETED -- LVHEAP = 56/185/186
 
-Layer MM1mk DELETED -- LVHEAP = 55/185/186
+Layer MM1mk DELETED -- LVHEAP = 56/185/186
 
 MR_cmm1.waffle.2::<1> = MM1_FILL INTERACT MR_cmm1.waffle.2::TMP<64>
 -------------------------------------------------------------------
 MR_cmm1.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 12  REAL TIME = 12  LVHEAP = 43/185/186  OPS COMPLETE = 356 OF 408  ELAPSED TIME = 392
+CPU TIME = 11  REAL TIME = 11  LVHEAP = 44/185/186  OPS COMPLETE = 356 OF 408  ELAPSED TIME = 389
 
-Layer MM1_FILL DELETED -- LVHEAP = 43/185/186
+Layer MM1_FILL DELETED -- LVHEAP = 44/185/186
 
-Layer MR_cmm1.waffle.2::TMP<64> DELETED -- LVHEAP = 43/185/186
+Layer MR_cmm1.waffle.2::TMP<64> DELETED -- LVHEAP = 44/185/186
 
-Layer MR_cmm1.waffle.2::<1> DELETED -- LVHEAP = 43/185/186
+Layer MR_cmm1.waffle.2::<1> DELETED -- LVHEAP = 44/185/186
 
 DRC RuleCheck MR_cmm1.waffle.2 COMPLETED. Number of Results = 0 (0)
 
 MM2_FILL = OR MM2_FILL
 ----------------------
-MM2_FILL (HIER TYP=1 CFG=1 HGC=9571468 FGC=9571468 HEC=38286839 FEC=38286839 IGC=74306 VHC=F VPC=F)
-CPU TIME = 14  REAL TIME = 14  LVHEAP = 48/185/186  OPS COMPLETE = 357 OF 408  ELAPSED TIME = 406
+MM2_FILL (HIER TYP=1 CFG=1 HGC=9557361 FGC=9557361 HEC=38230409 FEC=38230409 IGC=74406 VHC=F VPC=F)
+CPU TIME = 14  REAL TIME = 14  LVHEAP = 48/185/186  OPS COMPLETE = 357 OF 408  ELAPSED TIME = 402
 
 Original Layer MM2_FILL DELETED -- LVHEAP = 48/185/186
 
 MM2mk = OR MM2mk
 ----------------
 MM2mk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 48/185/186  OPS COMPLETE = 358 OF 408  ELAPSED TIME = 406
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 48/185/186  OPS COMPLETE = 358 OF 408  ELAPSED TIME = 402
 
 Original Layer MM2mk DELETED -- LVHEAP = 48/185/186
 
 TMP<54> = MM2mk OR MM2_FILL
 ---------------------------
-TMP<54> (HIER TYP=1 CFG=0 HGC=9571472 FGC=9571472 HEC=38286887 FEC=38286887 IGC=74306 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 56/185/186  OPS COMPLETE = 359 OF 408  ELAPSED TIME = 407
+TMP<54> (HIER TYP=1 CFG=0 HGC=9557365 FGC=9557365 HEC=38230457 FEC=38230457 IGC=74406 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 57/185/186  OPS COMPLETE = 359 OF 408  ELAPSED TIME = 404
 
 MM2pd = met2 OR TMP<54>
 -----------------------
-MM2pd (HIER TYP=1 CFG=1 HGC=9769223 FGC=9907131 HEC=40540088 FEC=41631434 IGC=81482 VHC=F VPC=F)
-CPU TIME = 6  REAL TIME = 6  LVHEAP = 59/185/186  OPS COMPLETE = 360 OF 408  ELAPSED TIME = 413
+MM2pd (HIER TYP=1 CFG=1 HGC=9760879 FGC=9898758 HEC=40564712 FEC=41655836 IGC=81623 VHC=F VPC=F)
+CPU TIME = 6  REAL TIME = 6  LVHEAP = 59/185/186  OPS COMPLETE = 360 OF 408  ELAPSED TIME = 409
 
 Layer TMP<54> DELETED -- LVHEAP = 59/185/186
 
 MR_cmm2.waffle.1::<1> = EXT MM2_FILL MM2pd < 0.2 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cmm2.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 74  REAL TIME = 74  LVHEAP = 59/185/186  OPS COMPLETE = 361 OF 408  ELAPSED TIME = 487
+CPU TIME = 73  REAL TIME = 73  LVHEAP = 59/185/186  OPS COMPLETE = 361 OF 408  ELAPSED TIME = 483
 
 Layer MR_cmm2.waffle.1::<1> DELETED -- LVHEAP = 59/185/186
 
@@ -7985,8 +7998,8 @@
 
 MR_cmm2.waffle.2::TMP<65> = met2 OR MM2mk
 -----------------------------------------
-MR_cmm2.waffle.2::TMP<65> (HIER TYP=1 CFG=1 HGC=197755 FGC=335663 HEC=2253249 FEC=3344595 IGC=29404 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 59/185/186  OPS COMPLETE = 362 OF 408  ELAPSED TIME = 487
+MR_cmm2.waffle.2::TMP<65> (HIER TYP=1 CFG=1 HGC=203518 FGC=341397 HEC=2334303 FEC=3425427 IGC=29641 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 59/185/186  OPS COMPLETE = 362 OF 408  ELAPSED TIME = 483
 
 Layer met2 DELETED -- LVHEAP = 59/185/186
 
@@ -7995,7 +8008,7 @@
 MR_cmm2.waffle.2::<1> = MM2_FILL INTERACT MR_cmm2.waffle.2::TMP<65>
 -------------------------------------------------------------------
 MR_cmm2.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 10  REAL TIME = 10  LVHEAP = 48/185/186  OPS COMPLETE = 363 OF 408  ELAPSED TIME = 497
+CPU TIME = 10  REAL TIME = 10  LVHEAP = 48/185/186  OPS COMPLETE = 363 OF 408  ELAPSED TIME = 493
 
 Layer MM2_FILL DELETED -- LVHEAP = 48/185/186
 
@@ -8007,34 +8020,34 @@
 
 MM3_FILL = OR MM3_FILL
 ----------------------
-MM3_FILL (HIER TYP=1 CFG=1 HGC=4025168 FGC=4025168 HEC=16101250 FEC=16101250 IGC=46194 VHC=F VPC=F)
-CPU TIME = 7  REAL TIME = 7  LVHEAP = 50/185/186  OPS COMPLETE = 364 OF 408  ELAPSED TIME = 504
+MM3_FILL (HIER TYP=1 CFG=1 HGC=4032393 FGC=4032393 HEC=16130146 FEC=16130146 IGC=45086 VHC=F VPC=F)
+CPU TIME = 7  REAL TIME = 7  LVHEAP = 50/185/186  OPS COMPLETE = 364 OF 408  ELAPSED TIME = 500
 
 Original Layer MM3_FILL DELETED -- LVHEAP = 50/185/186
 
 MM3mk = OR MM3mk
 ----------------
 MM3mk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 365 OF 408  ELAPSED TIME = 504
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 365 OF 408  ELAPSED TIME = 500
 
 Original Layer MM3mk DELETED -- LVHEAP = 50/185/186
 
 TMP<55> = MM3mk OR MM3_FILL
 ---------------------------
-TMP<55> (HIER TYP=1 CFG=0 HGC=4025172 FGC=4025172 HEC=16101298 FEC=16101298 IGC=46194 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 54/185/186  OPS COMPLETE = 366 OF 408  ELAPSED TIME = 504
+TMP<55> (HIER TYP=1 CFG=0 HGC=4032397 FGC=4032397 HEC=16130194 FEC=16130194 IGC=45086 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 55/185/186  OPS COMPLETE = 366 OF 408  ELAPSED TIME = 500
 
 MM3pd = met3 OR TMP<55>
 -----------------------
-MM3pd (HIER TYP=1 CFG=1 HGC=4065308 FGC=4084343 HEC=16434338 FEC=16545129 IGC=50091 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 55/185/186  OPS COMPLETE = 367 OF 408  ELAPSED TIME = 507
+MM3pd (HIER TYP=1 CFG=1 HGC=4073888 FGC=4092907 HEC=16481556 FEC=16592283 IGC=48990 VHC=F VPC=F)
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 55/185/186  OPS COMPLETE = 367 OF 408  ELAPSED TIME = 504
 
 Layer TMP<55> DELETED -- LVHEAP = 55/185/186
 
 MR_cmm3.waffle.1::<1> = EXT MM3_FILL MM3pd < 0.3 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cmm3.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 36  REAL TIME = 36  LVHEAP = 55/185/186  OPS COMPLETE = 368 OF 408  ELAPSED TIME = 544
+CPU TIME = 35  REAL TIME = 35  LVHEAP = 55/185/186  OPS COMPLETE = 368 OF 408  ELAPSED TIME = 539
 
 Layer MR_cmm3.waffle.1::<1> DELETED -- LVHEAP = 55/185/186
 
@@ -8042,8 +8055,8 @@
 
 MR_cmm3.waffle.2::TMP<66> = met3 OR MM3mk
 -----------------------------------------
-MR_cmm3.waffle.2::TMP<66> (HIER TYP=1 CFG=1 HGC=40140 FGC=59175 HEC=333088 FEC=443879 IGC=13019 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 55/185/186  OPS COMPLETE = 369 OF 408  ELAPSED TIME = 544
+MR_cmm3.waffle.2::TMP<66> (HIER TYP=1 CFG=1 HGC=41495 FGC=60514 HEC=351410 FEC=462137 IGC=13087 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 55/185/186  OPS COMPLETE = 369 OF 408  ELAPSED TIME = 539
 
 Layer met3 DELETED -- LVHEAP = 55/185/186
 
@@ -8052,7 +8065,7 @@
 MR_cmm3.waffle.2::<1> = MM3_FILL INTERACT MR_cmm3.waffle.2::TMP<66>
 -------------------------------------------------------------------
 MR_cmm3.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 7  REAL TIME = 7  LVHEAP = 50/185/186  OPS COMPLETE = 370 OF 408  ELAPSED TIME = 550
+CPU TIME = 6  REAL TIME = 6  LVHEAP = 50/185/186  OPS COMPLETE = 370 OF 408  ELAPSED TIME = 546
 
 Layer MM3_FILL DELETED -- LVHEAP = 50/185/186
 
@@ -8064,34 +8077,34 @@
 
 MM4_FILL = OR MM4_FILL
 ----------------------
-MM4_FILL (HIER TYP=1 CFG=1 HGC=3254923 FGC=3254923 HEC=13020172 FEC=13020172 IGC=41758 VHC=F VPC=F)
-CPU TIME = 5  REAL TIME = 5  LVHEAP = 50/185/186  OPS COMPLETE = 371 OF 408  ELAPSED TIME = 555
+MM4_FILL (HIER TYP=1 CFG=1 HGC=3262359 FGC=3262359 HEC=13049910 FEC=13049910 IGC=41785 VHC=F VPC=F)
+CPU TIME = 5  REAL TIME = 5  LVHEAP = 51/185/186  OPS COMPLETE = 371 OF 408  ELAPSED TIME = 551
 
-Original Layer MM4_FILL DELETED -- LVHEAP = 50/185/186
+Original Layer MM4_FILL DELETED -- LVHEAP = 51/185/186
 
 MM4mk = OR MM4mk
 ----------------
 MM4mk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 372 OF 408  ELAPSED TIME = 555
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 372 OF 408  ELAPSED TIME = 551
 
-Original Layer MM4mk DELETED -- LVHEAP = 50/185/186
+Original Layer MM4mk DELETED -- LVHEAP = 51/185/186
 
 TMP<56> = MM4mk OR MM4_FILL
 ---------------------------
-TMP<56> (HIER TYP=1 CFG=0 HGC=3254927 FGC=3254927 HEC=13020220 FEC=13020220 IGC=41758 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 53/185/186  OPS COMPLETE = 373 OF 408  ELAPSED TIME = 556
+TMP<56> (HIER TYP=1 CFG=0 HGC=3262363 FGC=3262363 HEC=13049958 FEC=13049958 IGC=41785 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 53/185/186  OPS COMPLETE = 373 OF 408  ELAPSED TIME = 551
 
 MM4pd = met4 OR TMP<56>
 -----------------------
-MM4pd (HIER TYP=1 CFG=1 HGC=3265687 FGC=3305872 HEC=13086440 FEC=13257178 IGC=39892 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 53/185/186  OPS COMPLETE = 374 OF 408  ELAPSED TIME = 557
+MM4pd (HIER TYP=1 CFG=1 HGC=3273402 FGC=3313579 HEC=13118086 FEC=13288792 IGC=39844 VHC=F VPC=F)
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 53/185/186  OPS COMPLETE = 374 OF 408  ELAPSED TIME = 552
 
 Layer TMP<56> DELETED -- LVHEAP = 53/185/186
 
 MR_cmm4.waffle.1::<1> = EXT MM4_FILL MM4pd < 0.3 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cmm4.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 22  REAL TIME = 22  LVHEAP = 53/185/186  OPS COMPLETE = 375 OF 408  ELAPSED TIME = 579
+CPU TIME = 22  REAL TIME = 22  LVHEAP = 53/185/186  OPS COMPLETE = 375 OF 408  ELAPSED TIME = 574
 
 Layer MR_cmm4.waffle.1::<1> DELETED -- LVHEAP = 53/185/186
 
@@ -8099,8 +8112,8 @@
 
 MR_cmm4.waffle.2::TMP<67> = met4 OR MM4mk
 -----------------------------------------
-MR_cmm4.waffle.2::TMP<67> (HIER TYP=1 CFG=1 HGC=10764 FGC=50949 HEC=66268 FEC=237006 IGC=12327 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 53/185/186  OPS COMPLETE = 376 OF 408  ELAPSED TIME = 579
+MR_cmm4.waffle.2::TMP<67> (HIER TYP=1 CFG=1 HGC=11043 FGC=51220 HEC=68176 FEC=238882 IGC=12490 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 53/185/186  OPS COMPLETE = 376 OF 408  ELAPSED TIME = 575
 
 Layer met4 DELETED -- LVHEAP = 53/185/186
 
@@ -8109,46 +8122,46 @@
 MR_cmm4.waffle.2::<1> = MM4_FILL INTERACT MR_cmm4.waffle.2::TMP<67>
 -------------------------------------------------------------------
 MR_cmm4.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 3  REAL TIME = 3  LVHEAP = 50/185/186  OPS COMPLETE = 377 OF 408  ELAPSED TIME = 582
+CPU TIME = 3  REAL TIME = 3  LVHEAP = 51/185/186  OPS COMPLETE = 377 OF 408  ELAPSED TIME = 577
 
-Layer MM4_FILL DELETED -- LVHEAP = 50/185/186
+Layer MM4_FILL DELETED -- LVHEAP = 51/185/186
 
-Layer MR_cmm4.waffle.2::TMP<67> DELETED -- LVHEAP = 50/185/186
+Layer MR_cmm4.waffle.2::TMP<67> DELETED -- LVHEAP = 51/185/186
 
-Layer MR_cmm4.waffle.2::<1> DELETED -- LVHEAP = 50/185/186
+Layer MR_cmm4.waffle.2::<1> DELETED -- LVHEAP = 51/185/186
 
 DRC RuleCheck MR_cmm4.waffle.2 COMPLETED. Number of Results = 0 (0)
 
 MM5_FILL = OR MM5_FILL
 ----------------------
-MM5_FILL (HIER TYP=1 CFG=1 HGC=312905 FGC=312905 HEC=1251844 FEC=1251844 IGC=19032 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 378 OF 408  ELAPSED TIME = 582
+MM5_FILL (HIER TYP=1 CFG=1 HGC=309402 FGC=309402 HEC=1237804 FEC=1237804 IGC=15831 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 378 OF 408  ELAPSED TIME = 578
 
-Original Layer MM5_FILL DELETED -- LVHEAP = 50/185/186
+Original Layer MM5_FILL DELETED -- LVHEAP = 51/185/186
 
 MM5mk = OR MM5mk
 ----------------
 MM5mk (HIER TYP=1 CFG=1 HGC=4 FGC=4 HEC=48 FEC=48 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 379 OF 408  ELAPSED TIME = 582
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 379 OF 408  ELAPSED TIME = 578
 
-Original Layer MM5mk DELETED -- LVHEAP = 50/185/186
+Original Layer MM5mk DELETED -- LVHEAP = 51/185/186
 
 TMP<57> = MM5mk OR MM5_FILL
 ---------------------------
-TMP<57> (HIER TYP=1 CFG=0 HGC=312909 FGC=312909 HEC=1251892 FEC=1251892 IGC=19032 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 380 OF 408  ELAPSED TIME = 582
+TMP<57> (HIER TYP=1 CFG=0 HGC=309406 FGC=309406 HEC=1237852 FEC=1237852 IGC=15831 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 380 OF 408  ELAPSED TIME = 578
 
 MM5pd = met5 OR TMP<57>
 -----------------------
-MM5pd (HIER TYP=1 CFG=1 HGC=315295 FGC=334357 HEC=1264112 FEC=1342733 IGC=20306 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 381 OF 408  ELAPSED TIME = 583
+MM5pd (HIER TYP=1 CFG=1 HGC=311863 FGC=330923 HEC=1250254 FEC=1328867 IGC=17167 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 381 OF 408  ELAPSED TIME = 578
 
 Layer TMP<57> DELETED -- LVHEAP = 51/185/186
 
 MR_cmm5.waffle.1::<1> = EXT MM5_FILL MM5pd < 1.6 REGION ABUT < 90 SINGULAR
 --------------------------------------------------------------------------
 MR_cmm5.waffle.1::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 51/185/186  OPS COMPLETE = 382 OF 408  ELAPSED TIME = 585
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 51/185/186  OPS COMPLETE = 382 OF 408  ELAPSED TIME = 580
 
 Layer MR_cmm5.waffle.1::<1> DELETED -- LVHEAP = 51/185/186
 
@@ -8156,8 +8169,8 @@
 
 MR_cmm5.waffle.2::TMP<68> = met5 OR MM5mk
 -----------------------------------------
-MR_cmm5.waffle.2::TMP<68> (HIER TYP=1 CFG=1 HGC=2390 FGC=21452 HEC=12268 FEC=90889 IGC=3780 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 383 OF 408  ELAPSED TIME = 585
+MR_cmm5.waffle.2::TMP<68> (HIER TYP=1 CFG=1 HGC=2461 FGC=21521 HEC=12450 FEC=91063 IGC=4021 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 383 OF 408  ELAPSED TIME = 580
 
 Layer met5 DELETED -- LVHEAP = 51/185/186
 
@@ -8166,34 +8179,34 @@
 MR_cmm5.waffle.2::<1> = MM5_FILL INTERACT MR_cmm5.waffle.2::TMP<68>
 -------------------------------------------------------------------
 MR_cmm5.waffle.2::<1> (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 384 OF 408  ELAPSED TIME = 585
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 384 OF 408  ELAPSED TIME = 581
 
-Layer MM5_FILL DELETED -- LVHEAP = 50/185/186
+Layer MM5_FILL DELETED -- LVHEAP = 51/185/186
 
-Layer MR_cmm5.waffle.2::TMP<68> DELETED -- LVHEAP = 50/185/186
+Layer MR_cmm5.waffle.2::TMP<68> DELETED -- LVHEAP = 51/185/186
 
-Layer MR_cmm5.waffle.2::<1> DELETED -- LVHEAP = 50/185/186
+Layer MR_cmm5.waffle.2::<1> DELETED -- LVHEAP = 51/185/186
 
 DRC RuleCheck MR_cmm5.waffle.2 COMPLETED. Number of Results = 0 (0)
 
 SEALwithHole = HOLES SEALID
 ---------------------------
-SEALwithHole (HIER TYP=1 CFG=1 HGC=906 FGC=9292 HEC=10301 FEC=53896 IGC=2191 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 385 OF 408  ELAPSED TIME = 585
+SEALwithHole (HIER TYP=1 CFG=1 HGC=909 FGC=9123 HEC=9467 FEC=52374 IGC=2212 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 385 OF 408  ELAPSED TIME = 581
 
-Layer SEALID DELETED -- LVHEAP = 50/185/186
+Layer SEALID DELETED -- LVHEAP = 51/185/186
 
 waffleChpBnd = COPY SEALwithHole
 --------------------------------
-waffleChpBnd (HIER TYP=1 CFG=1 HGC=906 FGC=9292 HEC=10301 FEC=53896 IGC=2191 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 386 OF 408  ELAPSED TIME = 585
+waffleChpBnd (HIER TYP=1 CFG=1 HGC=909 FGC=9123 HEC=9467 FEC=52374 IGC=2212 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 51/185/186  OPS COMPLETE = 386 OF 408  ELAPSED TIME = 581
 
 fomMinPD_err = DENSITY FOMpd < 0.33 INSIDE OF LAYER waffleChpBnd WINDOW 700 STEP 70 BACKUP RDB fom_minPD.rdb
 fomMaxPD_err = DENSITY FOMpd > 0.57 INSIDE OF LAYER waffleChpBnd WINDOW 700 STEP 70 BACKUP RDB fom_maxPD.rdb
 ------------------------------------------------------------------------------------------------------------
 fomMinPD_err (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 fomMaxPD_err (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 50/185/186  OPS COMPLETE = 388 OF 408  ELAPSED TIME = 586
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 50/185/186  OPS COMPLETE = 388 OF 408  ELAPSED TIME = 581
 
 Layer FOMpd DELETED -- LVHEAP = 50/185/186
 
@@ -8209,8 +8222,8 @@
 
 TMP<70> = LI1Mmk OR LI1M_FILL
 -----------------------------
-TMP<70> (HIER TYP=1 CFG=0 HGC=1251903 FGC=1251903 HEC=5008173 FEC=5008173 IGC=17750 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 389 OF 408  ELAPSED TIME = 586
+TMP<70> (HIER TYP=1 CFG=0 HGC=1251905 FGC=1251905 HEC=5008181 FEC=5008181 IGC=17758 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 389 OF 408  ELAPSED TIME = 581
 
 Layer LI1Mmk DELETED -- LVHEAP = 50/185/186
 
@@ -8218,8 +8231,8 @@
 
 TMP<69> = li1 OR TMP<70>
 ------------------------
-TMP<69> (HIER TYP=1 CFG=0 HGC=1486146 FGC=3141929 HEC=5986174 FEC=19079666 IGC=26344 VHC=F VPC=F)
-CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 390 OF 408  ELAPSED TIME = 586
+TMP<69> (HIER TYP=1 CFG=0 HGC=1493401 FGC=3162443 HEC=6016358 FEC=19216564 IGC=26913 VHC=F VPC=F)
+CPU TIME = 0  REAL TIME = 0  LVHEAP = 50/185/186  OPS COMPLETE = 390 OF 408  ELAPSED TIME = 582
 
 Layer li1 DELETED -- LVHEAP = 50/185/186
 
@@ -8227,17 +8240,17 @@
 
 CAnotLI1M = SEALwithHole NOT TMP<69>
 ------------------------------------
-CAnotLI1M (HIER TYP=1 CFG=1 HGC=85683 FGC=240214 HEC=14676596 FEC=20568741 IGC=241489 VHC=F VPC=F)
-CPU TIME = 24  REAL TIME = 24  LVHEAP = 54/185/186  OPS COMPLETE = 391 OF 408  ELAPSED TIME = 610
+CAnotLI1M (HIER TYP=1 CFG=1 HGC=86625 FGC=240194 HEC=14805422 FEC=20675816 IGC=241511 VHC=F VPC=F)
+CPU TIME = 23  REAL TIME = 23  LVHEAP = 55/185/186  OPS COMPLETE = 391 OF 408  ELAPSED TIME = 605
 
-Layer TMP<69> DELETED -- LVHEAP = 54/185/186
+Layer TMP<69> DELETED -- LVHEAP = 55/185/186
 
 li1mPDCAmin = DENSITY CAnotLI1M < 0.4 INSIDE OF LAYER SEALwithHole BACKUP RDB li1mCAmin_PD.rdb
 li1mPDCAmax = DENSITY CAnotLI1M > 0.65 INSIDE OF LAYER SEALwithHole BACKUP RDB li1mCAmax_PD.rdb
 -----------------------------------------------------------------------------------------------
 li1mPDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 li1mPDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 7  REAL TIME = 7  LVHEAP = 48/185/186  OPS COMPLETE = 393 OF 408  ELAPSED TIME = 617
+CPU TIME = 7  REAL TIME = 7  LVHEAP = 48/185/186  OPS COMPLETE = 393 OF 408  ELAPSED TIME = 612
 
 Layer CAnotLI1M DELETED -- LVHEAP = 48/185/186
 
@@ -8251,17 +8264,17 @@
 
 CAnotMM1 = SEALwithHole NOT MM1pd
 ---------------------------------
-CAnotMM1 (HIER TYP=1 CFG=1 HGC=789762 FGC=2515998 HEC=72298921 FEC=91819508 IGC=2578618 VHC=F VPC=F)
-CPU TIME = 89  REAL TIME = 89  LVHEAP = 55/311/312  OPS COMPLETE = 394 OF 408  ELAPSED TIME = 706
+CAnotMM1 (HIER TYP=1 CFG=1 HGC=783322 FGC=2504640 HEC=72228246 FEC=91652131 IGC=2578456 VHC=F VPC=F)
+CPU TIME = 88  REAL TIME = 88  LVHEAP = 56/311/312  OPS COMPLETE = 394 OF 408  ELAPSED TIME = 699
 
-Layer MM1pd DELETED -- LVHEAP = 55/311/312
+Layer MM1pd DELETED -- LVHEAP = 56/311/312
 
 mm1PDCAmin = DENSITY CAnotMM1 < 0.4 INSIDE OF LAYER SEALwithHole BACKUP RDB mm1CAmin_PD.rdb
 mm1PDCAmax = DENSITY CAnotMM1 > 0.65 INSIDE OF LAYER SEALwithHole BACKUP RDB mm1CAmax_PD.rdb
 --------------------------------------------------------------------------------------------
 mm1PDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 mm1PDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 33  REAL TIME = 33  LVHEAP = 36/373/374  OPS COMPLETE = 396 OF 408  ELAPSED TIME = 739
+CPU TIME = 32  REAL TIME = 33  LVHEAP = 36/373/374  OPS COMPLETE = 396 OF 408  ELAPSED TIME = 732
 
 Layer CAnotMM1 DELETED -- LVHEAP = 36/373/374
 
@@ -8275,17 +8288,17 @@
 
 CAnotMM2 = SEALwithHole NOT MM2pd
 ---------------------------------
-CAnotMM2 (HIER TYP=1 CFG=1 HGC=372017 FGC=821390 HEC=53545737 FEC=59818804 IGC=1613526 VHC=F VPC=F)
-CPU TIME = 66  REAL TIME = 66  LVHEAP = 42/373/374  OPS COMPLETE = 397 OF 408  ELAPSED TIME = 805
+CAnotMM2 (HIER TYP=1 CFG=1 HGC=373131 FGC=824594 HEC=53569104 FEC=59850061 IGC=1613497 VHC=F VPC=F)
+CPU TIME = 64  REAL TIME = 64  LVHEAP = 43/373/374  OPS COMPLETE = 397 OF 408  ELAPSED TIME = 796
 
-Layer MM2pd DELETED -- LVHEAP = 42/373/374
+Layer MM2pd DELETED -- LVHEAP = 43/373/374
 
 mm2PDCAmin = DENSITY CAnotMM2 < 0.4 INSIDE OF LAYER SEALwithHole BACKUP RDB mm2CAmin_PD.rdb
 mm2PDCAmax = DENSITY CAnotMM2 > 0.65 INSIDE OF LAYER SEALwithHole BACKUP RDB mm2CAmax_PD.rdb
 --------------------------------------------------------------------------------------------
 mm2PDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 mm2PDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 25  REAL TIME = 25  LVHEAP = 25/373/374  OPS COMPLETE = 399 OF 408  ELAPSED TIME = 829
+CPU TIME = 24  REAL TIME = 24  LVHEAP = 25/373/374  OPS COMPLETE = 399 OF 408  ELAPSED TIME = 820
 
 Layer CAnotMM2 DELETED -- LVHEAP = 25/373/374
 
@@ -8299,8 +8312,8 @@
 
 CAnotMM3 = SEALwithHole NOT MM3pd
 ---------------------------------
-CAnotMM3 (HIER TYP=1 CFG=1 HGC=201964 FGC=474577 HEC=23378572 FEC=27467992 IGC=659103 VHC=F VPC=F)
-CPU TIME = 38  REAL TIME = 38  LVHEAP = 28/373/374  OPS COMPLETE = 400 OF 408  ELAPSED TIME = 868
+CAnotMM3 (HIER TYP=1 CFG=1 HGC=202692 FGC=475444 HEC=23450537 FEC=27545885 IGC=659288 VHC=F VPC=F)
+CPU TIME = 37  REAL TIME = 37  LVHEAP = 28/373/374  OPS COMPLETE = 400 OF 408  ELAPSED TIME = 857
 
 Layer MM3pd DELETED -- LVHEAP = 28/373/374
 
@@ -8309,7 +8322,7 @@
 --------------------------------------------------------------------------------------------
 mm3PDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 mm3PDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 11  REAL TIME = 11  LVHEAP = 20/373/374  OPS COMPLETE = 402 OF 408  ELAPSED TIME = 879
+CPU TIME = 11  REAL TIME = 11  LVHEAP = 20/373/374  OPS COMPLETE = 402 OF 408  ELAPSED TIME = 868
 
 Layer CAnotMM3 DELETED -- LVHEAP = 20/373/374
 
@@ -8323,41 +8336,41 @@
 
 CAnotMM4 = SEALwithHole NOT MM4pd
 ---------------------------------
-CAnotMM4 (HIER TYP=1 CFG=1 HGC=197745 FGC=443245 HEC=18325777 FEC=20967340 IGC=632908 VHC=F VPC=F)
-CPU TIME = 22  REAL TIME = 22  LVHEAP = 22/373/374  OPS COMPLETE = 403 OF 408  ELAPSED TIME = 901
+CAnotMM4 (HIER TYP=1 CFG=1 HGC=198337 FGC=443833 HEC=18367419 FEC=21011536 IGC=632886 VHC=F VPC=F)
+CPU TIME = 22  REAL TIME = 22  LVHEAP = 23/373/374  OPS COMPLETE = 403 OF 408  ELAPSED TIME = 890
 
-Layer MM4pd DELETED -- LVHEAP = 22/373/374
+Layer MM4pd DELETED -- LVHEAP = 23/373/374
 
 mm4PDCAmin = DENSITY CAnotMM4 < 0.4 INSIDE OF LAYER SEALwithHole BACKUP RDB mm4CAmin_PD.rdb
 mm4PDCAmax = DENSITY CAnotMM4 > 0.65 INSIDE OF LAYER SEALwithHole BACKUP RDB mm4CAmax_PD.rdb
 --------------------------------------------------------------------------------------------
 mm4PDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 mm4PDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 7  REAL TIME = 7  LVHEAP = 17/373/374  OPS COMPLETE = 405 OF 408  ELAPSED TIME = 908
+CPU TIME = 7  REAL TIME = 7  LVHEAP = 18/373/374  OPS COMPLETE = 405 OF 408  ELAPSED TIME = 897
 
-Layer CAnotMM4 DELETED -- LVHEAP = 17/373/374
+Layer CAnotMM4 DELETED -- LVHEAP = 18/373/374
 
-Layer mm4PDCAmin DELETED -- LVHEAP = 17/373/374
+Layer mm4PDCAmin DELETED -- LVHEAP = 18/373/374
 
 DRC RuleCheck MR_cmm4.pd.3 COMPLETED. Number of Results = 0 (0)
 
-Layer mm4PDCAmax DELETED -- LVHEAP = 17/373/374
+Layer mm4PDCAmax DELETED -- LVHEAP = 18/373/374
 
 DRC RuleCheck MR_cmm4.pd.4 COMPLETED. Number of Results = 0 (0)
 
 CAnotMM5 = SEALwithHole NOT MM5pd
 ---------------------------------
-CAnotMM5 (HIER TYP=1 CFG=1 HGC=9361 FGC=21254 HEC=1622540 FEC=1707232 IGC=56891 VHC=F VPC=F)
-CPU TIME = 2  REAL TIME = 2  LVHEAP = 17/373/374  OPS COMPLETE = 406 OF 408  ELAPSED TIME = 910
+CAnotMM5 (HIER TYP=1 CFG=1 HGC=8105 FGC=19355 HEC=1603445 FEC=1682684 IGC=53904 VHC=F VPC=F)
+CPU TIME = 2  REAL TIME = 2  LVHEAP = 18/373/374  OPS COMPLETE = 406 OF 408  ELAPSED TIME = 898
 
-Layer MM5pd DELETED -- LVHEAP = 17/373/374
+Layer MM5pd DELETED -- LVHEAP = 18/373/374
 
 mm5PDCAmin = DENSITY CAnotMM5 < 0.24 INSIDE OF LAYER SEALwithHole BACKUP RDB mm5CAmin_PD.rdb
 mm5PDCAmax = DENSITY CAnotMM5 > 0.55 INSIDE OF LAYER SEALwithHole BACKUP RDB mm5CAmax_PD.rdb
 --------------------------------------------------------------------------------------------
 mm5PDCAmin (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
 mm5PDCAmax (HIER TYP=1 CFG=1 HGC=0 FGC=0 HEC=0 FEC=0 IGC=0 VHC=F VPC=F)
-CPU TIME = 1  REAL TIME = 1  LVHEAP = 17/373/374  OPS COMPLETE = 408 OF 408  ELAPSED TIME = 910
+CPU TIME = 1  REAL TIME = 1  LVHEAP = 17/373/374  OPS COMPLETE = 408 OF 408  ELAPSED TIME = 899
 
 Layer CAnotMM5 DELETED -- LVHEAP = 17/373/374
 
@@ -8373,10 +8386,10 @@
 
 DRC RuleCheck MR_cmm5.pd.5 COMPLETED. Number of Results = 0 (0)
 
-Cumulative ONE-LAYER BOOLEAN Time: CPU = 67  REAL = 67
-Cumulative TWO-LAYER BOOLEAN Time: CPU = 279  REAL = 279
+Cumulative ONE-LAYER BOOLEAN Time: CPU = 66  REAL = 66
+Cumulative TWO-LAYER BOOLEAN Time: CPU = 273  REAL = 273
 Cumulative INSIDE/EXTENT CELL Time: CPU = 0  REAL = 0
-Cumulative POLYGON TOPOLOGICAL Time: CPU = 43  REAL = 43
+Cumulative POLYGON TOPOLOGICAL Time: CPU = 42  REAL = 42
 Cumulative POLYGON MEASUREMENT Time: CPU = 10  REAL = 10
 Cumulative HOLES Time: CPU = 5  REAL = 5
 Cumulative SIZE Time: CPU = 0  REAL = 0
@@ -8384,20 +8397,20 @@
 Cumulative EDGE TOPOLOGICAL Time: CPU = 0  REAL = 0
 Cumulative EDGE MEASUREMENT Time: CPU = 13  REAL = 13
 Cumulative ONE-LAYER DRC Time: CPU = 25  REAL = 25
-Cumulative TWO-LAYER DRC Time: CPU = 335  REAL = 335
+Cumulative TWO-LAYER DRC Time: CPU = 333  REAL = 333
 Cumulative DENSITY Time: CPU = 83  REAL = 83
 Cumulative WITH EDGE Time: CPU = 0  REAL = 0
 Cumulative MISCELLANEOUS Time: CPU = 0  REAL = 0
 Cumulative CONNECT Time: CPU = 18  REAL = 19
 Cumulative RDB Time: CPU = 0  REAL = 0
 
---- CALIBRE::DRC-H EXECUTIVE MODULE COMPLETED.  CPU TIME = 888  REAL TIME = 889
+--- CALIBRE::DRC-H EXECUTIVE MODULE COMPLETED.  CPU TIME = 878  REAL TIME = 879
 --- TOTAL RULECHECKS EXECUTED = 171
 --- TOTAL RESULTS GENERATED = 0 (0)
 --- DRC RESULTS DATABASE FILE = caravel_00020021.drc.results (ASCII)
 
---- CALIBRE::DRC-H COMPLETED - Tue Dec  7 01:49:26 2021
---- TOTAL CPU TIME = 904  REAL TIME = 909
+--- CALIBRE::DRC-H COMPLETED - Fri ... XX XX:XX:XX 2...
+--- TOTAL CPU TIME = 893  REAL TIME = 898
 --- PROCESSOR COUNT = 1
 --- SUMMARY REPORT FILE = caravel_00020021.drc.summary
 
diff --git a/signoff/cdrcpost/caravel_00020021/drcmr/_s8_drcRules_MR_ b/signoff/cdrcpost/caravel_00020021/drcmr/_s8_drcRules_MR_
index 11090e9..3237eae 100644
--- a/signoff/cdrcpost/caravel_00020021/drcmr/_s8_drcRules_MR_
+++ b/signoff/cdrcpost/caravel_00020021/drcmr/_s8_drcRules_MR_
@@ -1,5 +1,5 @@
 //
-//  Rule file generated on Tue Dec 07 01:34:16 EST 2021
+//  Rule file generated on Fri Dec 10 14:01:28 EST 2021
 //     by Calibre Interactive - DRC (v2018.4_34.26)
 //
 //      *** PLEASE DO NOT MODIFY THIS FILE ***
diff --git a/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.results b/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.results
index 1732569..1ed189b 100755
--- a/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.results
+++ b/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.results
@@ -1,690 +1,690 @@
 caravel_00020021 1000
 MR_dnwell.2
-0 0 2 Dec  7 01:34:37 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 dnwell.2: 3 min. width of dnwell
 MR_nwell.1
-0 0 2 Dec  7 01:34:37 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 nwell.1: 0.84 min. width of nwell
 MR_nwell.2a
-0 0 2 Dec  7 01:34:37 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 nwell.2a: 1.27 min. spacing/notch of nwell
 MR_hvtp.1
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvtp.1: 0.38 min. width of hvtp
 MR_hvtp.2
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvtp.2: 0.38 min. spacing/notch of hvtp
 MR_hvtr.1
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvtr.1: 0.38 min. width of hvtr
 MR_hvtr.2
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvtr.2: 0.38 min. spacing of hvtr & hvtp
 MR_hvtr.2_a
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvtr.2: hvtr must not overlap hvtp
 MR_lvtn.1a
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 lvtn.1a: 0.38 min. width of lvtn
 MR_lvtn.2
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 lvtn.2: 0.38 min. spacing/notch of lvtn
 MR_ncm.1
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ncm.1: 0.38 min. width of ncmPeri
 MR_ncm.2a
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ncm.2a: 0.38 min. spacing/notch of ncmPeri
 MR_difftap.1
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 difftap.1: 0.15 min. width of diff across areaid:ce
 MR_difftap.1_a
-0 0 2 Dec  7 01:34:38 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 difftap.1: 0.15 min. width of diff in PERI
 MR_difftap.1_b
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 difftap.1: 0.15 min. width of tap across areaid:ce
 MR_difftap.1_c
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 difftap.1: 0.15 min. width of tap in PERI
 MR_difftap.3
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 difftap.3: 0.27 min. spacing/notch of diff or tap
 MR_tunm.1
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 tunm.1: 0.41 min. width of tunm
 MR_tunm.2
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 tunm.2: 0.5 min. spacing/notch of tunm
 MR_poly.1a
-0 0 2 Dec  7 01:34:39 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 poly.1a: 0.15 min. width of poly
 MR_poly.2
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 poly.2: 0.21 min. spacing/notch of "poly" in periphery
 MR_rpm.1a
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 rpm.1a: 1.27 min. width of rpm
 MR_rpm.2
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 rpm.2: 0.84 min. spacing/notch of rpm
 MR_urpm.1a
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 urpm.1a: 1.27 min. width of urpm
 MR_urpm.2
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 urpm.2: 0.84 min. spacing/notch of urpm
 MR_npc.1
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 npc.1: 0.27 min. width of npc
 MR_npc.2
-0 0 2 Dec  7 01:34:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 npc.2: 0.27 min. spacing/notch of npc
 MR_licon.1
-0 0 2 Dec  7 01:34:41 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.1: rectLCON1 should be rectangular
 MR_licon.1_a
-0 0 2 Dec  7 01:34:41 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.1: 0.17 min. width of rectLCON1Out(Rpm OR URpm)
 MR_licon.1_b
-0 0 2 Dec  7 01:34:42 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.1: 0.17 max. length of rectLCON1
 MR_licon.13
-0 0 2 Dec  7 01:34:43 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.13: 0.09 min. spacing of "licon1 on diffTap" in periphery & npc
 MR_licon.13_a
-0 0 2 Dec  7 01:34:43 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.13: "licon1 on diffTap" in periphery must not overlap npc
 MR_licon.17
-0 0 2 Dec  7 01:34:44 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 licon.17: licon1 overlapping poly must not overlap diffTap
 MR_li.1
-0 0 2 Dec  7 01:34:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li.1: 0.17 min. width of li1
 MR_li.3
-0 0 2 Dec  7 01:34:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li.3: 0.17 min. spacing/notch of li1
 MR_li.5
-0 0 2 Dec  7 01:35:10 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li.5: 0.08 min. enclosure of adj. sides of "licon1" in periphery by li1
 MR_li.6
-0 0 2 Dec  7 01:35:13 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li.6: 0.0561 min. area of li1 
 MR_ct.1
-0 0 2 Dec  7 01:35:18 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.1: non-ring mcon should be rectangular
 MR_ct.1_a
-0 0 2 Dec  7 01:35:20 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.1: 0.17 min. width of non-ring mcon
 MR_ct.1_b
-0 0 2 Dec  7 01:35:27 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.1: 0.17 max. length of non-ring mcon
 MR_ct.2
-0 0 2 Dec  7 01:35:29 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.2: 0.19 min. spacing/notch of mcon
 MR_ct.3
-0 0 2 Dec  7 01:35:29 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.3: 0.17 min. width of ring-shaped mcon
 MR_ct.3_a
-0 0 2 Dec  7 01:35:29 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.3: 0.175 max. width of ring-shaped mcon
 MR_ct.3_b
-0 0 2 Dec  7 01:35:29 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.3: ring-shaped mcon must be enclosed by SEALID
 MR_ct.4
-0 0 2 Dec  7 01:35:30 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 ct.4: "mcon" in periphery must be enclosed by li1
 MR_capm.1
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.1: 1 min. width of capm
 MR_capm.2a
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.2a: 0.84 min. spacing/notch of capm
 MR_capm.2b
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.2b: 1.2 min spacing between bottom plates
 MR_capm.2b_a
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.2b: 1.2 min. spacing of m3_bot_plate 
 MR_capm.3
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.3: 0.14 min. enclosure of capm by met3
 MR_capm.4
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.4: 0.14 min. enclosure of via3 by capm
 MR_capm.5
-0 0 2 Dec  7 01:35:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 capm.5: 0.14 min. spacing of capm & via3
 MR_cap2m.1
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.1: 1 min. width of cap2m
 MR_cap2m.2a
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.2a: 0.84 min. spacing/notch of cap2m
 MR_cap2m.2b
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.2b: 1.2 min spacing between m4 bottom plates
 MR_cap2m.2b_a
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.2b: 1.2 min. spacing of m4_bot_plate
 MR_cap2m.3
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.3: 0.14 min. enclosure of cap2m by met4
 MR_cap2m.4
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.4: 0.20 min. enclosure of via4 by cap2m
 MR_cap2m.5
-0 0 2 Dec  7 01:35:57 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cap2m.5: 0.20 min. spacing of cap2m & via4
 MR_m1.1
-0 0 2 Dec  7 01:36:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.1: 0.14 min. width of met1
 MR_m1.2
-0 0 2 Dec  7 01:36:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.2: 0.14 min. spacing/notch of met1
 MR_m1.3b
-0 0 2 Dec  7 01:36:06 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.3b: 0.28 min. spacing between huge met1 and normal met1  
 MR_m1.3a
-0 0 2 Dec  7 01:36:06 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.3a: 0.28 min. spacing/notch of huge met1+nearby met1  
 MR_791_m1.4
-0 0 2 Dec  7 01:36:10 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.4: 0.03 min. enclosure of mcon_PERI_4 by met1
 MR_m1.4
-0 0 2 Dec  7 01:36:11 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.4: mcon_PERI_4 must be enclosed by met1
 MR_m1.4a
-0 0 2 Dec  7 01:36:11 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.4a: 0.005 min. enclosure of mcon_PERI_4a by met1
 MR_m1.4a_a
-0 0 2 Dec  7 01:36:11 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.4a: mcon_PERI_4a must be enclosed by met1
 MR_m1.5
-0 0 2 Dec  7 01:36:20 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.5: 0.06 min. enclosure of adj. sides of "mcon" in periphery by met1
 MR_m1.6
-0 0 2 Dec  7 01:36:22 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.6: 0.083 min. area of met1
 MR_m1.7
-0 0 2 Dec  7 01:36:25 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.7: 0.14 min. area of met1Hole
 MR_m1.7_a
-0 0 2 Dec  7 01:36:25 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m1.7: 0.14 min. area of met1HoleEmpty
 MR_via.1a
-0 0 2 Dec  7 01:36:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.1a: via outside of moduleCut should be rectangular
 MR_via.1a_a
-0 0 2 Dec  7 01:36:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.1a: 0.15 min. width of via outside of moduleCut
 MR_via.1a_b
-0 0 2 Dec  7 01:36:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.1a: 0.15 max. length of via outside of moduleCut
 MR_via.2
-0 0 2 Dec  7 01:36:27 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.2: 0.17 min. spacing/notch of via
 MR_via.3
-0 0 2 Dec  7 01:36:27 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.3: 0.2 min. width of ring-shaped via
 MR_via.3_a
-0 0 2 Dec  7 01:36:27 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.3: 0.205 max. width of ring-shaped via
 MR_via.3_b
-0 0 2 Dec  7 01:36:27 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.3: ring-shaped via must be enclosed by SEALID
 MR_via.4a
-0 0 2 Dec  7 01:36:31 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.4a: 0.055 min. enclosure of 0.15um via by met1
 MR_via.4a_a
-0 0 2 Dec  7 01:36:32 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.4a: 0.15um via must be enclosed by met1
 MR_via.5a
-0 0 2 Dec  7 01:36:40 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via.5a: 0.085 min. enclosure of adj. sides of 0.15um via by met1
 MR_m2.1
-0 0 2 Dec  7 01:36:42 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.1: 0.14 min. width of met2
 MR_m2.2
-0 0 2 Dec  7 01:36:42 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.2: 0.14 min. spacing/notch of met2
 MR_m2.3b
-0 0 2 Dec  7 01:36:45 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.3b: 0.28 min. spacing between huge met2 and normal met2  
 MR_m2.3a
-0 0 2 Dec  7 01:36:45 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.3a: 0.28 min. spacing/notch of huge met2+nearby met2  
 MR_m2.4
-0 0 2 Dec  7 01:36:46 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.4: 0.055 min. enclosure of "via" in periphery by met2
 MR_m2.4_a
-0 0 2 Dec  7 01:36:46 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.4: "via" in periphery must be enclosed by met2
 MR_m2.5
-0 0 2 Dec  7 01:36:52 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.5: 0.085 min. enclosure of adj. sides of via by met2
 MR_m2.6
-0 0 2 Dec  7 01:36:52 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.6: 0.0676 min. area of met2
 MR_m2.7
-0 0 2 Dec  7 01:36:54 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.7: 0.14 min. area of met2Hole
 MR_m2.7_a
-0 0 2 Dec  7 01:36:54 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m2.7: 0.14 min. area of met2HoleEmpty
 MR_via2.1a
-0 0 2 Dec  7 01:36:54 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.1a: rectVIA2noMT should be rectangular
 MR_via2.1a_a
-0 0 2 Dec  7 01:36:54 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.1a: 0.2 min. width of rectVIA2noMT
 MR_via2.1a_b
-0 0 2 Dec  7 01:36:54 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.1a: 0.2 max. length of rectVIA2noMT
 MR_via2.2
-0 0 2 Dec  7 01:36:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.2: 0.2 min. spacing/notch of via2
 MR_via2.3
-0 0 2 Dec  7 01:36:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.3: 0.2 min. width of ring-shaped via2
 MR_via2.3_a
-0 0 2 Dec  7 01:36:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.3: 0.205 max. width of ring-shaped via2
 MR_via2.3_b
-0 0 2 Dec  7 01:36:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.3: ring-shaped via2 must be enclosed by SEALID
 MR_via2.4
-0 0 2 Dec  7 01:36:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.4: 0.04 min. enclosure of via2 by met2
 MR_via2.4_a
-0 0 2 Dec  7 01:36:56 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.4: via2 must be enclosed by met2
 MR_via2.5
-0 0 2 Dec  7 01:36:58 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via2.5: 0.085 min. enclosure of adj. sides of via2 by met2
 MR_m3.1
-0 0 2 Dec  7 01:36:58 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.1: 0.3 min. width of met3
 MR_m3.2
-0 0 2 Dec  7 01:36:58 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.2: 0.3 min. spacing/notch of met3
 MR_m3.4
-0 0 2 Dec  7 01:36:59 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.4: 0.065 min. enclosure of via2 by met3
 MR_m3.4_a
-0 0 2 Dec  7 01:36:59 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.4: via2 must be enclosed by met3
 MR_m3.3d
-0 0 2 Dec  7 01:37:00 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.3d: 0.4 min. spacing between huge met3 and normal met3  
 MR_m3.3c
-0 0 2 Dec  7 01:37:00 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m3.3c: 0.4 min. spacing/notch of huge met3+nearby met3  
 MR_via3.1
-0 0 2 Dec  7 01:37:00 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.1: rectVIA3noMT should be rectangular
 MR_via3.1_a
-0 0 2 Dec  7 01:37:00 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.1: 0.2 min. width of rectVIA3noMT
 MR_via3.1_b
-0 0 2 Dec  7 01:37:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.1: 0.2 max. length of rectVIA3noMT
 MR_via3.2
-0 0 2 Dec  7 01:37:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.2: 0.2 min. spacing/notch of via3
 MR_via3.4
-0 0 2 Dec  7 01:37:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.4: 0.06 min. enclosure of non-ring via3 by met3
 MR_via3.4_a
-0 0 2 Dec  7 01:37:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.4: non-ring via3 must be enclosed by met3
 MR_via3.5
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via3.5: 0.09 min. enclosure of adj. sides of via3 by met3
 MR_m4.1
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.1: 0.3 min. width of met4
 MR_m4.2
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.2: 0.3 min. spacing/notch of met4
 MR_m4.3
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.3: 0.065 min. enclosure of via3 by met4
 MR_m4.3_a
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.3: via3 must be enclosed by met4
 MR_m4.4a
-0 0 2 Dec  7 01:37:03 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.4a: 0.24 min. area of met4
 MR_m4.5b
-0 0 2 Dec  7 01:37:04 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.5b: 0.4 min. spacing between huge met4 and normal met4  
 MR_m4.5a
-0 0 2 Dec  7 01:37:04 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m4.5a: 0.4 min. spacing/notch of huge met4+nearby met4  
 MR_via4.1
-0 0 2 Dec  7 01:37:04 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.1: non-ring via4 should be rectangular
 MR_via4.1_a
-0 0 2 Dec  7 01:37:04 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.1: 0.8 min. width of non-ring via4
 MR_via4.1_b
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.1: 0.8 max. length of non-ring via4
 MR_via4.2
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.2: 0.8 min. spacing/notch of via4
 MR_via4.3
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.3: 0.8 min. width of ring-shaped via4
 MR_via4.3_a
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.3: 0.805 max. width of ring-shaped via4
 MR_via4.3_b
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.3: ring-shaped via4 must be enclosed by SEALID
 MR_via4.4
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.4: 0.19 min. enclosure of non-ring via4 by met4
 MR_via4.4_a
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 via4.4: non-ring via4 must be enclosed by met4
 MR_m5.1
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m5.1: 1.6 min. width of met5
 MR_m5.2
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m5.2: 1.6 min. spacing/notch of met5
 MR_m5.3
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m5.3: 0.31 min. enclosure of via4 by met5
 MR_m5.3_a
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m5.3: via4 must be enclosed by met5
 MR_m5.4
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 m5.4: 4 min. area of met5
 MR_pad.2
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 pad.2: 1.27 min. spacing/notch of pad
 MR_hvi.1
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvi.1: 0.6 min. width of hvi_peri
 MR_hvi.2a
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvi.2a: 0.7 min. spacing/notch of hvi_peri
 MR_hvntm.1
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvntm.1: 0.7 min. width of hvntm_peri
 MR_hvntm.2
-0 0 2 Dec  7 01:37:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 hvntm.2: 0.7 min. spacing/notch of hvntm_peri
 MR_cfom.waffle.1
-0 0 2 Dec  7 01:37:12 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cfom.waffle.1: 0.4 min spacing of FOM_FILL to any fom
 MR_cfom.waffle.2
-0 0 2 Dec  7 01:37:13 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cfom.waffle.2: FOM_FILL may not touch fom
 MR_cfom.waffle.2a
-0 0 2 Dec  7 01:37:28 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cfom.waffle.2: FOM_FILL may not touch poly
 MR_cp1m.waffle.1
-0 0 2 Dec  7 01:38:10 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cp1m.waffle.1: 0.36 min spacing of P1M_FILL to any poly
 MR_cp1m.waffle.2a
-0 0 2 Dec  7 01:38:16 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cp1m.waffle.2: P1M_FILL may not touch fom
 MR_li1m.waffle.1
-0 0 2 Dec  7 01:38:41 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li1m.waffle.1: 0.5 min spacing of LI1M_FILL to any li1
 MR_li1m.waffle.2a
-0 0 2 Dec  7 01:38:43 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 li1m.waffle.2: LI1M_FILL may not touch fom or poly
 MR_cmm1.waffle.1
-0 0 2 Dec  7 01:40:36 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm1.waffle.1: 0.2 min spacing of MM1_FILL to any met1
 MR_cmm1.waffle.2
-0 0 2 Dec  7 01:40:48 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm1.waffle.2: MM1_FILL may not touch met1
 MR_cmm2.waffle.1
-0 0 2 Dec  7 01:42:23 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm2.waffle.1: 0.2 min spacing of MM2_FILL to any met2
 MR_cmm2.waffle.2
-0 0 2 Dec  7 01:42:33 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm2.waffle.2: MM2_FILL may not touch met2
 MR_cmm3.waffle.1
-0 0 2 Dec  7 01:43:20 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm3.waffle.1: 0.3 min spacing of MM3_FILL to any met3
 MR_cmm3.waffle.2
-0 0 2 Dec  7 01:43:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm3.waffle.2: MM3_FILL may not touch met3
 MR_cmm4.waffle.1
-0 0 2 Dec  7 01:43:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm4.waffle.1: 0.3 min spacing of MM4_FILL to any met4
 MR_cmm4.waffle.2
-0 0 2 Dec  7 01:43:58 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm4.waffle.2: MM4_FILL may not touch met4
 MR_cmm5.waffle.1
-0 0 2 Dec  7 01:44:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm5.waffle.1: 1.6 min spacing of MM5_FILL to any met5
 MR_cmm5.waffle.2
-0 0 2 Dec  7 01:44:01 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm5.waffle.2: MM5_FILL may not touch met5
 MR_cfom.pd.1d
-0 0 2 Dec  7 01:44:02 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cfom.pd.1d: cfom.pd.1d: 0.28 min FOM pattern density
 MR_cfom.pd.1e
-0 0 2 Dec  7 01:44:02 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cfom.pd.1e: cfom.pd.1e: 0.62 max FOM pattern density
 MR_cli1m.4
-0 0 2 Dec  7 01:44:33 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cli1m.4: 0.40 min. pattern density of clearArea not li1m.mk inside sealRing
 MR_cli1m.5
-0 0 2 Dec  7 01:44:33 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cli1m.5: 0.65 max. pattern density of clearArea not li1m.mk inside sealRing
 MR_cmm1.pd.3
-0 0 2 Dec  7 01:46:35 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm1.pd.3: 0.4 min. pattern density of clearArea not mm1.mk inside sealRing
 MR_cmm1.pd.4
-0 0 2 Dec  7 01:46:35 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm1.pd.4: 0.65 max. pattern density of clearArea not mm1.mk inside sealRing
 MR_cmm2.pd.3
-0 0 2 Dec  7 01:48:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm2.pd.3: 0.4 min. pattern density of clearArea not mm2.mk inside sealRing
 MR_cmm2.pd.4
-0 0 2 Dec  7 01:48:05 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm2.pd.4: 0.65 max. pattern density of clearArea not mm2.mk inside sealRing
 MR_cmm3.pd.3
-0 0 2 Dec  7 01:48:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm3.pd.3: 0.40 min. pattern density of clearArea not mm3.mk inside sealRing
 MR_cmm3.pd.4
-0 0 2 Dec  7 01:48:55 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm3.pd.4: 0.65 max. pattern density of clearArea not mm3.mk inside sealRing
 MR_cmm4.pd.3
-0 0 2 Dec  7 01:49:24 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm4.pd.3: 0.4 min. pattern density of clearArea not mm4.mk inside sealRing
 MR_cmm4.pd.4
-0 0 2 Dec  7 01:49:24 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm4.pd.4: 0.65 max. pattern density of clearArea not mm4.mk inside sealRing
 MR_cmm5.pd.4
-0 0 2 Dec  7 01:49:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm5.4: 0.24 min. pattern density of clearArea not mm5.mk inside sealRing
 MR_cmm5.pd.5
-0 0 2 Dec  7 01:49:26 2021                     
+0 0 2 ... XX XX:XX:XX 2...                     
 Rule File Pathname: /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 cmm5.5: 0.55 max. pattern density of clearArea not mm5.mk inside sealRing
 DENSITY_RDBS
-0 0 14 Dec  7 01:49:26 2021
+0 0 14 ... XX XX:XX:XX 2...
 fom_minPD.rdb 0
 fom_maxPD.rdb 0
 li1mCAmin_PD.rdb 0
diff --git a/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.summary b/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.summary
index 78d51e9..7e5a21b 100644
--- a/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.summary
+++ b/signoff/cdrcpost/caravel_00020021/drcmr/caravel_00020021.drc.summary
@@ -3,7 +3,7 @@
 ==================================================================================
 === CALIBRE::DRC-H SUMMARY REPORT
 ===
-Execution Date/Time:       Tue Dec  7 01:34:17 2021
+Execution Date/Time:       Fri ... XX XX:XX:XX 2...
 Calibre Version:           v2018.4_34.26    Mon Dec 3 14:41:18 PST 2018
 Rule File Pathname:        /usr/local/google/home/tansell/work/openflow-drc-tests/torture_tests/caravel_00020021/drcmr/_s8_drcRules_MR_
 Rule File Title:           
@@ -39,50 +39,50 @@
 ---
 LAYER COREID .......... TOTAL Original Geometry Count = 4        (17160)
 LAYER ncm ............. TOTAL Original Geometry Count = 0        (0)
-LAYER diff ............ TOTAL Original Geometry Count = 4612     (922230)
+LAYER diff ............ TOTAL Original Geometry Count = 4678     (923535)
 LAYER tap ............. TOTAL Original Geometry Count = 895      (144433)
-LAYER poly ............ TOTAL Original Geometry Count = 9422     (1209714)
-LAYER licon1 .......... TOTAL Original Geometry Count = 170970   (7107683)
-LAYER diffTap ......... TOTAL Original Geometry Count = 5507     (1066663)
+LAYER poly ............ TOTAL Original Geometry Count = 9496     (1210072)
+LAYER licon1 .......... TOTAL Original Geometry Count = 171815   (7141634)
+LAYER diffTap ......... TOTAL Original Geometry Count = 5573     (1067968)
 LAYER urpm ............ TOTAL Original Geometry Count = 4        (6)
 LAYER rpm ............. TOTAL Original Geometry Count = 0        (0)
-LAYER li1 ............. TOTAL Original Geometry Count = 242977   (2426501)
-LAYER mcon ............ TOTAL Original Geometry Count = 412989   (6484896)
-LAYER nwell ........... TOTAL Original Geometry Count = 1197     (399247)
-LAYER npc ............. TOTAL Original Geometry Count = 2683     (321116)
+LAYER li1 ............. TOTAL Original Geometry Count = 250228   (2444493)
+LAYER mcon ............ TOTAL Original Geometry Count = 420614   (6492690)
+LAYER nwell ........... TOTAL Original Geometry Count = 1211     (400878)
+LAYER npc ............. TOTAL Original Geometry Count = 2697     (319285)
 LAYER capm ............ TOTAL Original Geometry Count = 1        (1)
-LAYER via3 ............ TOTAL Original Geometry Count = 322570   (892664)
+LAYER via3 ............ TOTAL Original Geometry Count = 322833   (892879)
 LAYER cap2m ........... TOTAL Original Geometry Count = 8        (12)
-LAYER via4 ............ TOTAL Original Geometry Count = 39060    (231348)
-LAYER met3 ............ TOTAL Original Geometry Count = 137437   (178931)
-LAYER met4 ............ TOTAL Original Geometry Count = 15854    (60392)
-LAYER met1 ............ TOTAL Original Geometry Count = 1237387  (2894034)
-LAYER via ............. TOTAL Original Geometry Count = 621857   (1583350)
+LAYER via4 ............ TOTAL Original Geometry Count = 39135    (231415)
+LAYER met3 ............ TOTAL Original Geometry Count = 145134   (186612)
+LAYER met4 ............ TOTAL Original Geometry Count = 16181    (60711)
+LAYER met1 ............ TOTAL Original Geometry Count = 1278212  (2938306)
+LAYER via ............. TOTAL Original Geometry Count = 632044   (1593460)
 LAYER moduleCutAREA ... TOTAL Original Geometry Count = 0        (0)
-LAYER met2 ............ TOTAL Original Geometry Count = 582351   (1195573)
-LAYER via2 ............ TOTAL Original Geometry Count = 294301   (987185)
-LAYER met5 ............ TOTAL Original Geometry Count = 3470     (26376)
+LAYER met2 ............ TOTAL Original Geometry Count = 603464   (1216629)
+LAYER via2 ............ TOTAL Original Geometry Count = 296802   (989638)
+LAYER met5 ............ TOTAL Original Geometry Count = 3455     (26359)
 LAYER hvi ............. TOTAL Original Geometry Count = 540      (40380)
 LAYER hvntm ........... TOTAL Original Geometry Count = 24       (45)
 LAYER SEALID .......... TOTAL Original Geometry Count = 24       (24)
-LAYER FOM_FILL ........ TOTAL Original Geometry Count = 491173   (491173)
+LAYER FOM_FILL ........ TOTAL Original Geometry Count = 491629   (491629)
 LAYER FOMmk ........... TOTAL Original Geometry Count = 12       (12)
 LAYER P1Mmk ........... TOTAL Original Geometry Count = 12       (12)
-LAYER P1M_FILL ........ TOTAL Original Geometry Count = 3809890  (3809890)
-LAYER MM1_FILL ........ TOTAL Original Geometry Count = 12023192 (12023192)
+LAYER P1M_FILL ........ TOTAL Original Geometry Count = 3809899  (3809899)
+LAYER MM1_FILL ........ TOTAL Original Geometry Count = 12004526 (12004526)
 LAYER MM1mk ........... TOTAL Original Geometry Count = 12       (12)
-LAYER MM2_FILL ........ TOTAL Original Geometry Count = 9514811  (9514811)
+LAYER MM2_FILL ........ TOTAL Original Geometry Count = 9500224  (9500224)
 LAYER MM2mk ........... TOTAL Original Geometry Count = 12       (12)
-LAYER MM3_FILL ........ TOTAL Original Geometry Count = 3984100  (3984100)
+LAYER MM3_FILL ........ TOTAL Original Geometry Count = 3992940  (3992940)
 LAYER MM3mk ........... TOTAL Original Geometry Count = 12       (12)
-LAYER MM4_FILL ........ TOTAL Original Geometry Count = 3211261  (3211261)
+LAYER MM4_FILL ........ TOTAL Original Geometry Count = 3217774  (3217774)
 LAYER MM4mk ........... TOTAL Original Geometry Count = 12       (12)
-LAYER MM5_FILL ........ TOTAL Original Geometry Count = 302352   (302352)
+LAYER MM5_FILL ........ TOTAL Original Geometry Count = 299407   (299407)
 LAYER MM5mk ........... TOTAL Original Geometry Count = 12       (12)
 LAYER LI1Mmk .......... TOTAL Original Geometry Count = 12       (12)
 LAYER LI1M_FILL ....... TOTAL Original Geometry Count = 2444432  (2444432)
 LAYER dnwell .......... TOTAL Original Geometry Count = 27       (424)
-LAYER hvtp ............ TOTAL Original Geometry Count = 518      (317981)
+LAYER hvtp ............ TOTAL Original Geometry Count = 533      (318851)
 LAYER hvtr ............ TOTAL Original Geometry Count = 0        (0)
 LAYER lvtn ............ TOTAL Original Geometry Count = 38       (4460)
 LAYER tunm ............ TOTAL Original Geometry Count = 0        (0)
@@ -268,8 +268,8 @@
 ----------------------------------------------------------------------------------
 --- SUMMARY
 ---
-TOTAL CPU Time:                  904
-TOTAL REAL Time:                 909
-TOTAL Original Layer Geometries: 39888035 (64294199)
+TOTAL CPU Time:                  893
+TOTAL REAL Time:                 898
+TOTAL Original Layer Geometries: 39966598 (64423350)
 TOTAL DRC RuleChecks Executed:   171
 TOTAL DRC Results Generated:     0 (0)
diff --git a/signoff/cdrcpost/caravel_00020021/run_calibre.out b/signoff/cdrcpost/caravel_00020021/run_calibre.out
index 52536c8..ebae5c3 100644
--- a/signoff/cdrcpost/caravel_00020021/run_calibre.out
+++ b/signoff/cdrcpost/caravel_00020021/run_calibre.out
@@ -6,7 +6,7 @@
 =====================================
 + cd /usr/local/google/home/tansell/work/openflow-drc-tests/
 + git checkout HEAD /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_drcmr_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_drc_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_fill_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_latchup_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_lures_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_lvs_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_soft_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_stress_runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_xRC_runset
-Updated 0 paths from 67b447a1
+Updated 0 paths from 151410ea
 + [[ ! -d /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/ ]]
 + cd /usr/local/google/home/tansell/github/google/skywater-pdk/s8/V1.3.0
 + calibre -gui -drc -runset /usr/local/google/home/tansell/work/openflow-drc-tests//runsets-oas/s8_drcmr_runset -batch
diff --git a/signoff/klayout_drc_fom.log b/signoff/klayout_drc_fom.log
index 287da27..6c87004 100644
--- a/signoff/klayout_drc_fom.log
+++ b/signoff/klayout_drc_fom.log
@@ -1,13 +1,13 @@
-fom_density.drc:: sourcing design file=./gds/caravel_00020021.gds topcell=caravel_00020021 ...
+fom_density.drc:: sourcing design file=./oas/caravel_00020021.oas topcell=caravel_00020021 ...
 done.
 flattening chip boundary...
 done.
 step size = 70.0
-llx=5.965 lly=6.0 urx=3594.035 ury=5194.0
+llx=5.964999999999999 lly=5.999999999999999 urx=3594.0349999999994 ury=5193.999999999999
 x_cnt = 51
 y_cnt = 74
-dbu = 0.001
-bbox_area = 18614907.16
+dbu = 0.0009999999999999998
+bbox_area = 18614907.159999993
 calculating subtile areas (= 3774)...
 tiles per step = 10
 calculating window step densities (= 2730)...
diff --git a/signoff/klayout_drc_met.log b/signoff/klayout_drc_met.log
index 26d79f5..557a997 100644
--- a/signoff/klayout_drc_met.log
+++ b/signoff/klayout_drc_met.log
@@ -1,6 +1,6 @@
-li1_ca_density is 0.41448697125274425
-m1_ca_density is 0.4833115000296718
-m2_ca_density is 0.49920066775106575
-m3_ca_density is 0.5019354093683188
-m4_ca_density is 0.46719819443787947
+li1_ca_density is 0.41450053586121505
+m1_ca_density is 0.4833446104386373
+m2_ca_density is 0.49940206051230907
+m3_ca_density is 0.5019467057040085
+m4_ca_density is 0.4672035866738671
 m5_ca_density is 0.415957475199362
diff --git a/signoff/make_final b/signoff/make_final
index 6f2473b..3eab6d0 100644
--- a/signoff/make_final
+++ b/signoff/make_final
@@ -1 +1 @@
-c55937ac2b6ef1dc79c3b4cdfa7a3a0a7ffdb29b  ./gds/caravel_00020021.gds
+fa6844db538022b6dbde34054b0fc8c2437715c6  ./gds/caravel_00020021.gds
diff --git a/signoff/tapeout.log b/signoff/tapeout.log
index 038799e..77ffc75 100644
--- a/signoff/tapeout.log
+++ b/signoff/tapeout.log
@@ -1,15 +1,16 @@
-2759920    4 drwx------   2 root     root         4096 Dec 10 00:22 /root/.ssh
-2759936    4 -rw-------   1 root     root          401 Dec 10 00:22 /root/.ssh/id_rsa.pub
-2759939    4 -rw-------   1 root     root         2757 Dec 10 00:22 /root/.ssh/known_hosts
-2759927    4 -rw-------   1 root     root          401 Dec 10 00:22 /root/.ssh/authorized_keys
-2759930    4 -rw-------   1 root     root          218 Dec 10 00:22 /root/.ssh/config
-2759933    4 -rw-------   1 root     root         1679 Dec 10 00:22 /root/.ssh/id_rsa
+2760281    4 drwx------   2 root     root         4096 Dec 27 07:46 /root/.ssh
+2760305    4 -rw-------   1 root     root          401 Dec 27 07:46 /root/.ssh/id_rsa.pub
+2760306    4 -rw-------   1 root     root         2757 Dec 27 07:46 /root/.ssh/known_hosts
+2760294    4 -rw-------   1 root     root          401 Dec 27 07:46 /root/.ssh/authorized_keys
+2760297    4 -rw-------   1 root     root          218 Dec 27 07:46 /root/.ssh/config
+2760300    4 -rw-------   1 root     root         1679 Dec 27 07:46 /root/.ssh/id_rsa
 Welcome to GitLab, @jeffdi!
+Project Type = analog
 -------------------------------------------------------------------------------------------
 -------------------------------------------------------------------------------------------
 Beginning tapeout for mpw-two, slot-033 digital_pll
 
-Fri Dec 10 00:22:37 UTC 2021
+Mon Dec 27 07:46:14 UTC 2021
 -------------------------------------------------------------------------------------------
 -------------------------------------------------------------------------------------------
 Everything up-to-date
@@ -58,77 +59,77 @@
 mkdir -p ./verilog/gl
 python3 /mnt/shuttles/shuttle/mpw-two/caravel/scripts/gen_gpio_defaults.py /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll 2>&1 | tee ./signoff/build/gpio_defaults.out
 Step 1:  Create new cells for new GPIO default vectors.
-Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
-Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
-Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
+Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
 Step 2:  Modify top-level layouts to use the specified defaults.
 Done.
 make[1]: Leaving directory `/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll'
 GPIO defaults completed.
-fatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+fatal: ambiguous argument 'main': unknown revision or path not in the working tree.
 Use '--' to separate paths from revisions, like this:
 'git <command> [<revision>...] -- [<file>...]'
 All files are uncompressed!
@@ -167,6 +168,7 @@
 caravan: 30000 rects
 caravan: 40000 rects
 caravan: 50000 rects
+Processing timestamp mismatches: gpio_defaults_block_0403, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_6.
 Warning:  Parent cell lists instance of "xres_buf" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/xres_buf.mag.
 The cell exists in the search paths at ../mag/xres_buf.mag.
 The discovered version will be used.
@@ -942,8 +944,8 @@
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbn_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbn_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbn_1.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__ebufn_1" at bad file path ../mag/sky130_fd_sc_hd__ebufn_1.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__ebufn_1.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "mgmt_protect" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/mgmt_protect.mag.
 The cell exists in the search paths at ../mag/mgmt_protect.mag.
@@ -964,12 +966,11 @@
 mgmt_protect: 140000 rects
 mgmt_protect: 150000 rects
 mgmt_protect: 160000 rects
-mgmt_protect: 170000 rects
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_4" at bad file path ../mag/sky130_fd_sc_hd__einvp_4.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_4.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2b_2" at bad file path ../mag/sky130_fd_sc_hd__and2b_2.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_2.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "sky130_fd_sc_hd__einvp_8" at bad file path ../mag/sky130_fd_sc_hd__einvp_8.mag.
-The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_8.mag.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__clkinv_16" at bad file path ../mag/sky130_fd_sc_hd__clkinv_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_16.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__and2_4" at bad file path ../mag/sky130_fd_sc_hd__and2_4.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag.
@@ -977,15 +978,15 @@
 Warning:  Parent cell lists instance of "sky130_fd_sc_hvl__conb_1" at bad file path ../mag/sky130_fd_sc_hvl__conb_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__conb_1.mag.
 The discovered version will be used.
+Warning:  Parent cell lists instance of "sky130_fd_sc_hd__inv_16" at bad file path ../mag/sky130_fd_sc_hd__inv_16.mag.
+The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_16.mag.
+The discovered version will be used.
 Warning:  Parent cell lists instance of "spare_logic_block" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/spare_logic_block.mag.
 The cell exists in the search paths at ../mag/spare_logic_block.mag.
 The discovered version will be used.
 Warning:  Parent cell lists instance of "sky130_fd_sc_hd__dfbbp_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbp_1.mag.
 The cell exists in the search paths at /mnt/shuttles/shuttle/mpw-two/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbp_1.mag.
 The discovered version will be used.
-Warning:  Parent cell lists instance of "gpio_defaults_block_0403" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/gpio_defaults_block_0403.mag.
-The cell exists in the search paths at ../mag/gpio_defaults_block_0403.mag.
-The discovered version will be used.
 Warning:  Parent cell lists instance of "chip_io_alt" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/chip_io_alt.mag.
 The cell exists in the search paths at ../mag/chip_io_alt.mag.
 The discovered version will be used.
@@ -1427,7 +1428,7 @@
 Warning:  Parent cell lists instance of "caravan_power_routing" at bad file path /mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/caravan_power_routing.mag.
 The cell exists in the search paths at ../mag/caravan_power_routing.mag.
 The discovered version will be used.
-Processing timestamp mismatches: sky130_ef_io__top_power_hvc, sky130_ef_io__analog_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, chip_io_alt, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__einvp_4, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__ebufn_1, sky130_fd_sc_hd__dfbbn_1, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__ebufn_8, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_1, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8.
+Processing timestamp mismatches: sky130_ef_io__top_power_hvc, sky130_ef_io__analog_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__corner_pad, chip_io_alt, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__fill_2, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, sky130_fd_sc_hd__inv_16, sky130_fd_sc_hvl__conb_1, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__clkinv_16, sky130_fd_sc_hd__and2b_2, mgmt_protect, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__einvp_8, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__inv_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__dfbbn_1, gpio_control_block, sky130_fd_sc_hd__clkdlybuf4s25_1, sky130_fd_sc_hd__or2_1, sky130_fd_sc_hd__or2b_1, sky130_fd_sc_hd__buf_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__ebufn_8, sky130_fd_sc_hd__a22oi_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__a311o_2, sky130_fd_sc_hd__a2bb2o_2, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__o41a_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_2, digital_pll, sky130_fd_sc_hd__o311a_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__or3_2, sky130_fd_sc_hd__or4_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__o221ai_2, sky130_fd_sc_hd__o22ai_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__a21bo_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__o2bb2ai_2, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or3b_4, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__or4b_4, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__nand4_4, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__o211ai_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__o221ai_4, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__o2111ai_4, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__o211ai_1, sky130_fd_sc_hd__o22a_4, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__o221ai_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a311oi_1, sky130_fd_sc_hd__a41o_2, sky130_fd_sc_hd__o22ai_4, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__mux2_4, sky130_fd_sc_hd__a22oi_1, sky130_fd_sc_hd__or3b_2, sky130_fd_sc_hd__ebufn_2, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__or4b_2, sky130_fd_sc_hd__or4_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__clkinvlp_2, sky130_fd_sc_hd__or2b_2, sky130_fd_sc_hd__o31ai_4, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__o22ai_1, sky130_fd_sc_hd__or4bb_4, sky130_fd_sc_hd__or2_4, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__or3b_1, sky130_fd_sc_hd__a22oi_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__or3_4, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__or3_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__or4_1, sky130_fd_sc_hd__or4b_1, sky130_fd_sc_hd__or4bb_1, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__dlygate4sd1_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__xor2_1, caravel_clocking, alpha_1, alpha_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_8.
    Generating output for cell sky130_fd_sc_hvl__decap_8
    Generating output for cell sky130_fd_sc_hvl__diode_2
    Generating output for cell sky130_fd_sc_hvl__decap_4
@@ -1507,35 +1508,35 @@
    Generating output for cell sky130_fd_sc_hd__o2bb2ai_2
    Generating output for cell sky130_fd_sc_hd__dfrtp_2
    Generating output for cell sky130_fd_sc_hd__mux2_1
-   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
-   Generating output for cell sky130_fd_sc_hd__buf_1
    Generating output for cell sky130_fd_sc_hd__dfrtp_1
+   Generating output for cell sky130_fd_sc_hd__buf_1
    Generating output for cell sky130_fd_sc_hd__or2b_1
+   Generating output for cell sky130_fd_sc_hd__clkdlybuf4s25_1
    Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
    Generating output for cell sky130_fd_sc_hd__inv_4
+   Generating output for cell sky130_fd_sc_hd__clkbuf_16
+   Generating output for cell sky130_fd_sc_hd__buf_12
+   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__clkbuf_2
    Generating output for cell sky130_fd_sc_hd__clkinv_2
    Generating output for cell sky130_fd_sc_hd__clkinv_4
-   Generating output for cell sky130_fd_sc_hd__buf_12
-   Generating output for cell sky130_fd_sc_hd__clkbuf_16
-   Generating output for cell sky130_fd_sc_hd__clkbuf_2
-   Generating output for cell sky130_fd_sc_hd__nand2_1
    Generating output for cell sky130_fd_sc_hd__and2_1
-   Generating output for cell sky130_fd_sc_hd__clkbuf_1
-   Generating output for cell sky130_fd_sc_hd__buf_2
+   Generating output for cell sky130_fd_sc_hd__nand2_1
    Generating output for cell sky130_fd_sc_hd__diode_2
    Generating output for cell sky130_fd_sc_hd__clkbuf_4
+   Generating output for cell sky130_fd_sc_hd__clkbuf_1
    Generating output for cell sky130_fd_sc_hd__mux2_2
    Generating output for cell sky130_fd_sc_hd__decap_8
-   Generating output for cell sky130_fd_sc_hd__nand2_2
-   Generating output for cell sky130_fd_sc_hd__inv_2
-   Generating output for cell sky130_fd_sc_hd__decap_6
-   Generating output for cell sky130_fd_sc_hd__conb_1
    Generating output for cell sky130_fd_sc_hd__fill_2
-   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__nand2_2
+   Generating output for cell sky130_fd_sc_hd__conb_1
    Generating output for cell sky130_fd_sc_hd__fill_1
+   Generating output for cell sky130_fd_sc_hd__decap_12
+   Generating output for cell sky130_fd_sc_hd__decap_4
    Generating output for cell sky130_fd_sc_hd__decap_3
    Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
-   Generating output for cell sky130_fd_sc_hd__decap_4
+   Generating output for cell sky130_fd_sc_hd__decap_6
+   Generating output for cell sky130_fd_sc_hd__inv_2
    Generating output for cell caravel_clocking
    Generating output for cell sky130_fd_sc_hd__o2111ai_2
    Generating output for cell sky130_fd_sc_hd__and4_2
@@ -1557,6 +1558,7 @@
    Generating output for cell sky130_fd_sc_hd__or3_2
    Generating output for cell sky130_fd_sc_hd__or2_2
    Generating output for cell sky130_fd_sc_hd__o311a_2
+   Generating output for cell sky130_fd_sc_hd__einvp_2
    Generating output for cell sky130_fd_sc_hd__clkinv_1
    Generating output for cell sky130_fd_sc_hd__einvn_8
    Generating output for cell sky130_fd_sc_hd__einvn_4
@@ -1570,11 +1572,16 @@
    Generating output for cell sky130_fd_sc_hd__a311o_2
    Generating output for cell sky130_fd_sc_hd__a21oi_2
    Generating output for cell sky130_fd_sc_hd__a22oi_2
-   Generating output for cell sky130_fd_sc_hd__einvp_2
    Generating output for cell sky130_fd_sc_hd__clkinv_8
    Generating output for cell sky130_fd_sc_hd__nor2_2
    Generating output for cell digital_pll
    Generating output for cell sky130_fd_sc_hd__ebufn_8
+   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__dfbbn_1
+   Generating output for cell sky130_fd_sc_hd__buf_6
+   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell gpio_logic_high
+   Generating output for cell gpio_control_block
    Generating output for cell sky130_fd_sc_hd__a221o_1
    Generating output for cell sky130_fd_sc_hd__or4bb_1
    Generating output for cell sky130_fd_sc_hd__or4b_1
@@ -1612,7 +1619,6 @@
    Generating output for cell sky130_fd_sc_hd__a32o_1
    Generating output for cell sky130_fd_sc_hd__ebufn_2
    Generating output for cell sky130_fd_sc_hd__or3b_2
-   Generating output for cell sky130_fd_sc_hd__clkbuf_8
    Generating output for cell sky130_fd_sc_hd__a22oi_1
    Generating output for cell sky130_fd_sc_hd__mux2_4
    Generating output for cell sky130_fd_sc_hd__a41o_1
@@ -1651,15 +1657,14 @@
    Generating output for cell sky130_fd_sc_hd__o21ai_4
    Generating output for cell sky130_fd_sc_hd__nor2_8
    Generating output for cell sky130_fd_sc_hd__a31oi_1
-   Generating output for cell sky130_fd_sc_hd__or2_1
+   Generating output for cell sky130_fd_sc_hd__clkbuf_8
    Generating output for cell sky130_fd_sc_hd__inv_12
    Generating output for cell sky130_fd_sc_hd__and2b_1
    Generating output for cell sky130_fd_sc_hd__buf_8
-   Generating output for cell sky130_fd_sc_hd__buf_6
    Generating output for cell sky130_fd_sc_hd__nand2_8
    Generating output for cell sky130_fd_sc_hd__nand2_4
-   Generating output for cell sky130_fd_sc_hd__inv_6
    Generating output for cell sky130_fd_sc_hd__buf_4
+   Generating output for cell sky130_fd_sc_hd__inv_6
    Generating output for cell sky130_fd_sc_hd__inv_8
    Generating output for cell housekeeping
    Generating output for cell user_id_programming
@@ -1674,10 +1679,6 @@
 Reading "sky130_fd_sc_hd__decap_12".
 Reading "user_id_programming".
    Generating output for cell gpio_defaults_block_1803
-   Generating output for cell sky130_fd_sc_hd__dfbbn_1
-   Generating output for cell sky130_fd_sc_hd__ebufn_1
-   Generating output for cell gpio_logic_high
-   Generating output for cell gpio_control_block
    Generating output for cell simple_por
 Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
@@ -2077,10 +2078,10 @@
 Reading "sky130_fd_sc_hd__o211a_4".
 Reading "mgmt_core".
 Reading "mgmt_core_wrapper".
-   Generating output for cell gpio_defaults_block_1800
-   Generating output for cell sky130_fd_sc_hd__einvp_4
-   Generating output for cell sky130_fd_sc_hd__einvp_8
+   Generating output for cell sky130_fd_sc_hd__and2b_2
+   Generating output for cell sky130_fd_sc_hd__clkinv_16
    Generating output for cell sky130_fd_sc_hd__and2_4
+   Generating output for cell sky130_fd_sc_hd__inv_16
    Generating output for cell sky130_fd_sc_hvl__conb_1
    Generating output for cell mgmt_protect_hv
    Generating output for cell mprj_logic_high
@@ -2920,7 +2921,7 @@
 -------------------------------------------------------------------------------------------
 {{ STEP 2 }} make truck completed for mpw-two, slot-033 : digital_pll
 -------------------------------------------------------------------------------------------
-okfatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+okfatal: ambiguous argument 'main': unknown revision or path not in the working tree.
 Use '--' to separate paths from revisions, like this:
 'git <command> [<revision>...] -- [<file>...]'
 USER_ID is set to 00020021
@@ -2947,7 +2948,7 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill.tcl" from command line.
-Started: 12/10/2021 00:25:00
+Started: 12/27/2021 07:49:21
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 3.0
 Library name: caravan
@@ -3030,35 +3031,35 @@
 Reading "sky130_fd_sc_hd__o2bb2ai_2".
 Reading "sky130_fd_sc_hd__dfrtp_2".
 Reading "sky130_fd_sc_hd__mux2_1".
-Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
-Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
 Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
 Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
 Reading "sky130_fd_sc_hd__clkinv_2".
 Reading "sky130_fd_sc_hd__clkinv_4".
-Reading "sky130_fd_sc_hd__buf_12".
-Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__clkbuf_2".
-Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__and2_1".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__diode_2".
 Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
 Reading "sky130_fd_sc_hd__mux2_2".
 Reading "sky130_fd_sc_hd__decap_8".
-Reading "sky130_fd_sc_hd__nand2_2".
-Reading "sky130_fd_sc_hd__inv_2".
-Reading "sky130_fd_sc_hd__decap_6".
-Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
 Reading "sky130_fd_sc_hd__decap_3".
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__inv_2".
 Reading "caravel_clocking".
 Reading "sky130_fd_sc_hd__o2111ai_2".
 Reading "sky130_fd_sc_hd__and4_2".
@@ -3080,6 +3081,7 @@
 Reading "sky130_fd_sc_hd__or3_2".
 Reading "sky130_fd_sc_hd__or2_2".
 Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_1".
 Reading "sky130_fd_sc_hd__einvn_8".
 Reading "sky130_fd_sc_hd__einvn_4".
@@ -3093,11 +3095,16 @@
 Reading "sky130_fd_sc_hd__a311o_2".
 Reading "sky130_fd_sc_hd__a21oi_2".
 Reading "sky130_fd_sc_hd__a22oi_2".
-Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_8".
 Reading "sky130_fd_sc_hd__nor2_2".
 Reading "digital_pll".
 Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
 Reading "sky130_fd_sc_hd__a221o_1".
 Reading "sky130_fd_sc_hd__or4bb_1".
 Reading "sky130_fd_sc_hd__or4b_1".
@@ -3135,7 +3142,6 @@
 Reading "sky130_fd_sc_hd__a32o_1".
 Reading "sky130_fd_sc_hd__ebufn_2".
 Reading "sky130_fd_sc_hd__or3b_2".
-Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__a22oi_1".
 Reading "sky130_fd_sc_hd__mux2_4".
 Reading "sky130_fd_sc_hd__a41o_1".
@@ -3174,15 +3180,14 @@
 Reading "sky130_fd_sc_hd__o21ai_4".
 Reading "sky130_fd_sc_hd__nor2_8".
 Reading "sky130_fd_sc_hd__a31oi_1".
-Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__inv_12".
 Reading "sky130_fd_sc_hd__and2b_1".
 Reading "sky130_fd_sc_hd__buf_8".
-Reading "sky130_fd_sc_hd__buf_6".
 Reading "sky130_fd_sc_hd__nand2_8".
 Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__inv_8".
 Reading "housekeeping".
     5000 uses
@@ -3199,10 +3204,6 @@
 Reading "R2_sky130_fd_sc_hd__decap_12".
 Reading "user_id_programming".
 Reading "gpio_defaults_block_1803".
-Reading "sky130_fd_sc_hd__dfbbn_1".
-Reading "sky130_fd_sc_hd__ebufn_1".
-Reading "gpio_logic_high".
-Reading "gpio_control_block".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
 Reading "DN_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
@@ -3643,10 +3644,10 @@
     140000 uses
     145000 uses
 Reading "mgmt_core_wrapper".
-Reading "gpio_defaults_block_1800".
-Reading "sky130_fd_sc_hd__einvp_4".
-Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__clkinv_16".
 Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__inv_16".
 Reading "sky130_fd_sc_hvl__conb_1".
 Reading "mgmt_protect_hv".
 Reading "mprj_logic_high".
@@ -3655,7 +3656,6 @@
     5000 uses
     10000 uses
     15000 uses
-    20000 uses
 Reading "sky130_fd_sc_hd__dfbbp_1".
 Reading "spare_logic_block".
 Reading "gpio_defaults_block_0403".
@@ -4542,42 +4542,42 @@
 Error message output from magic:
 CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
 CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223975090): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223975122): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977714): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977746): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977778): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977810): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977842): NODE elements not supported: skipping.
-Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223977938): NODE elements not supported: skipping.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_LDO" (byte position 278502304): Warning:  Cell UP_LDO boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Error_amplifier" (byte position 293948382): Warning:  Cell UP_Error_amplifier boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
-Error while reading cell "UP_Bandgap1v8" (byte position 295280928): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223371174): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223371206): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373798): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373830): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373862): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373894): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223373926): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 223374022): NODE elements not supported: skipping.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_LDO" (byte position 277898388): Warning:  Cell UP_LDO boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Error_amplifier" (byte position 293344466): Warning:  Cell UP_Error_amplifier boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
+Error while reading cell "UP_Bandgap1v8" (byte position 294677012): Warning:  Cell UP_Bandgap1v8 boundary was redefined.
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -6112,343 +6112,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_1_1: 10000 rects
-caravel_00020021_fill_pattern_1_1: 20000 rects
-caravel_00020021_fill_pattern_1_1: 30000 rects
-caravel_00020021_fill_pattern_1_1: 40000 rects
-caravel_00020021_fill_pattern_1_1: 50000 rects
-caravel_00020021_fill_pattern_1_1: 60000 rects
-caravel_00020021_fill_pattern_1_1: 70000 rects
-caravel_00020021_fill_pattern_1_1: 80000 rects
-caravel_00020021_fill_pattern_1_1: 90000 rects
-caravel_00020021_fill_pattern_1_1: 100000 rects
-caravel_00020021_fill_pattern_1_1: 110000 rects
-caravel_00020021_fill_pattern_1_1: 120000 rects
-caravel_00020021_fill_pattern_1_1: 130000 rects
-caravel_00020021_fill_pattern_1_1: 140000 rects
-caravel_00020021_fill_pattern_1_1: 150000 rects
-caravel_00020021_fill_pattern_1_1: 160000 rects
-caravel_00020021_fill_pattern_1_1: 170000 rects
-caravel_00020021_fill_pattern_1_1: 180000 rects
-caravel_00020021_fill_pattern_1_1: 190000 rects
-caravel_00020021_fill_pattern_1_1: 200000 rects
-caravel_00020021_fill_pattern_1_1: 210000 rects
-caravel_00020021_fill_pattern_1_1: 220000 rects
-caravel_00020021_fill_pattern_1_1: 230000 rects
-caravel_00020021_fill_pattern_1_1: 240000 rects
-caravel_00020021_fill_pattern_1_1: 250000 rects
-caravel_00020021_fill_pattern_1_1: 260000 rects
-caravel_00020021_fill_pattern_1_1: 270000 rects
-caravel_00020021_fill_pattern_1_1: 280000 rects
-caravel_00020021_fill_pattern_1_1: 290000 rects
-caravel_00020021_fill_pattern_1_1: 300000 rects
-caravel_00020021_fill_pattern_1_1: 310000 rects
-caravel_00020021_fill_pattern_1_1: 320000 rects
-caravel_00020021_fill_pattern_1_1: 330000 rects
-caravel_00020021_fill_pattern_1_1: 340000 rects
-caravel_00020021_fill_pattern_1_1: 350000 rects
-caravel_00020021_fill_pattern_1_1: 360000 rects
-caravel_00020021_fill_pattern_1_1: 370000 rects
-caravel_00020021_fill_pattern_1_1: 380000 rects
-caravel_00020021_fill_pattern_1_1: 390000 rects
-caravel_00020021_fill_pattern_1_1: 400000 rects
-caravel_00020021_fill_pattern_1_1: 410000 rects
-caravel_00020021_fill_pattern_1_1: 420000 rects
-caravel_00020021_fill_pattern_1_1: 430000 rects
-caravel_00020021_fill_pattern_1_1: 440000 rects
-caravel_00020021_fill_pattern_1_1: 450000 rects
-caravel_00020021_fill_pattern_1_1: 460000 rects
-caravel_00020021_fill_pattern_1_1: 470000 rects
-caravel_00020021_fill_pattern_1_1: 480000 rects
-caravel_00020021_fill_pattern_1_1: 490000 rects
-caravel_00020021_fill_pattern_1_1: 500000 rects
-caravel_00020021_fill_pattern_1_1: 510000 rects
-caravel_00020021_fill_pattern_1_1: 520000 rects
-caravel_00020021_fill_pattern_1_1: 530000 rects
-caravel_00020021_fill_pattern_1_1: 540000 rects
-caravel_00020021_fill_pattern_1_1: 550000 rects
-caravel_00020021_fill_pattern_1_1: 560000 rects
-caravel_00020021_fill_pattern_1_1: 570000 rects
-caravel_00020021_fill_pattern_1_1: 580000 rects
-caravel_00020021_fill_pattern_1_1: 590000 rects
-caravel_00020021_fill_pattern_1_1: 600000 rects
-caravel_00020021_fill_pattern_1_1: 610000 rects
-caravel_00020021_fill_pattern_1_1: 620000 rects
-caravel_00020021_fill_pattern_1_1: 630000 rects
-caravel_00020021_fill_pattern_1_1: 640000 rects
-caravel_00020021_fill_pattern_1_1: 650000 rects
-caravel_00020021_fill_pattern_1_1: 660000 rects
-caravel_00020021_fill_pattern_1_1: 670000 rects
-caravel_00020021_fill_pattern_1_1: 680000 rects
-caravel_00020021_fill_pattern_1_1: 690000 rects
-caravel_00020021_fill_pattern_1_1: 700000 rects
-caravel_00020021_fill_pattern_1_1: 710000 rects
-caravel_00020021_fill_pattern_1_1: 720000 rects
-caravel_00020021_fill_pattern_1_1: 730000 rects
-caravel_00020021_fill_pattern_1_1: 740000 rects
-caravel_00020021_fill_pattern_1_1: 750000 rects
-caravel_00020021_fill_pattern_1_1: 760000 rects
-caravel_00020021_fill_pattern_1_1: 770000 rects
-caravel_00020021_fill_pattern_1_1: 780000 rects
-caravel_00020021_fill_pattern_1_1: 790000 rects
-caravel_00020021_fill_pattern_1_1: 800000 rects
-caravel_00020021_fill_pattern_1_1: 810000 rects
-caravel_00020021_fill_pattern_1_1: 820000 rects
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-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
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 caravel_00020021_fill_pattern_0_0: 20000 rects
 caravel_00020021_fill_pattern_0_0: 30000 rects
@@ -6954,6 +6617,343 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
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+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_3_1: 10000 rects
 caravel_00020021_fill_pattern_3_1: 20000 rects
 caravel_00020021_fill_pattern_3_1: 30000 rects
@@ -9410,7 +9410,7 @@
    Generating output for cell caravel_00020021_fill_pattern_5_7
 Reading "caravel_00020021_fill_pattern_5_7".
    Generating output for cell caravel_00020021_fill_pattern
-Ended: 12/10/2021 00:42:18
+Ended: 12/27/2021 08:16:37
 Done!
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
@@ -9710,226 +9710,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_5_1: 10000 rects
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-caravel_00020021_fill_pattern_5_1: 920000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_5_1
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_5_2: 10000 rects
-caravel_00020021_fill_pattern_5_2: 20000 rects
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-caravel_00020021_fill_pattern_5_2: 90000 rects
-caravel_00020021_fill_pattern_5_2: 100000 rects
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-caravel_00020021_fill_pattern_5_2: 270000 rects
-caravel_00020021_fill_pattern_5_2: 280000 rects
-caravel_00020021_fill_pattern_5_2: 290000 rects
-caravel_00020021_fill_pattern_5_2: 300000 rects
-caravel_00020021_fill_pattern_5_2: 310000 rects
-caravel_00020021_fill_pattern_5_2: 320000 rects
-caravel_00020021_fill_pattern_5_2: 330000 rects
-caravel_00020021_fill_pattern_5_2: 340000 rects
-caravel_00020021_fill_pattern_5_2: 350000 rects
-caravel_00020021_fill_pattern_5_2: 360000 rects
-caravel_00020021_fill_pattern_5_2: 370000 rects
-caravel_00020021_fill_pattern_5_2: 380000 rects
-caravel_00020021_fill_pattern_5_2: 390000 rects
-caravel_00020021_fill_pattern_5_2: 400000 rects
-caravel_00020021_fill_pattern_5_2: 410000 rects
-caravel_00020021_fill_pattern_5_2: 420000 rects
-caravel_00020021_fill_pattern_5_2: 430000 rects
-caravel_00020021_fill_pattern_5_2: 440000 rects
-caravel_00020021_fill_pattern_5_2: 450000 rects
-caravel_00020021_fill_pattern_5_2: 460000 rects
-caravel_00020021_fill_pattern_5_2: 470000 rects
-caravel_00020021_fill_pattern_5_2: 480000 rects
-caravel_00020021_fill_pattern_5_2: 490000 rects
-caravel_00020021_fill_pattern_5_2: 500000 rects
-caravel_00020021_fill_pattern_5_2: 510000 rects
-caravel_00020021_fill_pattern_5_2: 520000 rects
-caravel_00020021_fill_pattern_5_2: 530000 rects
-caravel_00020021_fill_pattern_5_2: 540000 rects
-caravel_00020021_fill_pattern_5_2: 550000 rects
-caravel_00020021_fill_pattern_5_2: 560000 rects
-caravel_00020021_fill_pattern_5_2: 570000 rects
-caravel_00020021_fill_pattern_5_2: 580000 rects
-caravel_00020021_fill_pattern_5_2: 590000 rects
-caravel_00020021_fill_pattern_5_2: 600000 rects
-caravel_00020021_fill_pattern_5_2: 610000 rects
-caravel_00020021_fill_pattern_5_2: 620000 rects
-caravel_00020021_fill_pattern_5_2: 630000 rects
-caravel_00020021_fill_pattern_5_2: 640000 rects
-caravel_00020021_fill_pattern_5_2: 650000 rects
-caravel_00020021_fill_pattern_5_2: 660000 rects
-caravel_00020021_fill_pattern_5_2: 670000 rects
-caravel_00020021_fill_pattern_5_2: 680000 rects
-caravel_00020021_fill_pattern_5_2: 690000 rects
-caravel_00020021_fill_pattern_5_2: 700000 rects
-caravel_00020021_fill_pattern_5_2: 710000 rects
-caravel_00020021_fill_pattern_5_2: 720000 rects
-caravel_00020021_fill_pattern_5_2: 730000 rects
-caravel_00020021_fill_pattern_5_2: 740000 rects
-caravel_00020021_fill_pattern_5_2: 750000 rects
-caravel_00020021_fill_pattern_5_2: 760000 rects
-caravel_00020021_fill_pattern_5_2: 770000 rects
-caravel_00020021_fill_pattern_5_2: 780000 rects
-caravel_00020021_fill_pattern_5_2: 790000 rects
-caravel_00020021_fill_pattern_5_2: 800000 rects
-caravel_00020021_fill_pattern_5_2: 810000 rects
-caravel_00020021_fill_pattern_5_2: 820000 rects
-caravel_00020021_fill_pattern_5_2: 830000 rects
-caravel_00020021_fill_pattern_5_2: 840000 rects
-caravel_00020021_fill_pattern_5_2: 850000 rects
-caravel_00020021_fill_pattern_5_2: 860000 rects
-caravel_00020021_fill_pattern_5_2: 870000 rects
-caravel_00020021_fill_pattern_5_2: 880000 rects
-caravel_00020021_fill_pattern_5_2: 890000 rects
-caravel_00020021_fill_pattern_5_2: 900000 rects
-caravel_00020021_fill_pattern_5_2: 910000 rects
-caravel_00020021_fill_pattern_5_2: 920000 rects
-caravel_00020021_fill_pattern_5_2: 930000 rects
-caravel_00020021_fill_pattern_5_2: 940000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_5_2
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_5_4: 10000 rects
 caravel_00020021_fill_pattern_5_4: 20000 rects
 caravel_00020021_fill_pattern_5_4: 30000 rects
@@ -10046,6 +9826,227 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_5_2: 10000 rects
+caravel_00020021_fill_pattern_5_2: 20000 rects
+caravel_00020021_fill_pattern_5_2: 30000 rects
+caravel_00020021_fill_pattern_5_2: 40000 rects
+caravel_00020021_fill_pattern_5_2: 50000 rects
+caravel_00020021_fill_pattern_5_2: 60000 rects
+caravel_00020021_fill_pattern_5_2: 70000 rects
+caravel_00020021_fill_pattern_5_2: 80000 rects
+caravel_00020021_fill_pattern_5_2: 90000 rects
+caravel_00020021_fill_pattern_5_2: 100000 rects
+caravel_00020021_fill_pattern_5_2: 110000 rects
+caravel_00020021_fill_pattern_5_2: 120000 rects
+caravel_00020021_fill_pattern_5_2: 130000 rects
+caravel_00020021_fill_pattern_5_2: 140000 rects
+caravel_00020021_fill_pattern_5_2: 150000 rects
+caravel_00020021_fill_pattern_5_2: 160000 rects
+caravel_00020021_fill_pattern_5_2: 170000 rects
+caravel_00020021_fill_pattern_5_2: 180000 rects
+caravel_00020021_fill_pattern_5_2: 190000 rects
+caravel_00020021_fill_pattern_5_2: 200000 rects
+caravel_00020021_fill_pattern_5_2: 210000 rects
+caravel_00020021_fill_pattern_5_2: 220000 rects
+caravel_00020021_fill_pattern_5_2: 230000 rects
+caravel_00020021_fill_pattern_5_2: 240000 rects
+caravel_00020021_fill_pattern_5_2: 250000 rects
+caravel_00020021_fill_pattern_5_2: 260000 rects
+caravel_00020021_fill_pattern_5_2: 270000 rects
+caravel_00020021_fill_pattern_5_2: 280000 rects
+caravel_00020021_fill_pattern_5_2: 290000 rects
+caravel_00020021_fill_pattern_5_2: 300000 rects
+caravel_00020021_fill_pattern_5_2: 310000 rects
+caravel_00020021_fill_pattern_5_2: 320000 rects
+caravel_00020021_fill_pattern_5_2: 330000 rects
+caravel_00020021_fill_pattern_5_2: 340000 rects
+caravel_00020021_fill_pattern_5_2: 350000 rects
+caravel_00020021_fill_pattern_5_2: 360000 rects
+caravel_00020021_fill_pattern_5_2: 370000 rects
+caravel_00020021_fill_pattern_5_2: 380000 rects
+caravel_00020021_fill_pattern_5_2: 390000 rects
+caravel_00020021_fill_pattern_5_2: 400000 rects
+caravel_00020021_fill_pattern_5_2: 410000 rects
+caravel_00020021_fill_pattern_5_2: 420000 rects
+caravel_00020021_fill_pattern_5_2: 430000 rects
+caravel_00020021_fill_pattern_5_2: 440000 rects
+caravel_00020021_fill_pattern_5_2: 450000 rects
+caravel_00020021_fill_pattern_5_2: 460000 rects
+caravel_00020021_fill_pattern_5_2: 470000 rects
+caravel_00020021_fill_pattern_5_2: 480000 rects
+caravel_00020021_fill_pattern_5_2: 490000 rects
+caravel_00020021_fill_pattern_5_2: 500000 rects
+caravel_00020021_fill_pattern_5_2: 510000 rects
+caravel_00020021_fill_pattern_5_2: 520000 rects
+caravel_00020021_fill_pattern_5_2: 530000 rects
+caravel_00020021_fill_pattern_5_2: 540000 rects
+caravel_00020021_fill_pattern_5_2: 550000 rects
+caravel_00020021_fill_pattern_5_2: 560000 rects
+caravel_00020021_fill_pattern_5_2: 570000 rects
+caravel_00020021_fill_pattern_5_2: 580000 rects
+caravel_00020021_fill_pattern_5_2: 590000 rects
+caravel_00020021_fill_pattern_5_2: 600000 rects
+caravel_00020021_fill_pattern_5_2: 610000 rects
+caravel_00020021_fill_pattern_5_2: 620000 rects
+caravel_00020021_fill_pattern_5_2: 630000 rects
+caravel_00020021_fill_pattern_5_2: 640000 rects
+caravel_00020021_fill_pattern_5_2: 650000 rects
+caravel_00020021_fill_pattern_5_2: 660000 rects
+caravel_00020021_fill_pattern_5_2: 670000 rects
+caravel_00020021_fill_pattern_5_2: 680000 rects
+caravel_00020021_fill_pattern_5_2: 690000 rects
+caravel_00020021_fill_pattern_5_2: 700000 rects
+caravel_00020021_fill_pattern_5_2: 710000 rects
+caravel_00020021_fill_pattern_5_2: 720000 rects
+caravel_00020021_fill_pattern_5_2: 730000 rects
+caravel_00020021_fill_pattern_5_2: 740000 rects
+caravel_00020021_fill_pattern_5_2: 750000 rects
+caravel_00020021_fill_pattern_5_2: 760000 rects
+caravel_00020021_fill_pattern_5_2: 770000 rects
+caravel_00020021_fill_pattern_5_2: 780000 rects
+caravel_00020021_fill_pattern_5_2: 790000 rects
+caravel_00020021_fill_pattern_5_2: 800000 rects
+caravel_00020021_fill_pattern_5_2: 810000 rects
+caravel_00020021_fill_pattern_5_2: 820000 rects
+caravel_00020021_fill_pattern_5_2: 830000 rects
+caravel_00020021_fill_pattern_5_2: 840000 rects
+caravel_00020021_fill_pattern_5_2: 850000 rects
+caravel_00020021_fill_pattern_5_2: 860000 rects
+caravel_00020021_fill_pattern_5_2: 870000 rects
+caravel_00020021_fill_pattern_5_2: 880000 rects
+caravel_00020021_fill_pattern_5_2: 890000 rects
+caravel_00020021_fill_pattern_5_2: 900000 rects
+caravel_00020021_fill_pattern_5_2: 910000 rects
+caravel_00020021_fill_pattern_5_2: 920000 rects
+caravel_00020021_fill_pattern_5_2: 930000 rects
+caravel_00020021_fill_pattern_5_2: 940000 rects
+caravel_00020021_fill_pattern_5_2: 950000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_5_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_5_1: 10000 rects
+caravel_00020021_fill_pattern_5_1: 20000 rects
+caravel_00020021_fill_pattern_5_1: 30000 rects
+caravel_00020021_fill_pattern_5_1: 40000 rects
+caravel_00020021_fill_pattern_5_1: 50000 rects
+caravel_00020021_fill_pattern_5_1: 60000 rects
+caravel_00020021_fill_pattern_5_1: 70000 rects
+caravel_00020021_fill_pattern_5_1: 80000 rects
+caravel_00020021_fill_pattern_5_1: 90000 rects
+caravel_00020021_fill_pattern_5_1: 100000 rects
+caravel_00020021_fill_pattern_5_1: 110000 rects
+caravel_00020021_fill_pattern_5_1: 120000 rects
+caravel_00020021_fill_pattern_5_1: 130000 rects
+caravel_00020021_fill_pattern_5_1: 140000 rects
+caravel_00020021_fill_pattern_5_1: 150000 rects
+caravel_00020021_fill_pattern_5_1: 160000 rects
+caravel_00020021_fill_pattern_5_1: 170000 rects
+caravel_00020021_fill_pattern_5_1: 180000 rects
+caravel_00020021_fill_pattern_5_1: 190000 rects
+caravel_00020021_fill_pattern_5_1: 200000 rects
+caravel_00020021_fill_pattern_5_1: 210000 rects
+caravel_00020021_fill_pattern_5_1: 220000 rects
+caravel_00020021_fill_pattern_5_1: 230000 rects
+caravel_00020021_fill_pattern_5_1: 240000 rects
+caravel_00020021_fill_pattern_5_1: 250000 rects
+caravel_00020021_fill_pattern_5_1: 260000 rects
+caravel_00020021_fill_pattern_5_1: 270000 rects
+caravel_00020021_fill_pattern_5_1: 280000 rects
+caravel_00020021_fill_pattern_5_1: 290000 rects
+caravel_00020021_fill_pattern_5_1: 300000 rects
+caravel_00020021_fill_pattern_5_1: 310000 rects
+caravel_00020021_fill_pattern_5_1: 320000 rects
+caravel_00020021_fill_pattern_5_1: 330000 rects
+caravel_00020021_fill_pattern_5_1: 340000 rects
+caravel_00020021_fill_pattern_5_1: 350000 rects
+caravel_00020021_fill_pattern_5_1: 360000 rects
+caravel_00020021_fill_pattern_5_1: 370000 rects
+caravel_00020021_fill_pattern_5_1: 380000 rects
+caravel_00020021_fill_pattern_5_1: 390000 rects
+caravel_00020021_fill_pattern_5_1: 400000 rects
+caravel_00020021_fill_pattern_5_1: 410000 rects
+caravel_00020021_fill_pattern_5_1: 420000 rects
+caravel_00020021_fill_pattern_5_1: 430000 rects
+caravel_00020021_fill_pattern_5_1: 440000 rects
+caravel_00020021_fill_pattern_5_1: 450000 rects
+caravel_00020021_fill_pattern_5_1: 460000 rects
+caravel_00020021_fill_pattern_5_1: 470000 rects
+caravel_00020021_fill_pattern_5_1: 480000 rects
+caravel_00020021_fill_pattern_5_1: 490000 rects
+caravel_00020021_fill_pattern_5_1: 500000 rects
+caravel_00020021_fill_pattern_5_1: 510000 rects
+caravel_00020021_fill_pattern_5_1: 520000 rects
+caravel_00020021_fill_pattern_5_1: 530000 rects
+caravel_00020021_fill_pattern_5_1: 540000 rects
+caravel_00020021_fill_pattern_5_1: 550000 rects
+caravel_00020021_fill_pattern_5_1: 560000 rects
+caravel_00020021_fill_pattern_5_1: 570000 rects
+caravel_00020021_fill_pattern_5_1: 580000 rects
+caravel_00020021_fill_pattern_5_1: 590000 rects
+caravel_00020021_fill_pattern_5_1: 600000 rects
+caravel_00020021_fill_pattern_5_1: 610000 rects
+caravel_00020021_fill_pattern_5_1: 620000 rects
+caravel_00020021_fill_pattern_5_1: 630000 rects
+caravel_00020021_fill_pattern_5_1: 640000 rects
+caravel_00020021_fill_pattern_5_1: 650000 rects
+caravel_00020021_fill_pattern_5_1: 660000 rects
+caravel_00020021_fill_pattern_5_1: 670000 rects
+caravel_00020021_fill_pattern_5_1: 680000 rects
+caravel_00020021_fill_pattern_5_1: 690000 rects
+caravel_00020021_fill_pattern_5_1: 700000 rects
+caravel_00020021_fill_pattern_5_1: 710000 rects
+caravel_00020021_fill_pattern_5_1: 720000 rects
+caravel_00020021_fill_pattern_5_1: 730000 rects
+caravel_00020021_fill_pattern_5_1: 740000 rects
+caravel_00020021_fill_pattern_5_1: 750000 rects
+caravel_00020021_fill_pattern_5_1: 760000 rects
+caravel_00020021_fill_pattern_5_1: 770000 rects
+caravel_00020021_fill_pattern_5_1: 780000 rects
+caravel_00020021_fill_pattern_5_1: 790000 rects
+caravel_00020021_fill_pattern_5_1: 800000 rects
+caravel_00020021_fill_pattern_5_1: 810000 rects
+caravel_00020021_fill_pattern_5_1: 820000 rects
+caravel_00020021_fill_pattern_5_1: 830000 rects
+caravel_00020021_fill_pattern_5_1: 840000 rects
+caravel_00020021_fill_pattern_5_1: 850000 rects
+caravel_00020021_fill_pattern_5_1: 860000 rects
+caravel_00020021_fill_pattern_5_1: 870000 rects
+caravel_00020021_fill_pattern_5_1: 880000 rects
+caravel_00020021_fill_pattern_5_1: 890000 rects
+caravel_00020021_fill_pattern_5_1: 900000 rects
+caravel_00020021_fill_pattern_5_1: 910000 rects
+caravel_00020021_fill_pattern_5_1: 920000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_5_1
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_3_7: 10000 rects
 caravel_00020021_fill_pattern_3_7: 20000 rects
 caravel_00020021_fill_pattern_3_7: 30000 rects
@@ -10118,36 +10119,13 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_7: 10000 rects
-caravel_00020021_fill_pattern_4_7: 20000 rects
-caravel_00020021_fill_pattern_4_7: 30000 rects
-caravel_00020021_fill_pattern_4_7: 40000 rects
-caravel_00020021_fill_pattern_4_7: 50000 rects
-caravel_00020021_fill_pattern_4_7: 60000 rects
-caravel_00020021_fill_pattern_4_7: 70000 rects
-caravel_00020021_fill_pattern_4_7: 80000 rects
-caravel_00020021_fill_pattern_4_7: 90000 rects
-caravel_00020021_fill_pattern_4_7: 100000 rects
-caravel_00020021_fill_pattern_4_7: 110000 rects
-caravel_00020021_fill_pattern_4_7: 120000 rects
-caravel_00020021_fill_pattern_4_7: 130000 rects
-caravel_00020021_fill_pattern_4_7: 140000 rects
-caravel_00020021_fill_pattern_4_7: 150000 rects
-caravel_00020021_fill_pattern_4_7: 160000 rects
-caravel_00020021_fill_pattern_4_7: 170000 rects
-caravel_00020021_fill_pattern_4_7: 180000 rects
-caravel_00020021_fill_pattern_4_7: 190000 rects
-caravel_00020021_fill_pattern_4_7: 200000 rects
-caravel_00020021_fill_pattern_4_7: 210000 rects
-caravel_00020021_fill_pattern_4_7: 220000 rects
-caravel_00020021_fill_pattern_4_7: 230000 rects
-caravel_00020021_fill_pattern_4_7: 240000 rects
-caravel_00020021_fill_pattern_4_7: 250000 rects
-caravel_00020021_fill_pattern_4_7: 260000 rects
-caravel_00020021_fill_pattern_4_7: 270000 rects
-caravel_00020021_fill_pattern_4_7: 280000 rects
+caravel_00020021_fill_pattern_0_7: 10000 rects
+caravel_00020021_fill_pattern_0_7: 20000 rects
+caravel_00020021_fill_pattern_0_7: 30000 rects
+caravel_00020021_fill_pattern_0_7: 40000 rects
+caravel_00020021_fill_pattern_0_7: 50000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_7
+   Generating output for cell caravel_00020021_fill_pattern_0_7
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10266,46 +10244,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_0_7: 10000 rects
-caravel_00020021_fill_pattern_0_7: 20000 rects
-caravel_00020021_fill_pattern_0_7: 30000 rects
-caravel_00020021_fill_pattern_0_7: 40000 rects
-caravel_00020021_fill_pattern_0_7: 50000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_7
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-Scaled magic input cell caravel_00020021_fill_pattern_2_3 geometry by factor of 2
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_2_3
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_2_2
 
@@ -10323,71 +10261,36 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_0_6: 10000 rects
-caravel_00020021_fill_pattern_0_6: 20000 rects
-caravel_00020021_fill_pattern_0_6: 30000 rects
-caravel_00020021_fill_pattern_0_6: 40000 rects
-caravel_00020021_fill_pattern_0_6: 50000 rects
-caravel_00020021_fill_pattern_0_6: 60000 rects
-caravel_00020021_fill_pattern_0_6: 70000 rects
-caravel_00020021_fill_pattern_0_6: 80000 rects
-caravel_00020021_fill_pattern_0_6: 90000 rects
-caravel_00020021_fill_pattern_0_6: 100000 rects
-caravel_00020021_fill_pattern_0_6: 110000 rects
-caravel_00020021_fill_pattern_0_6: 120000 rects
-caravel_00020021_fill_pattern_0_6: 130000 rects
-caravel_00020021_fill_pattern_0_6: 140000 rects
-caravel_00020021_fill_pattern_0_6: 150000 rects
-caravel_00020021_fill_pattern_0_6: 160000 rects
-caravel_00020021_fill_pattern_0_6: 170000 rects
-caravel_00020021_fill_pattern_0_6: 180000 rects
-caravel_00020021_fill_pattern_0_6: 190000 rects
-caravel_00020021_fill_pattern_0_6: 200000 rects
-caravel_00020021_fill_pattern_0_6: 210000 rects
-caravel_00020021_fill_pattern_0_6: 220000 rects
-caravel_00020021_fill_pattern_0_6: 230000 rects
-caravel_00020021_fill_pattern_0_6: 240000 rects
-caravel_00020021_fill_pattern_0_6: 250000 rects
-caravel_00020021_fill_pattern_0_6: 260000 rects
-caravel_00020021_fill_pattern_0_6: 270000 rects
-caravel_00020021_fill_pattern_0_6: 280000 rects
-caravel_00020021_fill_pattern_0_6: 290000 rects
-caravel_00020021_fill_pattern_0_6: 300000 rects
-caravel_00020021_fill_pattern_0_6: 310000 rects
-caravel_00020021_fill_pattern_0_6: 320000 rects
-caravel_00020021_fill_pattern_0_6: 330000 rects
-caravel_00020021_fill_pattern_0_6: 340000 rects
-caravel_00020021_fill_pattern_0_6: 350000 rects
-caravel_00020021_fill_pattern_0_6: 360000 rects
-caravel_00020021_fill_pattern_0_6: 370000 rects
-caravel_00020021_fill_pattern_0_6: 380000 rects
-caravel_00020021_fill_pattern_0_6: 390000 rects
-caravel_00020021_fill_pattern_0_6: 400000 rects
-caravel_00020021_fill_pattern_0_6: 410000 rects
-caravel_00020021_fill_pattern_0_6: 420000 rects
-caravel_00020021_fill_pattern_0_6: 430000 rects
-caravel_00020021_fill_pattern_0_6: 440000 rects
-caravel_00020021_fill_pattern_0_6: 450000 rects
-caravel_00020021_fill_pattern_0_6: 460000 rects
-caravel_00020021_fill_pattern_0_6: 470000 rects
-caravel_00020021_fill_pattern_0_6: 480000 rects
-caravel_00020021_fill_pattern_0_6: 490000 rects
-caravel_00020021_fill_pattern_0_6: 500000 rects
-caravel_00020021_fill_pattern_0_6: 510000 rects
-caravel_00020021_fill_pattern_0_6: 520000 rects
-caravel_00020021_fill_pattern_0_6: 530000 rects
-caravel_00020021_fill_pattern_0_6: 540000 rects
-caravel_00020021_fill_pattern_0_6: 550000 rects
-caravel_00020021_fill_pattern_0_6: 560000 rects
-caravel_00020021_fill_pattern_0_6: 570000 rects
-caravel_00020021_fill_pattern_0_6: 580000 rects
-caravel_00020021_fill_pattern_0_6: 590000 rects
-caravel_00020021_fill_pattern_0_6: 600000 rects
-caravel_00020021_fill_pattern_0_6: 610000 rects
-caravel_00020021_fill_pattern_0_6: 620000 rects
-caravel_00020021_fill_pattern_0_6: 630000 rects
+caravel_00020021_fill_pattern_4_7: 10000 rects
+caravel_00020021_fill_pattern_4_7: 20000 rects
+caravel_00020021_fill_pattern_4_7: 30000 rects
+caravel_00020021_fill_pattern_4_7: 40000 rects
+caravel_00020021_fill_pattern_4_7: 50000 rects
+caravel_00020021_fill_pattern_4_7: 60000 rects
+caravel_00020021_fill_pattern_4_7: 70000 rects
+caravel_00020021_fill_pattern_4_7: 80000 rects
+caravel_00020021_fill_pattern_4_7: 90000 rects
+caravel_00020021_fill_pattern_4_7: 100000 rects
+caravel_00020021_fill_pattern_4_7: 110000 rects
+caravel_00020021_fill_pattern_4_7: 120000 rects
+caravel_00020021_fill_pattern_4_7: 130000 rects
+caravel_00020021_fill_pattern_4_7: 140000 rects
+caravel_00020021_fill_pattern_4_7: 150000 rects
+caravel_00020021_fill_pattern_4_7: 160000 rects
+caravel_00020021_fill_pattern_4_7: 170000 rects
+caravel_00020021_fill_pattern_4_7: 180000 rects
+caravel_00020021_fill_pattern_4_7: 190000 rects
+caravel_00020021_fill_pattern_4_7: 200000 rects
+caravel_00020021_fill_pattern_4_7: 210000 rects
+caravel_00020021_fill_pattern_4_7: 220000 rects
+caravel_00020021_fill_pattern_4_7: 230000 rects
+caravel_00020021_fill_pattern_4_7: 240000 rects
+caravel_00020021_fill_pattern_4_7: 250000 rects
+caravel_00020021_fill_pattern_4_7: 260000 rects
+caravel_00020021_fill_pattern_4_7: 270000 rects
+caravel_00020021_fill_pattern_4_7: 280000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_6
+   Generating output for cell caravel_00020021_fill_pattern_4_7
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10426,84 +10329,27 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_4: 10000 rects
-caravel_00020021_fill_pattern_3_4: 20000 rects
-caravel_00020021_fill_pattern_3_4: 30000 rects
-caravel_00020021_fill_pattern_3_4: 40000 rects
-caravel_00020021_fill_pattern_3_4: 50000 rects
-caravel_00020021_fill_pattern_3_4: 60000 rects
-caravel_00020021_fill_pattern_3_4: 70000 rects
-caravel_00020021_fill_pattern_3_4: 80000 rects
-caravel_00020021_fill_pattern_3_4: 90000 rects
-caravel_00020021_fill_pattern_3_4: 100000 rects
-caravel_00020021_fill_pattern_3_4: 110000 rects
-caravel_00020021_fill_pattern_3_4: 120000 rects
-caravel_00020021_fill_pattern_3_4: 130000 rects
-caravel_00020021_fill_pattern_3_4: 140000 rects
-caravel_00020021_fill_pattern_3_4: 150000 rects
-caravel_00020021_fill_pattern_3_4: 160000 rects
-caravel_00020021_fill_pattern_3_4: 170000 rects
-caravel_00020021_fill_pattern_3_4: 180000 rects
-caravel_00020021_fill_pattern_3_4: 190000 rects
-caravel_00020021_fill_pattern_3_4: 200000 rects
-caravel_00020021_fill_pattern_3_4: 210000 rects
-caravel_00020021_fill_pattern_3_4: 220000 rects
-caravel_00020021_fill_pattern_3_4: 230000 rects
-caravel_00020021_fill_pattern_3_4: 240000 rects
-caravel_00020021_fill_pattern_3_4: 250000 rects
-caravel_00020021_fill_pattern_3_4: 260000 rects
-caravel_00020021_fill_pattern_3_4: 270000 rects
-caravel_00020021_fill_pattern_3_4: 280000 rects
-caravel_00020021_fill_pattern_3_4: 290000 rects
-caravel_00020021_fill_pattern_3_4: 300000 rects
-caravel_00020021_fill_pattern_3_4: 310000 rects
-caravel_00020021_fill_pattern_3_4: 320000 rects
-caravel_00020021_fill_pattern_3_4: 330000 rects
-caravel_00020021_fill_pattern_3_4: 340000 rects
-caravel_00020021_fill_pattern_3_4: 350000 rects
-caravel_00020021_fill_pattern_3_4: 360000 rects
-caravel_00020021_fill_pattern_3_4: 370000 rects
-caravel_00020021_fill_pattern_3_4: 380000 rects
-caravel_00020021_fill_pattern_3_4: 390000 rects
-caravel_00020021_fill_pattern_3_4: 400000 rects
-caravel_00020021_fill_pattern_3_4: 410000 rects
-caravel_00020021_fill_pattern_3_4: 420000 rects
-caravel_00020021_fill_pattern_3_4: 430000 rects
-caravel_00020021_fill_pattern_3_4: 440000 rects
-caravel_00020021_fill_pattern_3_4: 450000 rects
-caravel_00020021_fill_pattern_3_4: 460000 rects
-caravel_00020021_fill_pattern_3_4: 470000 rects
-caravel_00020021_fill_pattern_3_4: 480000 rects
-caravel_00020021_fill_pattern_3_4: 490000 rects
-caravel_00020021_fill_pattern_3_4: 500000 rects
-caravel_00020021_fill_pattern_3_4: 510000 rects
-caravel_00020021_fill_pattern_3_4: 520000 rects
-caravel_00020021_fill_pattern_3_4: 530000 rects
-caravel_00020021_fill_pattern_3_4: 540000 rects
-caravel_00020021_fill_pattern_3_4: 550000 rects
-caravel_00020021_fill_pattern_3_4: 560000 rects
-caravel_00020021_fill_pattern_3_4: 570000 rects
-caravel_00020021_fill_pattern_3_4: 580000 rects
-caravel_00020021_fill_pattern_3_4: 590000 rects
-caravel_00020021_fill_pattern_3_4: 600000 rects
-caravel_00020021_fill_pattern_3_4: 610000 rects
-caravel_00020021_fill_pattern_3_4: 620000 rects
-caravel_00020021_fill_pattern_3_4: 630000 rects
-caravel_00020021_fill_pattern_3_4: 640000 rects
-caravel_00020021_fill_pattern_3_4: 650000 rects
-caravel_00020021_fill_pattern_3_4: 660000 rects
-caravel_00020021_fill_pattern_3_4: 670000 rects
-caravel_00020021_fill_pattern_3_4: 680000 rects
-caravel_00020021_fill_pattern_3_4: 690000 rects
-caravel_00020021_fill_pattern_3_4: 700000 rects
-caravel_00020021_fill_pattern_3_4: 710000 rects
-caravel_00020021_fill_pattern_3_4: 720000 rects
-caravel_00020021_fill_pattern_3_4: 730000 rects
-caravel_00020021_fill_pattern_3_4: 740000 rects
-caravel_00020021_fill_pattern_3_4: 750000 rects
-caravel_00020021_fill_pattern_3_4: 760000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_4
+   Generating output for cell caravel_00020021_fill_pattern_1_2
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_1_3: 10000 rects
+caravel_00020021_fill_pattern_1_3: 20000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_1_3
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10536,42 +10382,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_2_6
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-Scaled magic input cell caravel_00020021_fill_pattern_3_3 geometry by factor of 2
-caravel_00020021_fill_pattern_3_3: 10000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_3
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_1_4: 10000 rects
 caravel_00020021_fill_pattern_1_4: 20000 rects
 caravel_00020021_fill_pattern_1_4: 30000 rects
@@ -10598,21 +10408,52 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_6: 10000 rects
-caravel_00020021_fill_pattern_3_6: 20000 rects
-caravel_00020021_fill_pattern_3_6: 30000 rects
-caravel_00020021_fill_pattern_3_6: 40000 rects
-caravel_00020021_fill_pattern_3_6: 50000 rects
-caravel_00020021_fill_pattern_3_6: 60000 rects
-caravel_00020021_fill_pattern_3_6: 70000 rects
-caravel_00020021_fill_pattern_3_6: 80000 rects
-caravel_00020021_fill_pattern_3_6: 90000 rects
-caravel_00020021_fill_pattern_3_6: 100000 rects
-caravel_00020021_fill_pattern_3_6: 110000 rects
-caravel_00020021_fill_pattern_3_6: 120000 rects
-caravel_00020021_fill_pattern_3_6: 130000 rects
+caravel_00020021_fill_pattern_4_6: 10000 rects
+caravel_00020021_fill_pattern_4_6: 20000 rects
+caravel_00020021_fill_pattern_4_6: 30000 rects
+caravel_00020021_fill_pattern_4_6: 40000 rects
+caravel_00020021_fill_pattern_4_6: 50000 rects
+caravel_00020021_fill_pattern_4_6: 60000 rects
+caravel_00020021_fill_pattern_4_6: 70000 rects
+caravel_00020021_fill_pattern_4_6: 80000 rects
+caravel_00020021_fill_pattern_4_6: 90000 rects
+caravel_00020021_fill_pattern_4_6: 100000 rects
+caravel_00020021_fill_pattern_4_6: 110000 rects
+caravel_00020021_fill_pattern_4_6: 120000 rects
+caravel_00020021_fill_pattern_4_6: 130000 rects
+caravel_00020021_fill_pattern_4_6: 140000 rects
+caravel_00020021_fill_pattern_4_6: 150000 rects
+caravel_00020021_fill_pattern_4_6: 160000 rects
+caravel_00020021_fill_pattern_4_6: 170000 rects
+caravel_00020021_fill_pattern_4_6: 180000 rects
+caravel_00020021_fill_pattern_4_6: 190000 rects
+caravel_00020021_fill_pattern_4_6: 200000 rects
+caravel_00020021_fill_pattern_4_6: 210000 rects
+caravel_00020021_fill_pattern_4_6: 220000 rects
+caravel_00020021_fill_pattern_4_6: 230000 rects
+caravel_00020021_fill_pattern_4_6: 240000 rects
+caravel_00020021_fill_pattern_4_6: 250000 rects
+caravel_00020021_fill_pattern_4_6: 260000 rects
+caravel_00020021_fill_pattern_4_6: 270000 rects
+caravel_00020021_fill_pattern_4_6: 280000 rects
+caravel_00020021_fill_pattern_4_6: 290000 rects
+caravel_00020021_fill_pattern_4_6: 300000 rects
+caravel_00020021_fill_pattern_4_6: 310000 rects
+caravel_00020021_fill_pattern_4_6: 320000 rects
+caravel_00020021_fill_pattern_4_6: 330000 rects
+caravel_00020021_fill_pattern_4_6: 340000 rects
+caravel_00020021_fill_pattern_4_6: 350000 rects
+caravel_00020021_fill_pattern_4_6: 360000 rects
+caravel_00020021_fill_pattern_4_6: 370000 rects
+caravel_00020021_fill_pattern_4_6: 380000 rects
+caravel_00020021_fill_pattern_4_6: 390000 rects
+caravel_00020021_fill_pattern_4_6: 400000 rects
+caravel_00020021_fill_pattern_4_6: 410000 rects
+caravel_00020021_fill_pattern_4_6: 420000 rects
+caravel_00020021_fill_pattern_4_6: 430000 rects
+caravel_00020021_fill_pattern_4_6: 440000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_6
+   Generating output for cell caravel_00020021_fill_pattern_4_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10629,7 +10470,119 @@
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_2
+   Generating output for cell caravel_00020021_fill_pattern_2_6
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_3_5: 10000 rects
+caravel_00020021_fill_pattern_3_5: 20000 rects
+caravel_00020021_fill_pattern_3_5: 30000 rects
+caravel_00020021_fill_pattern_3_5: 40000 rects
+caravel_00020021_fill_pattern_3_5: 50000 rects
+caravel_00020021_fill_pattern_3_5: 60000 rects
+caravel_00020021_fill_pattern_3_5: 70000 rects
+caravel_00020021_fill_pattern_3_5: 80000 rects
+caravel_00020021_fill_pattern_3_5: 90000 rects
+caravel_00020021_fill_pattern_3_5: 100000 rects
+caravel_00020021_fill_pattern_3_5: 110000 rects
+caravel_00020021_fill_pattern_3_5: 120000 rects
+caravel_00020021_fill_pattern_3_5: 130000 rects
+caravel_00020021_fill_pattern_3_5: 140000 rects
+caravel_00020021_fill_pattern_3_5: 150000 rects
+caravel_00020021_fill_pattern_3_5: 160000 rects
+caravel_00020021_fill_pattern_3_5: 170000 rects
+caravel_00020021_fill_pattern_3_5: 180000 rects
+caravel_00020021_fill_pattern_3_5: 190000 rects
+caravel_00020021_fill_pattern_3_5: 200000 rects
+caravel_00020021_fill_pattern_3_5: 210000 rects
+caravel_00020021_fill_pattern_3_5: 220000 rects
+caravel_00020021_fill_pattern_3_5: 230000 rects
+caravel_00020021_fill_pattern_3_5: 240000 rects
+caravel_00020021_fill_pattern_3_5: 250000 rects
+caravel_00020021_fill_pattern_3_5: 260000 rects
+caravel_00020021_fill_pattern_3_5: 270000 rects
+caravel_00020021_fill_pattern_3_5: 280000 rects
+caravel_00020021_fill_pattern_3_5: 290000 rects
+caravel_00020021_fill_pattern_3_5: 300000 rects
+caravel_00020021_fill_pattern_3_5: 310000 rects
+caravel_00020021_fill_pattern_3_5: 320000 rects
+caravel_00020021_fill_pattern_3_5: 330000 rects
+caravel_00020021_fill_pattern_3_5: 340000 rects
+caravel_00020021_fill_pattern_3_5: 350000 rects
+caravel_00020021_fill_pattern_3_5: 360000 rects
+caravel_00020021_fill_pattern_3_5: 370000 rects
+caravel_00020021_fill_pattern_3_5: 380000 rects
+caravel_00020021_fill_pattern_3_5: 390000 rects
+caravel_00020021_fill_pattern_3_5: 400000 rects
+caravel_00020021_fill_pattern_3_5: 410000 rects
+caravel_00020021_fill_pattern_3_5: 420000 rects
+caravel_00020021_fill_pattern_3_5: 430000 rects
+caravel_00020021_fill_pattern_3_5: 440000 rects
+caravel_00020021_fill_pattern_3_5: 450000 rects
+caravel_00020021_fill_pattern_3_5: 460000 rects
+caravel_00020021_fill_pattern_3_5: 470000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_3_5
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+Scaled magic input cell caravel_00020021_fill_pattern_2_3 geometry by factor of 2
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_2_3
+
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_3_6: 10000 rects
+caravel_00020021_fill_pattern_3_6: 20000 rects
+caravel_00020021_fill_pattern_3_6: 30000 rects
+caravel_00020021_fill_pattern_3_6: 40000 rects
+caravel_00020021_fill_pattern_3_6: 50000 rects
+caravel_00020021_fill_pattern_3_6: 60000 rects
+caravel_00020021_fill_pattern_3_6: 70000 rects
+caravel_00020021_fill_pattern_3_6: 80000 rects
+caravel_00020021_fill_pattern_3_6: 90000 rects
+caravel_00020021_fill_pattern_3_6: 100000 rects
+caravel_00020021_fill_pattern_3_6: 110000 rects
+caravel_00020021_fill_pattern_3_6: 120000 rects
+caravel_00020021_fill_pattern_3_6: 130000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_3_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10778,10 +10731,10 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_1_3: 10000 rects
-caravel_00020021_fill_pattern_1_3: 20000 rects
+Scaled magic input cell caravel_00020021_fill_pattern_3_3 geometry by factor of 2
+caravel_00020021_fill_pattern_3_3: 10000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_3
+   Generating output for cell caravel_00020021_fill_pattern_3_3
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10824,55 +10777,84 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_3_5: 10000 rects
-caravel_00020021_fill_pattern_3_5: 20000 rects
-caravel_00020021_fill_pattern_3_5: 30000 rects
-caravel_00020021_fill_pattern_3_5: 40000 rects
-caravel_00020021_fill_pattern_3_5: 50000 rects
-caravel_00020021_fill_pattern_3_5: 60000 rects
-caravel_00020021_fill_pattern_3_5: 70000 rects
-caravel_00020021_fill_pattern_3_5: 80000 rects
-caravel_00020021_fill_pattern_3_5: 90000 rects
-caravel_00020021_fill_pattern_3_5: 100000 rects
-caravel_00020021_fill_pattern_3_5: 110000 rects
-caravel_00020021_fill_pattern_3_5: 120000 rects
-caravel_00020021_fill_pattern_3_5: 130000 rects
-caravel_00020021_fill_pattern_3_5: 140000 rects
-caravel_00020021_fill_pattern_3_5: 150000 rects
-caravel_00020021_fill_pattern_3_5: 160000 rects
-caravel_00020021_fill_pattern_3_5: 170000 rects
-caravel_00020021_fill_pattern_3_5: 180000 rects
-caravel_00020021_fill_pattern_3_5: 190000 rects
-caravel_00020021_fill_pattern_3_5: 200000 rects
-caravel_00020021_fill_pattern_3_5: 210000 rects
-caravel_00020021_fill_pattern_3_5: 220000 rects
-caravel_00020021_fill_pattern_3_5: 230000 rects
-caravel_00020021_fill_pattern_3_5: 240000 rects
-caravel_00020021_fill_pattern_3_5: 250000 rects
-caravel_00020021_fill_pattern_3_5: 260000 rects
-caravel_00020021_fill_pattern_3_5: 270000 rects
-caravel_00020021_fill_pattern_3_5: 280000 rects
-caravel_00020021_fill_pattern_3_5: 290000 rects
-caravel_00020021_fill_pattern_3_5: 300000 rects
-caravel_00020021_fill_pattern_3_5: 310000 rects
-caravel_00020021_fill_pattern_3_5: 320000 rects
-caravel_00020021_fill_pattern_3_5: 330000 rects
-caravel_00020021_fill_pattern_3_5: 340000 rects
-caravel_00020021_fill_pattern_3_5: 350000 rects
-caravel_00020021_fill_pattern_3_5: 360000 rects
-caravel_00020021_fill_pattern_3_5: 370000 rects
-caravel_00020021_fill_pattern_3_5: 380000 rects
-caravel_00020021_fill_pattern_3_5: 390000 rects
-caravel_00020021_fill_pattern_3_5: 400000 rects
-caravel_00020021_fill_pattern_3_5: 410000 rects
-caravel_00020021_fill_pattern_3_5: 420000 rects
-caravel_00020021_fill_pattern_3_5: 430000 rects
-caravel_00020021_fill_pattern_3_5: 440000 rects
-caravel_00020021_fill_pattern_3_5: 450000 rects
-caravel_00020021_fill_pattern_3_5: 460000 rects
-caravel_00020021_fill_pattern_3_5: 470000 rects
+caravel_00020021_fill_pattern_3_4: 10000 rects
+caravel_00020021_fill_pattern_3_4: 20000 rects
+caravel_00020021_fill_pattern_3_4: 30000 rects
+caravel_00020021_fill_pattern_3_4: 40000 rects
+caravel_00020021_fill_pattern_3_4: 50000 rects
+caravel_00020021_fill_pattern_3_4: 60000 rects
+caravel_00020021_fill_pattern_3_4: 70000 rects
+caravel_00020021_fill_pattern_3_4: 80000 rects
+caravel_00020021_fill_pattern_3_4: 90000 rects
+caravel_00020021_fill_pattern_3_4: 100000 rects
+caravel_00020021_fill_pattern_3_4: 110000 rects
+caravel_00020021_fill_pattern_3_4: 120000 rects
+caravel_00020021_fill_pattern_3_4: 130000 rects
+caravel_00020021_fill_pattern_3_4: 140000 rects
+caravel_00020021_fill_pattern_3_4: 150000 rects
+caravel_00020021_fill_pattern_3_4: 160000 rects
+caravel_00020021_fill_pattern_3_4: 170000 rects
+caravel_00020021_fill_pattern_3_4: 180000 rects
+caravel_00020021_fill_pattern_3_4: 190000 rects
+caravel_00020021_fill_pattern_3_4: 200000 rects
+caravel_00020021_fill_pattern_3_4: 210000 rects
+caravel_00020021_fill_pattern_3_4: 220000 rects
+caravel_00020021_fill_pattern_3_4: 230000 rects
+caravel_00020021_fill_pattern_3_4: 240000 rects
+caravel_00020021_fill_pattern_3_4: 250000 rects
+caravel_00020021_fill_pattern_3_4: 260000 rects
+caravel_00020021_fill_pattern_3_4: 270000 rects
+caravel_00020021_fill_pattern_3_4: 280000 rects
+caravel_00020021_fill_pattern_3_4: 290000 rects
+caravel_00020021_fill_pattern_3_4: 300000 rects
+caravel_00020021_fill_pattern_3_4: 310000 rects
+caravel_00020021_fill_pattern_3_4: 320000 rects
+caravel_00020021_fill_pattern_3_4: 330000 rects
+caravel_00020021_fill_pattern_3_4: 340000 rects
+caravel_00020021_fill_pattern_3_4: 350000 rects
+caravel_00020021_fill_pattern_3_4: 360000 rects
+caravel_00020021_fill_pattern_3_4: 370000 rects
+caravel_00020021_fill_pattern_3_4: 380000 rects
+caravel_00020021_fill_pattern_3_4: 390000 rects
+caravel_00020021_fill_pattern_3_4: 400000 rects
+caravel_00020021_fill_pattern_3_4: 410000 rects
+caravel_00020021_fill_pattern_3_4: 420000 rects
+caravel_00020021_fill_pattern_3_4: 430000 rects
+caravel_00020021_fill_pattern_3_4: 440000 rects
+caravel_00020021_fill_pattern_3_4: 450000 rects
+caravel_00020021_fill_pattern_3_4: 460000 rects
+caravel_00020021_fill_pattern_3_4: 470000 rects
+caravel_00020021_fill_pattern_3_4: 480000 rects
+caravel_00020021_fill_pattern_3_4: 490000 rects
+caravel_00020021_fill_pattern_3_4: 500000 rects
+caravel_00020021_fill_pattern_3_4: 510000 rects
+caravel_00020021_fill_pattern_3_4: 520000 rects
+caravel_00020021_fill_pattern_3_4: 530000 rects
+caravel_00020021_fill_pattern_3_4: 540000 rects
+caravel_00020021_fill_pattern_3_4: 550000 rects
+caravel_00020021_fill_pattern_3_4: 560000 rects
+caravel_00020021_fill_pattern_3_4: 570000 rects
+caravel_00020021_fill_pattern_3_4: 580000 rects
+caravel_00020021_fill_pattern_3_4: 590000 rects
+caravel_00020021_fill_pattern_3_4: 600000 rects
+caravel_00020021_fill_pattern_3_4: 610000 rects
+caravel_00020021_fill_pattern_3_4: 620000 rects
+caravel_00020021_fill_pattern_3_4: 630000 rects
+caravel_00020021_fill_pattern_3_4: 640000 rects
+caravel_00020021_fill_pattern_3_4: 650000 rects
+caravel_00020021_fill_pattern_3_4: 660000 rects
+caravel_00020021_fill_pattern_3_4: 670000 rects
+caravel_00020021_fill_pattern_3_4: 680000 rects
+caravel_00020021_fill_pattern_3_4: 690000 rects
+caravel_00020021_fill_pattern_3_4: 700000 rects
+caravel_00020021_fill_pattern_3_4: 710000 rects
+caravel_00020021_fill_pattern_3_4: 720000 rects
+caravel_00020021_fill_pattern_3_4: 730000 rects
+caravel_00020021_fill_pattern_3_4: 740000 rects
+caravel_00020021_fill_pattern_3_4: 750000 rects
+caravel_00020021_fill_pattern_3_4: 760000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_3_5
+   Generating output for cell caravel_00020021_fill_pattern_3_4
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -10993,82 +10975,71 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_6: 10000 rects
-caravel_00020021_fill_pattern_4_6: 20000 rects
-caravel_00020021_fill_pattern_4_6: 30000 rects
-caravel_00020021_fill_pattern_4_6: 40000 rects
-caravel_00020021_fill_pattern_4_6: 50000 rects
-caravel_00020021_fill_pattern_4_6: 60000 rects
-caravel_00020021_fill_pattern_4_6: 70000 rects
-caravel_00020021_fill_pattern_4_6: 80000 rects
-caravel_00020021_fill_pattern_4_6: 90000 rects
-caravel_00020021_fill_pattern_4_6: 100000 rects
-caravel_00020021_fill_pattern_4_6: 110000 rects
-caravel_00020021_fill_pattern_4_6: 120000 rects
-caravel_00020021_fill_pattern_4_6: 130000 rects
-caravel_00020021_fill_pattern_4_6: 140000 rects
-caravel_00020021_fill_pattern_4_6: 150000 rects
-caravel_00020021_fill_pattern_4_6: 160000 rects
-caravel_00020021_fill_pattern_4_6: 170000 rects
-caravel_00020021_fill_pattern_4_6: 180000 rects
-caravel_00020021_fill_pattern_4_6: 190000 rects
-caravel_00020021_fill_pattern_4_6: 200000 rects
-caravel_00020021_fill_pattern_4_6: 210000 rects
-caravel_00020021_fill_pattern_4_6: 220000 rects
-caravel_00020021_fill_pattern_4_6: 230000 rects
-caravel_00020021_fill_pattern_4_6: 240000 rects
-caravel_00020021_fill_pattern_4_6: 250000 rects
-caravel_00020021_fill_pattern_4_6: 260000 rects
-caravel_00020021_fill_pattern_4_6: 270000 rects
-caravel_00020021_fill_pattern_4_6: 280000 rects
-caravel_00020021_fill_pattern_4_6: 290000 rects
-caravel_00020021_fill_pattern_4_6: 300000 rects
-caravel_00020021_fill_pattern_4_6: 310000 rects
-caravel_00020021_fill_pattern_4_6: 320000 rects
-caravel_00020021_fill_pattern_4_6: 330000 rects
-caravel_00020021_fill_pattern_4_6: 340000 rects
-caravel_00020021_fill_pattern_4_6: 350000 rects
-caravel_00020021_fill_pattern_4_6: 360000 rects
-caravel_00020021_fill_pattern_4_6: 370000 rects
-caravel_00020021_fill_pattern_4_6: 380000 rects
-caravel_00020021_fill_pattern_4_6: 390000 rects
-caravel_00020021_fill_pattern_4_6: 400000 rects
-caravel_00020021_fill_pattern_4_6: 410000 rects
-caravel_00020021_fill_pattern_4_6: 420000 rects
-caravel_00020021_fill_pattern_4_6: 430000 rects
-caravel_00020021_fill_pattern_4_6: 440000 rects
+caravel_00020021_fill_pattern_0_6: 10000 rects
+caravel_00020021_fill_pattern_0_6: 20000 rects
+caravel_00020021_fill_pattern_0_6: 30000 rects
+caravel_00020021_fill_pattern_0_6: 40000 rects
+caravel_00020021_fill_pattern_0_6: 50000 rects
+caravel_00020021_fill_pattern_0_6: 60000 rects
+caravel_00020021_fill_pattern_0_6: 70000 rects
+caravel_00020021_fill_pattern_0_6: 80000 rects
+caravel_00020021_fill_pattern_0_6: 90000 rects
+caravel_00020021_fill_pattern_0_6: 100000 rects
+caravel_00020021_fill_pattern_0_6: 110000 rects
+caravel_00020021_fill_pattern_0_6: 120000 rects
+caravel_00020021_fill_pattern_0_6: 130000 rects
+caravel_00020021_fill_pattern_0_6: 140000 rects
+caravel_00020021_fill_pattern_0_6: 150000 rects
+caravel_00020021_fill_pattern_0_6: 160000 rects
+caravel_00020021_fill_pattern_0_6: 170000 rects
+caravel_00020021_fill_pattern_0_6: 180000 rects
+caravel_00020021_fill_pattern_0_6: 190000 rects
+caravel_00020021_fill_pattern_0_6: 200000 rects
+caravel_00020021_fill_pattern_0_6: 210000 rects
+caravel_00020021_fill_pattern_0_6: 220000 rects
+caravel_00020021_fill_pattern_0_6: 230000 rects
+caravel_00020021_fill_pattern_0_6: 240000 rects
+caravel_00020021_fill_pattern_0_6: 250000 rects
+caravel_00020021_fill_pattern_0_6: 260000 rects
+caravel_00020021_fill_pattern_0_6: 270000 rects
+caravel_00020021_fill_pattern_0_6: 280000 rects
+caravel_00020021_fill_pattern_0_6: 290000 rects
+caravel_00020021_fill_pattern_0_6: 300000 rects
+caravel_00020021_fill_pattern_0_6: 310000 rects
+caravel_00020021_fill_pattern_0_6: 320000 rects
+caravel_00020021_fill_pattern_0_6: 330000 rects
+caravel_00020021_fill_pattern_0_6: 340000 rects
+caravel_00020021_fill_pattern_0_6: 350000 rects
+caravel_00020021_fill_pattern_0_6: 360000 rects
+caravel_00020021_fill_pattern_0_6: 370000 rects
+caravel_00020021_fill_pattern_0_6: 380000 rects
+caravel_00020021_fill_pattern_0_6: 390000 rects
+caravel_00020021_fill_pattern_0_6: 400000 rects
+caravel_00020021_fill_pattern_0_6: 410000 rects
+caravel_00020021_fill_pattern_0_6: 420000 rects
+caravel_00020021_fill_pattern_0_6: 430000 rects
+caravel_00020021_fill_pattern_0_6: 440000 rects
+caravel_00020021_fill_pattern_0_6: 450000 rects
+caravel_00020021_fill_pattern_0_6: 460000 rects
+caravel_00020021_fill_pattern_0_6: 470000 rects
+caravel_00020021_fill_pattern_0_6: 480000 rects
+caravel_00020021_fill_pattern_0_6: 490000 rects
+caravel_00020021_fill_pattern_0_6: 500000 rects
+caravel_00020021_fill_pattern_0_6: 510000 rects
+caravel_00020021_fill_pattern_0_6: 520000 rects
+caravel_00020021_fill_pattern_0_6: 530000 rects
+caravel_00020021_fill_pattern_0_6: 540000 rects
+caravel_00020021_fill_pattern_0_6: 550000 rects
+caravel_00020021_fill_pattern_0_6: 560000 rects
+caravel_00020021_fill_pattern_0_6: 570000 rects
+caravel_00020021_fill_pattern_0_6: 580000 rects
+caravel_00020021_fill_pattern_0_6: 590000 rects
+caravel_00020021_fill_pattern_0_6: 600000 rects
+caravel_00020021_fill_pattern_0_6: 610000 rects
+caravel_00020021_fill_pattern_0_6: 620000 rects
+caravel_00020021_fill_pattern_0_6: 630000 rects
 CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_6
-
-caravel_00020021_fill_pattern_0_2: 1560000 rects
-caravel_00020021_fill_pattern_0_2: 1570000 rects
-caravel_00020021_fill_pattern_0_2: 1580000 rects
-caravel_00020021_fill_pattern_0_2: 1590000 rects
-caravel_00020021_fill_pattern_0_2: 1600000 rects
-caravel_00020021_fill_pattern_0_2: 1610000 rects
-caravel_00020021_fill_pattern_0_2: 1620000 rects
-caravel_00020021_fill_pattern_0_2: 1630000 rects
-caravel_00020021_fill_pattern_0_2: 1640000 rects
-caravel_00020021_fill_pattern_0_2: 1650000 rects
-caravel_00020021_fill_pattern_0_2: 1660000 rects
-caravel_00020021_fill_pattern_0_2: 1670000 rects
-caravel_00020021_fill_pattern_0_2: 1680000 rects
-caravel_00020021_fill_pattern_0_2: 1690000 rects
-caravel_00020021_fill_pattern_0_2: 1700000 rects
-caravel_00020021_fill_pattern_0_2: 1710000 rects
-caravel_00020021_fill_pattern_0_2: 1720000 rects
-caravel_00020021_fill_pattern_0_2: 1730000 rects
-caravel_00020021_fill_pattern_0_2: 1740000 rects
-caravel_00020021_fill_pattern_0_2: 1750000 rects
-caravel_00020021_fill_pattern_0_2: 1760000 rects
-caravel_00020021_fill_pattern_0_2: 1770000 rects
-caravel_00020021_fill_pattern_0_2: 1780000 rects
-caravel_00020021_fill_pattern_0_2: 1790000 rects
-caravel_00020021_fill_pattern_0_2: 1800000 rects
-caravel_00020021_fill_pattern_0_2: 1810000 rects
-caravel_00020021_fill_pattern_0_2: 1820000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_0_2
+   Generating output for cell caravel_00020021_fill_pattern_0_6
 
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
@@ -11163,94 +11134,6 @@
 Scaled tech values by 2 / 1 to match internal grid scaling
 Loading sky130A Device Generator Menu ...
 Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
-caravel_00020021_fill_pattern_4_5: 10000 rects
-caravel_00020021_fill_pattern_4_5: 20000 rects
-caravel_00020021_fill_pattern_4_5: 30000 rects
-caravel_00020021_fill_pattern_4_5: 40000 rects
-caravel_00020021_fill_pattern_4_5: 50000 rects
-caravel_00020021_fill_pattern_4_5: 60000 rects
-caravel_00020021_fill_pattern_4_5: 70000 rects
-caravel_00020021_fill_pattern_4_5: 80000 rects
-caravel_00020021_fill_pattern_4_5: 90000 rects
-caravel_00020021_fill_pattern_4_5: 100000 rects
-caravel_00020021_fill_pattern_4_5: 110000 rects
-caravel_00020021_fill_pattern_4_5: 120000 rects
-caravel_00020021_fill_pattern_4_5: 130000 rects
-caravel_00020021_fill_pattern_4_5: 140000 rects
-caravel_00020021_fill_pattern_4_5: 150000 rects
-caravel_00020021_fill_pattern_4_5: 160000 rects
-caravel_00020021_fill_pattern_4_5: 170000 rects
-caravel_00020021_fill_pattern_4_5: 180000 rects
-caravel_00020021_fill_pattern_4_5: 190000 rects
-caravel_00020021_fill_pattern_4_5: 200000 rects
-caravel_00020021_fill_pattern_4_5: 210000 rects
-caravel_00020021_fill_pattern_4_5: 220000 rects
-caravel_00020021_fill_pattern_4_5: 230000 rects
-caravel_00020021_fill_pattern_4_5: 240000 rects
-caravel_00020021_fill_pattern_4_5: 250000 rects
-caravel_00020021_fill_pattern_4_5: 260000 rects
-caravel_00020021_fill_pattern_4_5: 270000 rects
-caravel_00020021_fill_pattern_4_5: 280000 rects
-caravel_00020021_fill_pattern_4_5: 290000 rects
-caravel_00020021_fill_pattern_4_5: 300000 rects
-caravel_00020021_fill_pattern_4_5: 310000 rects
-caravel_00020021_fill_pattern_4_5: 320000 rects
-caravel_00020021_fill_pattern_4_5: 330000 rects
-caravel_00020021_fill_pattern_4_5: 340000 rects
-caravel_00020021_fill_pattern_4_5: 350000 rects
-caravel_00020021_fill_pattern_4_5: 360000 rects
-caravel_00020021_fill_pattern_4_5: 370000 rects
-caravel_00020021_fill_pattern_4_5: 380000 rects
-caravel_00020021_fill_pattern_4_5: 390000 rects
-caravel_00020021_fill_pattern_4_5: 400000 rects
-caravel_00020021_fill_pattern_4_5: 410000 rects
-caravel_00020021_fill_pattern_4_5: 420000 rects
-caravel_00020021_fill_pattern_4_5: 430000 rects
-caravel_00020021_fill_pattern_4_5: 440000 rects
-caravel_00020021_fill_pattern_4_5: 450000 rects
-caravel_00020021_fill_pattern_4_5: 460000 rects
-caravel_00020021_fill_pattern_4_5: 470000 rects
-caravel_00020021_fill_pattern_4_5: 480000 rects
-caravel_00020021_fill_pattern_4_5: 490000 rects
-caravel_00020021_fill_pattern_4_5: 500000 rects
-caravel_00020021_fill_pattern_4_5: 510000 rects
-caravel_00020021_fill_pattern_4_5: 520000 rects
-caravel_00020021_fill_pattern_4_5: 530000 rects
-caravel_00020021_fill_pattern_4_5: 540000 rects
-caravel_00020021_fill_pattern_4_5: 550000 rects
-caravel_00020021_fill_pattern_4_5: 560000 rects
-caravel_00020021_fill_pattern_4_5: 570000 rects
-caravel_00020021_fill_pattern_4_5: 580000 rects
-caravel_00020021_fill_pattern_4_5: 590000 rects
-caravel_00020021_fill_pattern_4_5: 600000 rects
-caravel_00020021_fill_pattern_4_5: 610000 rects
-caravel_00020021_fill_pattern_4_5: 620000 rects
-caravel_00020021_fill_pattern_4_5: 630000 rects
-caravel_00020021_fill_pattern_4_5: 640000 rects
-caravel_00020021_fill_pattern_4_5: 650000 rects
-caravel_00020021_fill_pattern_4_5: 660000 rects
-caravel_00020021_fill_pattern_4_5: 670000 rects
-caravel_00020021_fill_pattern_4_5: 680000 rects
-caravel_00020021_fill_pattern_4_5: 690000 rects
-caravel_00020021_fill_pattern_4_5: 700000 rects
-caravel_00020021_fill_pattern_4_5: 710000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_5
-
-Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-site.pre: In custom site.pre...
-site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
-Processing system .magicrc file
-site.def: In custom site.def...
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130(vendor): scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
 caravel_00020021_fill_pattern_4_2: 10000 rects
 caravel_00020021_fill_pattern_4_2: 20000 rects
 caravel_00020021_fill_pattern_4_2: 30000 rects
@@ -11338,6 +11221,124 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_4_2
 
+Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+site.pre: In custom site.pre...
+site.pre: altered 'path sys' to: . $CAD_ROOT/magic/sys/ef-lib-magic/sys/style $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Processing system .magicrc file
+site.def: In custom site.def...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/mnt/shuttles/shuttle/mpw-two/slot-033/digital_pll/mag/generate_fill_dist.tcl" from command line.
+caravel_00020021_fill_pattern_4_5: 10000 rects
+caravel_00020021_fill_pattern_4_5: 20000 rects
+caravel_00020021_fill_pattern_4_5: 30000 rects
+caravel_00020021_fill_pattern_4_5: 40000 rects
+caravel_00020021_fill_pattern_4_5: 50000 rects
+caravel_00020021_fill_pattern_4_5: 60000 rects
+caravel_00020021_fill_pattern_4_5: 70000 rects
+caravel_00020021_fill_pattern_4_5: 80000 rects
+caravel_00020021_fill_pattern_4_5: 90000 rects
+caravel_00020021_fill_pattern_4_5: 100000 rects
+caravel_00020021_fill_pattern_4_5: 110000 rects
+caravel_00020021_fill_pattern_4_5: 120000 rects
+caravel_00020021_fill_pattern_4_5: 130000 rects
+caravel_00020021_fill_pattern_4_5: 140000 rects
+caravel_00020021_fill_pattern_4_5: 150000 rects
+caravel_00020021_fill_pattern_4_5: 160000 rects
+caravel_00020021_fill_pattern_4_5: 170000 rects
+caravel_00020021_fill_pattern_4_5: 180000 rects
+caravel_00020021_fill_pattern_4_5: 190000 rects
+caravel_00020021_fill_pattern_4_5: 200000 rects
+caravel_00020021_fill_pattern_4_5: 210000 rects
+caravel_00020021_fill_pattern_4_5: 220000 rects
+caravel_00020021_fill_pattern_4_5: 230000 rects
+caravel_00020021_fill_pattern_4_5: 240000 rects
+caravel_00020021_fill_pattern_4_5: 250000 rects
+caravel_00020021_fill_pattern_4_5: 260000 rects
+caravel_00020021_fill_pattern_4_5: 270000 rects
+caravel_00020021_fill_pattern_4_5: 280000 rects
+caravel_00020021_fill_pattern_4_5: 290000 rects
+caravel_00020021_fill_pattern_4_5: 300000 rects
+caravel_00020021_fill_pattern_4_5: 310000 rects
+caravel_00020021_fill_pattern_4_5: 320000 rects
+caravel_00020021_fill_pattern_4_5: 330000 rects
+caravel_00020021_fill_pattern_4_5: 340000 rects
+caravel_00020021_fill_pattern_4_5: 350000 rects
+caravel_00020021_fill_pattern_4_5: 360000 rects
+caravel_00020021_fill_pattern_4_5: 370000 rects
+caravel_00020021_fill_pattern_4_5: 380000 rects
+caravel_00020021_fill_pattern_4_5: 390000 rects
+caravel_00020021_fill_pattern_4_5: 400000 rects
+caravel_00020021_fill_pattern_4_5: 410000 rects
+caravel_00020021_fill_pattern_4_5: 420000 rects
+caravel_00020021_fill_pattern_4_5: 430000 rects
+caravel_00020021_fill_pattern_4_5: 440000 rects
+caravel_00020021_fill_pattern_4_5: 450000 rects
+caravel_00020021_fill_pattern_4_5: 460000 rects
+caravel_00020021_fill_pattern_4_5: 470000 rects
+caravel_00020021_fill_pattern_4_5: 480000 rects
+caravel_00020021_fill_pattern_4_5: 490000 rects
+caravel_00020021_fill_pattern_4_5: 500000 rects
+caravel_00020021_fill_pattern_4_5: 510000 rects
+caravel_00020021_fill_pattern_4_5: 520000 rects
+caravel_00020021_fill_pattern_4_5: 530000 rects
+caravel_00020021_fill_pattern_4_5: 540000 rects
+caravel_00020021_fill_pattern_4_5: 550000 rects
+caravel_00020021_fill_pattern_4_5: 560000 rects
+caravel_00020021_fill_pattern_4_5: 570000 rects
+caravel_00020021_fill_pattern_4_5: 580000 rects
+caravel_00020021_fill_pattern_4_5: 590000 rects
+caravel_00020021_fill_pattern_4_5: 600000 rects
+caravel_00020021_fill_pattern_4_5: 610000 rects
+caravel_00020021_fill_pattern_4_5: 620000 rects
+caravel_00020021_fill_pattern_4_5: 630000 rects
+caravel_00020021_fill_pattern_4_5: 640000 rects
+caravel_00020021_fill_pattern_4_5: 650000 rects
+caravel_00020021_fill_pattern_4_5: 660000 rects
+caravel_00020021_fill_pattern_4_5: 670000 rects
+caravel_00020021_fill_pattern_4_5: 680000 rects
+caravel_00020021_fill_pattern_4_5: 690000 rects
+caravel_00020021_fill_pattern_4_5: 700000 rects
+caravel_00020021_fill_pattern_4_5: 710000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_4_5
+
+caravel_00020021_fill_pattern_0_2: 1560000 rects
+caravel_00020021_fill_pattern_0_2: 1570000 rects
+caravel_00020021_fill_pattern_0_2: 1580000 rects
+caravel_00020021_fill_pattern_0_2: 1590000 rects
+caravel_00020021_fill_pattern_0_2: 1600000 rects
+caravel_00020021_fill_pattern_0_2: 1610000 rects
+caravel_00020021_fill_pattern_0_2: 1620000 rects
+caravel_00020021_fill_pattern_0_2: 1630000 rects
+caravel_00020021_fill_pattern_0_2: 1640000 rects
+caravel_00020021_fill_pattern_0_2: 1650000 rects
+caravel_00020021_fill_pattern_0_2: 1660000 rects
+caravel_00020021_fill_pattern_0_2: 1670000 rects
+caravel_00020021_fill_pattern_0_2: 1680000 rects
+caravel_00020021_fill_pattern_0_2: 1690000 rects
+caravel_00020021_fill_pattern_0_2: 1700000 rects
+caravel_00020021_fill_pattern_0_2: 1710000 rects
+caravel_00020021_fill_pattern_0_2: 1720000 rects
+caravel_00020021_fill_pattern_0_2: 1730000 rects
+caravel_00020021_fill_pattern_0_2: 1740000 rects
+caravel_00020021_fill_pattern_0_2: 1750000 rects
+caravel_00020021_fill_pattern_0_2: 1760000 rects
+caravel_00020021_fill_pattern_0_2: 1770000 rects
+caravel_00020021_fill_pattern_0_2: 1780000 rects
+caravel_00020021_fill_pattern_0_2: 1790000 rects
+caravel_00020021_fill_pattern_0_2: 1800000 rects
+caravel_00020021_fill_pattern_0_2: 1810000 rects
+caravel_00020021_fill_pattern_0_2: 1820000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_0_2
+
 caravel_00020021_fill_pattern_0_5: 1560000 rects
 caravel_00020021_fill_pattern_0_5: 1570000 rects
 caravel_00020021_fill_pattern_0_5: 1580000 rects
@@ -11367,6 +11368,7 @@
 caravel_00020021_fill_pattern_0_5: 1820000 rects
 caravel_00020021_fill_pattern_0_5: 1830000 rects
 caravel_00020021_fill_pattern_0_5: 1840000 rects
+caravel_00020021_fill_pattern_0_5: 1850000 rects
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_5
 
@@ -11397,110 +11399,6 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_4
 
-caravel_00020021_fill_pattern_4_0: 1560000 rects
-caravel_00020021_fill_pattern_4_0: 1570000 rects
-caravel_00020021_fill_pattern_4_0: 1580000 rects
-caravel_00020021_fill_pattern_4_0: 1590000 rects
-caravel_00020021_fill_pattern_4_0: 1600000 rects
-caravel_00020021_fill_pattern_4_0: 1610000 rects
-caravel_00020021_fill_pattern_4_0: 1620000 rects
-caravel_00020021_fill_pattern_4_0: 1630000 rects
-caravel_00020021_fill_pattern_4_0: 1640000 rects
-caravel_00020021_fill_pattern_4_0: 1650000 rects
-caravel_00020021_fill_pattern_4_0: 1660000 rects
-caravel_00020021_fill_pattern_4_0: 1670000 rects
-caravel_00020021_fill_pattern_4_0: 1680000 rects
-caravel_00020021_fill_pattern_4_0: 1690000 rects
-caravel_00020021_fill_pattern_4_0: 1700000 rects
-caravel_00020021_fill_pattern_4_0: 1710000 rects
-caravel_00020021_fill_pattern_4_0: 1720000 rects
-caravel_00020021_fill_pattern_4_0: 1730000 rects
-caravel_00020021_fill_pattern_4_0: 1740000 rects
-caravel_00020021_fill_pattern_4_0: 1750000 rects
-caravel_00020021_fill_pattern_4_0: 1760000 rects
-caravel_00020021_fill_pattern_4_0: 1770000 rects
-caravel_00020021_fill_pattern_4_0: 1780000 rects
-caravel_00020021_fill_pattern_4_0: 1790000 rects
-caravel_00020021_fill_pattern_4_0: 1800000 rects
-caravel_00020021_fill_pattern_4_0: 1810000 rects
-caravel_00020021_fill_pattern_4_0: 1820000 rects
-caravel_00020021_fill_pattern_4_0: 1830000 rects
-caravel_00020021_fill_pattern_4_0: 1840000 rects
-caravel_00020021_fill_pattern_4_0: 1850000 rects
-caravel_00020021_fill_pattern_4_0: 1860000 rects
-caravel_00020021_fill_pattern_4_0: 1870000 rects
-caravel_00020021_fill_pattern_4_0: 1880000 rects
-caravel_00020021_fill_pattern_4_0: 1890000 rects
-caravel_00020021_fill_pattern_4_0: 1900000 rects
-caravel_00020021_fill_pattern_4_0: 1910000 rects
-caravel_00020021_fill_pattern_4_0: 1920000 rects
-caravel_00020021_fill_pattern_4_0: 1930000 rects
-caravel_00020021_fill_pattern_4_0: 1940000 rects
-caravel_00020021_fill_pattern_4_0: 1950000 rects
-caravel_00020021_fill_pattern_4_0: 1960000 rects
-caravel_00020021_fill_pattern_4_0: 1970000 rects
-caravel_00020021_fill_pattern_4_0: 1980000 rects
-caravel_00020021_fill_pattern_4_0: 1990000 rects
-caravel_00020021_fill_pattern_4_0: 2000000 rects
-caravel_00020021_fill_pattern_4_0: 2010000 rects
-caravel_00020021_fill_pattern_4_0: 2020000 rects
-caravel_00020021_fill_pattern_4_0: 2030000 rects
-caravel_00020021_fill_pattern_4_0: 2040000 rects
-caravel_00020021_fill_pattern_4_0: 2050000 rects
-caravel_00020021_fill_pattern_4_0: 2060000 rects
-caravel_00020021_fill_pattern_4_0: 2070000 rects
-caravel_00020021_fill_pattern_4_0: 2080000 rects
-caravel_00020021_fill_pattern_4_0: 2090000 rects
-caravel_00020021_fill_pattern_4_0: 2100000 rects
-caravel_00020021_fill_pattern_4_0: 2110000 rects
-caravel_00020021_fill_pattern_4_0: 2120000 rects
-caravel_00020021_fill_pattern_4_0: 2130000 rects
-caravel_00020021_fill_pattern_4_0: 2140000 rects
-caravel_00020021_fill_pattern_4_0: 2150000 rects
-caravel_00020021_fill_pattern_4_0: 2160000 rects
-caravel_00020021_fill_pattern_4_0: 2170000 rects
-caravel_00020021_fill_pattern_4_0: 2180000 rects
-caravel_00020021_fill_pattern_4_0: 2190000 rects
-caravel_00020021_fill_pattern_4_0: 2200000 rects
-caravel_00020021_fill_pattern_4_0: 2210000 rects
-caravel_00020021_fill_pattern_4_0: 2220000 rects
-caravel_00020021_fill_pattern_4_0: 2230000 rects
-caravel_00020021_fill_pattern_4_0: 2240000 rects
-caravel_00020021_fill_pattern_4_0: 2250000 rects
-caravel_00020021_fill_pattern_4_0: 2260000 rects
-caravel_00020021_fill_pattern_4_0: 2270000 rects
-caravel_00020021_fill_pattern_4_0: 2280000 rects
-caravel_00020021_fill_pattern_4_0: 2290000 rects
-caravel_00020021_fill_pattern_4_0: 2300000 rects
-caravel_00020021_fill_pattern_4_0: 2310000 rects
-caravel_00020021_fill_pattern_4_0: 2320000 rects
-caravel_00020021_fill_pattern_4_0: 2330000 rects
-caravel_00020021_fill_pattern_4_0: 2340000 rects
-caravel_00020021_fill_pattern_4_0: 2350000 rects
-caravel_00020021_fill_pattern_4_0: 2360000 rects
-caravel_00020021_fill_pattern_4_0: 2370000 rects
-caravel_00020021_fill_pattern_4_0: 2380000 rects
-caravel_00020021_fill_pattern_4_0: 2390000 rects
-caravel_00020021_fill_pattern_4_0: 2400000 rects
-caravel_00020021_fill_pattern_4_0: 2410000 rects
-caravel_00020021_fill_pattern_4_0: 2420000 rects
-caravel_00020021_fill_pattern_4_0: 2430000 rects
-caravel_00020021_fill_pattern_4_0: 2440000 rects
-caravel_00020021_fill_pattern_4_0: 2450000 rects
-caravel_00020021_fill_pattern_4_0: 2460000 rects
-caravel_00020021_fill_pattern_4_0: 2470000 rects
-caravel_00020021_fill_pattern_4_0: 2480000 rects
-caravel_00020021_fill_pattern_4_0: 2490000 rects
-caravel_00020021_fill_pattern_4_0: 2500000 rects
-caravel_00020021_fill_pattern_4_0: 2510000 rects
-caravel_00020021_fill_pattern_4_0: 2520000 rects
-caravel_00020021_fill_pattern_4_0: 2530000 rects
-caravel_00020021_fill_pattern_4_0: 2540000 rects
-caravel_00020021_fill_pattern_4_0: 2550000 rects
-caravel_00020021_fill_pattern_4_0: 2560000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_4_0
-
 Magic 8.3 revision 234 - Compiled on Tue Nov 30 13:45:49 PST 2021.
 Starting magic under Tcl interpreter
 Using the terminal as the console.
@@ -11630,6 +11528,110 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_2_5
 
+caravel_00020021_fill_pattern_4_0: 1560000 rects
+caravel_00020021_fill_pattern_4_0: 1570000 rects
+caravel_00020021_fill_pattern_4_0: 1580000 rects
+caravel_00020021_fill_pattern_4_0: 1590000 rects
+caravel_00020021_fill_pattern_4_0: 1600000 rects
+caravel_00020021_fill_pattern_4_0: 1610000 rects
+caravel_00020021_fill_pattern_4_0: 1620000 rects
+caravel_00020021_fill_pattern_4_0: 1630000 rects
+caravel_00020021_fill_pattern_4_0: 1640000 rects
+caravel_00020021_fill_pattern_4_0: 1650000 rects
+caravel_00020021_fill_pattern_4_0: 1660000 rects
+caravel_00020021_fill_pattern_4_0: 1670000 rects
+caravel_00020021_fill_pattern_4_0: 1680000 rects
+caravel_00020021_fill_pattern_4_0: 1690000 rects
+caravel_00020021_fill_pattern_4_0: 1700000 rects
+caravel_00020021_fill_pattern_4_0: 1710000 rects
+caravel_00020021_fill_pattern_4_0: 1720000 rects
+caravel_00020021_fill_pattern_4_0: 1730000 rects
+caravel_00020021_fill_pattern_4_0: 1740000 rects
+caravel_00020021_fill_pattern_4_0: 1750000 rects
+caravel_00020021_fill_pattern_4_0: 1760000 rects
+caravel_00020021_fill_pattern_4_0: 1770000 rects
+caravel_00020021_fill_pattern_4_0: 1780000 rects
+caravel_00020021_fill_pattern_4_0: 1790000 rects
+caravel_00020021_fill_pattern_4_0: 1800000 rects
+caravel_00020021_fill_pattern_4_0: 1810000 rects
+caravel_00020021_fill_pattern_4_0: 1820000 rects
+caravel_00020021_fill_pattern_4_0: 1830000 rects
+caravel_00020021_fill_pattern_4_0: 1840000 rects
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+caravel_00020021_fill_pattern_4_0: 1860000 rects
+caravel_00020021_fill_pattern_4_0: 1870000 rects
+caravel_00020021_fill_pattern_4_0: 1880000 rects
+caravel_00020021_fill_pattern_4_0: 1890000 rects
+caravel_00020021_fill_pattern_4_0: 1900000 rects
+caravel_00020021_fill_pattern_4_0: 1910000 rects
+caravel_00020021_fill_pattern_4_0: 1920000 rects
+caravel_00020021_fill_pattern_4_0: 1930000 rects
+caravel_00020021_fill_pattern_4_0: 1940000 rects
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+caravel_00020021_fill_pattern_4_0: 1960000 rects
+caravel_00020021_fill_pattern_4_0: 1970000 rects
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+caravel_00020021_fill_pattern_4_0: 1990000 rects
+caravel_00020021_fill_pattern_4_0: 2000000 rects
+caravel_00020021_fill_pattern_4_0: 2010000 rects
+caravel_00020021_fill_pattern_4_0: 2020000 rects
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+caravel_00020021_fill_pattern_4_0: 2040000 rects
+caravel_00020021_fill_pattern_4_0: 2050000 rects
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+caravel_00020021_fill_pattern_4_0: 2070000 rects
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+caravel_00020021_fill_pattern_4_0: 2100000 rects
+caravel_00020021_fill_pattern_4_0: 2110000 rects
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+caravel_00020021_fill_pattern_4_0: 2130000 rects
+caravel_00020021_fill_pattern_4_0: 2140000 rects
+caravel_00020021_fill_pattern_4_0: 2150000 rects
+caravel_00020021_fill_pattern_4_0: 2160000 rects
+caravel_00020021_fill_pattern_4_0: 2170000 rects
+caravel_00020021_fill_pattern_4_0: 2180000 rects
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+caravel_00020021_fill_pattern_4_0: 2200000 rects
+caravel_00020021_fill_pattern_4_0: 2210000 rects
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+caravel_00020021_fill_pattern_4_0: 2260000 rects
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+caravel_00020021_fill_pattern_4_0: 2280000 rects
+caravel_00020021_fill_pattern_4_0: 2290000 rects
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+caravel_00020021_fill_pattern_4_0: 2330000 rects
+caravel_00020021_fill_pattern_4_0: 2340000 rects
+caravel_00020021_fill_pattern_4_0: 2350000 rects
+caravel_00020021_fill_pattern_4_0: 2360000 rects
+caravel_00020021_fill_pattern_4_0: 2370000 rects
+caravel_00020021_fill_pattern_4_0: 2380000 rects
+caravel_00020021_fill_pattern_4_0: 2390000 rects
+caravel_00020021_fill_pattern_4_0: 2400000 rects
+caravel_00020021_fill_pattern_4_0: 2410000 rects
+caravel_00020021_fill_pattern_4_0: 2420000 rects
+caravel_00020021_fill_pattern_4_0: 2430000 rects
+caravel_00020021_fill_pattern_4_0: 2440000 rects
+caravel_00020021_fill_pattern_4_0: 2450000 rects
+caravel_00020021_fill_pattern_4_0: 2460000 rects
+caravel_00020021_fill_pattern_4_0: 2470000 rects
+caravel_00020021_fill_pattern_4_0: 2480000 rects
+caravel_00020021_fill_pattern_4_0: 2490000 rects
+caravel_00020021_fill_pattern_4_0: 2500000 rects
+caravel_00020021_fill_pattern_4_0: 2510000 rects
+caravel_00020021_fill_pattern_4_0: 2520000 rects
+caravel_00020021_fill_pattern_4_0: 2530000 rects
+caravel_00020021_fill_pattern_4_0: 2540000 rects
+caravel_00020021_fill_pattern_4_0: 2550000 rects
+caravel_00020021_fill_pattern_4_0: 2560000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_4_0
+
 caravel_00020021_fill_pattern_4_1: 1560000 rects
 caravel_00020021_fill_pattern_4_1: 1570000 rects
 caravel_00020021_fill_pattern_4_1: 1580000 rects
@@ -11935,91 +11937,6 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_1
 
-caravel_00020021_fill_pattern_1_1: 3240000 rects
-caravel_00020021_fill_pattern_1_1: 3250000 rects
-caravel_00020021_fill_pattern_1_1: 3260000 rects
-caravel_00020021_fill_pattern_1_1: 3270000 rects
-caravel_00020021_fill_pattern_1_1: 3280000 rects
-caravel_00020021_fill_pattern_1_1: 3290000 rects
-caravel_00020021_fill_pattern_1_1: 3300000 rects
-caravel_00020021_fill_pattern_1_1: 3310000 rects
-caravel_00020021_fill_pattern_1_1: 3320000 rects
-caravel_00020021_fill_pattern_1_1: 3330000 rects
-caravel_00020021_fill_pattern_1_1: 3340000 rects
-caravel_00020021_fill_pattern_1_1: 3350000 rects
-caravel_00020021_fill_pattern_1_1: 3360000 rects
-caravel_00020021_fill_pattern_1_1: 3370000 rects
-caravel_00020021_fill_pattern_1_1: 3380000 rects
-caravel_00020021_fill_pattern_1_1: 3390000 rects
-caravel_00020021_fill_pattern_1_1: 3400000 rects
-caravel_00020021_fill_pattern_1_1: 3410000 rects
-caravel_00020021_fill_pattern_1_1: 3420000 rects
-caravel_00020021_fill_pattern_1_1: 3430000 rects
-caravel_00020021_fill_pattern_1_1: 3440000 rects
-caravel_00020021_fill_pattern_1_1: 3450000 rects
-caravel_00020021_fill_pattern_1_1: 3460000 rects
-caravel_00020021_fill_pattern_1_1: 3470000 rects
-caravel_00020021_fill_pattern_1_1: 3480000 rects
-caravel_00020021_fill_pattern_1_1: 3490000 rects
-caravel_00020021_fill_pattern_1_1: 3500000 rects
-caravel_00020021_fill_pattern_1_1: 3510000 rects
-caravel_00020021_fill_pattern_1_1: 3520000 rects
-caravel_00020021_fill_pattern_1_1: 3530000 rects
-caravel_00020021_fill_pattern_1_1: 3540000 rects
-caravel_00020021_fill_pattern_1_1: 3550000 rects
-caravel_00020021_fill_pattern_1_1: 3560000 rects
-caravel_00020021_fill_pattern_1_1: 3570000 rects
-caravel_00020021_fill_pattern_1_1: 3580000 rects
-caravel_00020021_fill_pattern_1_1: 3590000 rects
-caravel_00020021_fill_pattern_1_1: 3600000 rects
-caravel_00020021_fill_pattern_1_1: 3610000 rects
-caravel_00020021_fill_pattern_1_1: 3620000 rects
-caravel_00020021_fill_pattern_1_1: 3630000 rects
-caravel_00020021_fill_pattern_1_1: 3640000 rects
-caravel_00020021_fill_pattern_1_1: 3650000 rects
-caravel_00020021_fill_pattern_1_1: 3660000 rects
-caravel_00020021_fill_pattern_1_1: 3670000 rects
-caravel_00020021_fill_pattern_1_1: 3680000 rects
-caravel_00020021_fill_pattern_1_1: 3690000 rects
-caravel_00020021_fill_pattern_1_1: 3700000 rects
-caravel_00020021_fill_pattern_1_1: 3710000 rects
-caravel_00020021_fill_pattern_1_1: 3720000 rects
-caravel_00020021_fill_pattern_1_1: 3730000 rects
-caravel_00020021_fill_pattern_1_1: 3740000 rects
-caravel_00020021_fill_pattern_1_1: 3750000 rects
-caravel_00020021_fill_pattern_1_1: 3760000 rects
-caravel_00020021_fill_pattern_1_1: 3770000 rects
-caravel_00020021_fill_pattern_1_1: 3780000 rects
-caravel_00020021_fill_pattern_1_1: 3790000 rects
-caravel_00020021_fill_pattern_1_1: 3800000 rects
-caravel_00020021_fill_pattern_1_1: 3810000 rects
-caravel_00020021_fill_pattern_1_1: 3820000 rects
-caravel_00020021_fill_pattern_1_1: 3830000 rects
-caravel_00020021_fill_pattern_1_1: 3840000 rects
-caravel_00020021_fill_pattern_1_1: 3850000 rects
-caravel_00020021_fill_pattern_1_1: 3860000 rects
-caravel_00020021_fill_pattern_1_1: 3870000 rects
-caravel_00020021_fill_pattern_1_1: 3880000 rects
-caravel_00020021_fill_pattern_1_1: 3890000 rects
-caravel_00020021_fill_pattern_1_1: 3900000 rects
-caravel_00020021_fill_pattern_1_1: 3910000 rects
-caravel_00020021_fill_pattern_1_1: 3920000 rects
-caravel_00020021_fill_pattern_1_1: 3930000 rects
-caravel_00020021_fill_pattern_1_1: 3940000 rects
-caravel_00020021_fill_pattern_1_1: 3950000 rects
-caravel_00020021_fill_pattern_1_1: 3960000 rects
-caravel_00020021_fill_pattern_1_1: 3970000 rects
-caravel_00020021_fill_pattern_1_1: 3980000 rects
-caravel_00020021_fill_pattern_1_1: 3990000 rects
-caravel_00020021_fill_pattern_1_1: 4000000 rects
-caravel_00020021_fill_pattern_1_1: 4010000 rects
-caravel_00020021_fill_pattern_1_1: 4020000 rects
-caravel_00020021_fill_pattern_1_1: 4030000 rects
-caravel_00020021_fill_pattern_1_1: 4040000 rects
-caravel_00020021_fill_pattern_1_1: 4050000 rects
-CIF output style is now "wafflefill(tiled)"
-   Generating output for cell caravel_00020021_fill_pattern_1_1
-
 caravel_00020021_fill_pattern_0_0: 4920000 rects
 caravel_00020021_fill_pattern_0_0: 4930000 rects
 caravel_00020021_fill_pattern_0_0: 4940000 rects
@@ -12154,6 +12071,90 @@
 CIF output style is now "wafflefill(tiled)"
    Generating output for cell caravel_00020021_fill_pattern_0_0
 
+caravel_00020021_fill_pattern_1_1: 3240000 rects
+caravel_00020021_fill_pattern_1_1: 3250000 rects
+caravel_00020021_fill_pattern_1_1: 3260000 rects
+caravel_00020021_fill_pattern_1_1: 3270000 rects
+caravel_00020021_fill_pattern_1_1: 3280000 rects
+caravel_00020021_fill_pattern_1_1: 3290000 rects
+caravel_00020021_fill_pattern_1_1: 3300000 rects
+caravel_00020021_fill_pattern_1_1: 3310000 rects
+caravel_00020021_fill_pattern_1_1: 3320000 rects
+caravel_00020021_fill_pattern_1_1: 3330000 rects
+caravel_00020021_fill_pattern_1_1: 3340000 rects
+caravel_00020021_fill_pattern_1_1: 3350000 rects
+caravel_00020021_fill_pattern_1_1: 3360000 rects
+caravel_00020021_fill_pattern_1_1: 3370000 rects
+caravel_00020021_fill_pattern_1_1: 3380000 rects
+caravel_00020021_fill_pattern_1_1: 3390000 rects
+caravel_00020021_fill_pattern_1_1: 3400000 rects
+caravel_00020021_fill_pattern_1_1: 3410000 rects
+caravel_00020021_fill_pattern_1_1: 3420000 rects
+caravel_00020021_fill_pattern_1_1: 3430000 rects
+caravel_00020021_fill_pattern_1_1: 3440000 rects
+caravel_00020021_fill_pattern_1_1: 3450000 rects
+caravel_00020021_fill_pattern_1_1: 3460000 rects
+caravel_00020021_fill_pattern_1_1: 3470000 rects
+caravel_00020021_fill_pattern_1_1: 3480000 rects
+caravel_00020021_fill_pattern_1_1: 3490000 rects
+caravel_00020021_fill_pattern_1_1: 3500000 rects
+caravel_00020021_fill_pattern_1_1: 3510000 rects
+caravel_00020021_fill_pattern_1_1: 3520000 rects
+caravel_00020021_fill_pattern_1_1: 3530000 rects
+caravel_00020021_fill_pattern_1_1: 3540000 rects
+caravel_00020021_fill_pattern_1_1: 3550000 rects
+caravel_00020021_fill_pattern_1_1: 3560000 rects
+caravel_00020021_fill_pattern_1_1: 3570000 rects
+caravel_00020021_fill_pattern_1_1: 3580000 rects
+caravel_00020021_fill_pattern_1_1: 3590000 rects
+caravel_00020021_fill_pattern_1_1: 3600000 rects
+caravel_00020021_fill_pattern_1_1: 3610000 rects
+caravel_00020021_fill_pattern_1_1: 3620000 rects
+caravel_00020021_fill_pattern_1_1: 3630000 rects
+caravel_00020021_fill_pattern_1_1: 3640000 rects
+caravel_00020021_fill_pattern_1_1: 3650000 rects
+caravel_00020021_fill_pattern_1_1: 3660000 rects
+caravel_00020021_fill_pattern_1_1: 3670000 rects
+caravel_00020021_fill_pattern_1_1: 3680000 rects
+caravel_00020021_fill_pattern_1_1: 3690000 rects
+caravel_00020021_fill_pattern_1_1: 3700000 rects
+caravel_00020021_fill_pattern_1_1: 3710000 rects
+caravel_00020021_fill_pattern_1_1: 3720000 rects
+caravel_00020021_fill_pattern_1_1: 3730000 rects
+caravel_00020021_fill_pattern_1_1: 3740000 rects
+caravel_00020021_fill_pattern_1_1: 3750000 rects
+caravel_00020021_fill_pattern_1_1: 3760000 rects
+caravel_00020021_fill_pattern_1_1: 3770000 rects
+caravel_00020021_fill_pattern_1_1: 3780000 rects
+caravel_00020021_fill_pattern_1_1: 3790000 rects
+caravel_00020021_fill_pattern_1_1: 3800000 rects
+caravel_00020021_fill_pattern_1_1: 3810000 rects
+caravel_00020021_fill_pattern_1_1: 3820000 rects
+caravel_00020021_fill_pattern_1_1: 3830000 rects
+caravel_00020021_fill_pattern_1_1: 3840000 rects
+caravel_00020021_fill_pattern_1_1: 3850000 rects
+caravel_00020021_fill_pattern_1_1: 3860000 rects
+caravel_00020021_fill_pattern_1_1: 3870000 rects
+caravel_00020021_fill_pattern_1_1: 3880000 rects
+caravel_00020021_fill_pattern_1_1: 3890000 rects
+caravel_00020021_fill_pattern_1_1: 3900000 rects
+caravel_00020021_fill_pattern_1_1: 3910000 rects
+caravel_00020021_fill_pattern_1_1: 3920000 rects
+caravel_00020021_fill_pattern_1_1: 3930000 rects
+caravel_00020021_fill_pattern_1_1: 3940000 rects
+caravel_00020021_fill_pattern_1_1: 3950000 rects
+caravel_00020021_fill_pattern_1_1: 3960000 rects
+caravel_00020021_fill_pattern_1_1: 3970000 rects
+caravel_00020021_fill_pattern_1_1: 3980000 rects
+caravel_00020021_fill_pattern_1_1: 3990000 rects
+caravel_00020021_fill_pattern_1_1: 4000000 rects
+caravel_00020021_fill_pattern_1_1: 4010000 rects
+caravel_00020021_fill_pattern_1_1: 4020000 rects
+caravel_00020021_fill_pattern_1_1: 4030000 rects
+caravel_00020021_fill_pattern_1_1: 4040000 rects
+CIF output style is now "wafflefill(tiled)"
+   Generating output for cell caravel_00020021_fill_pattern_1_1
+
 caravel_00020021_fill_pattern_3_1: 3240000 rects
 caravel_00020021_fill_pattern_3_1: 3250000 rects
 caravel_00020021_fill_pattern_3_1: 3260000 rects
@@ -12747,7 +12748,7 @@
 -------------------------------------------------------------------------------------------
 {{ STEP 3 }} fill generated for mpw-two, slot-033 : digital_pll
 -------------------------------------------------------------------------------------------
-okfatal: ambiguous argument 'develop': unknown revision or path not in the working tree.
+okfatal: ambiguous argument 'main': unknown revision or path not in the working tree.
 Use '--' to separate paths from revisions, like this:
 'git <command> [<revision>...] -- [<file>...]'
 USER_ID is set to 00020021
@@ -12987,35 +12988,35 @@
 Reading "sky130_fd_sc_hd__o2bb2ai_2".
 Reading "sky130_fd_sc_hd__dfrtp_2".
 Reading "sky130_fd_sc_hd__mux2_1".
-Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
-Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__buf_1".
 Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
 Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
 Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__clkbuf_2".
 Reading "sky130_fd_sc_hd__clkinv_2".
 Reading "sky130_fd_sc_hd__clkinv_4".
-Reading "sky130_fd_sc_hd__buf_12".
-Reading "sky130_fd_sc_hd__clkbuf_16".
-Reading "sky130_fd_sc_hd__clkbuf_2".
-Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__and2_1".
-Reading "sky130_fd_sc_hd__clkbuf_1".
-Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__nand2_1".
 Reading "sky130_fd_sc_hd__diode_2".
 Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
 Reading "sky130_fd_sc_hd__mux2_2".
 Reading "sky130_fd_sc_hd__decap_8".
-Reading "sky130_fd_sc_hd__nand2_2".
-Reading "sky130_fd_sc_hd__inv_2".
-Reading "sky130_fd_sc_hd__decap_6".
-Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__conb_1".
 Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
 Reading "sky130_fd_sc_hd__decap_3".
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
-Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__inv_2".
 Reading "caravel_clocking".
 Reading "sky130_fd_sc_hd__o2111ai_2".
 Reading "sky130_fd_sc_hd__and4_2".
@@ -13037,6 +13038,7 @@
 Reading "sky130_fd_sc_hd__or3_2".
 Reading "sky130_fd_sc_hd__or2_2".
 Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_1".
 Reading "sky130_fd_sc_hd__einvn_8".
 Reading "sky130_fd_sc_hd__einvn_4".
@@ -13050,11 +13052,16 @@
 Reading "sky130_fd_sc_hd__a311o_2".
 Reading "sky130_fd_sc_hd__a21oi_2".
 Reading "sky130_fd_sc_hd__a22oi_2".
-Reading "sky130_fd_sc_hd__einvp_2".
 Reading "sky130_fd_sc_hd__clkinv_8".
 Reading "sky130_fd_sc_hd__nor2_2".
 Reading "digital_pll".
 Reading "sky130_fd_sc_hd__ebufn_8".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfbbn_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__einvp_8".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
 Reading "sky130_fd_sc_hd__a221o_1".
 Reading "sky130_fd_sc_hd__or4bb_1".
 Reading "sky130_fd_sc_hd__or4b_1".
@@ -13092,7 +13099,6 @@
 Reading "sky130_fd_sc_hd__a32o_1".
 Reading "sky130_fd_sc_hd__ebufn_2".
 Reading "sky130_fd_sc_hd__or3b_2".
-Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__a22oi_1".
 Reading "sky130_fd_sc_hd__mux2_4".
 Reading "sky130_fd_sc_hd__a41o_1".
@@ -13131,15 +13137,14 @@
 Reading "sky130_fd_sc_hd__o21ai_4".
 Reading "sky130_fd_sc_hd__nor2_8".
 Reading "sky130_fd_sc_hd__a31oi_1".
-Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
 Reading "sky130_fd_sc_hd__inv_12".
 Reading "sky130_fd_sc_hd__and2b_1".
 Reading "sky130_fd_sc_hd__buf_8".
-Reading "sky130_fd_sc_hd__buf_6".
 Reading "sky130_fd_sc_hd__nand2_8".
 Reading "sky130_fd_sc_hd__nand2_4".
-Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__inv_6".
 Reading "sky130_fd_sc_hd__inv_8".
 Reading "housekeeping".
 Reading "R2_sky130_fd_sc_hd__decap_3".
@@ -13153,10 +13158,6 @@
 Reading "R2_sky130_fd_sc_hd__decap_12".
 Reading "user_id_programming".
 Reading "gpio_defaults_block_1803".
-Reading "sky130_fd_sc_hd__dfbbn_1".
-Reading "sky130_fd_sc_hd__ebufn_1".
-Reading "gpio_logic_high".
-Reading "gpio_control_block".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
 Reading "DN_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
 Reading "DN_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
@@ -13554,10 +13555,10 @@
 Reading "RO_sky130_fd_sc_hd__o211a_4".
 Reading "RO_mgmt_core".
 Reading "mgmt_core_wrapper".
-Reading "gpio_defaults_block_1800".
-Reading "sky130_fd_sc_hd__einvp_4".
-Reading "sky130_fd_sc_hd__einvp_8".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__clkinv_16".
 Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__inv_16".
 Reading "sky130_fd_sc_hvl__conb_1".
 Reading "mgmt_protect_hv".
 Reading "mprj_logic_high".
@@ -14401,31 +14402,32 @@
 -------------------------------------------------------------------------------------------
 {{ STEP 4 }} final gds generated for mpw-two, slot-033 : digital_pll
 -------------------------------------------------------------------------------------------
-ok[main 653836f] final gds oasis
+ok[main 2c490d5] final gds oasis
  2 files changed, 1 insertion(+), 1 deletion(-)
+ create mode 100644 oas/caravel_00020021.oas
 To https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-033.git
-   1bffef7..653836f  HEAD -> main
+   0cedcb9..2c490d5  HEAD -> main
 -------------------------------------------------------------------------------------------
 {{ STEP 6 }} fom & met density checks mpw-two, slot-033 : digital_pll
 -------------------------------------------------------------------------------------------
 {{ MET CHECK }} running met density check () for mpw-two, slot-033 : digital_pll
-li1_ca_density is 0.41448697125274425
-m1_ca_density is 0.4833115000296718
-m2_ca_density is 0.49920066775106575
-m3_ca_density is 0.5019354093683188
-m4_ca_density is 0.46719819443787947
+li1_ca_density is 0.41450053586121505
+m1_ca_density is 0.4833446104386373
+m2_ca_density is 0.49940206051230907
+m3_ca_density is 0.5019467057040085
+m4_ca_density is 0.4672035866738671
 m5_ca_density is 0.415957475199362
 ok{{ FOM CHECK }} running FOM check (70) for mpw-two, slot-033 : digital_pll
-fom_density.drc:: sourcing design file=./gds/caravel_00020021.gds topcell=caravel_00020021 ...
+fom_density.drc:: sourcing design file=./oas/caravel_00020021.oas topcell=caravel_00020021 ...
 done.
 flattening chip boundary...
 done.
 step size = 70.0
-llx=5.965 lly=6.0 urx=3594.035 ury=5194.0
+llx=5.964999999999999 lly=5.999999999999999 urx=3594.0349999999994 ury=5193.999999999999
 x_cnt = 51
 y_cnt = 74
-dbu = 0.001
-bbox_area = 18614907.16
+dbu = 0.0009999999999999998
+bbox_area = 18614907.159999993
 calculating subtile areas (= 3774)...
 tiles per step = 10
 calculating window step densities (= 2730)...
@@ -14488,6 +14490,18 @@
 gds/caravel_00020021_fill_pattern.gds.gz -> gds/caravel_00020021_fill_pattern.gds.gz.00.split gds/caravel_00020021_fill_pattern.gds.gz.01.split gds/caravel_00020021_fill_pattern.gds.gz.02.split gds/caravel_00020021_fill_pattern.gds.gz.03.split gds/caravel_00020021_fill_pattern.gds.gz.04.split
 gds/caravel_00020021.area0.gds.gz -> gds/caravel_00020021.area0.gds.gz.00.split gds/caravel_00020021.area0.gds.gz.01.split gds/caravel_00020021.area0.gds.gz.02.split gds/caravel_00020021.area0.gds.gz.03.split gds/caravel_00020021.area0.gds.gz.04.split
 Files larger than 100 MBytes are compressed!
+warning: You ran 'git add' with neither '-A (--all)' or '--ignore-removal',
+whose behaviour will change in Git 2.0 with respect to paths you removed.
+Paths like 'mag/gpio_defaults_block_1800.mag' that are
+removed from your working tree are ignored with this version of Git.
+
+* 'git add --ignore-removal <pathspec>', which is the current default,
+  ignores paths you removed from your working tree.
+
+* 'git add --all <pathspec>' will let you also record the removals.
+
+Run 'git status' to check the paths you removed from your working tree.
+
 fatal: pathspec 'maglef' did not match any files
 -------------------------------------------------------------------------------------------
 {{ STEP 8 }} pushing tapeout updates to shuttle-repo for mpw-two, slot-033 : digital_pll
diff --git a/signoff/versions b/signoff/versions
index a33861b..d2f5d39 100644
--- a/signoff/versions
+++ b/signoff/versions
@@ -1,20 +1,20 @@
 ------------------------------------
-make_ship: Fri Dec 10 00:24:11 UTC 2021
-make_ship: caravel = commit develop
+make_ship: Mon Dec 27 07:48:26 UTC 2021
+make_ship: caravel = commit main
 make_ship: magic = 8.3.234
 make_ship: sky130A tech = version 1.0.250-1-g89f6ff4
 make_ship: open_pdks = 1.0.251
 make_ship: klayout = KLayout 0.27.3
 ------------------------------------
-generate_fill: Fri Dec 10 00:24:58 UTC 2021
-generate_fill: caravel = commit develop
+generate_fill: Mon Dec 27 07:49:19 UTC 2021
+generate_fill: caravel = commit main
 generate_fill: magic = 8.3.234
 generate_fill: sky130A tech = version 1.0.250-1-g89f6ff4
 generate_fill: open_pdks = 1.0.251
 generate_fill: klayout = KLayout 0.27.3
 ------------------------------------
-make_final: Fri Dec 10 00:42:21 UTC 2021
-make_final: caravel = commit develop
+make_final: Mon Dec 27 08:17:04 UTC 2021
+make_final: caravel = commit main
 make_final: magic = 8.3.234
 make_final: sky130A tech = version 1.0.250-1-g89f6ff4
 make_final: open_pdks = 1.0.251
diff --git a/verilog/gl/caravan.v b/verilog/gl/caravan.v
index bd4d4df..c7e19ad 100644
--- a/verilog/gl/caravan.v
+++ b/verilog/gl/caravan.v
@@ -2703,27 +2703,27 @@
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_10 (
+  gpio_defaults_block_0403 gpio_defaults_block_10 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_11 (
+  gpio_defaults_block_0403 gpio_defaults_block_11 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_12 (
+  gpio_defaults_block_0403 gpio_defaults_block_12 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_13 (
+  gpio_defaults_block_0403 gpio_defaults_block_13 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_14 (
+  gpio_defaults_block_0403 gpio_defaults_block_14 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
@@ -2743,87 +2743,87 @@
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_26 (
+  gpio_defaults_block_0403 gpio_defaults_block_26 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_27 (
+  gpio_defaults_block_0403 gpio_defaults_block_27 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_28 (
+  gpio_defaults_block_0403 gpio_defaults_block_28 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_29 (
+  gpio_defaults_block_0403 gpio_defaults_block_29 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_30 (
+  gpio_defaults_block_0403 gpio_defaults_block_30 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_31 (
+  gpio_defaults_block_0403 gpio_defaults_block_31 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_32 (
+  gpio_defaults_block_0403 gpio_defaults_block_32 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_33 (
+  gpio_defaults_block_0403 gpio_defaults_block_33 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_34 (
+  gpio_defaults_block_0403 gpio_defaults_block_34 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_35 (
+  gpio_defaults_block_0403 gpio_defaults_block_35 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_36 (
+  gpio_defaults_block_0403 gpio_defaults_block_36 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_37 (
+  gpio_defaults_block_0403 gpio_defaults_block_37 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_5 (
+  gpio_defaults_block_0403 gpio_defaults_block_5 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_6 (
+  gpio_defaults_block_0403 gpio_defaults_block_6 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_7 (
+  gpio_defaults_block_0403 gpio_defaults_block_7 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_8 (
+  gpio_defaults_block_0403 gpio_defaults_block_8 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_9 (
+  gpio_defaults_block_0403 gpio_defaults_block_9 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })
diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v
index 91ae7a2..899c692 100644
--- a/verilog/gl/caravel.v
+++ b/verilog/gl/caravel.v
@@ -3001,67 +3001,67 @@
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_10 (
+  gpio_defaults_block_0403 gpio_defaults_block_10 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_11 (
+  gpio_defaults_block_0403 gpio_defaults_block_11 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_12 (
+  gpio_defaults_block_0403 gpio_defaults_block_12 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_13 (
+  gpio_defaults_block_0403 gpio_defaults_block_13 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_14 (
+  gpio_defaults_block_0403 gpio_defaults_block_14 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_15 (
+  gpio_defaults_block_0403 gpio_defaults_block_15 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_16 (
+  gpio_defaults_block_0403 gpio_defaults_block_16 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_17 (
+  gpio_defaults_block_0403 gpio_defaults_block_17 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_18 (
+  gpio_defaults_block_0403 gpio_defaults_block_18 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_19 (
+  gpio_defaults_block_0403 gpio_defaults_block_19 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_20 (
+  gpio_defaults_block_0403 gpio_defaults_block_20 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_21 (
+  gpio_defaults_block_0403 gpio_defaults_block_21 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_22 (
+  gpio_defaults_block_0403 gpio_defaults_block_22 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286]  })
@@ -3081,102 +3081,102 @@
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_23 (
+  gpio_defaults_block_0403 gpio_defaults_block_23 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_24 (
+  gpio_defaults_block_0403 gpio_defaults_block_24 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_25 (
+  gpio_defaults_block_0403 gpio_defaults_block_25 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_26 (
+  gpio_defaults_block_0403 gpio_defaults_block_26 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_27 (
+  gpio_defaults_block_0403 gpio_defaults_block_27 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_28 (
+  gpio_defaults_block_0403 gpio_defaults_block_28 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_29 (
+  gpio_defaults_block_0403 gpio_defaults_block_29 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_30 (
+  gpio_defaults_block_0403 gpio_defaults_block_30 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_31 (
+  gpio_defaults_block_0403 gpio_defaults_block_31 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_32 (
+  gpio_defaults_block_0403 gpio_defaults_block_32 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_33 (
+  gpio_defaults_block_0403 gpio_defaults_block_33 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_34 (
+  gpio_defaults_block_0403 gpio_defaults_block_34 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_35 (
+  gpio_defaults_block_0403 gpio_defaults_block_35 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_36 (
+  gpio_defaults_block_0403 gpio_defaults_block_36 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_37 (
+  gpio_defaults_block_0403 gpio_defaults_block_37 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_5 (
+  gpio_defaults_block_0403 gpio_defaults_block_5 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_6 (
+  gpio_defaults_block_0403 gpio_defaults_block_6 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_7 (
+  gpio_defaults_block_0403 gpio_defaults_block_7 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_8 (
+  gpio_defaults_block_0403 gpio_defaults_block_8 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104]  })
   );
-  gpio_defaults_block_1800 gpio_defaults_block_9 (
+  gpio_defaults_block_0403 gpio_defaults_block_9 (
     .VGND(vssd_core),
     .VPWR(vccd_core),
     .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117]  })