)]}'
{
  "commit": "694bfd3c5ee03d3716541b7b55bcd5fc13343bfd",
  "tree": "455cd31c435b60209c3d823b7e7777bb2b17e3bb",
  "parents": [
    "599c0a77f2a8c40dbccdd604ea3ce08f2f8dc0a8"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Apr 23 10:55:41 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Apr 23 10:55:41 2021 -0400"
  },
  "message": "Added the 3 user IRQ lines to the project wrapper and zeroed them\nin the project example RTL.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "774121074abe9f4d81da64ec91427412623cca6c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "177a73332bf39136a76a8fb3bc7168bbcee5b9d8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    },
    {
      "type": "modify",
      "old_id": "95cad71fdd19fb6e691c7eb104a6a59ea0c667b6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "17c25111b40caf9fa07516d8f536f84a568a2888",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}