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"094eb763b3d4947b8b21d9e8f78874610932d52f", "parents": [ "dba051e726bcb22cdf4106c3bd1fe34450daf44c" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Fri May 07 09:52:15 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Fri May 07 09:52:15 2021 -0400" }, "message": "Corrected ngspice testbenches for change in the name of the parameter\nto turn on/off the mismatch parameters. Restored the boundary layer\nto the example user project layout, moved the boundary layer origin\nand everything else to the grid origin, and rewrote GDS for the\nexample project.\n" }, { "commit": "dba051e726bcb22cdf4106c3bd1fe34450daf44c", "tree": "443918287b0e0c7c99602cf7bb016d5ec6057fbe", "parents": [ "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 15:14:34 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 15:14:34 2021 -0400" }, "message": "Modifications to the wrapper testbench schematic (not quite working\nyet, though).\n" }, { "commit": "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7", "tree": "3839b58f5e7c2df6cc3bd737b04f59502d7460f7", "parents": [ "a26abdd4844c5057f87540780fca689753eab258" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 11:54:28 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 11:54:28 2021 -0400" }, "message": "Added xschem schematic and symbol for the analog project wrapper, and a\nscript to run netgen LVS against the schematic.\n" }, { "commit": "a26abdd4844c5057f87540780fca689753eab258", "tree": "42b93d7a3efde5537294072381345123dc788437", "parents": [ "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 10:36:21 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu May 06 10:36:21 2021 -0400" }, "message": "Redid the layout for the example analog project based on the updated\nwrapper layout. Generated GDS and extracted netlist.\n" }, { "commit": "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb", "tree": "1be4834144cc29e3d384574a65e161f8170a7030", "parents": [ "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f" ], "author": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Wed May 05 23:41:20 2021 +0200" }, "committer": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Wed May 05 23:41:20 2021 +0200" }, "message": "Update Makefile\n" }, { "commit": "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f", "tree": "28e86ff15d3d9c7b7135dcfd185dff90696809fa", "parents": [ "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 21:56:02 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 21:56:02 2021 -0400" }, "message": "Corrected the info.yaml file to point to the caravan.v file as the\ntop level netlist.\n" }, { "commit": "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b", "tree": "dfcc6d0c729180e17ff87abb94ec7c61109d6b64", "parents": [ "5ea70cb2ca8bfa33e4a4d4356799e2baf73a6400" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 17:19:26 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 17:19:26 2021 -0400" }, "message": "Added layout for the user_analog_project_wrapper example.\n" }, { "commit": "5ea70cb2ca8bfa33e4a4d4356799e2baf73a6400", "tree": "9fb9c7308b25d4c57b035e6b150c5140629bee98", "parents": [ "796099ed315805cfb93927d461c2a3f987660daa" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:40:10 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:40:10 2021 -0400" }, "message": "Changed the schematics so that the resistor does not set a W\nvalue, but the underlying model does anyway so this has no effect\non the LVS, which still flags property errors.\n" }, { "commit": "796099ed315805cfb93927d461c2a3f987660daa", "tree": "a8daa2bef539b81d4dcd68725ac203fd681f8f4f", "parents": [ "dfc24ad0d2edaec6065144b7e2600c8d02bdd592" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:30:42 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:30:42 2021 -0400" }, "message": "Corrected the schematic for the proper orientation of the topmost\ncapacitor; the circuit now passes LVS.\n" }, { "commit": "dfc24ad0d2edaec6065144b7e2600c8d02bdd592", "tree": "ab3abe59c6d04da54485c3087f85db84355b1ec6", "parents": [ "fb1300105269c80e54ebc41efd883396ddbc382f" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:18:51 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Thu Apr 29 16:18:51 2021 -0400" }, "message": "Added xschem schematic of the POR and testbench simulations and\nresults.\n" }, { "commit": "fb1300105269c80e54ebc41efd883396ddbc382f", "tree": "9508e96380dc29acf6a6c46fad52e5ce171d0bed", "parents": [ "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Wed Apr 28 14:08:25 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Wed Apr 28 14:08:25 2021 -0400" }, "message": "Simple layout, unwired (needs modifications to the project wrapper)\n" }, { "commit": "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0", "tree": "f283a100f106709d046072587377dee6e5656f78", "parents": [ "6af7408dc6bbf5dde440266476933cebd69f3ba7" ], "author": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Wed Apr 28 14:05:41 2021 -0400" }, "committer": { "name": "Tim Edwards", "email": "tim@opencircuitdesign.com", "time": "Wed Apr 28 14:05:41 2021 -0400" }, "message": "Preliminary work on the analog user project example. Added verilog RTL and\ntestbench. The design passes the testbench.\n" }, { "commit": "6af7408dc6bbf5dde440266476933cebd69f3ba7", "tree": "c6e60b12e76336e2f23956900965769c1215ade5", "parents": [], "author": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Mon Apr 26 14:56:35 2021 +0200" }, "committer": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Mon Apr 26 14:56:35 2021 +0200" }, "message": "Initial commit\n" } ] }