Add schematics and layputs of PLL v1.

commit: b038f199accb0941e47d4617a8c08d4ce7db53a2 [log] [tgz]
author: Diego Hernando <djhernando96@gmail.com> Fri Jun 18 01:26:40 2021 -0300
committer: Diego Hernando <djhernando96@gmail.com> Fri Jun 18 01:26:40 2021 -0300
tree: b821a1e824328df82f6d4efde5a129fee3e40f25
parent: 67640ef400d8df3cfb0a49c79a3b7e14136869b5 [diff]
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..19e5b0a
--- /dev/null
+++ b/.gitignore

@@ -0,0 +1,16 @@
+# De ser necesario se pueden incluir con git add --force archivo-a-NO-ignorar
+
+#Archivos de extraccion con magic
+*.ext
+*.sim
+*.nodes
+
+#Archivos de logueo en general
+*.log
+
+#Salida de comparaciones LVS
+*.out
+
+#Archivos con resultados numericos de simulacion
+*.raw
+

diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 6c15cc7..60be86d 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ

diff --git a/mag/DFlipFlop.mag b/mag/DFlipFlop.mag
new file mode 100644
index 0000000..836e57a
--- /dev/null
+++ b/mag/DFlipFlop.mag

@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623898709
+<< nwell >>
+rect 559 2292 1181 3068
+rect 559 0 1181 776
+<< pwell >>
+rect 559 1729 1740 2292
+rect 460 1400 1740 1729
+rect 559 776 1740 1400
+<< psubdiff >>
+rect 433 2222 654 2256
+rect 489 1718 1242 1752
+rect 487 1316 1249 1350
+rect 1000 812 1307 846
+<< poly >>
+rect 741 2104 1000 2170
+rect 740 898 999 964
+<< locali >>
+rect 433 2222 462 2256
+rect 556 2222 654 2256
+rect 483 1718 1265 1752
+rect 489 1316 1256 1350
+rect 1028 812 1205 846
+rect 1299 812 1310 846
+<< viali >>
+rect 462 2222 556 2256
+rect 1205 812 1299 846
+<< metal1 >>
+rect 523 3027 1200 3038
+rect 523 2998 1253 3027
+rect -1244 2944 1740 2998
+rect 523 2940 1195 2944
+rect 523 2904 1198 2940
+rect -131 2240 -121 2344
+rect 450 2256 596 2262
+rect 450 2222 462 2256
+rect 556 2222 596 2256
+rect 450 2216 596 2222
+rect 219 1802 229 1854
+rect 361 1814 371 1854
+rect 361 1802 373 1814
+rect 1393 1811 1403 1863
+rect 1486 1811 1496 1863
+rect 587 1712 636 1758
+rect -1244 1498 69 1570
+rect 1105 1310 1167 1356
+rect 219 1254 231 1266
+rect 221 1214 231 1254
+rect 361 1254 373 1266
+rect 361 1214 371 1254
+rect 1392 1208 1402 1260
+rect 1486 1208 1496 1260
+rect 1157 846 1311 852
+rect -91 724 -81 828
+rect 1157 812 1205 846
+rect 1299 812 1311 846
+rect 1157 806 1311 812
+rect 559 124 1181 164
+rect -1244 70 1740 124
+rect 559 30 1181 70
+<< via1 >>
+rect -190 2240 -131 2344
+rect 229 1802 361 1854
+rect 1403 1811 1486 1863
+rect 231 1214 361 1266
+rect 1402 1208 1486 1260
+rect -150 724 -91 828
+<< metal2 >>
+rect -190 2344 -131 2354
+rect -131 2266 40 2318
+rect -190 2230 -131 2240
+rect -12 1854 40 2266
+rect 1521 2258 1577 2369
+rect 229 1854 361 1864
+rect -12 1802 229 1854
+rect 229 1792 361 1802
+rect 1403 1863 1486 1873
+rect 1403 1801 1486 1811
+rect 373 1748 429 1758
+rect 1413 1722 1473 1801
+rect 429 1662 1473 1722
+rect 373 1626 429 1636
+rect 163 1432 219 1442
+rect 219 1346 1473 1406
+rect 163 1310 219 1320
+rect 231 1266 361 1276
+rect 1413 1270 1473 1346
+rect -12 1214 231 1266
+rect -150 828 -91 838
+rect -12 802 40 1214
+rect 231 1204 361 1214
+rect 1402 1260 1486 1270
+rect 1402 1198 1486 1208
+rect -91 750 40 802
+rect -150 714 -91 724
+rect 1311 699 1367 810
+<< via2 >>
+rect 373 1636 429 1748
+rect 163 1320 219 1432
+<< metal3 >>
+rect -997 804 -937 2264
+rect 363 1748 439 1753
+rect 363 1636 373 1748
+rect 429 1636 439 1748
+rect 363 1631 439 1636
+rect 153 1432 229 1437
+rect 153 1320 163 1432
+rect 219 1320 229 1432
+rect 153 1315 229 1320
+use clock_inverter  clock_inverter_0
+timestamp 1623799048
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
+use latch_diff  latch_diff_1
+timestamp 1623798783
+transform -1 0 1707 0 -1 2352
+box -33 -716 1147 2352
+use latch_diff  latch_diff_0
+timestamp 1623798783
+transform 1 0 33 0 1 716
+box -33 -716 1147 2352
+<< labels >>
+rlabel metal1 -1244 1498 69 1570 1 vss
+rlabel metal1 -1244 2944 1740 2998 1 vdd
+rlabel metal3 -997 1498 -937 1570 1 D
+rlabel poly 740 898 999 964 1 CLK
+rlabel poly 741 2104 1000 2170 1 nCLK
+rlabel metal2 1311 699 1367 810 1 nQ
+rlabel metal2 1521 2258 1577 2369 1 Q
+<< end >>

diff --git a/mag/example_por.mag b/mag/Old/example_por.mag
similarity index 100%
rename from mag/example_por.mag
rename to mag/Old/example_por.mag


diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag b/mag/Old/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag
rename to mag/Old/sky130_fd_pr__cap_mim_m3_1_WRT4AW.mag


diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag b/mag/Old/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
similarity index 100%
rename from mag/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag
rename to mag/Old/sky130_fd_pr__cap_mim_m3_2_W5U4AW.mag


diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag


diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag


diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/Old/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
similarity index 100%
rename from mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
rename to mag/Old/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag


diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag


diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag


diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag


diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag


diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/Old/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
similarity index 100%
rename from mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
rename to mag/Old/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag


diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/Old/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
similarity index 100%
rename from mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
rename to mag/Old/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag


diff --git a/mag/user_analog_proj_example.mag b/mag/Old/user_analog_proj_example.mag
similarity index 100%
rename from mag/user_analog_proj_example.mag
rename to mag/Old/user_analog_proj_example.mag


diff --git a/mag/Old/user_analog_project_wrapper.mag b/mag/Old/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..ebc5e1b
--- /dev/null
+++ b/mag/Old/user_analog_project_wrapper.mag

@@ -0,0 +1,2305 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1620395479
+<< mvpsubdiff >>
+rect 345740 628255 345764 629032
+rect 371078 628255 371102 629032
+<< mvpsubdiffcont >>
+rect 345764 628255 371078 629032
+<< locali >>
+rect 345748 628255 345764 629032
+rect 371078 628255 371094 629032
+<< viali >>
+rect 357593 628300 359298 629000
+<< metal1 >>
+rect 357470 629399 359442 629457
+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
+<< via1 >>
+rect 357538 629000 359388 629399
+rect 357538 628300 357593 629000
+rect 357593 628300 359298 629000
+rect 359298 628300 359388 629000
+rect 357538 628057 359388 628300
+<< metal2 >>
+rect 357470 629399 359442 629457
+rect 357470 628057 357538 629399
+rect 359388 628057 359442 629399
+rect 357470 627990 359442 628057
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+<< via2 >>
+rect 357538 628057 359388 629399
+<< metal3 >>
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+rect 68194 702300 73194 704800
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+<< via3 >>
+rect 170894 684327 173094 690603
+rect 173394 684327 175594 690603
+rect 222594 684360 224794 690636
+rect 225094 684360 227294 690636
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+rect 573548 500050 576743 500162
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+rect 13991 191430 17427 196230
+rect 573605 191430 576629 196230
+<< metal4 >>
+rect 170628 690636 526162 690737
+rect 170628 690603 222594 690636
+rect 170628 684327 170894 690603
+rect 173094 684327 173394 690603
+rect 175594 684360 222594 690603
+rect 224794 684360 225094 690636
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+rect 175594 684327 526162 684332
+rect 170628 684183 526162 684327
+rect 318330 649837 359973 649898
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+rect 560425 644584 566979 644980
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+rect 364987 615255 365157 617835
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+rect 369823 613756 370980 618859
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+rect 556059 545362 562613 550562
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+rect 562346 540562 562613 545362
+rect 556059 540155 562613 540562
+rect 573464 500162 576816 500473
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+rect 576743 500050 576816 500162
+rect 13814 462510 17684 462771
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+rect 17564 462398 17684 462510
+rect 13814 419288 17684 462398
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+rect 17599 419176 17684 419288
+rect 13814 227257 17684 419176
+rect 573464 455740 576816 500050
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+rect 576731 455628 576816 455740
+rect 13811 196230 17688 227257
+rect 13811 191430 13991 196230
+rect 17427 191430 17688 196230
+rect 13811 191098 17688 191430
+rect 573464 196230 576816 455628
+rect 573464 191430 573605 196230
+rect 576629 191430 576816 196230
+rect 573464 191191 576816 191430
+<< via4 >>
+rect 357559 643394 359314 649837
+rect 352028 615249 353603 617829
+rect 363412 615255 364987 617835
+rect 363414 597231 364992 601572
+<< metal5 >>
+rect 357521 649837 359350 649991
+rect 357521 643394 357559 649837
+rect 359314 643394 359350 649837
+rect 351918 617829 353747 617929
+rect 351918 615249 352028 617829
+rect 353603 615249 353747 617829
+rect 351918 614900 353747 615249
+rect 357521 614900 359350 643394
+rect 351918 613071 359350 614900
+rect 363318 617835 365147 617929
+rect 363318 615255 363412 617835
+rect 364987 615255 365147 617835
+rect 363318 601572 365147 615255
+rect 363318 597231 363414 601572
+rect 364992 597231 365147 601572
+rect 363318 597052 365147 597231
+<< comment >>
+rect -100 704000 584100 704100
+rect -100 0 0 704000
+rect 584000 0 584100 704000
+rect -100 -100 584100 0
+use user_analog_proj_example  user_analog_proj_example_0
+timestamp 1620310959
+transform 1 0 345668 0 -1 627114
+box -59 -22 25476 8324
+<< labels >>
+flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -800 381864 480 381976 0 FreeSans 1120 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -800 338642 480 338754 0 FreeSans 1120 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -800 295420 480 295532 0 FreeSans 1120 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -800 252398 480 252510 0 FreeSans 1120 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -800 124776 480 124888 0 FreeSans 1120 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -800 81554 480 81666 0 FreeSans 1120 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -800 38332 480 38444 0 FreeSans 1120 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -800 16910 480 17022 0 FreeSans 1120 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 583520 313652 584800 313764 0 FreeSans 1120 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 583520 358874 584800 358986 0 FreeSans 1120 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 583520 405296 584800 405408 0 FreeSans 1120 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 583520 449718 584800 449830 0 FreeSans 1120 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 583520 494140 584800 494252 0 FreeSans 1120 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 583520 583562 584800 583674 0 FreeSans 1120 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -800 511530 480 511642 0 FreeSans 1120 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -800 468308 480 468420 0 FreeSans 1120 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -800 425086 480 425198 0 FreeSans 1120 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 583520 270412 584800 270524 0 FreeSans 1120 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -800 380682 480 380794 0 FreeSans 1120 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -800 337460 480 337572 0 FreeSans 1120 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -800 294238 480 294350 0 FreeSans 1120 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -800 251216 480 251328 0 FreeSans 1120 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -800 123594 480 123706 0 FreeSans 1120 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -800 80372 480 80484 0 FreeSans 1120 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -800 37150 480 37262 0 FreeSans 1120 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -800 15728 480 15840 0 FreeSans 1120 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 583520 314834 584800 314946 0 FreeSans 1120 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 583520 360056 584800 360168 0 FreeSans 1120 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 583520 406478 584800 406590 0 FreeSans 1120 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 583520 450900 584800 451012 0 FreeSans 1120 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 583520 495322 584800 495434 0 FreeSans 1120 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 583520 584744 584800 584856 0 FreeSans 1120 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -800 510348 480 510460 0 FreeSans 1120 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -800 467126 480 467238 0 FreeSans 1120 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -800 423904 480 424016 0 FreeSans 1120 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 582300 677984 584800 682984 0 FreeSans 1120 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 680242 1700 685242 0 FreeSans 1120 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 566594 702300 571594 704800 0 FreeSans 1920 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 465394 702300 470394 704800 0 FreeSans 1920 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 413394 702300 418394 704800 0 FreeSans 1920 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 329294 702300 334294 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 227594 702300 232594 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 175894 702300 180894 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 120194 702300 125194 704800 0 FreeSans 1920 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 68194 702300 73194 704800 0 FreeSans 1920 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 16194 702300 21194 704800 0 FreeSans 1920 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 318994 702300 323994 704800 0 FreeSans 1920 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 217294 702300 222294 704800 0 FreeSans 1920 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 165594 702300 170594 704800 0 FreeSans 1920 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 326794 702300 328994 704800 0 FreeSans 1920 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 225094 702300 227294 704800 0 FreeSans 1920 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 173394 702300 175594 704800 0 FreeSans 1920 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 324294 702300 326494 704800 0 FreeSans 1920 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 222594 702300 224794 704800 0 FreeSans 1920 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 170894 702300 173094 704800 0 FreeSans 1920 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 583520 2726 584800 2838 0 FreeSans 1120 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 583520 408842 584800 408954 0 FreeSans 1120 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 583520 453264 584800 453376 0 FreeSans 1120 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 583520 497686 584800 497798 0 FreeSans 1120 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 583520 587108 584800 587220 0 FreeSans 1120 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -800 507984 480 508096 0 FreeSans 1120 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -800 464762 480 464874 0 FreeSans 1120 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -800 421540 480 421652 0 FreeSans 1120 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -800 378318 480 378430 0 FreeSans 1120 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -800 335096 480 335208 0 FreeSans 1120 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -800 291874 480 291986 0 FreeSans 1120 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 583520 7454 584800 7566 0 FreeSans 1120 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -800 248852 480 248964 0 FreeSans 1120 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -800 121230 480 121342 0 FreeSans 1120 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -800 78008 480 78120 0 FreeSans 1120 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -800 34786 480 34898 0 FreeSans 1120 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -800 13364 480 13476 0 FreeSans 1120 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -800 8636 480 8748 0 FreeSans 1120 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -800 3908 480 4020 0 FreeSans 1120 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 583520 12182 584800 12294 0 FreeSans 1120 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 583520 16910 584800 17022 0 FreeSans 1120 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 583520 21638 584800 21750 0 FreeSans 1120 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 583520 48096 584800 48208 0 FreeSans 1120 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 583520 92754 584800 92866 0 FreeSans 1120 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 583520 272776 584800 272888 0 FreeSans 1120 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 583520 317198 584800 317310 0 FreeSans 1120 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 583520 362420 584800 362532 0 FreeSans 1120 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 583520 1544 584800 1656 0 FreeSans 1120 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 583520 407660 584800 407772 0 FreeSans 1120 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 583520 452082 584800 452194 0 FreeSans 1120 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 583520 496504 584800 496616 0 FreeSans 1120 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 583520 585926 584800 586038 0 FreeSans 1120 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -800 509166 480 509278 0 FreeSans 1120 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -800 465944 480 466056 0 FreeSans 1120 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -800 422722 480 422834 0 FreeSans 1120 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -800 379500 480 379612 0 FreeSans 1120 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -800 336278 480 336390 0 FreeSans 1120 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -800 293056 480 293168 0 FreeSans 1120 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 583520 6272 584800 6384 0 FreeSans 1120 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -800 250034 480 250146 0 FreeSans 1120 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -800 122412 480 122524 0 FreeSans 1120 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -800 79190 480 79302 0 FreeSans 1120 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -800 35968 480 36080 0 FreeSans 1120 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -800 14546 480 14658 0 FreeSans 1120 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -800 9818 480 9930 0 FreeSans 1120 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -800 5090 480 5202 0 FreeSans 1120 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 583520 11000 584800 11112 0 FreeSans 1120 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 583520 15728 584800 15840 0 FreeSans 1120 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 583520 20456 584800 20568 0 FreeSans 1120 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 583520 46914 584800 47026 0 FreeSans 1120 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 583520 91572 584800 91684 0 FreeSans 1120 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 583520 271594 584800 271706 0 FreeSans 1120 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 583520 316016 584800 316128 0 FreeSans 1120 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 583520 361238 584800 361350 0 FreeSans 1120 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 583520 5090 584800 5202 0 FreeSans 1120 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 583520 411206 584800 411318 0 FreeSans 1120 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 583520 455628 584800 455740 0 FreeSans 1120 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 583520 500050 584800 500162 0 FreeSans 1120 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 583520 589472 584800 589584 0 FreeSans 1120 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -800 505620 480 505732 0 FreeSans 1120 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -800 462398 480 462510 0 FreeSans 1120 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -800 419176 480 419288 0 FreeSans 1120 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -800 375954 480 376066 0 FreeSans 1120 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -800 332732 480 332844 0 FreeSans 1120 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -800 289510 480 289622 0 FreeSans 1120 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 583520 9818 584800 9930 0 FreeSans 1120 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -800 246488 480 246600 0 FreeSans 1120 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -800 118866 480 118978 0 FreeSans 1120 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -800 75644 480 75756 0 FreeSans 1120 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -800 32422 480 32534 0 FreeSans 1120 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -800 11000 480 11112 0 FreeSans 1120 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -800 6272 480 6384 0 FreeSans 1120 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -800 1544 480 1656 0 FreeSans 1120 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 583520 14546 584800 14658 0 FreeSans 1120 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 583520 19274 584800 19386 0 FreeSans 1120 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1120 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1120 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1120 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1120 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1120 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1120 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1120 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1120 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1120 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1120 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1120 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1120 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1120 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1120 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1120 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1120 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1120 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 583520 8636 584800 8748 0 FreeSans 1120 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -800 247670 480 247782 0 FreeSans 1120 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -800 120048 480 120160 0 FreeSans 1120 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1120 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1120 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1120 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1120 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1120 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1120 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1120 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1120 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1120 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1120 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1120 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1120 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1120 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 125816 -800 125928 480 0 FreeSans 1120 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 480416 -800 480528 480 0 FreeSans 1120 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 483962 -800 484074 480 0 FreeSans 1120 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 487508 -800 487620 480 0 FreeSans 1120 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 491054 -800 491166 480 0 FreeSans 1120 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 494600 -800 494712 480 0 FreeSans 1120 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 498146 -800 498258 480 0 FreeSans 1120 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 501692 -800 501804 480 0 FreeSans 1120 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 505238 -800 505350 480 0 FreeSans 1120 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 508784 -800 508896 480 0 FreeSans 1120 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 512330 -800 512442 480 0 FreeSans 1120 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 161276 -800 161388 480 0 FreeSans 1120 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 515876 -800 515988 480 0 FreeSans 1120 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 519422 -800 519534 480 0 FreeSans 1120 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 522968 -800 523080 480 0 FreeSans 1120 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 526514 -800 526626 480 0 FreeSans 1120 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 530060 -800 530172 480 0 FreeSans 1120 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 533606 -800 533718 480 0 FreeSans 1120 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 537152 -800 537264 480 0 FreeSans 1120 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 540698 -800 540810 480 0 FreeSans 1120 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 544244 -800 544356 480 0 FreeSans 1120 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 547790 -800 547902 480 0 FreeSans 1120 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 164822 -800 164934 480 0 FreeSans 1120 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 551336 -800 551448 480 0 FreeSans 1120 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 554882 -800 554994 480 0 FreeSans 1120 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 558428 -800 558540 480 0 FreeSans 1120 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 561974 -800 562086 480 0 FreeSans 1120 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 565520 -800 565632 480 0 FreeSans 1120 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 569066 -800 569178 480 0 FreeSans 1120 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 572612 -800 572724 480 0 FreeSans 1120 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 576158 -800 576270 480 0 FreeSans 1120 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 168368 -800 168480 480 0 FreeSans 1120 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 171914 -800 172026 480 0 FreeSans 1120 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 175460 -800 175572 480 0 FreeSans 1120 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 179006 -800 179118 480 0 FreeSans 1120 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 182552 -800 182664 480 0 FreeSans 1120 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 186098 -800 186210 480 0 FreeSans 1120 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 189644 -800 189756 480 0 FreeSans 1120 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 193190 -800 193302 480 0 FreeSans 1120 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 129362 -800 129474 480 0 FreeSans 1120 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 196736 -800 196848 480 0 FreeSans 1120 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 200282 -800 200394 480 0 FreeSans 1120 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 203828 -800 203940 480 0 FreeSans 1120 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 207374 -800 207486 480 0 FreeSans 1120 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 210920 -800 211032 480 0 FreeSans 1120 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 214466 -800 214578 480 0 FreeSans 1120 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 218012 -800 218124 480 0 FreeSans 1120 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 221558 -800 221670 480 0 FreeSans 1120 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 225104 -800 225216 480 0 FreeSans 1120 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 228650 -800 228762 480 0 FreeSans 1120 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 132908 -800 133020 480 0 FreeSans 1120 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 232196 -800 232308 480 0 FreeSans 1120 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 235742 -800 235854 480 0 FreeSans 1120 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 239288 -800 239400 480 0 FreeSans 1120 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 242834 -800 242946 480 0 FreeSans 1120 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 246380 -800 246492 480 0 FreeSans 1120 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 249926 -800 250038 480 0 FreeSans 1120 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 253472 -800 253584 480 0 FreeSans 1120 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 257018 -800 257130 480 0 FreeSans 1120 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 260564 -800 260676 480 0 FreeSans 1120 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 264110 -800 264222 480 0 FreeSans 1120 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 136454 -800 136566 480 0 FreeSans 1120 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 267656 -800 267768 480 0 FreeSans 1120 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 271202 -800 271314 480 0 FreeSans 1120 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 274748 -800 274860 480 0 FreeSans 1120 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 278294 -800 278406 480 0 FreeSans 1120 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 281840 -800 281952 480 0 FreeSans 1120 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 285386 -800 285498 480 0 FreeSans 1120 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 288932 -800 289044 480 0 FreeSans 1120 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 292478 -800 292590 480 0 FreeSans 1120 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 296024 -800 296136 480 0 FreeSans 1120 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 299570 -800 299682 480 0 FreeSans 1120 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 140000 -800 140112 480 0 FreeSans 1120 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 303116 -800 303228 480 0 FreeSans 1120 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 306662 -800 306774 480 0 FreeSans 1120 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 310208 -800 310320 480 0 FreeSans 1120 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 313754 -800 313866 480 0 FreeSans 1120 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 317300 -800 317412 480 0 FreeSans 1120 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 320846 -800 320958 480 0 FreeSans 1120 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 324392 -800 324504 480 0 FreeSans 1120 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 327938 -800 328050 480 0 FreeSans 1120 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 331484 -800 331596 480 0 FreeSans 1120 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 335030 -800 335142 480 0 FreeSans 1120 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 143546 -800 143658 480 0 FreeSans 1120 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 338576 -800 338688 480 0 FreeSans 1120 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 342122 -800 342234 480 0 FreeSans 1120 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 345668 -800 345780 480 0 FreeSans 1120 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 349214 -800 349326 480 0 FreeSans 1120 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 352760 -800 352872 480 0 FreeSans 1120 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 356306 -800 356418 480 0 FreeSans 1120 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 359852 -800 359964 480 0 FreeSans 1120 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 363398 -800 363510 480 0 FreeSans 1120 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 366944 -800 367056 480 0 FreeSans 1120 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 370490 -800 370602 480 0 FreeSans 1120 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 147092 -800 147204 480 0 FreeSans 1120 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 374036 -800 374148 480 0 FreeSans 1120 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 377582 -800 377694 480 0 FreeSans 1120 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 381128 -800 381240 480 0 FreeSans 1120 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 384674 -800 384786 480 0 FreeSans 1120 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 388220 -800 388332 480 0 FreeSans 1120 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 391766 -800 391878 480 0 FreeSans 1120 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 395312 -800 395424 480 0 FreeSans 1120 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 398858 -800 398970 480 0 FreeSans 1120 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 402404 -800 402516 480 0 FreeSans 1120 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 405950 -800 406062 480 0 FreeSans 1120 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 150638 -800 150750 480 0 FreeSans 1120 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 409496 -800 409608 480 0 FreeSans 1120 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 413042 -800 413154 480 0 FreeSans 1120 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 416588 -800 416700 480 0 FreeSans 1120 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 420134 -800 420246 480 0 FreeSans 1120 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 423680 -800 423792 480 0 FreeSans 1120 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 427226 -800 427338 480 0 FreeSans 1120 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 430772 -800 430884 480 0 FreeSans 1120 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 434318 -800 434430 480 0 FreeSans 1120 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 437864 -800 437976 480 0 FreeSans 1120 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 441410 -800 441522 480 0 FreeSans 1120 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 154184 -800 154296 480 0 FreeSans 1120 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 444956 -800 445068 480 0 FreeSans 1120 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 448502 -800 448614 480 0 FreeSans 1120 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 452048 -800 452160 480 0 FreeSans 1120 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 455594 -800 455706 480 0 FreeSans 1120 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 459140 -800 459252 480 0 FreeSans 1120 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 462686 -800 462798 480 0 FreeSans 1120 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 466232 -800 466344 480 0 FreeSans 1120 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 469778 -800 469890 480 0 FreeSans 1120 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 473324 -800 473436 480 0 FreeSans 1120 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 476870 -800 476982 480 0 FreeSans 1120 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 157730 -800 157842 480 0 FreeSans 1120 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 126998 -800 127110 480 0 FreeSans 1120 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 481598 -800 481710 480 0 FreeSans 1120 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 485144 -800 485256 480 0 FreeSans 1120 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 488690 -800 488802 480 0 FreeSans 1120 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 492236 -800 492348 480 0 FreeSans 1120 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 495782 -800 495894 480 0 FreeSans 1120 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 499328 -800 499440 480 0 FreeSans 1120 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 502874 -800 502986 480 0 FreeSans 1120 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 506420 -800 506532 480 0 FreeSans 1120 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 509966 -800 510078 480 0 FreeSans 1120 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 513512 -800 513624 480 0 FreeSans 1120 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 162458 -800 162570 480 0 FreeSans 1120 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 517058 -800 517170 480 0 FreeSans 1120 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 520604 -800 520716 480 0 FreeSans 1120 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 524150 -800 524262 480 0 FreeSans 1120 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 527696 -800 527808 480 0 FreeSans 1120 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 531242 -800 531354 480 0 FreeSans 1120 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 534788 -800 534900 480 0 FreeSans 1120 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 538334 -800 538446 480 0 FreeSans 1120 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 541880 -800 541992 480 0 FreeSans 1120 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 545426 -800 545538 480 0 FreeSans 1120 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 548972 -800 549084 480 0 FreeSans 1120 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 166004 -800 166116 480 0 FreeSans 1120 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 552518 -800 552630 480 0 FreeSans 1120 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 556064 -800 556176 480 0 FreeSans 1120 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 559610 -800 559722 480 0 FreeSans 1120 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 563156 -800 563268 480 0 FreeSans 1120 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 566702 -800 566814 480 0 FreeSans 1120 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 570248 -800 570360 480 0 FreeSans 1120 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 573794 -800 573906 480 0 FreeSans 1120 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 577340 -800 577452 480 0 FreeSans 1120 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 169550 -800 169662 480 0 FreeSans 1120 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 173096 -800 173208 480 0 FreeSans 1120 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 176642 -800 176754 480 0 FreeSans 1120 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 180188 -800 180300 480 0 FreeSans 1120 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 183734 -800 183846 480 0 FreeSans 1120 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 187280 -800 187392 480 0 FreeSans 1120 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 190826 -800 190938 480 0 FreeSans 1120 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 194372 -800 194484 480 0 FreeSans 1120 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 130544 -800 130656 480 0 FreeSans 1120 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 197918 -800 198030 480 0 FreeSans 1120 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 201464 -800 201576 480 0 FreeSans 1120 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 205010 -800 205122 480 0 FreeSans 1120 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 208556 -800 208668 480 0 FreeSans 1120 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 212102 -800 212214 480 0 FreeSans 1120 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 215648 -800 215760 480 0 FreeSans 1120 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 219194 -800 219306 480 0 FreeSans 1120 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 222740 -800 222852 480 0 FreeSans 1120 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 226286 -800 226398 480 0 FreeSans 1120 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 229832 -800 229944 480 0 FreeSans 1120 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 134090 -800 134202 480 0 FreeSans 1120 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 233378 -800 233490 480 0 FreeSans 1120 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 236924 -800 237036 480 0 FreeSans 1120 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 240470 -800 240582 480 0 FreeSans 1120 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 244016 -800 244128 480 0 FreeSans 1120 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 247562 -800 247674 480 0 FreeSans 1120 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 251108 -800 251220 480 0 FreeSans 1120 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 254654 -800 254766 480 0 FreeSans 1120 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 258200 -800 258312 480 0 FreeSans 1120 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 261746 -800 261858 480 0 FreeSans 1120 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 265292 -800 265404 480 0 FreeSans 1120 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 137636 -800 137748 480 0 FreeSans 1120 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 268838 -800 268950 480 0 FreeSans 1120 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 272384 -800 272496 480 0 FreeSans 1120 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 275930 -800 276042 480 0 FreeSans 1120 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 279476 -800 279588 480 0 FreeSans 1120 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 283022 -800 283134 480 0 FreeSans 1120 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 286568 -800 286680 480 0 FreeSans 1120 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 290114 -800 290226 480 0 FreeSans 1120 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 293660 -800 293772 480 0 FreeSans 1120 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 297206 -800 297318 480 0 FreeSans 1120 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 300752 -800 300864 480 0 FreeSans 1120 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 141182 -800 141294 480 0 FreeSans 1120 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 304298 -800 304410 480 0 FreeSans 1120 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 307844 -800 307956 480 0 FreeSans 1120 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 311390 -800 311502 480 0 FreeSans 1120 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 314936 -800 315048 480 0 FreeSans 1120 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 318482 -800 318594 480 0 FreeSans 1120 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 322028 -800 322140 480 0 FreeSans 1120 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 325574 -800 325686 480 0 FreeSans 1120 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 329120 -800 329232 480 0 FreeSans 1120 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 332666 -800 332778 480 0 FreeSans 1120 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 336212 -800 336324 480 0 FreeSans 1120 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 144728 -800 144840 480 0 FreeSans 1120 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 339758 -800 339870 480 0 FreeSans 1120 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 343304 -800 343416 480 0 FreeSans 1120 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 346850 -800 346962 480 0 FreeSans 1120 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 350396 -800 350508 480 0 FreeSans 1120 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 353942 -800 354054 480 0 FreeSans 1120 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 357488 -800 357600 480 0 FreeSans 1120 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 361034 -800 361146 480 0 FreeSans 1120 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 364580 -800 364692 480 0 FreeSans 1120 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 368126 -800 368238 480 0 FreeSans 1120 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 371672 -800 371784 480 0 FreeSans 1120 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 148274 -800 148386 480 0 FreeSans 1120 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 375218 -800 375330 480 0 FreeSans 1120 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 378764 -800 378876 480 0 FreeSans 1120 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 382310 -800 382422 480 0 FreeSans 1120 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 385856 -800 385968 480 0 FreeSans 1120 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 389402 -800 389514 480 0 FreeSans 1120 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 392948 -800 393060 480 0 FreeSans 1120 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 396494 -800 396606 480 0 FreeSans 1120 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 400040 -800 400152 480 0 FreeSans 1120 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 403586 -800 403698 480 0 FreeSans 1120 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 407132 -800 407244 480 0 FreeSans 1120 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 151820 -800 151932 480 0 FreeSans 1120 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 410678 -800 410790 480 0 FreeSans 1120 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 414224 -800 414336 480 0 FreeSans 1120 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 417770 -800 417882 480 0 FreeSans 1120 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 421316 -800 421428 480 0 FreeSans 1120 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 424862 -800 424974 480 0 FreeSans 1120 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 428408 -800 428520 480 0 FreeSans 1120 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 431954 -800 432066 480 0 FreeSans 1120 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 435500 -800 435612 480 0 FreeSans 1120 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 439046 -800 439158 480 0 FreeSans 1120 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 442592 -800 442704 480 0 FreeSans 1120 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 155366 -800 155478 480 0 FreeSans 1120 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 446138 -800 446250 480 0 FreeSans 1120 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 449684 -800 449796 480 0 FreeSans 1120 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 453230 -800 453342 480 0 FreeSans 1120 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 456776 -800 456888 480 0 FreeSans 1120 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 460322 -800 460434 480 0 FreeSans 1120 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 463868 -800 463980 480 0 FreeSans 1120 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 467414 -800 467526 480 0 FreeSans 1120 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 470960 -800 471072 480 0 FreeSans 1120 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 474506 -800 474618 480 0 FreeSans 1120 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 478052 -800 478164 480 0 FreeSans 1120 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 158912 -800 159024 480 0 FreeSans 1120 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 128180 -800 128292 480 0 FreeSans 1120 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 482780 -800 482892 480 0 FreeSans 1120 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 486326 -800 486438 480 0 FreeSans 1120 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 489872 -800 489984 480 0 FreeSans 1120 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 493418 -800 493530 480 0 FreeSans 1120 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 496964 -800 497076 480 0 FreeSans 1120 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 500510 -800 500622 480 0 FreeSans 1120 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 504056 -800 504168 480 0 FreeSans 1120 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 507602 -800 507714 480 0 FreeSans 1120 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 511148 -800 511260 480 0 FreeSans 1120 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 514694 -800 514806 480 0 FreeSans 1120 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 163640 -800 163752 480 0 FreeSans 1120 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 518240 -800 518352 480 0 FreeSans 1120 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 521786 -800 521898 480 0 FreeSans 1120 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 525332 -800 525444 480 0 FreeSans 1120 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 528878 -800 528990 480 0 FreeSans 1120 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 532424 -800 532536 480 0 FreeSans 1120 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 535970 -800 536082 480 0 FreeSans 1120 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 539516 -800 539628 480 0 FreeSans 1120 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 543062 -800 543174 480 0 FreeSans 1120 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 546608 -800 546720 480 0 FreeSans 1120 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 550154 -800 550266 480 0 FreeSans 1120 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 167186 -800 167298 480 0 FreeSans 1120 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 553700 -800 553812 480 0 FreeSans 1120 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 557246 -800 557358 480 0 FreeSans 1120 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 560792 -800 560904 480 0 FreeSans 1120 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 564338 -800 564450 480 0 FreeSans 1120 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 567884 -800 567996 480 0 FreeSans 1120 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 571430 -800 571542 480 0 FreeSans 1120 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 574976 -800 575088 480 0 FreeSans 1120 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 578522 -800 578634 480 0 FreeSans 1120 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 170732 -800 170844 480 0 FreeSans 1120 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 174278 -800 174390 480 0 FreeSans 1120 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 177824 -800 177936 480 0 FreeSans 1120 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 181370 -800 181482 480 0 FreeSans 1120 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 184916 -800 185028 480 0 FreeSans 1120 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 188462 -800 188574 480 0 FreeSans 1120 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 192008 -800 192120 480 0 FreeSans 1120 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 195554 -800 195666 480 0 FreeSans 1120 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 131726 -800 131838 480 0 FreeSans 1120 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 199100 -800 199212 480 0 FreeSans 1120 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 202646 -800 202758 480 0 FreeSans 1120 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 206192 -800 206304 480 0 FreeSans 1120 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 209738 -800 209850 480 0 FreeSans 1120 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 213284 -800 213396 480 0 FreeSans 1120 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 216830 -800 216942 480 0 FreeSans 1120 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 220376 -800 220488 480 0 FreeSans 1120 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 223922 -800 224034 480 0 FreeSans 1120 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 227468 -800 227580 480 0 FreeSans 1120 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 231014 -800 231126 480 0 FreeSans 1120 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 135272 -800 135384 480 0 FreeSans 1120 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 234560 -800 234672 480 0 FreeSans 1120 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 238106 -800 238218 480 0 FreeSans 1120 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 241652 -800 241764 480 0 FreeSans 1120 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 245198 -800 245310 480 0 FreeSans 1120 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 248744 -800 248856 480 0 FreeSans 1120 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 252290 -800 252402 480 0 FreeSans 1120 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 255836 -800 255948 480 0 FreeSans 1120 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 259382 -800 259494 480 0 FreeSans 1120 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 262928 -800 263040 480 0 FreeSans 1120 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 266474 -800 266586 480 0 FreeSans 1120 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 138818 -800 138930 480 0 FreeSans 1120 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 270020 -800 270132 480 0 FreeSans 1120 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 273566 -800 273678 480 0 FreeSans 1120 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 277112 -800 277224 480 0 FreeSans 1120 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 280658 -800 280770 480 0 FreeSans 1120 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 284204 -800 284316 480 0 FreeSans 1120 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 287750 -800 287862 480 0 FreeSans 1120 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 291296 -800 291408 480 0 FreeSans 1120 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 294842 -800 294954 480 0 FreeSans 1120 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 298388 -800 298500 480 0 FreeSans 1120 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 301934 -800 302046 480 0 FreeSans 1120 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 142364 -800 142476 480 0 FreeSans 1120 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 305480 -800 305592 480 0 FreeSans 1120 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 309026 -800 309138 480 0 FreeSans 1120 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 312572 -800 312684 480 0 FreeSans 1120 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 316118 -800 316230 480 0 FreeSans 1120 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 319664 -800 319776 480 0 FreeSans 1120 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 323210 -800 323322 480 0 FreeSans 1120 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 326756 -800 326868 480 0 FreeSans 1120 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 330302 -800 330414 480 0 FreeSans 1120 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 333848 -800 333960 480 0 FreeSans 1120 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 337394 -800 337506 480 0 FreeSans 1120 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 145910 -800 146022 480 0 FreeSans 1120 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 340940 -800 341052 480 0 FreeSans 1120 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 344486 -800 344598 480 0 FreeSans 1120 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 348032 -800 348144 480 0 FreeSans 1120 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 351578 -800 351690 480 0 FreeSans 1120 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 355124 -800 355236 480 0 FreeSans 1120 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 358670 -800 358782 480 0 FreeSans 1120 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 362216 -800 362328 480 0 FreeSans 1120 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 365762 -800 365874 480 0 FreeSans 1120 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 369308 -800 369420 480 0 FreeSans 1120 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 372854 -800 372966 480 0 FreeSans 1120 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 149456 -800 149568 480 0 FreeSans 1120 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 376400 -800 376512 480 0 FreeSans 1120 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 379946 -800 380058 480 0 FreeSans 1120 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 383492 -800 383604 480 0 FreeSans 1120 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 387038 -800 387150 480 0 FreeSans 1120 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 390584 -800 390696 480 0 FreeSans 1120 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 394130 -800 394242 480 0 FreeSans 1120 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 397676 -800 397788 480 0 FreeSans 1120 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 401222 -800 401334 480 0 FreeSans 1120 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 404768 -800 404880 480 0 FreeSans 1120 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 408314 -800 408426 480 0 FreeSans 1120 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 153002 -800 153114 480 0 FreeSans 1120 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 411860 -800 411972 480 0 FreeSans 1120 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 415406 -800 415518 480 0 FreeSans 1120 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 418952 -800 419064 480 0 FreeSans 1120 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 422498 -800 422610 480 0 FreeSans 1120 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 426044 -800 426156 480 0 FreeSans 1120 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 429590 -800 429702 480 0 FreeSans 1120 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 433136 -800 433248 480 0 FreeSans 1120 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 436682 -800 436794 480 0 FreeSans 1120 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 440228 -800 440340 480 0 FreeSans 1120 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 443774 -800 443886 480 0 FreeSans 1120 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 156548 -800 156660 480 0 FreeSans 1120 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 447320 -800 447432 480 0 FreeSans 1120 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 450866 -800 450978 480 0 FreeSans 1120 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 454412 -800 454524 480 0 FreeSans 1120 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 457958 -800 458070 480 0 FreeSans 1120 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 461504 -800 461616 480 0 FreeSans 1120 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 465050 -800 465162 480 0 FreeSans 1120 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 468596 -800 468708 480 0 FreeSans 1120 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 472142 -800 472254 480 0 FreeSans 1120 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 475688 -800 475800 480 0 FreeSans 1120 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 479234 -800 479346 480 0 FreeSans 1120 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 160094 -800 160206 480 0 FreeSans 1120 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 579704 -800 579816 480 0 FreeSans 1120 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 580886 -800 580998 480 0 FreeSans 1120 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 582068 -800 582180 480 0 FreeSans 1120 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 583250 -800 583362 480 0 FreeSans 1120 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 582340 639784 584800 644584 0 FreeSans 1120 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 582340 629784 584800 634584 0 FreeSans 1120 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 643842 1660 648642 0 FreeSans 1120 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 633842 1660 638642 0 FreeSans 1120 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 582340 540562 584800 545362 0 FreeSans 1120 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 582340 550562 584800 555362 0 FreeSans 1120 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 582340 235230 584800 240030 0 FreeSans 1120 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 582340 225230 584800 230030 0 FreeSans 1120 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 204888 1660 209688 0 FreeSans 1120 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 214888 1660 219688 0 FreeSans 1120 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 520594 702340 525394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 510594 702340 515394 704800 0 FreeSans 1920 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 582340 146830 584800 151630 0 FreeSans 1120 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 582340 136830 584800 141630 0 FreeSans 1120 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 559442 1660 564242 0 FreeSans 1120 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 549442 1660 554242 0 FreeSans 1120 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 582340 191430 584800 196230 0 FreeSans 1120 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 582340 181430 584800 186230 0 FreeSans 1120 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 172888 1660 177688 0 FreeSans 1120 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 162888 1660 167688 0 FreeSans 1120 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 524 -800 636 480 0 FreeSans 1120 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 1706 -800 1818 480 0 FreeSans 1120 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 2888 -800 3000 480 0 FreeSans 1120 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 7616 -800 7728 480 0 FreeSans 1120 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 47804 -800 47916 480 0 FreeSans 1120 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 51350 -800 51462 480 0 FreeSans 1120 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 54896 -800 55008 480 0 FreeSans 1120 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 58442 -800 58554 480 0 FreeSans 1120 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 61988 -800 62100 480 0 FreeSans 1120 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 65534 -800 65646 480 0 FreeSans 1120 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 69080 -800 69192 480 0 FreeSans 1120 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 72626 -800 72738 480 0 FreeSans 1120 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 76172 -800 76284 480 0 FreeSans 1120 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 79718 -800 79830 480 0 FreeSans 1120 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 12344 -800 12456 480 0 FreeSans 1120 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 83264 -800 83376 480 0 FreeSans 1120 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 86810 -800 86922 480 0 FreeSans 1120 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 90356 -800 90468 480 0 FreeSans 1120 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 93902 -800 94014 480 0 FreeSans 1120 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 97448 -800 97560 480 0 FreeSans 1120 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 100994 -800 101106 480 0 FreeSans 1120 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 104540 -800 104652 480 0 FreeSans 1120 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 108086 -800 108198 480 0 FreeSans 1120 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 111632 -800 111744 480 0 FreeSans 1120 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 115178 -800 115290 480 0 FreeSans 1120 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 17072 -800 17184 480 0 FreeSans 1120 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 118724 -800 118836 480 0 FreeSans 1120 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 122270 -800 122382 480 0 FreeSans 1120 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 21800 -800 21912 480 0 FreeSans 1120 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 26528 -800 26640 480 0 FreeSans 1120 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 30074 -800 30186 480 0 FreeSans 1120 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 33620 -800 33732 480 0 FreeSans 1120 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 37166 -800 37278 480 0 FreeSans 1120 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 40712 -800 40824 480 0 FreeSans 1120 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 44258 -800 44370 480 0 FreeSans 1120 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 4070 -800 4182 480 0 FreeSans 1120 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 8798 -800 8910 480 0 FreeSans 1120 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 48986 -800 49098 480 0 FreeSans 1120 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 52532 -800 52644 480 0 FreeSans 1120 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 56078 -800 56190 480 0 FreeSans 1120 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 59624 -800 59736 480 0 FreeSans 1120 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 63170 -800 63282 480 0 FreeSans 1120 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 66716 -800 66828 480 0 FreeSans 1120 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 70262 -800 70374 480 0 FreeSans 1120 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 73808 -800 73920 480 0 FreeSans 1120 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 77354 -800 77466 480 0 FreeSans 1120 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 80900 -800 81012 480 0 FreeSans 1120 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 13526 -800 13638 480 0 FreeSans 1120 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 84446 -800 84558 480 0 FreeSans 1120 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 87992 -800 88104 480 0 FreeSans 1120 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 91538 -800 91650 480 0 FreeSans 1120 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 95084 -800 95196 480 0 FreeSans 1120 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 98630 -800 98742 480 0 FreeSans 1120 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 102176 -800 102288 480 0 FreeSans 1120 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 105722 -800 105834 480 0 FreeSans 1120 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 109268 -800 109380 480 0 FreeSans 1120 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 112814 -800 112926 480 0 FreeSans 1120 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 116360 -800 116472 480 0 FreeSans 1120 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 18254 -800 18366 480 0 FreeSans 1120 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 119906 -800 120018 480 0 FreeSans 1120 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 123452 -800 123564 480 0 FreeSans 1120 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 22982 -800 23094 480 0 FreeSans 1120 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 27710 -800 27822 480 0 FreeSans 1120 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 31256 -800 31368 480 0 FreeSans 1120 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 34802 -800 34914 480 0 FreeSans 1120 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1120 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1120 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1120 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1120 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1120 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1120 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1120 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1120 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1120 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1120 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1120 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1120 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1120 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1120 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1120 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1120 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1120 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1120 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1120 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1120 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1120 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1120 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1120 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1120 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1120 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1120 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1120 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1120 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1120 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1120 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1120 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1120 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1120 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1120 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1120 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1120 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1120 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1120 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1120 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1120 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
+flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
+flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
+flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>

diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/Old/user_analog_project_wrapper_empty.mag
similarity index 100%
rename from mag/user_analog_project_wrapper_empty.mag
rename to mag/Old/user_analog_project_wrapper_empty.mag


diff --git a/mag/PFD.gds b/mag/PFD.gds
new file mode 100644
index 0000000..1514b3c
--- /dev/null
+++ b/mag/PFD.gds
Binary files differ

diff --git a/mag/PFD.mag b/mag/PFD.mag
new file mode 100644
index 0000000..88574a2
--- /dev/null
+++ b/mag/PFD.mag

@@ -0,0 +1,101 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623767380
+<< nwell >>
+rect 2872 706 3790 1304
+rect 3241 700 3768 706
+<< metal1 >>
+rect 1390 1234 1400 1268
+rect 0 1180 1400 1234
+rect 1390 1146 1400 1180
+rect 1472 1234 1482 1268
+rect 2836 1234 3504 1274
+rect 1472 1180 3504 1234
+rect 1472 1146 1482 1180
+rect 2836 1140 3504 1180
+rect 0 652 210 718
+rect 3150 676 3504 1140
+rect 3754 97 3775 101
+rect 2123 36 2176 39
+rect 175 30 2786 36
+rect 0 -30 2872 30
+rect 2952 -26 2962 78
+rect 3014 -26 3024 78
+rect 3651 45 3661 97
+rect 3765 45 3775 97
+rect 3754 35 3775 45
+rect 175 -36 2123 -30
+rect 2159 -36 2786 -30
+rect 3752 -32 3775 -22
+rect 2865 -164 2919 -58
+rect 3651 -84 3661 -32
+rect 3765 -84 3775 -32
+rect 3716 -88 3775 -84
+rect 2872 -434 2919 -164
+rect 0 -718 210 -652
+rect 1390 -1180 1400 -1146
+rect 0 -1234 1400 -1180
+rect 1390 -1268 1400 -1234
+rect 1472 -1180 1482 -1146
+rect 1472 -1234 2872 -1180
+rect 1472 -1268 1482 -1234
+<< via1 >>
+rect 1400 1146 1472 1268
+rect 2962 -26 3014 78
+rect 3661 45 3765 97
+rect 3661 -84 3765 -32
+rect 1400 -1268 1472 -1146
+<< metal2 >>
+rect 1400 1268 1472 1278
+rect 1400 1136 1472 1146
+rect 2802 572 3790 624
+rect 2159 36 2211 436
+rect 3686 107 3738 572
+rect 3661 97 3765 107
+rect 2962 78 3014 88
+rect 2159 -26 2962 36
+rect 3014 -26 3024 36
+rect 3661 35 3765 45
+rect 2159 -36 3024 -26
+rect 3661 -32 3765 -22
+rect 2159 -436 2211 -36
+rect 3661 -94 3765 -84
+rect 3686 -572 3738 -94
+rect 2806 -624 3789 -572
+rect 1400 -1146 1472 -1136
+rect 1400 -1278 1472 -1268
+<< via2 >>
+rect 1400 1146 1472 1268
+rect 1400 -1268 1472 -1146
+<< metal3 >>
+rect 1390 1268 1482 1273
+rect 1390 1146 1400 1268
+rect 1472 1146 1482 1268
+rect 1390 1141 1482 1146
+rect 1400 -1141 1472 1141
+rect 1390 -1146 1482 -1141
+rect 1390 -1268 1400 -1146
+rect 1472 -1268 1482 -1146
+rect 1390 -1273 1482 -1268
+use dff_pfd  dff_pfd_1
+timestamp 1623456247
+transform 1 0 0 0 -1 0
+box 0 0 2872 1304
+use dff_pfd  dff_pfd_0
+timestamp 1623456247
+transform 1 0 0 0 1 0
+box 0 0 2872 1304
+use and_pfd  and_pfd_0
+timestamp 1623541727
+transform -1 0 3790 0 1 -598
+box 0 0 918 1304
+<< labels >>
+rlabel metal1 0 652 210 718 1 A
+rlabel metal1 0 -718 210 -652 1 B
+rlabel metal1 0 -30 2872 30 1 vss
+rlabel metal2 2802 572 3790 624 1 Up
+rlabel metal2 2806 -624 3789 -572 1 Down
+rlabel metal1 0 1180 3504 1234 1 vdd
+rlabel metal2 2159 -436 2211 436 1 Reset
+<< end >>

diff --git a/mag/and.gds b/mag/and.gds
new file mode 100644
index 0000000..022c09a
--- /dev/null
+++ b/mag/and.gds
Binary files differ

diff --git a/mag/and_pfd.mag b/mag/and_pfd.mag
new file mode 100644
index 0000000..2302111
--- /dev/null
+++ b/mag/and_pfd.mag

@@ -0,0 +1,139 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623541727
+<< nwell >>
+rect 0 1216 918 1304
+rect 0 598 96 1216
+<< pwell >>
+rect 0 0 918 88
+<< psubdiff >>
+rect 108 36 132 70
+rect 786 36 810 70
+<< nsubdiff >>
+rect 204 1234 228 1268
+rect 786 1234 810 1268
+rect 36 1146 213 1180
+rect 552 1146 616 1180
+rect 36 1087 70 1146
+rect 36 671 70 733
+<< psubdiffcont >>
+rect 132 36 786 70
+<< nsubdiffcont >>
+rect 228 1234 786 1268
+rect 36 733 70 1087
+<< poly >>
+rect 170 720 326 786
+rect 170 707 230 720
+rect 170 625 183 707
+rect 217 625 230 707
+rect 392 669 458 786
+rect 170 414 230 625
+rect 296 609 458 669
+rect 656 640 722 786
+rect 296 584 356 609
+rect 296 502 309 584
+rect 343 502 356 584
+rect 296 456 356 502
+rect 656 558 667 640
+rect 701 558 722 640
+rect 656 410 722 558
+<< polycont >>
+rect 183 625 217 707
+rect 309 502 343 584
+rect 667 558 701 640
+<< locali >>
+rect 36 1087 70 1146
+rect 36 671 70 733
+rect 183 707 217 723
+rect 183 609 217 625
+rect 667 640 701 656
+rect 309 584 343 600
+rect 667 542 701 558
+rect 309 486 343 502
+<< viali >>
+rect 36 1234 228 1268
+rect 228 1234 786 1268
+rect 786 1234 882 1268
+rect 36 1146 882 1180
+rect 183 625 217 707
+rect 309 502 343 584
+rect 667 558 701 640
+rect 848 158 882 528
+rect 36 124 882 158
+rect 36 36 132 70
+rect 132 36 786 70
+rect 786 36 882 70
+<< metal1 >>
+rect 0 1268 918 1274
+rect 0 1234 36 1268
+rect 882 1234 918 1268
+rect 0 1180 918 1234
+rect 0 1146 36 1180
+rect 882 1146 918 1180
+rect 0 1140 918 1146
+rect 240 997 286 1140
+rect 432 985 478 1140
+rect 640 988 686 1140
+rect 336 789 382 829
+rect 336 743 478 789
+rect 177 707 223 719
+rect 177 699 183 707
+rect 36 633 183 699
+rect 177 625 183 633
+rect 217 625 223 707
+rect 177 613 223 625
+rect 432 631 478 743
+rect 661 640 707 652
+rect 661 631 667 640
+rect 303 584 349 596
+rect 303 576 309 584
+rect 36 510 309 576
+rect 303 502 309 510
+rect 343 502 349 584
+rect 303 490 349 502
+rect 432 565 667 631
+rect 432 462 478 565
+rect 661 558 667 565
+rect 701 558 707 640
+rect 661 546 707 558
+rect 336 416 478 462
+rect 336 388 382 416
+rect 144 164 190 307
+rect 528 164 574 308
+rect 640 164 686 302
+rect 766 298 812 997
+rect 842 528 888 540
+rect 842 164 848 528
+rect 0 158 848 164
+rect 882 164 888 528
+rect 0 124 36 158
+rect 882 124 918 164
+rect 0 70 918 124
+rect 0 36 36 70
+rect 882 36 918 70
+rect 0 30 918 36
+rect 884 28 918 30
+use sky130_fd_pr__pfet_01v8_7T83YG  sky130_fd_pr__pfet_01v8_7T83YG_0
+timestamp 1623450397
+transform 1 0 359 0 1 907
+box -263 -309 263 309
+use sky130_fd_pr__nfet_01v8_ZCYAJJ  sky130_fd_pr__nfet_01v8_ZCYAJJ_0
+timestamp 1623449341
+transform 1 0 359 0 1 343
+box -359 -255 359 255
+use sky130_fd_pr__nfet_01v8_ZXAV3F  sky130_fd_pr__nfet_01v8_ZXAV3F_0
+timestamp 1623449341
+transform 1 0 707 0 1 343
+box -211 -255 211 255
+use sky130_fd_pr__pfet_01v8_4F7GBC  sky130_fd_pr__pfet_01v8_4F7GBC_0
+timestamp 1623450719
+transform 1 0 707 0 1 907
+box -211 -309 211 309
+<< labels >>
+rlabel metal1 0 70 918 124 1 vss
+rlabel metal1 0 1180 918 1234 1 vdd
+rlabel metal1 36 633 183 699 1 A
+rlabel metal1 36 510 309 576 1 B
+rlabel metal1 766 298 812 997 1 out
+<< end >>

diff --git a/mag/bias.mag b/mag/bias.mag
new file mode 100644
index 0000000..123116e
--- /dev/null
+++ b/mag/bias.mag

@@ -0,0 +1,89 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623869799
+<< metal1 >>
+rect -53 2101 44316 2168
+rect 20168 984 24096 1056
+rect 20259 715 20305 778
+rect 20555 710 20601 773
+rect 20851 716 20897 779
+rect 21147 716 21193 779
+rect 21442 716 21488 779
+rect 21739 718 21785 781
+rect 22035 719 22081 782
+rect 22331 718 22377 781
+rect 22627 719 22673 782
+rect 22923 719 22969 782
+rect 23219 721 23265 784
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+rect 36316 -412 40215 -273
+rect 40350 -412 44249 -273
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_1
+timestamp 1623863898
+transform -1 0 5997 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_0
+timestamp 1623863898
+transform 1 0 1964 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_2
+timestamp 1623863898
+transform -1 0 10031 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_3
+timestamp 1623863898
+transform -1 0 14064 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_4
+timestamp 1623863898
+transform -1 0 18098 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_5
+timestamp 1623863898
+transform 1 0 22132 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_6
+timestamp 1623863898
+transform -1 0 26163 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_7
+timestamp 1623863898
+transform -1 0 30197 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_8
+timestamp 1623863898
+transform -1 0 34231 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_9
+timestamp 1623863898
+transform -1 0 38265 0 1 1042
+box -2018 -1454 2017 1196
+use sky130_fd_pr__pfet_01v8_lvt_8P223X  sky130_fd_pr__pfet_01v8_lvt_8P223X_10
+timestamp 1623863898
+transform -1 0 42299 0 1 1042
+box -2018 -1454 2017 1196
+<< labels >>
+rlabel metal1 -53 2101 44316 2168 1 vdd
+rlabel metal1 20182 -412 24081 -273 1 iref
+rlabel metal1 8082 -412 11981 -273 1 iref_2
+rlabel metal1 12115 -412 16014 -273 1 iref_3
+rlabel metal1 16149 -412 20048 -273 1 iref_4
+rlabel metal1 24214 -412 28113 -273 1 iref_5
+rlabel metal1 28248 -412 32147 -273 1 iref_6
+rlabel metal1 32282 -412 36181 -273 1 iref_7
+rlabel metal1 36316 -412 40215 -273 1 iref_8
+rlabel metal1 40350 -412 44249 -273 1 iref_9
+rlabel metal1 14 -412 3913 -273 1 iref_0
+rlabel metal1 4048 -412 7947 -273 1 iref_1
+<< end >>

diff --git a/mag/cap_vco.mag b/mag/cap_vco.mag
new file mode 100644
index 0000000..ade2f44
--- /dev/null
+++ b/mag/cap_vco.mag

@@ -0,0 +1,84 @@
+magic
+tech sky130A
+timestamp 1623247475
+<< metal1 >>
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+<< via1 >>
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+<< metal2 >>
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+rect 277 -3 317 23
+rect 343 -3 397 23
+rect 423 -3 463 23
+<< labels >>
+rlabel via1 357 231 383 257 1 b
+rlabel metal2 357 -3 383 23 1 t
+<< end >>

diff --git a/mag/charge_pump.mag b/mag/charge_pump.mag
new file mode 100644
index 0000000..df5cac7
--- /dev/null
+++ b/mag/charge_pump.mag

@@ -0,0 +1,578 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623940058
+<< isosubstrate >>
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+<< nwell >>
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+<< psubdiffcont >>
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+timestamp 1623774805
+transform 1 0 4691 0 1 742
+box -1957 -254 1957 254
+use sky130_fd_pr__nfet_01v8_MUHGM9  sky130_fd_pr__nfet_01v8_MUHGM9_0
+timestamp 1623774805
+transform 1 0 3861 0 1 285
+box -1127 -285 1127 285
+use sky130_fd_pr__nfet_01v8_YCGG98  sky130_fd_pr__nfet_01v8_YCGG98_0
+timestamp 1623774805
+transform 1 0 6355 0 1 285
+box -1367 -285 1367 285
+use sky130_fd_pr__pfet_01v8_4ML9WA  sky130_fd_pr__pfet_01v8_4ML9WA_0
+timestamp 1623774805
+transform 1 0 5228 0 1 1630
+box -2457 -634 2457 634
+use sky130_fd_pr__nfet_01v8_YCGG98  sky130_fd_pr__nfet_01v8_YCGG98_1
+timestamp 1623774805
+transform -1 0 1367 0 1 285
+box -1367 -285 1367 285
+use sky130_fd_pr__nfet_01v8_YCGG98  sky130_fd_pr__nfet_01v8_YCGG98_2
+timestamp 1623774805
+transform -1 0 1367 0 -1 711
+box -1367 -285 1367 285
+use sky130_fd_pr__pfet_01v8_ND88ZC  sky130_fd_pr__pfet_01v8_ND88ZC_1
+timestamp 1623774805
+transform -1 0 1367 0 1 2523
+box -1367 -369 1367 369
+use sky130_fd_pr__pfet_01v8_ND88ZC  sky130_fd_pr__pfet_01v8_ND88ZC_0
+timestamp 1623774805
+transform 1 0 6355 0 1 2523
+box -1367 -369 1367 369
+use sky130_fd_pr__pfet_01v8_NKZXKB  sky130_fd_pr__pfet_01v8_NKZXKB_0
+timestamp 1623774805
+transform 1 0 3861 0 1 2523
+box -1127 -369 1127 369
+<< labels >>
+rlabel metal2 4957 243 5038 435 1 nswitch
+rlabel metal2 4950 2300 5034 2641 1 pswitch
+rlabel poly 3222 382 3540 652 1 Down
+rlabel metal2 6953 348 7581 2395 1 out
+rlabel poly 3894 382 4788 448 1 nDown
+rlabel poly 3894 2276 4788 2347 1 Up
+rlabel metal1 2676 2224 2780 2775 1 biasp
+rlabel metal1 0 2856 7722 2918 1 vdd
+rlabel metal1 0 -26 7722 36 1 vss
+rlabel metal1 210 452 2524 544 1 iref
+rlabel poly 3216 2084 3540 2342 1 nUp
+<< end >>

diff --git a/mag/clock_inverter.mag b/mag/clock_inverter.mag
new file mode 100644
index 0000000..84291be
--- /dev/null
+++ b/mag/clock_inverter.mag

@@ -0,0 +1,89 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623799048
+<< metal1 >>
+rect 520 2998 530 3028
+rect 0 2944 530 2998
+rect 520 2914 530 2944
+rect 714 2998 724 3028
+rect 714 2944 1244 2998
+rect 714 2914 724 2944
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 442 2259 848 2325
+rect 1054 2070 1100 2523
+rect 0 1504 1244 1564
+rect 221 804 226 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 221 743 226 748
+rect 478 743 720 809
+rect 1094 307 1152 1328
+rect 520 124 530 154
+rect 0 70 530 124
+rect 520 40 530 70
+rect 714 124 724 154
+rect 714 70 1244 124
+rect 714 40 724 70
+<< via1 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal2 >>
+rect 530 3028 714 3038
+rect 530 2904 714 2914
+rect 220 2320 334 2330
+rect 220 2254 334 2264
+rect 220 804 334 814
+rect 220 738 334 748
+rect 530 154 714 164
+rect 530 30 714 40
+<< via2 >>
+rect 530 2914 714 3028
+rect 220 2264 334 2320
+rect 220 748 334 804
+rect 530 40 714 154
+<< metal3 >>
+rect 520 3028 724 3033
+rect 520 2914 530 3028
+rect 714 2914 724 3028
+rect 520 2909 724 2914
+rect 210 2320 344 2325
+rect 210 2264 220 2320
+rect 334 2264 344 2320
+rect 210 2259 344 2264
+rect 247 809 307 2259
+rect 210 804 344 809
+rect 210 748 220 804
+rect 334 748 344 804
+rect 210 743 344 748
+rect 586 159 658 2909
+rect 520 154 724 159
+rect 520 40 530 154
+rect 714 40 724 154
+rect 520 35 724 40
+use inverter_cp_x1  inverter_cp_x1_1 
+timestamp 1623798692
+transform 1 0 0 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1  inverter_cp_x1_2
+timestamp 1623798692
+transform 1 0 622 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1  inverter_cp_x1_0
+timestamp 1623798692
+transform 1 0 0 0 -1 776
+box 0 -758 622 776
+use trans_gate  trans_gate_0
+timestamp 1623610677
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
+<< labels >>
+rlabel metal1 0 1504 1244 1564 1 vss
+rlabel metal1 0 2944 1244 2998 1 vdd
+rlabel metal3 247 1504 307 1564 1 CLK
+rlabel metal1 1054 2070 1100 2523 1 CLK_d
+rlabel metal1 1094 307 1152 1328 1 nCLK_d
+<< end >>

diff --git a/mag/csvco_branch.mag b/mag/csvco_branch.mag
new file mode 100644
index 0000000..7fceea7
--- /dev/null
+++ b/mag/csvco_branch.mag

@@ -0,0 +1,265 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623248172
+<< nwell >>
+rect -363 1865 931 1954
+rect -363 1858 911 1865
+rect -363 1835 -280 1858
+<< pwell >>
+rect 500 321 931 387
+rect 922 -121 931 321
+rect 500 -193 931 -121
+rect 924 -226 931 -193
+rect -354 -904 929 -869
+rect -363 -1001 929 -904
+rect -363 -1002 -231 -1001
+rect 799 -1002 929 -1001
+<< psubdiff >>
+rect 608 -174 632 -140
+rect 790 -174 814 -140
+rect -255 -966 -231 -932
+rect 799 -966 823 -932
+<< nsubdiff >>
+rect -255 1884 -231 1918
+rect 799 1884 823 1918
+<< psubdiffcont >>
+rect 632 -174 790 -140
+rect -231 -966 799 -932
+<< nsubdiffcont >>
+rect -231 1884 799 1918
+<< viali >>
+rect -327 1884 -231 1918
+rect -231 1884 799 1918
+rect 799 1884 895 1918
+rect -327 1795 895 1829
+rect -327 1197 -293 1795
+rect 861 1197 895 1795
+rect -327 1163 895 1197
+rect 536 -85 886 -51
+rect 536 -174 632 -140
+rect 632 -174 790 -140
+rect 790 -174 886 -140
+rect -327 -263 895 -229
+rect -327 -843 -293 -263
+rect 861 -843 895 -263
+rect -327 -877 895 -843
+rect -327 -966 -231 -932
+rect -231 -966 799 -932
+rect 799 -966 895 -932
+<< metal1 >>
+rect -363 1918 931 1924
+rect -363 1884 -327 1918
+rect 895 1884 931 1918
+rect -363 1829 931 1884
+rect -363 1163 -327 1829
+rect -293 1789 861 1795
+rect -293 1203 -287 1789
+rect -180 1693 -170 1745
+rect 738 1693 748 1745
+rect -126 1636 -73 1646
+rect -219 1203 -173 1348
+rect -126 1346 -73 1356
+rect 65 1636 119 1646
+rect 65 1356 66 1636
+rect 257 1637 311 1646
+rect -27 1203 19 1351
+rect 65 1346 119 1356
+rect 165 1203 211 1358
+rect 310 1357 311 1637
+rect 450 1636 502 1646
+rect 257 1346 311 1357
+rect 357 1203 403 1360
+rect 642 1636 694 1646
+rect 450 1346 502 1356
+rect 549 1203 595 1360
+rect 642 1346 694 1356
+rect 741 1203 787 1359
+rect 855 1203 861 1789
+rect -293 1197 861 1203
+rect 895 1163 931 1829
+rect -363 1157 931 1163
+rect 68 1108 500 1157
+rect 209 897 261 907
+rect 209 607 261 617
+rect 68 361 78 413
+rect 286 361 296 413
+rect 356 361 366 413
+rect 490 361 500 413
+rect 631 361 641 413
+rect 693 361 703 413
+rect 209 167 261 177
+rect 644 173 690 361
+rect 772 89 818 556
+rect 209 27 261 37
+rect 619 8 629 60
+rect 733 8 743 60
+rect 500 -51 931 -45
+rect 500 -85 536 -51
+rect 886 -85 931 -51
+rect 500 -140 805 -85
+rect 861 -140 931 -85
+rect 500 -174 536 -140
+rect 886 -174 931 -140
+rect 68 -223 931 -174
+rect -363 -229 931 -223
+rect -363 -877 -327 -229
+rect -293 -269 861 -263
+rect -293 -837 -287 -269
+rect -219 -403 -173 -269
+rect -126 -413 -73 -403
+rect -27 -404 19 -269
+rect 165 -403 211 -269
+rect 357 -403 403 -269
+rect 549 -403 595 -269
+rect 741 -403 787 -269
+rect -126 -703 -73 -693
+rect 65 -413 119 -403
+rect 65 -693 66 -413
+rect 65 -703 119 -693
+rect 257 -412 311 -403
+rect 310 -692 311 -412
+rect 257 -703 311 -692
+rect 450 -413 502 -403
+rect 450 -703 502 -693
+rect 642 -413 694 -403
+rect 642 -703 694 -693
+rect -180 -793 -170 -741
+rect 738 -793 748 -741
+rect 855 -837 861 -269
+rect -293 -843 861 -837
+rect 895 -877 931 -229
+rect -363 -932 931 -877
+rect -363 -966 -327 -932
+rect 895 -966 931 -932
+rect -363 -972 931 -966
+<< via1 >>
+rect -170 1693 738 1745
+rect -126 1356 -73 1636
+rect 66 1356 119 1636
+rect 257 1357 310 1637
+rect 450 1356 502 1636
+rect 642 1356 694 1636
+rect 209 617 261 897
+rect 78 361 286 413
+rect 366 361 490 413
+rect 641 361 693 413
+rect 209 37 261 167
+rect 629 8 733 60
+rect 805 -140 861 -85
+rect 805 -141 861 -140
+rect -126 -693 -73 -413
+rect 66 -693 119 -413
+rect 257 -692 310 -412
+rect 450 -693 502 -413
+rect 642 -693 694 -413
+rect -170 -793 738 -741
+<< metal2 >>
+rect -180 1745 748 1755
+rect -180 1693 -170 1745
+rect 738 1693 748 1745
+rect -180 1683 748 1693
+rect -126 1636 -73 1646
+rect 66 1636 119 1646
+rect -73 1436 66 1563
+rect -126 1346 -73 1356
+rect 257 1637 310 1647
+rect 119 1436 257 1563
+rect 66 1346 119 1356
+rect 209 1357 257 1436
+rect 450 1636 502 1646
+rect 310 1436 450 1563
+rect 209 1347 310 1357
+rect 642 1636 694 1646
+rect 502 1436 642 1563
+rect 209 897 261 1347
+rect 450 1346 502 1356
+rect 642 1346 694 1356
+rect 639 1042 719 1046
+rect 831 1042 851 1046
+rect 209 607 261 617
+rect 78 413 286 423
+rect 68 361 78 413
+rect 78 351 286 361
+rect 366 413 490 423
+rect 641 413 693 423
+rect 490 361 641 413
+rect 693 361 931 413
+rect 366 351 490 361
+rect 641 351 693 361
+rect 209 167 261 177
+rect 209 -402 261 37
+rect 629 62 733 72
+rect 629 -4 733 6
+rect 805 -85 861 -75
+rect 805 -151 861 -141
+rect -126 -413 -73 -403
+rect 66 -413 119 -403
+rect -73 -613 66 -486
+rect -126 -703 -73 -693
+rect 209 -412 310 -402
+rect 209 -486 257 -412
+rect 119 -613 257 -486
+rect 66 -703 119 -693
+rect 450 -413 502 -403
+rect 310 -613 450 -486
+rect 257 -702 310 -692
+rect 642 -413 694 -403
+rect 502 -613 642 -486
+rect 450 -703 502 -693
+rect 642 -703 694 -693
+rect -180 -741 748 -731
+rect -180 -793 -170 -741
+rect 738 -793 748 -741
+rect -180 -802 748 -793
+rect -180 -803 738 -802
+<< via2 >>
+rect 719 990 831 1046
+rect 629 60 733 62
+rect 629 8 733 60
+rect 629 6 733 8
+rect 805 -141 861 -85
+<< metal3 >>
+rect 709 1046 863 1051
+rect 709 990 719 1046
+rect 831 990 863 1046
+rect 709 985 863 990
+rect 619 62 743 67
+rect 619 6 629 62
+rect 733 6 743 62
+rect 619 1 743 6
+rect 650 -194 710 1
+rect 803 -80 863 985
+rect 795 -85 871 -80
+rect 795 -141 805 -85
+rect 861 -141 871 -85
+rect 795 -146 871 -141
+use cap_vco  cap_vco_0
+timestamp 1623247475
+transform 1 0 5 0 1 528
+box 554 -6 926 514
+use inverter_csvco  inverter_csvco_0
+timestamp 1623162837
+transform 1 0 68 0 1 387
+box 0 -597 432 757
+use sky130_fd_pr__pfet_01v8_8DL6ZL  sky130_fd_pr__pfet_01v8_8DL6ZL_0
+timestamp 1622843784
+transform -1 0 284 0 -1 1496
+box -647 -369 647 369
+use sky130_fd_pr__nfet_01v8_7H8F5S  sky130_fd_pr__nfet_01v8_7H8F5S_0
+timestamp 1622843784
+transform 1 0 284 0 -1 -553
+box -647 -360 647 360
+use sky130_fd_pr__nfet_01v8_EDT3AT  sky130_fd_pr__nfet_01v8_EDT3AT_0
+timestamp 1623244079
+transform 1 0 711 0 1 100
+box -211 -221 211 221
+<< labels >>
+rlabel metal1 -363 1829 931 1884 1 vdd
+rlabel metal1 -363 -932 931 -877 1 vss
+rlabel metal2 -180 -803 -170 -731 1 vctrl
+rlabel metal2 -180 1683 -170 1755 1 vbp
+rlabel metal2 68 361 78 413 1 in
+rlabel metal3 650 -194 710 6 1 D0
+rlabel metal2 693 361 931 413 1 out
+<< end >>

diff --git a/mag/dff_pfd.mag b/mag/dff_pfd.mag
new file mode 100644
index 0000000..2cd12a0
--- /dev/null
+++ b/mag/dff_pfd.mag

@@ -0,0 +1,88 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623456247
+<< metal1 >>
+rect 0 1180 2872 1234
+rect 0 652 210 718
+rect 545 714 846 718
+rect 545 662 791 714
+rect 895 662 905 714
+rect 1438 662 1448 714
+rect 1552 662 1562 714
+rect 545 652 846 662
+rect 1979 652 2308 718
+rect 1234 572 1244 624
+rect 1348 572 1358 624
+rect 256 497 266 549
+rect 370 497 380 549
+rect 896 472 906 524
+rect 1010 472 1020 524
+rect 1616 481 1626 533
+rect 1730 481 1740 533
+rect 2154 436 2220 557
+rect 2680 481 2690 533
+rect 2794 481 2804 533
+rect 1949 380 1959 432
+rect 2063 380 2073 432
+rect 2149 332 2159 436
+rect 2211 332 2221 436
+rect 2154 329 2220 332
+rect 0 70 2872 124
+<< via1 >>
+rect 791 662 895 714
+rect 1448 662 1552 714
+rect 1244 572 1348 624
+rect 266 497 370 549
+rect 906 472 1010 524
+rect 1626 481 1730 533
+rect 2690 481 2794 533
+rect 1959 380 2063 432
+rect 2159 332 2211 436
+<< metal2 >>
+rect 791 714 895 724
+rect 1448 714 1552 724
+rect 895 662 1448 714
+rect 791 652 895 662
+rect 1448 652 1552 662
+rect 1244 624 1348 634
+rect 266 572 1244 624
+rect 1348 572 2872 624
+rect 266 549 370 572
+rect 1244 562 1348 572
+rect 266 487 370 497
+rect 906 524 1010 534
+rect 906 462 1010 472
+rect 1626 533 2794 543
+rect 1730 491 2690 533
+rect 1626 471 1730 481
+rect 2690 471 2794 481
+rect 931 432 983 462
+rect 1959 432 2063 442
+rect 931 380 1959 432
+rect 1959 370 2063 380
+rect 2159 436 2211 446
+rect 2159 322 2211 332
+use nor_pfd  nor_pfd_0
+timestamp 1623456049
+transform 1 0 235 0 1 -468
+box -235 468 483 1772
+use nor_pfd  nor_pfd_1
+timestamp 1623456049
+transform 1 0 953 0 1 -468
+box -235 468 483 1772
+use nor_pfd  nor_pfd_2
+timestamp 1623456049
+transform 1 0 1671 0 1 -468
+box -235 468 483 1772
+use nor_pfd  nor_pfd_3
+timestamp 1623456049
+transform 1 0 2389 0 1 -468
+box -235 468 483 1772
+<< labels >>
+rlabel metal1 0 652 210 718 1 CLK
+rlabel metal1 0 1180 2872 1234 1 vdd
+rlabel metal1 0 70 2872 124 1 vss
+rlabel metal2 2768 572 2872 624 1 Q
+rlabel via1 2159 332 2211 436 1 Reset
+<< end >>

diff --git a/mag/div_by_2.mag b/mag/div_by_2.mag
new file mode 100644
index 0000000..f0ce90a
--- /dev/null
+++ b/mag/div_by_2.mag

@@ -0,0 +1,204 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623948030
+<< nwell >>
+rect 2984 2989 4228 3068
+rect 3203 118 4219 142
+rect 3203 84 4228 118
+rect 3203 83 4219 84
+rect 3203 79 4228 83
+rect 2984 0 4228 79
+<< pwell >>
+rect 2983 1339 4228 1819
+<< locali >>
+rect 1986 2123 2002 2157
+rect 2224 2123 2240 2157
+<< metal1 >>
+rect 2984 3022 4228 3038
+rect 2947 2998 4228 3022
+rect -1244 2957 4228 2998
+rect -1244 2944 3720 2957
+rect 2947 2931 3720 2944
+rect 2986 2918 3533 2931
+rect -190 2228 -180 2356
+rect -116 2228 -106 2356
+rect 2984 2267 2994 2323
+rect 3218 2267 3228 2323
+rect 3352 2253 3753 2333
+rect 4061 2249 4228 2327
+rect 1990 2121 2000 2173
+rect 2226 2121 2236 2173
+rect 1990 2117 2236 2121
+rect 2915 1848 2984 1864
+rect 2915 1825 3020 1848
+rect 2915 1730 4224 1825
+rect 2915 1700 4228 1730
+rect -1244 1498 1313 1570
+rect 2915 1369 3020 1700
+rect 3412 1369 3726 1700
+rect 2915 1339 4228 1369
+rect 2915 1321 3726 1339
+rect 2915 1282 3556 1321
+rect 2915 1266 3130 1282
+rect 2915 1246 3020 1266
+rect 2915 1204 2984 1246
+rect 1992 947 2238 951
+rect 1992 895 2002 947
+rect 2228 895 2238 947
+rect -150 712 -140 840
+rect -76 712 -66 840
+rect 2981 748 2991 804
+rect 3215 748 3225 804
+rect 3352 736 3753 816
+rect 4061 742 4228 820
+rect 2915 148 4220 164
+rect 2915 30 4228 148
+<< via1 >>
+rect -180 2228 -116 2356
+rect 2994 2267 3218 2323
+rect 2000 2121 2226 2173
+rect 2002 895 2228 947
+rect -140 712 -76 840
+rect 2991 748 3215 804
+<< metal2 >>
+rect -180 2356 -116 2366
+rect -180 2218 -116 2228
+rect 2081 2321 2145 2331
+rect 2000 2173 2081 2183
+rect 2994 2323 3218 2333
+rect 2994 2257 3218 2267
+rect 2145 2173 2226 2183
+rect 2000 2111 2226 2121
+rect 250 1569 306 1579
+rect 2555 1570 2611 1580
+rect 306 1477 2555 1549
+rect 306 1475 323 1477
+rect 250 1447 306 1457
+rect 2611 1477 2621 1549
+rect 2555 1448 2611 1458
+rect 2002 947 2228 957
+rect 2002 885 2083 895
+rect -140 840 -76 850
+rect 2147 885 2228 895
+rect 2083 734 2147 744
+rect 2991 804 3215 814
+rect 2991 738 3215 748
+rect -140 702 -76 712
+<< via2 >>
+rect -180 2228 -116 2356
+rect 2081 2173 2145 2321
+rect 2994 2267 3218 2323
+rect 2081 2121 2145 2173
+rect 250 1457 306 1569
+rect 2555 1458 2611 1570
+rect 2083 895 2147 900
+rect -140 712 -76 840
+rect 2083 744 2147 895
+rect 2991 748 3215 804
+<< metal3 >>
+rect -190 2356 -106 2361
+rect -997 804 -937 2264
+rect -190 2228 -180 2356
+rect -116 2228 -106 2356
+rect -190 2223 -106 2228
+rect 2071 2321 2155 2326
+rect 2071 2121 2081 2321
+rect 2145 2121 2155 2321
+rect 2763 2325 2823 2474
+rect 2984 2325 3228 2328
+rect 2763 2323 3246 2325
+rect 2763 2267 2994 2323
+rect 3218 2267 3246 2323
+rect 2763 2265 3246 2267
+rect 2071 2116 2155 2121
+rect 2553 1575 2613 2258
+rect 240 1569 316 1574
+rect 240 1457 250 1569
+rect 306 1457 316 1569
+rect 240 1452 316 1457
+rect 2545 1570 2621 1575
+rect 2545 1458 2555 1570
+rect 2611 1458 2621 1570
+rect 2545 1453 2621 1458
+rect 2073 945 2157 950
+rect -150 840 -66 845
+rect -150 712 -140 840
+rect -76 712 -66 840
+rect 2073 744 2083 945
+rect 2147 744 2157 945
+rect 2073 739 2157 744
+rect -150 707 -66 712
+rect 2553 596 2613 1453
+rect 2763 810 2823 2265
+rect 2984 2262 3228 2265
+rect 2981 808 3225 809
+rect 2977 804 3225 808
+rect 2977 748 2991 804
+rect 3215 748 3225 804
+rect 2977 743 3225 748
+rect 2977 596 3037 743
+rect 2528 536 3037 596
+<< via3 >>
+rect -180 2228 -116 2356
+rect 2081 2121 2145 2321
+rect -140 712 -76 840
+rect 2083 900 2147 945
+rect 2083 744 2147 900
+<< metal4 >>
+rect -181 2356 -115 2357
+rect -181 2228 -180 2356
+rect -116 2324 -115 2356
+rect -116 2322 2139 2324
+rect -116 2321 2146 2322
+rect -116 2260 2081 2321
+rect -116 2228 -115 2260
+rect -181 2227 -115 2228
+rect 2080 2121 2081 2260
+rect 2145 2121 2146 2321
+rect 2080 2120 2146 2121
+rect 2082 945 2148 946
+rect -141 840 -75 841
+rect -141 712 -140 840
+rect -76 808 -75 840
+rect 2082 808 2083 945
+rect -76 744 2083 808
+rect 2147 744 2148 945
+rect -76 712 -75 744
+rect 2082 743 2148 744
+rect -141 711 -75 712
+use DFlipFlop  DFlipFlop_0
+timestamp 1623898709
+transform 1 0 1244 0 -1 3068
+box -1244 0 1740 3068
+use clock_inverter  clock_inverter_0
+timestamp 1623799048
+transform 1 0 -1244 0 1 0
+box 0 0 1244 3068
+use inverter_min_x2  inverter_min_x2_0
+timestamp 1623898709
+transform 1 0 3037 0 -1 723
+box -53 -615 473 655
+use inverter_min_x2  inverter_min_x2_1
+timestamp 1623898709
+transform 1 0 3037 0 1 2345
+box -53 -615 473 655
+use inverter_min_x4  inverter_min_x4_0
+timestamp 1623895985
+transform 1 0 3563 0 1 2346
+box -53 -616 665 643
+use inverter_min_x4  inverter_min_x4_1
+timestamp 1623895985
+transform 1 0 3563 0 -1 723
+box -53 -616 665 643
+<< labels >>
+rlabel metal1 -1244 2944 2984 2998 1 vdd
+rlabel metal1 -1244 1498 1313 1570 1 vss
+rlabel metal3 -997 1498 -937 1570 1 CLK
+rlabel metal3 2553 1570 2613 2258 1 nout_div
+rlabel metal3 2763 810 2823 2474 1 out_div
+rlabel metal1 4061 2249 4228 2327 1 CLK_2
+rlabel metal1 3352 2253 3753 2333 1 o1
+rlabel metal1 3352 736 3753 816 1 o2
+rlabel metal1 4061 742 4228 820 1 nCLK_2
+<< end >>

diff --git a/mag/div_by_5.mag b/mag/div_by_5.mag
new file mode 100644
index 0000000..37d560d
--- /dev/null
+++ b/mag/div_by_5.mag

@@ -0,0 +1,363 @@
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+<< nwell >>
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+rect 12333 884 12343 948
+rect 12583 884 12593 948
+rect 12333 879 12593 884
+<< via3 >>
+rect 1997 2120 2237 2184
+rect 5537 2120 5777 2184
+rect 9365 2120 9605 2184
+rect 12349 2120 12589 2184
+rect 1991 884 2231 948
+rect 5531 884 5771 948
+rect 9359 884 9599 948
+rect 12343 884 12583 948
+<< metal4 >>
+rect 1996 2184 12590 2185
+rect 1996 2120 1997 2184
+rect 2237 2120 5537 2184
+rect 5777 2120 9365 2184
+rect 9605 2120 12349 2184
+rect 12589 2120 12590 2184
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+rect 1990 948 12584 949
+rect 1990 884 1991 948
+rect 2231 884 5531 948
+rect 5771 884 9359 948
+rect 9599 884 12343 948
+rect 12583 884 12584 948
+rect 1990 883 12584 884
+use DFlipFlop  DFlipFlop_3
+timestamp 1623898709
+transform 1 0 11596 0 -1 3068
+box -1244 0 1740 3068
+use DFlipFlop  DFlipFlop_1
+timestamp 1623898709
+transform 1 0 4784 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop  DFlipFlop_2
+timestamp 1623898709
+transform 1 0 8612 0 1 0
+box -1244 0 1740 3068
+use DFlipFlop  DFlipFlop_0
+timestamp 1623898709
+transform 1 0 1244 0 1 0
+box -1244 0 1740 3068
+use sky130_fd_sc_hs__or2_1  sky130_fd_sc_hs__or2_1_0
+timestamp 1622592543
+transform 1 0 13374 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__and2_1  sky130_fd_sc_hs__and2_1_0
+timestamp 1622592543
+transform 1 0 -518 0 1 1960
+box -38 -49 518 715
+use sky130_fd_sc_hs__xor2_1  sky130_fd_sc_hs__xor2_1_0
+timestamp 1622592543
+transform -1 0 7330 0 1 1960
+box -38 -49 806 715
+use sky130_fd_sc_hs__and2_1  sky130_fd_sc_hs__and2_1_1
+timestamp 1622592543
+transform 1 0 3022 0 -1 1108
+box -38 -49 518 715
+<< labels >>
+rlabel metal2 7175 2568 10572 2700 1 Q1
+rlabel metal1 6263 2308 7075 2367 1 Q0
+rlabel metal1 -556 1370 0 1698 1 vss
+rlabel metal1 2652 701 3023 760 1 nQ2
+rlabel metal4 5771 883 9359 949 1 CLK
+rlabel metal4 5777 2119 9365 2185 1 nCLK
+rlabel metal1 -556 2904 13892 3038 1 vdd
+rlabel viali 13765 2324 13836 2537 1 CLK_5
+rlabel metal2 3237 1518 6095 1594 1 nQ0
+rlabel metal2 13089 2464 13529 2540 1 Q1_shift
+<< end >>

diff --git a/mag/inverter_cp_x1.mag b/mag/inverter_cp_x1.mag
new file mode 100644
index 0000000..9863834
--- /dev/null
+++ b/mag/inverter_cp_x1.mag

@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623798692
+<< nwell >>
+rect 0 688 622 776
+<< pwell >>
+rect 2 -669 622 -626
+rect 0 -721 622 -669
+rect 2 -722 622 -721
+rect 0 -758 622 -722
+<< psubdiff >>
+rect 108 -722 132 -688
+rect 490 -722 514 -688
+<< nsubdiff >>
+rect 108 706 132 740
+rect 490 706 514 740
+<< psubdiffcont >>
+rect 132 -722 490 -688
+<< nsubdiffcont >>
+rect 132 706 490 740
+<< poly >>
+rect 278 33 344 188
+rect 210 17 344 33
+rect 210 -17 226 17
+rect 328 -17 344 17
+rect 210 -33 344 -17
+rect 278 -184 344 -33
+<< polycont >>
+rect 226 -17 328 17
+<< locali >>
+rect 210 -17 226 17
+rect 328 -17 344 17
+<< viali >>
+rect 36 706 132 740
+rect 132 706 490 740
+rect 490 706 586 740
+rect 36 618 586 652
+rect 226 -17 328 17
+rect 36 -634 586 -600
+rect 36 -722 132 -688
+rect 132 -722 490 -688
+rect 490 -722 586 -688
+<< metal1 >>
+rect 0 740 622 746
+rect 0 706 36 740
+rect 586 706 622 740
+rect 0 652 622 706
+rect 0 618 36 652
+rect 586 618 622 652
+rect 0 612 622 618
+rect 144 469 190 612
+rect 336 469 382 612
+rect 240 173 286 231
+rect 432 173 478 222
+rect 240 127 478 173
+rect 210 17 344 33
+rect 210 -17 226 17
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+rect 210 -33 344 -17
+rect 432 -118 478 127
+rect 240 -164 478 -118
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+rect 144 -594 190 -455
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+rect 0 -600 622 -594
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+rect 586 -634 622 -600
+rect 0 -688 622 -634
+rect 0 -722 36 -688
+rect 586 -722 622 -688
+rect 0 -728 622 -722
+use sky130_fd_pr__pfet_01v8_7KT7MH  sky130_fd_pr__pfet_01v8_7KT7MH_0
+timestamp 1623610677
+transform 1 0 311 0 1 344
+box -311 -344 311 344
+use sky130_fd_pr__nfet_01v8_2BS6QM  sky130_fd_pr__nfet_01v8_2BS6QM_0
+timestamp 1623610677
+transform 1 0 311 0 1 -335
+box -311 -335 311 335
+<< labels >>
+rlabel metal1 0 652 622 706 1 vdd
+rlabel metal1 0 -688 622 -634 1 vss
+rlabel metal1 210 -33 226 33 1 in
+rlabel metal1 432 -210 478 222 1 out
+<< end >>

diff --git a/mag/inverter_cp_x2.mag b/mag/inverter_cp_x2.mag
new file mode 100644
index 0000000..917203f
--- /dev/null
+++ b/mag/inverter_cp_x2.mag

@@ -0,0 +1,96 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623355426
+<< nwell >>
+rect 0 0 910 776
+<< pwell >>
+rect 0 -758 910 0
+<< psubdiff >>
+rect 108 -722 132 -688
+rect 778 -722 802 -688
+<< nsubdiff >>
+rect 108 706 132 740
+rect 778 706 802 740
+<< psubdiffcont >>
+rect 132 -722 778 -688
+<< nsubdiffcont >>
+rect 132 706 778 740
+<< poly >>
+rect 200 124 710 190
+rect 422 27 488 124
+rect 422 -27 432 27
+rect 478 -27 488 27
+rect 422 -118 488 -27
+rect 200 -184 710 -118
+<< polycont >>
+rect 432 -27 478 27
+<< locali >>
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+rect 422 -27 428 27
+rect 482 -27 488 27
+rect 422 -43 488 -27
+<< viali >>
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+rect 132 706 778 740
+rect 778 706 874 740
+rect 36 618 874 652
+rect 428 -27 432 27
+rect 432 -27 478 27
+rect 478 -27 482 27
+rect 36 -634 874 -600
+rect 36 -722 132 -688
+rect 132 -722 778 -688
+rect 778 -722 874 -688
+<< metal1 >>
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+rect 0 652 910 706
+rect 0 618 36 652
+rect 874 618 910 652
+rect 0 612 910 618
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+rect 720 33 766 139
+rect 0 27 494 33
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+rect 0 -600 910 -594
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+rect 874 -634 910 -600
+rect 0 -688 910 -634
+rect 0 -722 36 -688
+rect 874 -722 910 -688
+rect 0 -728 910 -722
+use sky130_fd_pr__pfet_01v8_XJXT7S  sky130_fd_pr__pfet_01v8_XJXT7S_0
+timestamp 1623353110
+transform 1 0 455 0 1 344
+box -455 -344 455 344
+use sky130_fd_pr__nfet_01v8_AZESM8  sky130_fd_pr__nfet_01v8_AZESM8_0
+timestamp 1623353949
+transform 1 0 455 0 1 -335
+box -455 -335 455 335
+<< labels >>
+rlabel metal1 0 -33 428 33 1 in
+rlabel metal1 720 -33 910 33 1 out
+rlabel metal1 0 -688 910 -634 1 vss
+rlabel metal1 0 652 910 706 1 vdd
+<< end >>

diff --git a/mag/inverter_csvco.mag b/mag/inverter_csvco.mag
new file mode 100644
index 0000000..ffe9576
--- /dev/null
+++ b/mag/inverter_csvco.mag

@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623162837
+<< nwell >>
+rect 0 668 432 757
+rect 197 47 231 131
+<< pwell >>
+rect 0 -508 430 -438
+rect 0 -597 432 -508
+<< psubdiff >>
+rect 108 -561 132 -527
+rect 300 -561 324 -527
+<< nsubdiff >>
+rect 108 687 132 721
+rect 300 687 324 721
+<< psubdiffcont >>
+rect 132 -561 300 -527
+<< nsubdiffcont >>
+rect 132 687 300 721
+<< poly >>
+rect 183 51 249 131
+rect 183 -51 197 51
+rect 231 -51 249 51
+rect 183 -122 249 -51
+<< polycont >>
+rect 197 -51 231 51
+<< locali >>
+rect 197 51 231 67
+rect 197 -67 231 -51
+<< viali >>
+rect 35 687 132 721
+rect 132 687 300 721
+rect 300 687 395 721
+rect 36 598 396 632
+rect 197 -51 231 51
+rect 36 -472 396 -438
+rect 36 -561 132 -527
+rect 132 -561 300 -527
+rect 300 -561 396 -527
+<< metal1 >>
+rect 0 721 432 727
+rect 0 687 35 721
+rect 395 687 432 721
+rect 0 632 432 687
+rect 0 598 36 632
+rect 396 598 432 632
+rect 0 592 432 598
+rect 144 220 190 520
+rect 185 51 243 57
+rect 185 26 197 51
+rect 0 -26 197 26
+rect 185 -51 197 -26
+rect 231 -51 243 51
+rect 185 -57 243 -51
+rect 288 26 334 520
+rect 288 -26 432 26
+rect 144 -360 190 -210
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+rect 0 -438 432 -432
+rect 0 -472 36 -438
+rect 396 -472 432 -438
+rect 0 -527 432 -472
+rect 0 -561 36 -527
+rect 396 -561 432 -527
+rect 0 -567 432 -561
+use sky130_fd_pr__nfet_01v8_AQR2CW  sky130_fd_pr__nfet_01v8_AQR2CW_0
+timestamp 1623162482
+transform 1 0 216 0 1 -254
+box -216 -254 216 254
+use sky130_fd_pr__pfet_01v8_HRYSXS  sky130_fd_pr__pfet_01v8_HRYSXS_0
+timestamp 1623162482
+transform 1 0 216 0 1 334
+box -216 -334 216 334
+<< labels >>
+rlabel metal1 0 -26 197 26 1 in
+rlabel metal1 288 -26 432 26 1 out
+rlabel metal1 0 632 432 687 1 vbulkp
+rlabel metal1 0 -527 432 -472 1 vbulkn
+rlabel metal1 144 220 190 520 1 vdd
+rlabel metal1 144 -360 190 -210 1 vss
+<< end >>

diff --git a/mag/inverter_min_x2.mag b/mag/inverter_min_x2.mag
new file mode 100644
index 0000000..73e8311
--- /dev/null
+++ b/mag/inverter_min_x2.mag

@@ -0,0 +1,88 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623898709
+<< nwell >>
+rect -53 551 473 655
+rect 24 543 385 551
+rect 29 539 371 543
+<< psubdiff >>
+rect 55 -609 79 -575
+rect 341 -609 365 -575
+<< nsubdiff >>
+rect 55 571 79 605
+rect 341 571 365 605
+<< psubdiffcont >>
+rect 79 -609 341 -575
+<< nsubdiffcont >>
+rect 79 571 341 605
+<< poly >>
+rect 147 91 273 140
+rect 147 -8 206 91
+rect 147 -94 159 -8
+rect 194 -94 206 -8
+rect 147 -188 206 -94
+rect 147 -237 273 -188
+<< polycont >>
+rect 159 -94 194 -8
+<< locali >>
+rect 143 -8 210 8
+rect 143 -94 159 -8
+rect 194 -94 210 -8
+rect 143 -110 210 -94
+<< viali >>
+rect -17 571 79 605
+rect 79 571 341 605
+rect 341 571 437 605
+rect -17 483 437 517
+rect 159 -94 194 -8
+rect -17 -521 437 -487
+rect -17 -609 79 -575
+rect 79 -609 341 -575
+rect 341 -609 437 -575
+<< metal1 >>
+rect -53 605 473 611
+rect -53 571 -17 605
+rect 437 571 473 605
+rect -53 517 473 571
+rect -53 483 -17 517
+rect 437 483 473 517
+rect -53 476 473 483
+rect 91 128 137 334
+rect 186 166 233 476
+rect 315 128 363 334
+rect 91 74 363 128
+rect 153 -8 200 4
+rect 153 -26 159 -8
+rect -53 -80 159 -26
+rect 153 -94 159 -80
+rect 194 -94 200 -8
+rect 153 -106 200 -94
+rect 315 -26 363 74
+rect 315 -80 473 -26
+rect 315 -166 363 -80
+rect 91 -220 363 -166
+rect 91 -347 137 -220
+rect 186 -481 233 -262
+rect 315 -351 363 -220
+rect -53 -487 473 -481
+rect -53 -521 -17 -487
+rect 437 -521 473 -487
+rect -53 -575 473 -521
+rect -53 -609 -17 -575
+rect 437 -609 473 -575
+rect -53 -615 473 -609
+use sky130_fd_pr__pfet_01v8_ZPB9BB  sky130_fd_pr__pfet_01v8_ZPB9BB_0
+timestamp 1623427962
+transform 1 0 210 0 1 250
+box -263 -303 263 303
+use sky130_fd_pr__nfet_01v8_5RJ8EK  sky130_fd_pr__nfet_01v8_5RJ8EK_0
+timestamp 1623427697
+transform 1 0 210 0 1 -305
+box -263 -252 263 252
+<< labels >>
+rlabel metal1 -53 -80 159 -26 1 in
+rlabel metal1 315 -80 473 -26 1 out
+rlabel metal1 -53 517 473 571 1 vdd
+rlabel metal1 -53 -575 473 -521 1 vss
+<< end >>

diff --git a/mag/inverter_min_x4.mag b/mag/inverter_min_x4.mag
new file mode 100644
index 0000000..d177d97
--- /dev/null
+++ b/mag/inverter_min_x4.mag

@@ -0,0 +1,92 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623895985
+<< nwell >>
+rect -53 531 665 643
+<< psubdiff >>
+rect 55 -610 79 -576
+rect 533 -610 557 -576
+<< nsubdiff >>
+rect 55 571 79 605
+rect 533 571 557 605
+<< psubdiffcont >>
+rect 79 -610 533 -576
+<< nsubdiffcont >>
+rect 79 571 533 605
+<< poly >>
+rect 147 360 465 417
+rect 147 83 465 140
+rect 147 10 300 83
+rect 147 -123 190 10
+rect 258 -123 300 10
+rect 147 -181 300 -123
+rect 147 -238 465 -181
+rect 147 -430 465 -373
+<< polycont >>
+rect 190 -123 258 10
+<< locali >>
+rect 174 10 274 26
+rect 174 -123 190 10
+rect 258 -123 274 10
+rect 174 -139 274 -123
+<< viali >>
+rect -17 571 79 605
+rect 79 571 533 605
+rect 533 571 629 605
+rect -17 483 629 517
+rect 190 -123 258 10
+rect -18 -521 629 -487
+rect -18 -610 79 -576
+rect 79 -610 533 -576
+rect 533 -610 629 -576
+<< metal1 >>
+rect -53 605 665 611
+rect -53 571 -17 605
+rect 629 571 665 605
+rect -53 517 665 571
+rect -53 483 -17 517
+rect 629 483 665 517
+rect -53 477 665 483
+rect 88 129 137 334
+rect 172 165 248 477
+rect 281 129 330 333
+rect 364 165 440 477
+rect 498 129 574 334
+rect 88 59 574 129
+rect 184 10 264 22
+rect 184 -13 190 10
+rect -53 -93 190 -13
+rect 184 -123 190 -93
+rect 258 -123 264 10
+rect 184 -135 264 -123
+rect 498 -19 574 59
+rect 498 -97 665 -19
+rect 498 -165 574 -97
+rect 90 -232 574 -165
+rect 90 -347 139 -232
+rect 172 -481 248 -263
+rect 282 -348 331 -232
+rect 364 -481 440 -263
+rect 498 -347 574 -232
+rect -53 -487 665 -481
+rect -53 -521 -18 -487
+rect 629 -521 665 -487
+rect -53 -576 665 -521
+rect -53 -610 -18 -576
+rect 629 -610 665 -576
+rect -53 -616 665 -610
+use sky130_fd_pr__nfet_01v8_DXA56D  sky130_fd_pr__nfet_01v8_DXA56D_0
+timestamp 1623431064
+transform 1 0 306 0 1 -305
+box -359 -252 359 252
+use sky130_fd_pr__pfet_01v8_ZP3U9B  sky130_fd_pr__pfet_01v8_ZP3U9B_0
+timestamp 1623431064
+transform 1 0 306 0 1 250
+box -359 -303 359 303
+<< labels >>
+rlabel metal1 -53 -576 665 -521 1 vss
+rlabel metal1 -53 -93 190 -13 1 in
+rlabel metal1 498 -97 665 -19 1 out
+rlabel metal1 -53 517 665 571 1 vdd
+<< end >>

diff --git a/mag/latch_diff.mag b/mag/latch_diff.mag
new file mode 100644
index 0000000..c3608e0
--- /dev/null
+++ b/mag/latch_diff.mag

@@ -0,0 +1,251 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623798783
+<< nwell >>
+rect -33 2264 526 2352
+rect -33 2261 525 2264
+rect -33 2137 307 2261
+rect -33 1900 340 2137
+rect -33 1576 526 1900
+rect -33 -1 526 60
+rect -33 -628 0 -1
+rect -33 -716 526 -628
+<< pwell >>
+rect -33 1030 0 1576
+rect -33 967 503 1030
+rect -33 669 526 967
+rect -33 668 503 669
+rect -33 60 0 668
+<< psubdiff >>
+rect 36 1506 434 1540
+rect 36 563 70 1027
+rect 453 1002 555 1036
+rect 424 600 633 634
+rect 36 130 70 182
+rect 36 96 613 130
+<< nsubdiff >>
+rect 107 2282 131 2316
+rect 393 2282 417 2316
+rect 108 -680 132 -646
+rect 394 -680 418 -646
+<< nsubdiffcont >>
+rect 131 2282 393 2316
+rect 132 -680 394 -646
+<< poly >>
+rect 99 1807 230 1824
+rect 99 1773 124 1807
+rect 192 1773 230 1807
+rect 99 1758 230 1773
+rect 296 -137 427 -122
+rect 296 -171 334 -137
+rect 402 -171 427 -137
+rect 296 -188 427 -171
+<< polycont >>
+rect 124 1773 192 1807
+rect 334 -171 402 -137
+<< locali >>
+rect 108 1773 124 1807
+rect 192 1773 208 1807
+rect 70 1506 434 1540
+rect 70 96 434 130
+rect 318 -171 334 -137
+rect 402 -171 418 -137
+<< viali >>
+rect 36 2282 131 2316
+rect 131 2282 393 2316
+rect 393 2282 490 2316
+rect 36 2194 490 2228
+rect 124 1773 192 1807
+rect 36 1036 70 1540
+rect 36 1002 555 1036
+rect 36 634 70 1002
+rect 36 600 1077 634
+rect 36 96 70 600
+rect 434 96 1112 130
+rect 334 -171 402 -137
+rect 36 -592 490 -558
+rect 36 -680 132 -646
+rect 132 -680 394 -646
+rect 394 -680 490 -646
+<< metal1 >>
+rect -33 2316 526 2322
+rect -33 2282 36 2316
+rect 490 2282 526 2316
+rect -33 2228 526 2282
+rect -33 2194 36 2228
+rect 490 2194 526 2228
+rect -33 2188 526 2194
+rect 144 2045 190 2188
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+rect 102 1761 112 1813
+rect 194 1761 204 1813
+rect 240 1651 286 1901
+rect 30 1540 76 1552
+rect 227 1547 237 1651
+rect 289 1547 299 1651
+rect 30 982 36 1540
+rect 70 1042 76 1540
+rect 240 1366 286 1547
+rect 198 1104 328 1138
+rect 70 1036 567 1042
+rect 555 1002 567 1036
+rect -33 654 36 982
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+rect 70 996 567 1002
+rect 70 640 76 996
+rect 70 634 1089 640
+rect 1077 600 1089 634
+rect 70 594 1089 600
+rect 70 96 76 594
+rect 198 498 328 532
+rect 766 519 812 594
+rect 958 519 1004 594
+rect 657 392 667 511
+rect 657 280 667 346
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+rect 30 84 76 96
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+rect 1112 96 1124 130
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+rect 227 -15 237 89
+rect 289 -15 299 89
+rect 240 -219 286 -15
+rect 322 -177 332 -125
+rect 414 -177 424 -125
+rect 144 -552 190 -408
+rect 336 -552 382 -399
+rect -33 -558 526 -552
+rect -33 -592 36 -558
+rect 490 -592 526 -558
+rect -33 -646 526 -592
+rect -33 -680 36 -646
+rect 490 -680 526 -646
+rect -33 -686 526 -680
+<< via1 >>
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+rect 112 1773 124 1807
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+rect 192 1773 194 1807
+rect 112 1761 194 1773
+rect 237 1547 289 1651
+rect 667 280 719 511
+rect 859 281 911 512
+rect 237 -15 289 89
+rect 332 -137 414 -125
+rect 332 -171 334 -137
+rect 334 -171 402 -137
+rect 402 -171 414 -137
+rect 332 -177 414 -171
+<< metal2 >>
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+rect 130 94 186 104
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+rect 237 89 289 99
+rect 186 7 237 66
+rect 130 -26 186 -17
+rect 237 -25 289 -15
+rect 312 -122 424 -112
+rect 312 -188 424 -178
+<< via2 >>
+rect 102 1813 214 1814
+rect 102 1761 112 1813
+rect 112 1761 194 1813
+rect 194 1761 214 1813
+rect 102 1758 214 1761
+rect 340 1542 396 1653
+rect 497 1211 553 1323
+rect 470 338 582 394
+rect 130 -17 186 94
+rect 312 -125 424 -122
+rect 312 -177 332 -125
+rect 332 -177 414 -125
+rect 414 -177 424 -125
+rect 312 -178 424 -177
+<< metal3 >>
+rect 92 1814 224 1819
+rect 92 1758 102 1814
+rect 214 1758 224 1814
+rect 92 1753 224 1758
+rect 128 99 188 1753
+rect 330 1653 406 1658
+rect 330 1542 340 1653
+rect 396 1542 406 1653
+rect 330 1537 406 1542
+rect 120 94 196 99
+rect 120 -17 130 94
+rect 186 -17 196 94
+rect 120 -22 196 -17
+rect 338 -117 398 1537
+rect 495 1328 555 1333
+rect 487 1323 563 1328
+rect 487 1211 497 1323
+rect 553 1211 563 1323
+rect 487 1206 563 1211
+rect 495 399 555 1206
+rect 460 394 592 399
+rect 460 338 470 394
+rect 582 338 592 394
+rect 460 333 592 338
+rect 495 323 555 333
+rect 302 -122 434 -117
+rect 302 -178 312 -122
+rect 424 -178 434 -122
+rect 302 -183 434 -178
+use sky130_fd_pr__nfet_01v8_2BS854  sky130_fd_pr__nfet_01v8_2BS854_0
+timestamp 1623795754
+transform 1 0 836 0 1 395
+box -311 -335 311 335
+use sky130_fd_pr__pfet_01v8_MJG8BZ  sky130_fd_pr__pfet_01v8_MJG8BZ_0
+timestamp 1623610677
+transform 1 0 263 0 1 1950
+box -263 -314 263 314
+use sky130_fd_pr__pfet_01v8_MJG8BZ  sky130_fd_pr__pfet_01v8_MJG8BZ_1
+timestamp 1623610677
+transform -1 0 263 0 -1 -314
+box -263 -314 263 314
+use sky130_fd_pr__nfet_01v8_KU9PSX  sky130_fd_pr__nfet_01v8_KU9PSX_1
+timestamp 1623610677
+transform 1 0 263 0 1 1271
+box -263 -305 263 305
+use sky130_fd_pr__nfet_01v8_KU9PSX  sky130_fd_pr__nfet_01v8_KU9PSX_0
+timestamp 1623610677
+transform 1 0 263 0 -1 365
+box -263 -305 263 305
+<< labels >>
+rlabel metal1 -33 654 36 982 1 vss
+rlabel metal1 -33 2228 526 2282 1 vdd
+rlabel metal3 128 94 188 1758 1 Q
+rlabel metal3 338 -122 398 1542 1 nQ
+rlabel metal1 198 1104 328 1138 1 D
+rlabel metal1 198 498 328 532 1 nD
+rlabel metal1 -33 -646 526 -592 1 vdd
+rlabel metal1 714 192 954 232 1 CLK
+<< end >>

diff --git a/mag/loop_filter.mag b/mag/loop_filter.mag
new file mode 100644
index 0000000..2ebb142
--- /dev/null
+++ b/mag/loop_filter.mag

@@ -0,0 +1,164 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623893910
+<< pwell >>
+rect -16462 -24206 34360 5780
+<< psubdiff >>
+rect -16450 4360 -14850 4384
+rect 32749 4360 34349 4384
+rect 151 -145 175 -79
+rect 4035 -145 4059 -79
+rect -16450 -21664 -14850 -21640
+rect -16450 -22594 -14851 -21664
+rect 32749 -22593 34349 -21640
+rect 32749 -22594 34348 -22593
+rect -16450 -24194 -11039 -22594
+rect 28961 -24194 34348 -22594
+<< psubdiffcont >>
+rect -16450 -21640 -14850 4360
+rect 175 -145 4035 -79
+rect 32749 -21640 34349 4360
+rect -11039 -24194 28961 -22594
+<< locali >>
+rect -16450 4360 -14850 4376
+rect 32749 4360 34349 4376
+rect -14851 -21656 -14850 -21640
+rect 34348 -21656 34349 -21640
+<< viali >>
+rect -16450 -21640 -14850 4360
+rect 36 36 4230 70
+rect 36 -79 4224 -49
+rect 36 -145 175 -79
+rect 175 -145 4035 -79
+rect 4035 -145 4224 -79
+rect 36 -168 4224 -145
+rect -16450 -22594 -14851 -21640
+rect 32749 -21640 34349 4360
+rect 32749 -22594 34348 -21640
+rect -16450 -24194 -11039 -22594
+rect -11039 -24194 28961 -22594
+rect 28961 -24194 34348 -22594
+<< metal1 >>
+rect -370 5080 -360 5680
+rect 640 5614 650 5680
+rect 2456 5614 2466 5680
+rect 640 5182 1312 5614
+rect 1560 5182 2466 5614
+rect 640 5080 650 5182
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+rect 3866 5614 3876 5680
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+rect -16456 4360 -14844 4372
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+rect -10 70 4297 90
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+rect -10 -49 4297 36
+rect -10 -168 36 -49
+rect 4224 -168 4297 -49
+rect -10 -185 4297 -168
+rect 1312 -1221 2954 -185
+rect 1312 -1273 2955 -1221
+rect 1313 -2326 2955 -1273
+rect -14850 -21640 -14839 -21634
+rect -14851 -22588 -14839 -21640
+rect 1313 -22588 2954 -2326
+rect 32743 -22588 32749 4360
+rect 34349 -21640 34355 4360
+rect -14851 -22594 32749 -22588
+rect 34348 -21652 34355 -21640
+rect 34348 -22588 34354 -21652
+rect 34348 -24194 34360 -22588
+rect -16462 -24200 34360 -24194
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+<< via1 >>
+rect -360 5080 640 5680
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+<< metal2 >>
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+rect -10029 -23963 -4329 -23953
+rect 9433 -22834 31413 -22824
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+<< via2 >>
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+rect 9433 -24034 31413 -22834
+<< metal3 >>
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+rect -4329 -23953 -4319 -23136
+rect -10039 -23958 -4319 -23953
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+rect 31413 -23602 31427 -22834
+rect 31413 -24034 31423 -23602
+rect 9423 -24039 31423 -24034
+rect 25394 -24061 26794 -24039
+<< via3 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+<< metal4 >>
+rect -12154 5680 740 5780
+rect -12154 5080 -360 5680
+rect 640 5080 740 5680
+rect -12154 4980 740 5080
+rect 2066 5680 29520 5780
+rect 2066 5080 2466 5680
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+rect -12154 -6696 -10754 4980
+rect -7779 -6696 -6379 4980
+rect -3405 -6534 -2005 4980
+rect 6722 -19031 8122 4980
+rect 12166 -19023 13566 4980
+rect 17484 -19174 18884 4980
+rect 22862 -19265 24262 4980
+rect 28119 -19235 29519 4980
+use sky130_fd_pr__cap_mim_m3_1_W3JTNJ  sky130_fd_pr__cap_mim_m3_1_W3JTNJ_0
+timestamp 1623892191
+transform 1 0 -7054 0 1 -1552
+box -6469 -6450 6468 6450
+use sky130_fd_pr__cap_mim_m3_1_MA89VW  sky130_fd_pr__cap_mim_m3_1_MA89VW_0
+timestamp 1623892191
+transform 1 0 18140 0 1 -8352
+box -13288 -13250 13287 13250
+use sky130_fd_pr__res_high_po_5p73_GW5RGE  sky130_fd_pr__res_high_po_5p73_GW5RGE_0
+timestamp 1623892191
+transform 1 0 2133 0 1 2890
+box -2133 -2890 2133 2890
+<< labels >>
+rlabel metal4 3866 4980 29520 5780 1 vc_pex
+rlabel metal4 -12154 4980 -360 5780 1 in
+rlabel metal1 1313 -22594 2954 -168 1 vss
+<< end >>

diff --git a/mag/loop_filter_v2.mag b/mag/loop_filter_v2.mag
new file mode 100644
index 0000000..7503cb8
--- /dev/null
+++ b/mag/loop_filter_v2.mag

@@ -0,0 +1,257 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623980668
+<< pwell >>
+rect -16462 -24206 34360 5780
+<< psubdiff >>
+rect -16450 4360 -14850 4384
+rect 32749 4360 34349 4384
+rect 151 -145 175 -79
+rect 4035 -145 4059 -79
+rect -16450 -21664 -14850 -21640
+rect -16450 -22594 -14851 -21664
+rect 32749 -22593 34349 -21640
+rect 32749 -22594 34348 -22593
+rect -16450 -24194 -11039 -22594
+rect 28961 -24194 34348 -22594
+<< psubdiffcont >>
+rect -16450 -21640 -14850 4360
+rect 175 -145 4035 -79
+rect 32749 -21640 34349 4360
+rect -11039 -24194 28961 -22594
+<< locali >>
+rect -16450 4360 -14850 4376
+rect 32749 4360 34349 4376
+rect -14851 -21656 -14850 -21640
+rect 34348 -21656 34349 -21640
+<< viali >>
+rect -16450 -21640 -14850 4360
+rect 36 36 4230 70
+rect 36 -79 4224 -49
+rect 36 -145 175 -79
+rect 175 -145 4035 -79
+rect 4035 -145 4224 -79
+rect 36 -168 4224 -145
+rect -7067 -9695 -6984 -8740
+rect -16450 -22594 -14851 -21640
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+rect 32749 -22594 34348 -21640
+rect -16450 -24194 -11039 -22594
+rect -11039 -24194 28961 -22594
+rect 28961 -24194 34348 -22594
+<< metal1 >>
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+rect 640 5614 650 5680
+rect 2456 5614 2466 5680
+rect 640 5182 1312 5614
+rect 1560 5182 2466 5614
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+rect 34348 -22588 34354 -21652
+rect 34348 -24194 34360 -22588
+rect -16462 -24200 34360 -24194
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+<< via1 >>
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+rect -7181 -9505 -7129 -8922
+rect -7009 -9581 -6984 -8828
+rect -6984 -9581 -6903 -8828
+rect -10029 -23953 -4329 -22753
+rect 9433 -24034 31413 -22834
+<< metal2 >>
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+rect 2466 5680 3866 5690
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+rect -6973 -8818 -6867 -8814
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+rect -10029 -23963 -4329 -23953
+rect 9433 -22834 31413 -22824
+rect 9433 -24044 31413 -24034
+<< via2 >>
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+rect -6973 -8828 -6867 -8824
+rect -7334 -9502 -7315 -8930
+rect -7315 -9502 -7267 -8930
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+rect -6973 -9577 -6903 -8828
+rect -6903 -9577 -6867 -8828
+rect -10029 -23953 -4329 -22753
+rect 9433 -24034 31413 -22834
+<< metal3 >>
+rect -370 5680 650 5685
+rect -370 5080 -360 5680
+rect 640 5080 650 5680
+rect -370 5075 650 5080
+rect 2456 5680 3876 5685
+rect 2456 5080 2466 5680
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+rect -13523 -8002 -586 4898
+rect -10029 -10424 -8629 -8002
+rect -6983 -8824 -6857 -8819
+rect -7191 -8923 -7104 -8918
+rect -7344 -8928 -7257 -8925
+rect -7379 -9504 -7369 -8928
+rect -7264 -9504 -7254 -8928
+rect -7344 -9508 -7257 -9504
+rect -7191 -9505 -7181 -8923
+rect -7082 -9505 -7072 -8923
+rect -7191 -9510 -7104 -9505
+rect -6983 -9577 -6973 -8824
+rect -6867 -8830 -6857 -8824
+rect -5695 -8830 -4295 -8002
+rect -6867 -9577 -4295 -8830
+rect -6983 -9582 -6857 -9577
+rect -5695 -10424 -4295 -9577
+rect -11511 -19024 -2893 -10424
+rect -10029 -22748 -8629 -19024
+rect -5695 -22748 -4295 -19024
+rect 4852 -21602 31427 4898
+rect -10039 -22753 -4295 -22748
+rect -10039 -23953 -10029 -22753
+rect -4329 -23136 -4295 -22753
+rect 9433 -22829 10833 -21602
+rect 14842 -22829 16242 -21602
+rect 20055 -22829 21455 -21602
+rect 25394 -22829 26794 -21602
+rect 30027 -22829 31427 -21602
+rect 9423 -22834 31427 -22829
+rect -4329 -23953 -4319 -23136
+rect -10039 -23958 -4319 -23953
+rect 9423 -24034 9433 -22834
+rect 31413 -23602 31427 -22834
+rect 31413 -24034 31423 -23602
+rect 9423 -24039 31423 -24034
+rect 25394 -24061 26794 -24039
+<< via3 >>
+rect -360 5080 640 5680
+rect 2466 5080 3866 5680
+rect -7369 -8930 -7264 -8928
+rect -7369 -9503 -7334 -8930
+rect -7334 -9503 -7267 -8930
+rect -7267 -9503 -7264 -8930
+rect -7369 -9504 -7264 -9503
+rect -7181 -9505 -7114 -8923
+rect -7114 -9505 -7082 -8923
+<< metal4 >>
+rect -12154 5680 740 5780
+rect -12154 5080 -360 5680
+rect 640 5080 740 5680
+rect -12154 4980 740 5080
+rect 2066 5680 29520 5780
+rect 2066 5080 2466 5680
+rect 3866 5080 29520 5680
+rect 2066 4980 29520 5080
+rect -12154 -6696 -10754 4980
+rect -7779 -6696 -6379 4980
+rect -3405 -6534 -2005 4980
+rect -11475 -8112 -11371 -7898
+rect -7156 -8112 -7052 -7866
+rect -2837 -8112 -2733 -7848
+rect -11475 -8216 -2733 -8112
+rect -7369 -8927 -7263 -8216
+rect -7182 -8923 -7081 -8922
+rect -7182 -8924 -7181 -8923
+rect -7370 -8928 -7263 -8927
+rect -7370 -9504 -7369 -8928
+rect -7264 -9504 -7263 -8928
+rect -7370 -9505 -7263 -9504
+rect -7183 -9505 -7181 -8924
+rect -7082 -8924 -7081 -8923
+rect -7082 -9505 -7077 -8924
+rect -7183 -10154 -7077 -9505
+rect -9463 -10258 -5040 -10154
+rect -9463 -10536 -9359 -10258
+rect -5144 -10528 -5040 -10258
+rect -9463 -19216 -9359 -18920
+rect -5144 -19216 -5040 -18920
+rect 6722 -19031 8122 4980
+rect 12166 -19023 13566 4980
+rect 17484 -19174 18884 4980
+rect -9463 -19320 -5040 -19216
+rect 22862 -19265 24262 4980
+rect 28119 -19235 29519 4980
+rect -5144 -19321 -5040 -19320
+use sky130_fd_pr__nfet_01v8_U2JGXT  sky130_fd_pr__nfet_01v8_U2JGXT_0
+timestamp 1623980668
+transform 1 0 -7220 0 1 -9214
+box -226 -510 226 510
+use sky130_fd_pr__cap_mim_m3_1_BC3K5K  sky130_fd_pr__cap_mim_m3_1_BC3K5K_0
+timestamp 1623980668
+transform 1 0 -7202 0 1 -14724
+box -4309 -4300 4309 4300
+use sky130_fd_pr__res_high_po_5p73_GW5RGE  sky130_fd_pr__res_high_po_5p73_GW5RGE_0
+timestamp 1623892191
+transform 1 0 2133 0 1 2890
+box -2133 -2890 2133 2890
+use sky130_fd_pr__cap_mim_m3_1_MA89VW  sky130_fd_pr__cap_mim_m3_1_MA89VW_0
+timestamp 1623892191
+transform 1 0 18140 0 1 -8352
+box -13288 -13250 13287 13250
+use sky130_fd_pr__cap_mim_m3_1_W3JTNJ  sky130_fd_pr__cap_mim_m3_1_W3JTNJ_0
+timestamp 1623892191
+transform 1 0 -7054 0 1 -1552
+box -6469 -6450 6468 6450
+<< labels >>
+rlabel metal4 3866 4980 29520 5780 1 vc_pex
+rlabel metal4 -12154 4980 -360 5780 1 in
+rlabel metal1 1313 -22594 2954 -168 1 vss
+<< end >>

diff --git a/mag/magicrc b/mag/magicrc
new file mode 100644
index 0000000..7901958
--- /dev/null
+++ b/mag/magicrc

@@ -0,0 +1,82 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+    scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+    set PDKPATH "~/skywater/pdk/skywater130/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+    addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+    addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}

diff --git a/mag/nor_pfd.mag b/mag/nor_pfd.mag
new file mode 100644
index 0000000..48c45df
--- /dev/null
+++ b/mag/nor_pfd.mag

@@ -0,0 +1,119 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623456049
+<< nwell >>
+rect -235 1684 483 1772
+<< pwell >>
+rect -235 1054 -139 1066
+rect 409 1064 483 1066
+rect -235 922 -131 1054
+rect -235 556 -139 922
+rect 387 556 483 1064
+rect -235 468 483 556
+<< psubdiff >>
+rect -199 861 -165 934
+rect -199 626 -165 655
+rect 413 872 447 934
+rect 413 626 447 666
+rect -199 592 -23 626
+rect 255 592 447 626
+rect -31 504 -7 538
+rect 255 504 279 538
+<< nsubdiff >>
+rect -127 1702 -103 1736
+rect 351 1702 375 1736
+<< psubdiffcont >>
+rect -199 655 -165 861
+rect 413 666 447 872
+rect -7 504 255 538
+<< nsubdiffcont >>
+rect -103 1702 351 1736
+<< poly >>
+rect -35 1193 31 1217
+rect -35 1111 -25 1193
+rect 9 1111 31 1193
+rect 253 1125 319 1259
+rect -35 948 31 1111
+rect 157 1059 319 1125
+rect 157 1053 223 1059
+rect 157 971 172 1053
+rect 206 971 223 1053
+rect -35 882 61 948
+rect 157 878 223 971
+<< polycont >>
+rect -25 1111 9 1193
+rect 172 971 206 1053
+<< locali >>
+rect -25 1193 9 1209
+rect -25 1095 9 1111
+rect 172 1053 206 1069
+rect 172 955 206 971
+rect -199 861 -165 934
+rect -199 626 -165 655
+rect 413 872 447 934
+rect 413 626 447 666
+rect -199 592 -103 626
+rect 351 592 447 626
+<< viali >>
+rect -199 1702 -103 1736
+rect -103 1702 351 1736
+rect 351 1702 447 1736
+rect -199 1614 447 1648
+rect -25 1111 9 1193
+rect 172 971 206 1053
+rect -103 592 351 626
+rect -103 504 -7 538
+rect -7 504 255 538
+rect 255 504 351 538
+<< metal1 >>
+rect -235 1736 483 1742
+rect -235 1702 -199 1736
+rect 447 1702 483 1736
+rect -235 1648 483 1702
+rect -235 1614 -199 1648
+rect 447 1614 483 1648
+rect -235 1608 483 1614
+rect -91 1463 -45 1608
+rect 293 1463 339 1608
+rect 293 1375 329 1463
+rect 101 1256 147 1297
+rect 101 1210 337 1256
+rect -31 1193 15 1205
+rect -31 1186 -25 1193
+rect -235 1120 -25 1186
+rect -31 1111 -25 1120
+rect 9 1111 15 1193
+rect -31 1099 15 1111
+rect 166 1053 212 1065
+rect 166 1025 172 1053
+rect -235 971 172 1025
+rect 206 971 212 1053
+rect -235 959 212 971
+rect 291 931 337 1210
+rect 101 885 337 931
+rect 101 855 147 885
+rect 5 632 51 774
+rect 197 632 243 776
+rect -235 626 483 632
+rect -235 592 -103 626
+rect 351 592 483 626
+rect -235 538 483 592
+rect -235 504 -103 538
+rect 351 504 483 538
+rect -235 498 483 504
+use sky130_fd_pr__nfet_01v8_C3YG4M  sky130_fd_pr__nfet_01v8_C3YG4M_0
+timestamp 1623451718
+transform 1 0 124 0 1 811
+box -263 -255 263 255
+use sky130_fd_pr__pfet_01v8_4F35BC  sky130_fd_pr__pfet_01v8_4F35BC_0
+timestamp 1623451685
+transform 1 0 124 0 1 1375
+box -359 -309 359 309
+<< labels >>
+rlabel metal1 -235 1648 483 1702 1 vdd
+rlabel metal1 -235 538 483 592 1 vss
+rlabel metal1 -235 1120 -25 1186 1 A
+rlabel metal1 -235 959 172 1025 1 B
+rlabel metal1 291 885 337 1256 1 out
+<< end >>

diff --git a/mag/pfd_cp_interface.mag b/mag/pfd_cp_interface.mag
new file mode 100644
index 0000000..d28e191
--- /dev/null
+++ b/mag/pfd_cp_interface.mag

@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623954650
+<< metal1 >>
+rect 983 2998 993 3026
+rect 0 2944 993 2998
+rect 983 2914 993 2944
+rect 1161 2998 1171 3026
+rect 1161 2944 2154 2998
+rect 1161 2914 1171 2944
+rect 0 2259 226 2325
+rect 442 2259 832 2325
+rect 1054 2259 1672 2325
+rect 1964 2259 2154 2325
+rect 0 1564 2143 1570
+rect 0 1504 2154 1564
+rect 0 1498 2143 1504
+rect 0 743 226 809
+rect 478 742 720 809
+rect 1094 743 1672 809
+rect 1964 743 2154 809
+rect 983 124 993 152
+rect 0 108 993 124
+rect 0 70 979 108
+rect 983 40 993 108
+rect 1161 124 1171 152
+rect 1161 108 2154 124
+rect 1161 40 1171 108
+rect 1176 70 2154 108
+<< via1 >>
+rect 993 2914 1161 3026
+rect 993 40 1161 152
+<< metal2 >>
+rect 993 3026 1161 3036
+rect 993 2904 1161 2914
+rect 993 152 1161 162
+rect 993 30 1161 40
+<< via2 >>
+rect 993 2914 1161 3026
+rect 993 40 1161 152
+<< metal3 >>
+rect 983 3026 1171 3031
+rect 983 2914 993 3026
+rect 1161 2914 1171 3026
+rect 983 2909 1171 2914
+rect 1017 157 1137 2909
+rect 983 152 1171 157
+rect 983 40 993 152
+rect 1161 40 1171 152
+rect 983 35 1171 40
+use trans_gate  trans_gate_0
+timestamp 1623610677
+transform 1 0 675 0 -1 723
+box -53 -811 569 723
+use inverter_cp_x2  inverter_cp_x2_0
+timestamp 1623355426
+transform 1 0 1244 0 -1 776
+box 0 -758 910 776
+use inverter_cp_x2  inverter_cp_x2_1
+timestamp 1623355426
+transform 1 0 1244 0 1 2292
+box 0 -758 910 776
+use inverter_cp_x1  inverter_cp_x1_0
+timestamp 1623798692
+transform 1 0 0 0 -1 776
+box 0 -758 622 776
+use inverter_cp_x1  inverter_cp_x1_2
+timestamp 1623798692
+transform 1 0 622 0 1 2292
+box 0 -758 622 776
+use inverter_cp_x1  inverter_cp_x1_1
+timestamp 1623798692
+transform 1 0 0 0 1 2292
+box 0 -758 622 776
+<< labels >>
+rlabel metal1 0 1498 2143 1570 1 vss
+rlabel metal1 0 2259 226 2325 1 QA
+rlabel metal1 0 743 226 809 1 QB
+rlabel metal1 1054 2259 1672 2325 1 Up
+rlabel metal1 1094 743 1672 809 1 nDown
+rlabel metal1 1964 743 2154 809 1 Down
+rlabel metal1 1964 2259 2154 2325 1 nUp
+rlabel metal1 0 2944 2154 2998 1 vdd
+<< end >>

diff --git a/mag/ring_osc.mag b/mag/ring_osc.mag
new file mode 100644
index 0000000..443d0ab
--- /dev/null
+++ b/mag/ring_osc.mag

@@ -0,0 +1,166 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623706675
+<< nwell >>
+rect -422 2867 0 2956
+<< pwell >>
+rect 1294 809 1725 1389
+rect 2588 809 3019 1389
+rect -422 165 -411 166
+rect -422 0 0 165
+<< psubdiff >>
+rect -314 36 -290 70
+rect -132 36 -108 70
+<< nsubdiff >>
+rect -314 2886 -290 2920
+rect -132 2886 -108 2920
+<< psubdiffcont >>
+rect -290 36 -132 70
+<< nsubdiffcont >>
+rect -290 2886 -132 2920
+<< viali >>
+rect -386 2886 -290 2920
+rect -290 2886 -132 2920
+rect -132 2886 -36 2920
+rect -386 2797 -36 2831
+rect -386 125 -36 159
+rect -386 36 -290 70
+rect -290 36 -132 70
+rect -132 36 -36 70
+<< metal1 >>
+rect -422 2920 0 2926
+rect -422 2886 -386 2920
+rect -36 2886 0 2920
+rect -422 2831 0 2886
+rect -422 2797 -386 2831
+rect -36 2797 0 2831
+rect -422 2791 0 2797
+rect -324 2348 -278 2791
+rect -243 2695 -233 2747
+rect -129 2695 -119 2747
+rect -243 2686 -144 2695
+rect -190 2646 -144 2686
+rect -190 2199 -144 2353
+rect -236 739 -98 2199
+rect 1294 779 1725 957
+rect 2588 779 3019 957
+rect -324 165 -278 599
+rect -190 597 -144 739
+rect -243 261 -119 270
+rect -243 209 -233 261
+rect -129 209 -119 261
+rect -422 159 0 165
+rect -422 125 -386 159
+rect -36 125 0 159
+rect -422 70 0 125
+rect -422 36 -386 70
+rect -36 36 0 70
+rect -422 30 0 36
+<< via1 >>
+rect -233 2695 -129 2747
+rect -233 209 -129 261
+<< metal2 >>
+rect -233 2747 3061 2757
+rect -129 2695 3061 2747
+rect -233 2685 3061 2695
+rect 440 1417 608 1427
+rect 3316 1417 3440 1427
+rect 1255 1363 1757 1415
+rect 2557 1363 3030 1415
+rect 440 1351 608 1361
+rect 3651 1363 3882 1415
+rect 3316 1351 3440 1361
+rect -233 261 2860 271
+rect -129 209 2860 261
+rect -233 199 2860 209
+rect 1015 159 1071 169
+rect 2309 159 2365 169
+rect 3603 159 3659 169
+rect 1005 103 1015 159
+rect 1071 103 2309 159
+rect 2365 103 3603 159
+rect 3659 103 3669 159
+rect 1015 94 1071 103
+rect 2309 94 2365 103
+rect 3603 94 3659 103
+<< via2 >>
+rect 440 1361 608 1417
+rect 3316 1361 3440 1417
+rect 1015 103 1071 159
+rect 2309 103 2365 159
+rect 3603 103 3659 159
+<< metal3 >>
+rect 430 1421 618 1422
+rect 430 1417 441 1421
+rect 607 1417 618 1421
+rect 430 1361 440 1417
+rect 608 1361 618 1417
+rect 430 1357 441 1361
+rect 607 1357 618 1361
+rect 430 1356 618 1357
+rect 3306 1421 3450 1425
+rect 3306 1417 3317 1421
+rect 3306 1361 3316 1417
+rect 3306 1357 3317 1361
+rect 3440 1357 3450 1421
+rect 3306 1353 3450 1357
+rect 1013 164 1073 970
+rect 2307 164 2367 1007
+rect 3601 164 3661 1007
+rect 1005 159 1081 164
+rect 1005 103 1015 159
+rect 1071 103 1081 159
+rect 1005 98 1081 103
+rect 2299 159 2375 164
+rect 2299 103 2309 159
+rect 2365 103 2375 159
+rect 2299 98 2375 103
+rect 3593 159 3669 164
+rect 3593 103 3603 159
+rect 3659 103 3669 159
+rect 3593 98 3669 103
+rect 1013 94 1073 98
+rect 2307 90 2367 98
+<< via3 >>
+rect 441 1417 607 1421
+rect 441 1361 607 1417
+rect 441 1357 607 1361
+rect 3317 1417 3440 1421
+rect 3317 1361 3440 1417
+rect 3317 1357 3440 1361
+<< metal4 >>
+rect 440 1421 608 1422
+rect 3316 1421 3441 1422
+rect 440 1357 441 1421
+rect 607 1357 3317 1421
+rect 3440 1357 3441 1421
+rect 440 1356 608 1357
+rect 3316 1356 3441 1357
+use csvco_branch  csvco_branch_2
+timestamp 1623248172
+transform 1 0 2951 0 1 1002
+box -363 -1002 931 1954
+use csvco_branch  csvco_branch_1
+timestamp 1623248172
+transform 1 0 1657 0 1 1002
+box -363 -1002 931 1954
+use csvco_branch  csvco_branch_0
+timestamp 1623248172
+transform 1 0 363 0 1 1002
+box -363 -1002 931 1954
+use sky130_fd_pr__pfet_01v8_4757AC  sky130_fd_pr__pfet_01v8_4757AC_0
+timestamp 1623181853
+transform 1 0 -211 0 1 2498
+box -211 -369 211 369
+use sky130_fd_pr__nfet_01v8_CBAU6Y  sky130_fd_pr__nfet_01v8_CBAU6Y_0
+timestamp 1623181853
+transform 1 0 -211 0 1 449
+box -211 -360 211 360
+<< labels >>
+rlabel metal2 -77 211 -25 263 1 vctrl
+rlabel metal1 -422 70 0 125 1 vss
+rlabel metal1 -422 2831 0 2886 1 vdd
+rlabel metal2 3651 1363 3882 1415 1 out_vco
+rlabel via2 2309 103 2365 159 1 D0
+<< end >>

diff --git a/mag/ring_osc_buffer.mag b/mag/ring_osc_buffer.mag
new file mode 100644
index 0000000..8c94c82
--- /dev/null
+++ b/mag/ring_osc_buffer.mag

@@ -0,0 +1,36 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623945368
+<< nwell >>
+rect 1 1259 1963 1270
+rect 1 744 1961 1259
+<< metal1 >>
+rect 491 1186 1963 1187
+rect 1 1133 1963 1186
+rect 1 1132 1954 1133
+rect 1 535 213 589
+rect 397 523 639 603
+rect 1078 519 1490 603
+rect 1796 519 1963 597
+rect 0 40 1963 94
+use inverter_min_x2  inverter_min_x2_0
+timestamp 1623898709
+transform 1 0 54 0 1 615
+box -53 -615 473 655
+use inverter_min_x4  inverter_min_x4_0
+timestamp 1623895985
+transform 1 0 580 0 1 616
+box -53 -616 665 643
+use inverter_min_x4  inverter_min_x4_1
+timestamp 1623895985
+transform 1 0 1298 0 1 616
+box -53 -616 665 643
+<< labels >>
+rlabel metal1 1 535 213 589 1 in_vco
+rlabel metal1 397 523 639 603 1 o1
+rlabel metal1 1078 519 1490 603 1 out_div
+rlabel metal1 1796 519 1963 597 1 out_pad
+rlabel metal1 491 1132 1954 1187 1 vdd
+rlabel metal1 0 40 1963 94 1 vss
+<< end >>

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_BC3K5K.mag b/mag/sky130_fd_pr__cap_mim_m3_1_BC3K5K.mag
new file mode 100644
index 0000000..91ea7bc
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_BC3K5K.mag

@@ -0,0 +1,104 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623980668
+<< error_p >>
+rect -70 50 -10 4250
+rect 10 50 70 4250
+rect -70 -4250 -10 -50
+rect 10 -4250 70 -50
+<< metal3 >>
+rect -4309 4222 -10 4250
+rect -4309 78 -94 4222
+rect -30 78 -10 4222
+rect -4309 50 -10 78
+rect 10 4222 4309 4250
+rect 10 78 4225 4222
+rect 4289 78 4309 4222
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+rect 4178 -4300 4282 -4238
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 10 50 4210 4250
+string parameters w 20.00 l 20.00 val 815.2 carea 2.00 cperi 0.19 nx 2 ny 2 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_MA89VW.mag b/mag/sky130_fd_pr__cap_mim_m3_1_MA89VW.mag
new file mode 100644
index 0000000..e2b6a0e
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_MA89VW.mag

@@ -0,0 +1,606 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623892191
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+rect 8127 2460 13049 2461
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+rect 13048 -2460 13049 2460
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+rect 2518 -8012 2622 -7888
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+rect -2511 -8140 2411 -8139
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+rect 2410 -13060 2411 -8140
+rect -2511 -13061 2411 -13060
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+rect -102 -13250 2 -13061
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+rect 2629 -13172 2645 -8028
+rect 5217 -8139 5321 -7761
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+rect 10536 -2839 10640 -2461
+rect 13156 -2572 13203 2572
+rect 13267 -2572 13283 2572
+rect 13156 -2588 13283 -2572
+rect 13156 -2712 13260 -2588
+rect 13156 -2728 13283 -2712
+rect 8127 -2840 13049 -2839
+rect 8127 -7760 8128 -2840
+rect 13048 -7760 13049 -2840
+rect 8127 -7761 13049 -7760
+rect 7837 -7888 7964 -7872
+rect 7837 -8012 7941 -7888
+rect 7837 -8028 7964 -8012
+rect 2808 -8140 7730 -8139
+rect 2808 -13060 2809 -8140
+rect 7729 -13060 7730 -8140
+rect 2808 -13061 7730 -13060
+rect 2518 -13188 2645 -13172
+rect 2518 -13250 2622 -13188
+rect 5217 -13250 5321 -13061
+rect 7837 -13172 7884 -8028
+rect 7948 -13172 7964 -8028
+rect 10536 -8139 10640 -7761
+rect 13156 -7872 13203 -2728
+rect 13267 -7872 13283 -2728
+rect 13156 -7888 13283 -7872
+rect 13156 -8012 13260 -7888
+rect 13156 -8028 13283 -8012
+rect 8127 -8140 13049 -8139
+rect 8127 -13060 8128 -8140
+rect 13048 -13060 13049 -8140
+rect 8127 -13061 13049 -13060
+rect 7837 -13188 7964 -13172
+rect 7837 -13250 7941 -13188
+rect 10536 -13250 10640 -13061
+rect 13156 -13172 13203 -8028
+rect 13267 -13172 13283 -8028
+rect 13156 -13188 13283 -13172
+rect 13156 -13250 13260 -13188
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 7988 8000 13188 13200
+string parameters w 25 l 25 val 1.269k carea 2.00 cperi 0.19 nx 5 ny 5 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag b/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag
new file mode 100644
index 0000000..c3f11cc
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_1_W3JTNJ.mag

@@ -0,0 +1,226 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623892191
+<< error_p >>
+rect -2390 2340 -2170 6400
+rect -6469 2200 -2170 2340
+rect -2150 2340 -1930 6400
+rect 1929 2340 2149 6400
+rect -2150 2200 2149 2340
+rect 2169 2340 2389 6400
+rect 2169 2200 6468 2340
+rect -6469 1960 -2170 2100
+rect -2390 -1960 -2170 1960
+rect -6469 -2100 -2170 -1960
+rect -2150 1960 2149 2100
+rect -2150 -1960 -1930 1960
+rect 1929 -1960 2149 1960
+rect -2150 -2100 2149 -1960
+rect 2169 1960 6468 2100
+rect 2169 -1960 2389 1960
+rect 2169 -2100 6468 -1960
+rect -6469 -2340 -2170 -2200
+rect -2390 -6400 -2170 -2340
+rect -2150 -2340 2149 -2200
+rect -2150 -6400 -1930 -2340
+rect 1929 -6400 2149 -2340
+rect 2169 -2340 6468 -2200
+rect 2169 -6400 2389 -2340
+<< metal3 >>
+rect -6469 6372 -2170 6400
+rect -6469 2228 -2254 6372
+rect -2190 2228 -2170 6372
+rect -6469 2200 -2170 2228
+rect -2150 6372 2149 6400
+rect -2150 2228 2065 6372
+rect 2129 2228 2149 6372
+rect -2150 2200 2149 2228
+rect 2169 6372 6468 6400
+rect 2169 2228 6384 6372
+rect 6448 2228 6468 6372
+rect 2169 2200 6468 2228
+rect -6469 2072 -2170 2100
+rect -6469 -2072 -2254 2072
+rect -2190 -2072 -2170 2072
+rect -6469 -2100 -2170 -2072
+rect -2150 2072 2149 2100
+rect -2150 -2072 2065 2072
+rect 2129 -2072 2149 2072
+rect -2150 -2100 2149 -2072
+rect 2169 2072 6468 2100
+rect 2169 -2072 6384 2072
+rect 6448 -2072 6468 2072
+rect 2169 -2100 6468 -2072
+rect -6469 -2228 -2170 -2200
+rect -6469 -6372 -2254 -2228
+rect -2190 -6372 -2170 -2228
+rect -6469 -6400 -2170 -6372
+rect -2150 -2228 2149 -2200
+rect -2150 -6372 2065 -2228
+rect 2129 -6372 2149 -2228
+rect -2150 -6400 2149 -6372
+rect 2169 -2228 6468 -2200
+rect 2169 -6372 6384 -2228
+rect 6448 -6372 6468 -2228
+rect 2169 -6400 6468 -6372
+<< via3 >>
+rect -2254 2228 -2190 6372
+rect 2065 2228 2129 6372
+rect 6384 2228 6448 6372
+rect -2254 -2072 -2190 2072
+rect 2065 -2072 2129 2072
+rect 6384 -2072 6448 2072
+rect -2254 -6372 -2190 -2228
+rect 2065 -6372 2129 -2228
+rect 6384 -6372 6448 -2228
+<< mimcap >>
+rect -6369 6260 -2369 6300
+rect -6369 2340 -6329 6260
+rect -2409 2340 -2369 6260
+rect -6369 2300 -2369 2340
+rect -2050 6260 1950 6300
+rect -2050 2340 -2010 6260
+rect 1910 2340 1950 6260
+rect -2050 2300 1950 2340
+rect 2269 6260 6269 6300
+rect 2269 2340 2309 6260
+rect 6229 2340 6269 6260
+rect 2269 2300 6269 2340
+rect -6369 1960 -2369 2000
+rect -6369 -1960 -6329 1960
+rect -2409 -1960 -2369 1960
+rect -6369 -2000 -2369 -1960
+rect -2050 1960 1950 2000
+rect -2050 -1960 -2010 1960
+rect 1910 -1960 1950 1960
+rect -2050 -2000 1950 -1960
+rect 2269 1960 6269 2000
+rect 2269 -1960 2309 1960
+rect 6229 -1960 6269 1960
+rect 2269 -2000 6269 -1960
+rect -6369 -2340 -2369 -2300
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+rect -2050 -2340 1950 -2300
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+rect 2269 -2340 6269 -2300
+rect 2269 -6260 2309 -2340
+rect 6229 -6260 6269 -2340
+rect 2269 -6300 6269 -6260
+<< mimcapcontact >>
+rect -6329 2340 -2409 6260
+rect -2010 2340 1910 6260
+rect 2309 2340 6229 6260
+rect -6329 -1960 -2409 1960
+rect -2010 -1960 1910 1960
+rect 2309 -1960 6229 1960
+rect -6329 -6260 -2409 -2340
+rect -2010 -6260 1910 -2340
+rect 2309 -6260 6229 -2340
+<< metal4 >>
+rect -4421 6261 -4317 6450
+rect -2301 6388 -2197 6450
+rect -2301 6372 -2174 6388
+rect -6330 6260 -2408 6261
+rect -6330 2340 -6329 6260
+rect -2409 2340 -2408 6260
+rect -6330 2339 -2408 2340
+rect -4421 1961 -4317 2339
+rect -2301 2228 -2254 6372
+rect -2190 2228 -2174 6372
+rect -102 6261 2 6450
+rect 2018 6388 2122 6450
+rect 2018 6372 2145 6388
+rect -2011 6260 1911 6261
+rect -2011 2340 -2010 6260
+rect 1910 2340 1911 6260
+rect -2011 2339 1911 2340
+rect -2301 2212 -2174 2228
+rect -2301 2088 -2197 2212
+rect -2301 2072 -2174 2088
+rect -6330 1960 -2408 1961
+rect -6330 -1960 -6329 1960
+rect -2409 -1960 -2408 1960
+rect -6330 -1961 -2408 -1960
+rect -4421 -2339 -4317 -1961
+rect -2301 -2072 -2254 2072
+rect -2190 -2072 -2174 2072
+rect -102 1961 2 2339
+rect 2018 2228 2065 6372
+rect 2129 2228 2145 6372
+rect 4217 6261 4321 6450
+rect 6337 6388 6441 6450
+rect 6337 6372 6464 6388
+rect 2308 6260 6230 6261
+rect 2308 2340 2309 6260
+rect 6229 2340 6230 6260
+rect 2308 2339 6230 2340
+rect 2018 2212 2145 2228
+rect 2018 2088 2122 2212
+rect 2018 2072 2145 2088
+rect -2011 1960 1911 1961
+rect -2011 -1960 -2010 1960
+rect 1910 -1960 1911 1960
+rect -2011 -1961 1911 -1960
+rect -2301 -2088 -2174 -2072
+rect -2301 -2212 -2197 -2088
+rect -2301 -2228 -2174 -2212
+rect -6330 -2340 -2408 -2339
+rect -6330 -6260 -6329 -2340
+rect -2409 -6260 -2408 -2340
+rect -6330 -6261 -2408 -6260
+rect -4421 -6450 -4317 -6261
+rect -2301 -6372 -2254 -2228
+rect -2190 -6372 -2174 -2228
+rect -102 -2339 2 -1961
+rect 2018 -2072 2065 2072
+rect 2129 -2072 2145 2072
+rect 4217 1961 4321 2339
+rect 6337 2228 6384 6372
+rect 6448 2228 6464 6372
+rect 6337 2212 6464 2228
+rect 6337 2088 6441 2212
+rect 6337 2072 6464 2088
+rect 2308 1960 6230 1961
+rect 2308 -1960 2309 1960
+rect 6229 -1960 6230 1960
+rect 2308 -1961 6230 -1960
+rect 2018 -2088 2145 -2072
+rect 2018 -2212 2122 -2088
+rect 2018 -2228 2145 -2212
+rect -2011 -2340 1911 -2339
+rect -2011 -6260 -2010 -2340
+rect 1910 -6260 1911 -2340
+rect -2011 -6261 1911 -6260
+rect -2301 -6388 -2174 -6372
+rect -2301 -6450 -2197 -6388
+rect -102 -6450 2 -6261
+rect 2018 -6372 2065 -2228
+rect 2129 -6372 2145 -2228
+rect 4217 -2339 4321 -1961
+rect 6337 -2072 6384 2072
+rect 6448 -2072 6464 2072
+rect 6337 -2088 6464 -2072
+rect 6337 -2212 6441 -2088
+rect 6337 -2228 6464 -2212
+rect 2308 -2340 6230 -2339
+rect 2308 -6260 2309 -2340
+rect 6229 -6260 6230 -2340
+rect 2308 -6261 6230 -6260
+rect 2018 -6388 2145 -6372
+rect 2018 -6450 2122 -6388
+rect 4217 -6450 4321 -6261
+rect 6337 -6372 6384 -2228
+rect 6448 -6372 6464 -2228
+rect 6337 -6388 6464 -6372
+rect 6337 -6450 6441 -6388
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX 2169 2200 6369 6400
+string parameters w 20 l 20 val 815.2 carea 2.00 cperi 0.19 nx 3 ny 3 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag b/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag
new file mode 100644
index 0000000..a815ca1
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_2BS6QM.mag

@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< psubdiffcont >>
+rect -275 -203 -241 203
+rect 241 -203 275 203
+rect -179 -299 179 -265
+<< poly >>
+rect -111 151 111 181
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -151 -81 -125
+rect -15 -151 15 -125
+rect 81 -151 111 -125
+<< locali >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_2BS854.mag b/mag/sky130_fd_pr__nfet_01v8_2BS854.mag
new file mode 100644
index 0000000..e3752b2
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_2BS854.mag

@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623795754
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -241 205 -179 239
+rect 179 205 241 239
+rect -241 -299 -179 -265
+rect 179 -299 241 -265
+<< psubdiffcont >>
+rect -179 205 179 239
+rect -179 -299 179 -265
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -147 -81 -125
+rect -15 -147 15 -125
+rect 81 -147 111 -125
+rect -129 -166 129 -147
+rect -129 -200 -106 -166
+rect 102 -200 129 -166
+rect -129 -213 129 -200
+<< polycont >>
+rect -106 -200 102 -166
+<< locali >>
+rect -241 205 -179 239
+rect 179 205 241 239
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -241 -299 -179 -265
+rect 179 -299 241 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+rect -122 -166 118 -163
+rect -122 -200 -106 -166
+rect -106 -200 102 -166
+rect 102 -200 118 -166
+rect -122 -203 118 -200
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+rect -134 -163 130 -157
+rect -134 -203 -122 -163
+rect 118 -203 130 -163
+rect -134 -209 130 -203
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag b/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag
new file mode 100644
index 0000000..18d97a6
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_5RJ8EK.mag

@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623427697
+<< pwell >>
+rect -263 -64 263 252
+rect -263 -66 -81 -64
+rect -63 -66 -33 -64
+rect -15 -66 263 -64
+rect -263 -252 263 -66
+<< nmos >>
+rect -63 -42 -33 42
+rect 33 -42 63 42
+<< ndiff >>
+rect -125 30 -63 42
+rect -125 -30 -113 30
+rect -79 -30 -63 30
+rect -125 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 125 42
+rect 63 -30 79 30
+rect 113 -30 125 30
+rect 63 -42 125 -30
+<< ndiffc >>
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+<< psubdiff >>
+rect -227 120 -193 182
+rect 193 120 227 182
+rect -227 -182 -193 -120
+rect 193 -182 227 -120
+rect -227 -216 -131 -182
+rect 131 -216 227 -182
+<< psubdiffcont >>
+rect -227 -120 -193 120
+rect 193 -120 227 120
+rect -131 -216 131 -182
+<< poly >>
+rect -63 42 -33 68
+rect 33 42 63 68
+rect -63 -68 -33 -42
+rect 33 -68 63 -42
+<< locali >>
+rect -227 120 -193 182
+rect 193 120 227 182
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect -227 -182 -193 -120
+rect 193 -182 227 -120
+rect -227 -216 -131 -182
+rect 131 -216 227 -182
+<< viali >>
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+<< metal1 >>
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -199 210 199
+string parameters w 0.420 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag b/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag
new file mode 100644
index 0000000..f4376d7
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_7H8F5S.mag

@@ -0,0 +1,261 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622843784
+<< pwell >>
+rect -647 -360 647 360
+<< nmos >>
+rect -447 -150 -417 150
+rect -351 -150 -321 150
+rect -255 -150 -225 150
+rect -159 -150 -129 150
+rect -63 -150 -33 150
+rect 33 -150 63 150
+rect 129 -150 159 150
+rect 225 -150 255 150
+rect 321 -150 351 150
+rect 417 -150 447 150
+<< ndiff >>
+rect -509 138 -447 150
+rect -509 -138 -497 138
+rect -463 -138 -447 138
+rect -509 -150 -447 -138
+rect -417 138 -351 150
+rect -417 -138 -401 138
+rect -367 -138 -351 138
+rect -417 -150 -351 -138
+rect -321 138 -255 150
+rect -321 -138 -305 138
+rect -271 -138 -255 138
+rect -321 -150 -255 -138
+rect -225 138 -159 150
+rect -225 -138 -209 138
+rect -175 -138 -159 138
+rect -225 -150 -159 -138
+rect -129 138 -63 150
+rect -129 -138 -113 138
+rect -79 -138 -63 138
+rect -129 -150 -63 -138
+rect -33 138 33 150
+rect -33 -138 -17 138
+rect 17 -138 33 138
+rect -33 -150 33 -138
+rect 63 138 129 150
+rect 63 -138 79 138
+rect 113 -138 129 138
+rect 63 -150 129 -138
+rect 159 138 225 150
+rect 159 -138 175 138
+rect 209 -138 225 138
+rect 159 -150 225 -138
+rect 255 138 321 150
+rect 255 -138 271 138
+rect 305 -138 321 138
+rect 255 -150 321 -138
+rect 351 138 417 150
+rect 351 -138 367 138
+rect 401 -138 417 138
+rect 351 -150 417 -138
+rect 447 138 509 150
+rect 447 -138 463 138
+rect 497 -138 509 138
+rect 447 -150 509 -138
+<< ndiffc >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< psubdiff >>
+rect -611 290 -515 324
+rect 515 290 611 324
+rect -611 228 -577 290
+rect 577 228 611 290
+rect -611 -290 -577 -228
+rect 577 -290 611 -228
+rect -611 -324 -515 -290
+rect 515 -324 611 -290
+<< psubdiffcont >>
+rect -515 290 515 324
+rect -611 -228 -577 228
+rect 577 -228 611 228
+rect -515 -324 515 -290
+<< poly >>
+rect -465 222 465 238
+rect -465 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 465 222
+rect -465 172 465 188
+rect -447 150 -417 172
+rect -351 150 -321 172
+rect -255 150 -225 172
+rect -159 150 -129 172
+rect -63 150 -33 172
+rect 33 150 63 172
+rect 129 150 159 172
+rect 225 150 255 172
+rect 321 150 351 172
+rect 417 150 447 172
+rect -447 -176 -417 -150
+rect -351 -176 -321 -150
+rect -255 -176 -225 -150
+rect -159 -176 -129 -150
+rect -63 -176 -33 -150
+rect 33 -176 63 -150
+rect 129 -176 159 -150
+rect 225 -176 255 -150
+rect 321 -176 351 -150
+rect 417 -176 447 -150
+<< polycont >>
+rect -449 188 -415 222
+rect -353 188 -319 222
+rect -257 188 -223 222
+rect -161 188 -127 222
+rect -65 188 -31 222
+rect 31 188 65 222
+rect 127 188 161 222
+rect 223 188 257 222
+rect 319 188 353 222
+rect 415 188 449 222
+<< locali >>
+rect -611 290 -515 324
+rect 515 290 611 324
+rect -611 228 -577 290
+rect 577 228 611 290
+rect -465 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 465 222
+rect -497 138 -463 154
+rect -497 -154 -463 -138
+rect -401 138 -367 154
+rect -401 -154 -367 -138
+rect -305 138 -271 154
+rect -305 -154 -271 -138
+rect -209 138 -175 154
+rect -209 -154 -175 -138
+rect -113 138 -79 154
+rect -113 -154 -79 -138
+rect -17 138 17 154
+rect -17 -154 17 -138
+rect 79 138 113 154
+rect 79 -154 113 -138
+rect 175 138 209 154
+rect 175 -154 209 -138
+rect 271 138 305 154
+rect 271 -154 305 -138
+rect 367 138 401 154
+rect 367 -154 401 -138
+rect 463 138 497 154
+rect 463 -154 497 -138
+rect -611 -290 -577 -228
+rect 577 -290 611 -228
+rect -611 -324 -515 -290
+rect 515 -324 611 -290
+<< viali >>
+rect -449 188 -415 222
+rect -353 188 -319 222
+rect -257 188 -223 222
+rect -161 188 -127 222
+rect -65 188 -31 222
+rect 31 188 65 222
+rect 127 188 161 222
+rect 223 188 257 222
+rect 319 188 353 222
+rect 415 188 449 222
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< metal1 >>
+rect -464 222 464 231
+rect -464 188 -449 222
+rect -415 188 -353 222
+rect -319 188 -257 222
+rect -223 188 -161 222
+rect -127 188 -65 222
+rect -31 188 31 222
+rect 65 188 127 222
+rect 161 188 223 222
+rect 257 188 319 222
+rect 353 188 415 222
+rect 449 188 464 222
+rect -464 179 464 188
+rect -503 138 -457 150
+rect -503 -138 -497 138
+rect -463 -138 -457 138
+rect -503 -150 -457 -138
+rect -407 138 -361 150
+rect -407 -138 -401 138
+rect -367 -138 -361 138
+rect -407 -150 -361 -138
+rect -311 138 -265 150
+rect -311 -138 -305 138
+rect -271 -138 -265 138
+rect -311 -150 -265 -138
+rect -215 138 -169 150
+rect -215 -138 -209 138
+rect -175 -138 -169 138
+rect -215 -150 -169 -138
+rect -119 138 -73 150
+rect -119 -138 -113 138
+rect -79 -138 -73 138
+rect -119 -150 -73 -138
+rect -23 138 23 150
+rect -23 -138 -17 138
+rect 17 -138 23 138
+rect -23 -150 23 -138
+rect 73 138 119 150
+rect 73 -138 79 138
+rect 113 -138 119 138
+rect 73 -150 119 -138
+rect 169 138 215 150
+rect 169 -138 175 138
+rect 209 -138 215 138
+rect 169 -150 215 -138
+rect 265 138 311 150
+rect 265 -138 271 138
+rect 305 -138 311 138
+rect 265 -150 311 -138
+rect 361 138 407 150
+rect 361 -138 367 138
+rect 401 -138 407 138
+rect 361 -150 407 -138
+rect 457 138 503 150
+rect 457 -138 463 138
+rect 497 -138 503 138
+rect 457 -150 503 -138
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -594 -307 594 307
+string parameters w 1.5 l 0.150 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag b/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag
new file mode 100644
index 0000000..7c8b45b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_8GRULZ.mag

@@ -0,0 +1,189 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< pwell >>
+rect -1957 -254 1957 254
+<< nmos >>
+rect -1761 -44 -1461 106
+rect -1403 -44 -1103 106
+rect -1045 -44 -745 106
+rect -687 -44 -387 106
+rect -329 -44 -29 106
+rect 29 -44 329 106
+rect 387 -44 687 106
+rect 745 -44 1045 106
+rect 1103 -44 1403 106
+rect 1461 -44 1761 106
+<< ndiff >>
+rect -1819 94 -1761 106
+rect -1819 -32 -1807 94
+rect -1773 -32 -1761 94
+rect -1819 -44 -1761 -32
+rect -1461 94 -1403 106
+rect -1461 -32 -1449 94
+rect -1415 -32 -1403 94
+rect -1461 -44 -1403 -32
+rect -1103 94 -1045 106
+rect -1103 -32 -1091 94
+rect -1057 -32 -1045 94
+rect -1103 -44 -1045 -32
+rect -745 94 -687 106
+rect -745 -32 -733 94
+rect -699 -32 -687 94
+rect -745 -44 -687 -32
+rect -387 94 -329 106
+rect -387 -32 -375 94
+rect -341 -32 -329 94
+rect -387 -44 -329 -32
+rect -29 94 29 106
+rect -29 -32 -17 94
+rect 17 -32 29 94
+rect -29 -44 29 -32
+rect 329 94 387 106
+rect 329 -32 341 94
+rect 375 -32 387 94
+rect 329 -44 387 -32
+rect 687 94 745 106
+rect 687 -32 699 94
+rect 733 -32 745 94
+rect 687 -44 745 -32
+rect 1045 94 1103 106
+rect 1045 -32 1057 94
+rect 1091 -32 1103 94
+rect 1045 -44 1103 -32
+rect 1403 94 1461 106
+rect 1403 -32 1415 94
+rect 1449 -32 1461 94
+rect 1403 -44 1461 -32
+rect 1761 94 1819 106
+rect 1761 -32 1773 94
+rect 1807 -32 1819 94
+rect 1761 -44 1819 -32
+<< ndiffc >>
+rect -1807 -32 -1773 94
+rect -1449 -32 -1415 94
+rect -1091 -32 -1057 94
+rect -733 -32 -699 94
+rect -375 -32 -341 94
+rect -17 -32 17 94
+rect 341 -32 375 94
+rect 699 -32 733 94
+rect 1057 -32 1091 94
+rect 1415 -32 1449 94
+rect 1773 -32 1807 94
+<< psubdiff >>
+rect -1887 184 -1825 218
+rect 1825 184 1887 218
+<< psubdiffcont >>
+rect -1825 184 1825 218
+<< poly >>
+rect -1761 106 -1461 132
+rect -1403 106 -1103 132
+rect -1045 106 -745 132
+rect -687 106 -387 132
+rect -329 106 -29 132
+rect 29 106 329 132
+rect 387 106 687 132
+rect 745 106 1045 132
+rect 1103 106 1403 132
+rect 1461 106 1761 132
+rect -1761 -66 -1461 -44
+rect -1403 -66 -1103 -44
+rect -1045 -66 -745 -44
+rect -687 -66 -387 -44
+rect -329 -66 -29 -44
+rect 29 -66 329 -44
+rect 387 -66 687 -44
+rect 745 -66 1045 -44
+rect 1103 -66 1403 -44
+rect 1461 -66 1761 -44
+rect -1761 -132 1761 -66
+<< locali >>
+rect -1887 184 -1825 218
+rect 1825 184 1887 218
+rect -1807 94 -1773 110
+rect -1807 -48 -1773 -32
+rect -1449 94 -1415 110
+rect -1449 -48 -1415 -32
+rect -1091 94 -1057 110
+rect -1091 -48 -1057 -32
+rect -733 94 -699 110
+rect -733 -48 -699 -32
+rect -375 94 -341 110
+rect -375 -48 -341 -32
+rect -17 94 17 110
+rect -17 -48 17 -32
+rect 341 94 375 110
+rect 341 -48 375 -32
+rect 699 94 733 110
+rect 699 -48 733 -32
+rect 1057 94 1091 110
+rect 1057 -48 1091 -32
+rect 1415 94 1449 110
+rect 1415 -48 1449 -32
+rect 1773 94 1807 110
+rect 1773 -48 1807 -32
+<< viali >>
+rect -1807 -32 -1773 94
+rect -1449 -32 -1415 94
+rect -1091 -32 -1057 94
+rect -733 -32 -699 94
+rect -375 -32 -341 94
+rect -17 -32 17 94
+rect 341 -32 375 94
+rect 699 -32 733 94
+rect 1057 -32 1091 94
+rect 1415 -32 1449 94
+rect 1773 -32 1807 94
+<< metal1 >>
+rect -1813 94 -1767 106
+rect -1813 -32 -1807 94
+rect -1773 -32 -1767 94
+rect -1813 -44 -1767 -32
+rect -1455 94 -1409 106
+rect -1455 -32 -1449 94
+rect -1415 -32 -1409 94
+rect -1455 -44 -1409 -32
+rect -1097 94 -1051 106
+rect -1097 -32 -1091 94
+rect -1057 -32 -1051 94
+rect -1097 -44 -1051 -32
+rect -739 94 -693 106
+rect -739 -32 -733 94
+rect -699 -32 -693 94
+rect -739 -44 -693 -32
+rect -381 94 -335 106
+rect -381 -32 -375 94
+rect -341 -32 -335 94
+rect -381 -44 -335 -32
+rect -23 94 23 106
+rect -23 -32 -17 94
+rect 17 -32 23 94
+rect -23 -44 23 -32
+rect 335 94 381 106
+rect 335 -32 341 94
+rect 375 -32 381 94
+rect 335 -44 381 -32
+rect 693 94 739 106
+rect 693 -32 699 94
+rect 733 -32 739 94
+rect 693 -44 739 -32
+rect 1051 94 1097 106
+rect 1051 -32 1057 94
+rect 1091 -32 1097 94
+rect 1051 -44 1097 -32
+rect 1409 94 1455 106
+rect 1409 -32 1415 94
+rect 1449 -32 1455 94
+rect 1409 -44 1455 -32
+rect 1767 94 1813 106
+rect 1767 -32 1773 94
+rect 1807 -32 1813 94
+rect 1767 -44 1813 -32
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1904 -201 1904 201
+string parameters w 0.75 l 1.5 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag b/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag
new file mode 100644
index 0000000..c3d1e46
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AQR2CW.mag

@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623162482
+<< pwell >>
+rect -216 -254 216 254
+<< nmos >>
+rect -20 -106 20 44
+<< ndiff >>
+rect -78 32 -20 44
+rect -78 -94 -66 32
+rect -32 -94 -20 32
+rect -78 -106 -20 -94
+rect 20 32 78 44
+rect 20 -94 32 32
+rect 66 -94 78 32
+rect 20 -106 78 -94
+<< ndiffc >>
+rect -66 -94 -32 32
+rect 32 -94 66 32
+<< psubdiff >>
+rect -180 122 -146 184
+rect 146 122 180 184
+rect -180 -184 -146 -122
+rect 146 -184 180 -122
+rect -180 -218 -84 -184
+rect 84 -218 180 -184
+<< psubdiffcont >>
+rect -180 -122 -146 122
+rect 146 -122 180 122
+rect -84 -218 84 -184
+<< poly >>
+rect -33 66 33 132
+rect -20 44 20 66
+rect -20 -132 20 -106
+<< locali >>
+rect -180 122 -146 184
+rect 146 122 180 184
+rect -66 32 -32 48
+rect -66 -110 -32 -94
+rect 32 32 66 48
+rect 32 -110 66 -94
+rect -180 -184 -146 -122
+rect 146 -184 180 -122
+rect -180 -218 -84 -184
+rect 84 -218 180 -184
+<< viali >>
+rect -66 -94 -32 32
+rect 32 -94 66 32
+<< metal1 >>
+rect -72 32 -26 44
+rect -72 -94 -66 32
+rect -32 -94 -26 32
+rect -72 -106 -26 -94
+rect 26 32 72 44
+rect 26 -94 32 32
+rect 66 -94 72 32
+rect 26 -106 72 -94
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -163 -201 163 201
+string parameters w 0.75 l 0.2 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag b/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag
new file mode 100644
index 0000000..77dfc18
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_AZESM8.mag

@@ -0,0 +1,138 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623353949
+<< pwell >>
+rect -455 -335 455 335
+<< nmos >>
+rect -255 -125 -225 125
+rect -159 -125 -129 125
+rect -63 -125 -33 125
+rect 33 -125 63 125
+rect 129 -125 159 125
+rect 225 -125 255 125
+<< ndiff >>
+rect -317 113 -255 125
+rect -317 -113 -305 113
+rect -271 -113 -255 113
+rect -317 -125 -255 -113
+rect -225 113 -159 125
+rect -225 -113 -209 113
+rect -175 -113 -159 113
+rect -225 -125 -159 -113
+rect -129 113 -63 125
+rect -129 -113 -113 113
+rect -79 -113 -63 113
+rect -129 -125 -63 -113
+rect -33 113 33 125
+rect -33 -113 -17 113
+rect 17 -113 33 113
+rect -33 -125 33 -113
+rect 63 113 129 125
+rect 63 -113 79 113
+rect 113 -113 129 113
+rect 63 -125 129 -113
+rect 159 113 225 125
+rect 159 -113 175 113
+rect 209 -113 225 113
+rect 159 -125 225 -113
+rect 255 113 317 125
+rect 255 -113 271 113
+rect 305 -113 317 113
+rect 255 -125 317 -113
+<< ndiffc >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< psubdiff >>
+rect -419 203 -385 265
+rect 385 203 419 265
+rect -419 -265 -385 -203
+rect 385 -265 419 -203
+rect -419 -299 -323 -265
+rect 323 -299 419 -265
+<< psubdiffcont >>
+rect -419 -203 -385 203
+rect 385 -203 419 203
+rect -323 -299 323 -265
+<< poly >>
+rect -255 125 -225 151
+rect -159 125 -129 151
+rect -63 125 -33 151
+rect 33 125 63 151
+rect 129 125 159 151
+rect 225 125 255 151
+rect -255 -151 -225 -125
+rect -159 -151 -129 -125
+rect -63 -151 -33 -125
+rect 33 -151 63 -125
+rect 129 -151 159 -125
+rect 225 -151 255 -125
+<< locali >>
+rect -419 203 -385 265
+rect 385 203 419 265
+rect -305 113 -271 129
+rect -305 -129 -271 -113
+rect -209 113 -175 129
+rect -209 -129 -175 -113
+rect -113 113 -79 129
+rect -113 -129 -79 -113
+rect -17 113 17 129
+rect -17 -129 17 -113
+rect 79 113 113 129
+rect 79 -129 113 -113
+rect 175 113 209 129
+rect 175 -129 209 -113
+rect 271 113 305 129
+rect 271 -129 305 -113
+rect -419 -265 -385 -203
+rect 385 -265 419 -203
+rect -419 -299 -323 -265
+rect 323 -299 419 -265
+<< viali >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< metal1 >>
+rect -311 113 -265 125
+rect -311 -113 -305 113
+rect -271 -113 -265 113
+rect -311 -125 -265 -113
+rect -215 113 -169 125
+rect -215 -113 -209 113
+rect -175 -113 -169 113
+rect -215 -125 -169 -113
+rect -119 113 -73 125
+rect -119 -113 -113 113
+rect -79 -113 -73 113
+rect -119 -125 -73 -113
+rect -23 113 23 125
+rect -23 -113 -17 113
+rect 17 -113 23 113
+rect -23 -125 23 -113
+rect 73 113 119 125
+rect 73 -113 79 113
+rect 113 -113 119 113
+rect 73 -125 119 -113
+rect 169 113 215 125
+rect 169 -113 175 113
+rect 209 -113 215 113
+rect 169 -125 215 -113
+rect 265 113 311 125
+rect 265 -113 271 113
+rect 305 -113 311 113
+rect 265 -125 311 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -402 -282 402 282
+string parameters w 1.25 l 0.150 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag
new file mode 100644
index 0000000..7a5d479
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_BHR94T.mag

@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
+rect -311 -335 311 335
+<< nmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< ndiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< ndiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< psubdiff >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< psubdiffcont >>
+rect -275 -203 -241 203
+rect 241 -203 275 203
+rect -179 -299 179 -265
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -151 -81 -125
+rect -15 -151 15 -125
+rect 81 -151 111 -125
+<< locali >>
+rect -275 203 -241 265
+rect 241 203 275 265
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -265 -241 -203
+rect 241 -265 275 -203
+rect -275 -299 -179 -265
+rect 179 -299 275 -265
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -258 -282 258 282
+string parameters w 1.25 l 0.150 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag b/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag
new file mode 100644
index 0000000..b91111d
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_C3YG4M.mag

@@ -0,0 +1,70 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623451718
+<< pwell >>
+rect -263 -255 263 255
+<< nmos >>
+rect -63 -45 -33 45
+rect 33 -45 63 45
+<< ndiff >>
+rect -125 33 -63 45
+rect -125 -33 -113 33
+rect -79 -33 -63 33
+rect -125 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 125 45
+rect 63 -33 79 33
+rect 113 -33 125 33
+rect 63 -45 125 -33
+<< ndiffc >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< psubdiff >>
+rect -193 -219 -131 -185
+rect 131 -219 193 -185
+<< psubdiffcont >>
+rect -131 -219 131 -185
+<< poly >>
+rect -129 71 -33 137
+rect -63 45 -33 71
+rect 33 67 99 133
+rect 33 45 63 67
+rect -63 -71 -33 -45
+rect 33 -71 63 -45
+<< locali >>
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+rect -193 -219 -131 -185
+rect 131 -219 193 -185
+<< viali >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< metal1 >>
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
+rect -119 -45 -73 -33
+rect -23 33 23 45
+rect -23 -33 -17 33
+rect 17 -33 23 33
+rect -23 -45 23 -33
+rect 73 33 119 45
+rect 73 -33 79 33
+rect 113 -33 119 33
+rect 73 -45 119 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -202 210 202
+string parameters w 0.45 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag b/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag
new file mode 100644
index 0000000..ac94e9a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_CBAU6Y.mag

@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623181853
+<< error_p >>
+rect -29 -188 29 -182
+rect -29 -222 -17 -188
+rect -29 -228 29 -222
+<< pwell >>
+rect -211 -360 211 360
+<< nmos >>
+rect -15 -150 15 150
+<< ndiff >>
+rect -73 138 -15 150
+rect -73 -138 -61 138
+rect -27 -138 -15 138
+rect -73 -150 -15 -138
+rect 15 138 73 150
+rect 15 -138 27 138
+rect 61 -138 73 138
+rect 15 -150 73 -138
+<< ndiffc >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< psubdiff >>
+rect -175 290 175 324
+rect -175 228 -141 290
+rect 141 228 175 290
+rect -175 -290 -141 -228
+rect 141 -290 175 -228
+rect -175 -324 -79 -290
+rect 79 -324 175 -290
+<< psubdiffcont >>
+rect -175 -228 -141 228
+rect 141 -228 175 228
+rect -79 -324 79 -290
+<< poly >>
+rect -15 150 15 176
+rect -15 -172 15 -150
+rect -33 -188 33 -172
+rect -33 -222 -17 -188
+rect 17 -222 33 -188
+rect -33 -238 33 -222
+<< polycont >>
+rect -17 -222 17 -188
+<< locali >>
+rect -175 290 175 324
+rect -175 228 -141 290
+rect 141 228 175 290
+rect -61 138 -27 154
+rect -61 -154 -27 -138
+rect 27 138 61 154
+rect 27 -154 61 -138
+rect -33 -222 -17 -188
+rect 17 -222 33 -188
+rect -175 -290 -141 -228
+rect 141 -290 175 -228
+rect -175 -324 -79 -290
+rect 79 -324 175 -290
+<< viali >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+rect -17 -222 17 -188
+<< metal1 >>
+rect -67 138 -21 150
+rect -67 -138 -61 138
+rect -27 -138 -21 138
+rect -67 -150 -21 -138
+rect 21 138 67 150
+rect 21 -138 27 138
+rect 61 -138 67 138
+rect 21 -150 67 -138
+rect -29 -188 29 -182
+rect -29 -222 -17 -188
+rect 17 -222 29 -188
+rect -29 -228 29 -222
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -307 158 307
+string parameters w 1.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag b/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag
new file mode 100644
index 0000000..f257bf6
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_DXA56D.mag

@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623431064
+<< pwell >>
+rect -359 -252 359 252
+<< nmos >>
+rect -159 -42 -129 42
+rect -63 -42 -33 42
+rect 33 -42 63 42
+rect 129 -42 159 42
+<< ndiff >>
+rect -221 30 -159 42
+rect -221 -30 -209 30
+rect -175 -30 -159 30
+rect -221 -42 -159 -30
+rect -129 30 -63 42
+rect -129 -30 -113 30
+rect -79 -30 -63 30
+rect -129 -42 -63 -30
+rect -33 30 33 42
+rect -33 -30 -17 30
+rect 17 -30 33 30
+rect -33 -42 33 -30
+rect 63 30 129 42
+rect 63 -30 79 30
+rect 113 -30 129 30
+rect 63 -42 129 -30
+rect 159 30 221 42
+rect 159 -30 175 30
+rect 209 -30 221 30
+rect 159 -42 221 -30
+<< ndiffc >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< psubdiff >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< psubdiffcont >>
+rect -323 -120 -289 120
+rect 289 -120 323 120
+rect -227 -216 227 -182
+<< poly >>
+rect -159 42 -129 68
+rect -63 42 -33 68
+rect 33 42 63 68
+rect 129 42 159 68
+rect -159 -68 -129 -42
+rect -63 -68 -33 -42
+rect 33 -68 63 -42
+rect 129 -68 159 -42
+<< locali >>
+rect -323 120 -289 182
+rect 289 120 323 182
+rect -209 30 -175 46
+rect -209 -46 -175 -30
+rect -113 30 -79 46
+rect -113 -46 -79 -30
+rect -17 30 17 46
+rect -17 -46 17 -30
+rect 79 30 113 46
+rect 79 -46 113 -30
+rect 175 30 209 46
+rect 175 -46 209 -30
+rect -323 -182 -289 -120
+rect 289 -182 323 -120
+rect -323 -216 -227 -182
+rect 227 -216 323 -182
+<< viali >>
+rect -209 -30 -175 30
+rect -113 -30 -79 30
+rect -17 -30 17 30
+rect 79 -30 113 30
+rect 175 -30 209 30
+<< metal1 >>
+rect -215 30 -169 42
+rect -215 -30 -209 30
+rect -175 -30 -169 30
+rect -215 -42 -169 -30
+rect -119 30 -73 42
+rect -119 -30 -113 30
+rect -79 -30 -73 30
+rect -119 -42 -73 -30
+rect -23 30 23 42
+rect -23 -30 -17 30
+rect 17 -30 23 30
+rect -23 -42 23 -30
+rect 73 30 119 42
+rect 73 -30 79 30
+rect 113 -30 119 30
+rect 73 -42 119 -30
+rect 169 30 215 42
+rect 169 -30 175 30
+rect 209 -30 215 30
+rect 169 -42 215 -30
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -199 306 199
+string parameters w 0.420 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag b/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag
new file mode 100644
index 0000000..4981460
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_EDT3AT.mag

@@ -0,0 +1,76 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623244079
+<< pwell >>
+rect -211 -221 211 221
+<< nmos >>
+rect -15 -11 15 73
+<< ndiff >>
+rect -73 61 -15 73
+rect -73 1 -61 61
+rect -27 1 -15 61
+rect -73 -11 -15 1
+rect 15 61 73 73
+rect 15 1 27 61
+rect 61 1 73 61
+rect 15 -11 73 1
+<< ndiffc >>
+rect -61 1 -27 61
+rect 27 1 61 61
+<< psubdiff >>
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< psubdiffcont >>
+rect -175 -89 -141 89
+rect 141 -89 175 89
+rect -79 -185 79 -151
+<< poly >>
+rect -15 73 15 99
+rect -15 -33 15 -11
+rect -33 -49 33 -33
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -33 -99 33 -83
+<< polycont >>
+rect -17 -83 17 -49
+<< locali >>
+rect -175 89 -141 151
+rect 141 89 175 151
+rect -61 61 -27 77
+rect -61 -15 -27 1
+rect 27 61 61 77
+rect 27 -15 61 1
+rect -33 -83 -17 -49
+rect 17 -83 33 -49
+rect -175 -151 -141 -89
+rect 141 -151 175 -89
+rect -175 -185 -79 -151
+rect 79 -185 175 -151
+<< viali >>
+rect -61 1 -27 61
+rect 27 1 61 61
+rect -17 -83 17 -49
+<< metal1 >>
+rect -67 61 -21 73
+rect -67 1 -61 61
+rect -27 1 -21 61
+rect -67 -11 -21 1
+rect 21 61 67 73
+rect 21 1 27 61
+rect 61 1 67 61
+rect 21 -11 67 1
+rect -32 -49 32 -40
+rect -32 -83 -17 -49
+rect 17 -83 32 -49
+rect -32 -92 32 -83
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -168 158 168
+string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag b/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag
new file mode 100644
index 0000000..45ca065
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_KU9PSX.mag

@@ -0,0 +1,103 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< pwell >>
+rect -263 -305 263 305
+<< nmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< ndiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< ndiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< psubdiff >>
+rect -227 173 -193 235
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< psubdiffcont >>
+rect -227 -173 -193 173
+rect -168 -269 178 -235
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -117 -33 -95
+rect 33 -117 63 -95
+rect -81 -133 81 -117
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -81 -183 81 -167
+<< polycont >>
+rect -65 -167 65 -133
+<< locali >>
+rect -227 173 -193 235
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -81 -167 -65 -133
+rect 65 -167 81 -133
+rect -227 -235 -193 -173
+rect -227 -269 -168 -235
+rect 178 -269 227 -235
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+rect -65 -167 65 -133
+<< metal1 >>
+rect -119 84 -73 95
+rect -132 -85 -122 84
+rect -70 -85 -60 84
+rect -23 83 23 95
+rect 73 84 119 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -119 -95 -73 -85
+rect -23 -95 23 -83
+rect 60 -85 70 84
+rect 122 -85 132 84
+rect 73 -95 119 -85
+rect -77 -133 77 -127
+rect -77 -167 -65 -133
+rect 65 -167 77 -133
+rect -77 -173 77 -167
+<< via1 >>
+rect -122 83 -70 84
+rect -122 -83 -113 83
+rect -113 -83 -79 83
+rect -79 -83 -70 83
+rect -122 -85 -70 -83
+rect 70 83 122 84
+rect 70 -83 79 83
+rect 79 -83 113 83
+rect 113 -83 122 83
+rect 70 -85 122 -83
+<< metal2 >>
+rect -122 84 -70 94
+rect 70 84 122 94
+rect -70 -85 70 84
+rect -122 -95 -70 -85
+rect 70 -95 122 -85
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -210 -252 210 252
+string parameters w 0.95 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag b/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag
new file mode 100644
index 0000000..4c1aa8b
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_MUHGM9.mag

@@ -0,0 +1,340 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< pwell >>
+rect -1127 -285 1127 285
+<< nmos >>
+rect -927 -75 -897 75
+rect -831 -75 -801 75
+rect -735 -75 -705 75
+rect -639 -75 -609 75
+rect -543 -75 -513 75
+rect -447 -75 -417 75
+rect -351 -75 -321 75
+rect -255 -75 -225 75
+rect -159 -75 -129 75
+rect -63 -75 -33 75
+rect 33 -75 63 75
+rect 129 -75 159 75
+rect 225 -75 255 75
+rect 321 -75 351 75
+rect 417 -75 447 75
+rect 513 -75 543 75
+rect 609 -75 639 75
+rect 705 -75 735 75
+rect 801 -75 831 75
+rect 897 -75 927 75
+<< ndiff >>
+rect -989 63 -927 75
+rect -989 -63 -977 63
+rect -943 -63 -927 63
+rect -989 -75 -927 -63
+rect -897 63 -831 75
+rect -897 -63 -881 63
+rect -847 -63 -831 63
+rect -897 -75 -831 -63
+rect -801 63 -735 75
+rect -801 -63 -785 63
+rect -751 -63 -735 63
+rect -801 -75 -735 -63
+rect -705 63 -639 75
+rect -705 -63 -689 63
+rect -655 -63 -639 63
+rect -705 -75 -639 -63
+rect -609 63 -543 75
+rect -609 -63 -593 63
+rect -559 -63 -543 63
+rect -609 -75 -543 -63
+rect -513 63 -447 75
+rect -513 -63 -497 63
+rect -463 -63 -447 63
+rect -513 -75 -447 -63
+rect -417 63 -351 75
+rect -417 -63 -401 63
+rect -367 -63 -351 63
+rect -417 -75 -351 -63
+rect -321 63 -255 75
+rect -321 -63 -305 63
+rect -271 -63 -255 63
+rect -321 -75 -255 -63
+rect -225 63 -159 75
+rect -225 -63 -209 63
+rect -175 -63 -159 63
+rect -225 -75 -159 -63
+rect -129 63 -63 75
+rect -129 -63 -113 63
+rect -79 -63 -63 63
+rect -129 -75 -63 -63
+rect -33 63 33 75
+rect -33 -63 -17 63
+rect 17 -63 33 63
+rect -33 -75 33 -63
+rect 63 63 129 75
+rect 63 -63 79 63
+rect 113 -63 129 63
+rect 63 -75 129 -63
+rect 159 63 225 75
+rect 159 -63 175 63
+rect 209 -63 225 63
+rect 159 -75 225 -63
+rect 255 63 321 75
+rect 255 -63 271 63
+rect 305 -63 321 63
+rect 255 -75 321 -63
+rect 351 63 417 75
+rect 351 -63 367 63
+rect 401 -63 417 63
+rect 351 -75 417 -63
+rect 447 63 513 75
+rect 447 -63 463 63
+rect 497 -63 513 63
+rect 447 -75 513 -63
+rect 543 63 609 75
+rect 543 -63 559 63
+rect 593 -63 609 63
+rect 543 -75 609 -63
+rect 639 63 705 75
+rect 639 -63 655 63
+rect 689 -63 705 63
+rect 639 -75 705 -63
+rect 735 63 801 75
+rect 735 -63 751 63
+rect 785 -63 801 63
+rect 735 -75 801 -63
+rect 831 63 897 75
+rect 831 -63 847 63
+rect 881 -63 897 63
+rect 831 -75 897 -63
+rect 927 63 989 75
+rect 927 -63 943 63
+rect 977 -63 989 63
+rect 927 -75 989 -63
+<< ndiffc >>
+rect -977 -63 -943 63
+rect -881 -63 -847 63
+rect -785 -63 -751 63
+rect -689 -63 -655 63
+rect -593 -63 -559 63
+rect -497 -63 -463 63
+rect -401 -63 -367 63
+rect -305 -63 -271 63
+rect -209 -63 -175 63
+rect -113 -63 -79 63
+rect -17 -63 17 63
+rect 79 -63 113 63
+rect 175 -63 209 63
+rect 271 -63 305 63
+rect 367 -63 401 63
+rect 463 -63 497 63
+rect 559 -63 593 63
+rect 655 -63 689 63
+rect 751 -63 785 63
+rect 847 -63 881 63
+rect 943 -63 977 63
+<< psubdiff >>
+rect -1057 -249 -995 -215
+rect 995 -249 1057 -215
+<< psubdiffcont >>
+rect -995 -249 995 -215
+<< poly >>
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+<< metal1 >>
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+rect 841 -75 887 -63
+rect 937 63 983 75
+rect 937 -63 943 63
+rect 977 -63 983 63
+rect 937 -75 983 -63
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1074 -232 1074 232
+string parameters w 0.75 l 0.150 m 1 nf 20 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag b/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag
new file mode 100644
index 0000000..ee8a86a
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_U2JGXT.mag

@@ -0,0 +1,86 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623980668
+<< pwell >>
+rect -226 -321 226 510
+rect -226 -387 -114 -321
+rect -48 -322 226 -321
+rect -226 -388 -111 -387
+rect -99 -388 226 -322
+rect -226 -510 226 -388
+<< nmos >>
+rect -30 -300 30 300
+<< ndiff >>
+rect -88 288 -30 300
+rect -88 -288 -76 288
+rect -42 -288 -30 288
+rect -88 -300 -30 -288
+rect 30 288 88 300
+rect 30 -288 42 288
+rect 76 -288 88 288
+rect 30 -300 88 -288
+<< ndiffc >>
+rect -76 -288 -42 288
+rect 42 -288 76 288
+<< psubdiff >>
+rect -190 440 -94 474
+rect 94 440 190 474
+rect -190 378 -156 440
+rect 156 378 190 440
+rect -190 -440 -156 -378
+rect 156 -440 190 -378
+rect -190 -474 -94 -440
+rect 94 -474 190 -440
+<< psubdiffcont >>
+rect -94 440 94 474
+rect -190 -378 -156 378
+rect 156 -378 190 378
+rect -94 -474 94 -440
+<< poly >>
+rect -30 300 30 326
+rect -30 -322 30 -300
+rect -99 -338 33 -322
+rect -99 -372 -83 -338
+rect 17 -372 33 -338
+rect -99 -388 33 -372
+<< polycont >>
+rect -83 -372 17 -338
+<< locali >>
+rect -190 440 -94 474
+rect 94 440 190 474
+rect -190 378 -156 440
+rect 156 378 190 440
+rect -76 288 -42 304
+rect -76 -304 -42 -288
+rect 42 288 76 304
+rect 42 -304 76 -288
+rect -99 -372 -83 -338
+rect 17 -372 33 -338
+rect -190 -440 -156 -378
+rect 156 -440 190 -378
+rect -190 -474 -94 -440
+rect 94 -474 190 -440
+<< viali >>
+rect -76 -288 -42 288
+rect 42 -288 76 288
+rect -83 -372 17 -338
+<< metal1 >>
+rect -82 288 -36 300
+rect -82 -288 -76 288
+rect -42 -288 -36 288
+rect -82 -300 -36 -288
+rect 36 288 82 300
+rect 36 -288 42 288
+rect 76 -288 82 288
+rect 36 -300 82 -288
+rect -98 -338 32 -329
+rect -98 -372 -83 -338
+rect 17 -372 32 -338
+rect -98 -381 32 -372
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -173 -457 173 457
+string parameters w 3 l 0.3 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag b/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag
new file mode 100644
index 0000000..a627d87
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_YCGG98.mag

@@ -0,0 +1,419 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< pwell >>
+rect -1367 -285 1367 285
+<< nmos >>
+rect -1167 -75 -1137 75
+rect -1071 -75 -1041 75
+rect -975 -75 -945 75
+rect -879 -75 -849 75
+rect -783 -75 -753 75
+rect -687 -75 -657 75
+rect -591 -75 -561 75
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+rect -399 -75 -369 75
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+rect -207 -75 -177 75
+rect -111 -75 -81 75
+rect -15 -75 15 75
+rect 81 -75 111 75
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+rect 657 -75 687 75
+rect 753 -75 783 75
+rect 849 -75 879 75
+rect 945 -75 975 75
+rect 1041 -75 1071 75
+rect 1137 -75 1167 75
+<< ndiff >>
+rect -1229 63 -1167 75
+rect -1229 -63 -1217 63
+rect -1183 -63 -1167 63
+rect -1229 -75 -1167 -63
+rect -1137 63 -1071 75
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+rect 687 63 753 75
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+rect 1217 -63 1229 63
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+rect 799 -63 833 63
+rect 895 -63 929 63
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+rect 1087 -63 1121 63
+rect 1183 -63 1217 63
+<< psubdiff >>
+rect 1297 153 1331 215
+rect 1297 -215 1331 -153
+rect -1297 -249 -1235 -215
+rect 1235 -249 1331 -215
+<< psubdiffcont >>
+rect 1297 -153 1331 153
+rect -1235 -249 1235 -215
+<< poly >>
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+rect -1167 75 -1137 101
+rect -1071 75 -1041 101
+rect -975 75 -945 101
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+rect -783 75 -753 101
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+rect -1167 -101 -1137 -75
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+rect 561 -101 591 -75
+rect 657 -101 687 -75
+rect 753 -101 783 -75
+rect 849 -101 879 -75
+rect 945 -101 975 -75
+rect 1041 -101 1071 -75
+rect 1137 -101 1167 -75
+<< locali >>
+rect 1297 153 1331 215
+rect -1217 63 -1183 79
+rect -1217 -79 -1183 -63
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+rect -1121 -79 -1087 -63
+rect -1025 63 -991 79
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+rect 1297 -215 1331 -153
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+rect 1235 -249 1331 -215
+<< viali >>
+rect -1217 -63 -1183 63
+rect -1121 -63 -1087 63
+rect -1025 -63 -991 63
+rect -929 -63 -895 63
+rect -833 -63 -799 63
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+rect 607 -63 641 63
+rect 703 -63 737 63
+rect 799 -63 833 63
+rect 895 -63 929 63
+rect 991 -63 1025 63
+rect 1087 -63 1121 63
+rect 1183 -63 1217 63
+<< metal1 >>
+rect -1223 63 -1177 75
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+rect -1183 -63 -1177 63
+rect -1223 -75 -1177 -63
+rect -1127 63 -1081 75
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+rect 25 63 71 75
+rect 25 -63 31 63
+rect 65 -63 71 63
+rect 25 -75 71 -63
+rect 121 63 167 75
+rect 121 -63 127 63
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+rect 217 63 263 75
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+rect 313 63 359 75
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+rect 409 63 455 75
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+rect 505 63 551 75
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+rect 545 -63 551 63
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+rect 601 63 647 75
+rect 601 -63 607 63
+rect 641 -63 647 63
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+rect 697 63 743 75
+rect 697 -63 703 63
+rect 737 -63 743 63
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+rect 793 63 839 75
+rect 793 -63 799 63
+rect 833 -63 839 63
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+rect 889 63 935 75
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+rect 929 -63 935 63
+rect 889 -75 935 -63
+rect 985 63 1031 75
+rect 985 -63 991 63
+rect 1025 -63 1031 63
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+rect 1081 63 1127 75
+rect 1081 -63 1087 63
+rect 1121 -63 1127 63
+rect 1081 -75 1127 -63
+rect 1177 63 1223 75
+rect 1177 -63 1183 63
+rect 1217 -63 1223 63
+rect 1177 -75 1223 -63
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -1314 -232 1314 232
+string parameters w 0.75 l 0.150 m 1 nf 25 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag b/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag
new file mode 100644
index 0000000..f43b4a4
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_ZCYAJJ.mag

@@ -0,0 +1,105 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< pwell >>
+rect -359 -255 359 255
+<< nmos >>
+rect -159 -45 -129 45
+rect -63 -45 -33 45
+rect 33 -45 63 45
+rect 129 -45 159 45
+<< ndiff >>
+rect -221 33 -159 45
+rect -221 -33 -209 33
+rect -175 -33 -159 33
+rect -221 -45 -159 -33
+rect -129 33 -63 45
+rect -129 -33 -113 33
+rect -79 -33 -63 33
+rect -129 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 129 45
+rect 63 -33 79 33
+rect 113 -33 129 33
+rect 63 -45 129 -33
+rect 159 33 221 45
+rect 159 -33 175 33
+rect 209 -33 221 33
+rect 159 -45 221 -33
+<< ndiffc >>
+rect -209 -33 -175 33
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+rect 175 -33 209 33
+<< psubdiff >>
+rect -323 123 -289 185
+rect -323 -185 -289 -123
+rect -323 -219 -227 -185
+rect 227 -219 289 -185
+<< psubdiffcont >>
+rect -323 -123 -289 123
+rect -227 -219 227 -185
+<< poly >>
+rect -63 113 159 173
+rect -159 45 -129 71
+rect -63 45 -33 113
+rect 33 45 63 71
+rect 129 45 159 113
+rect -159 -113 -129 -45
+rect -63 -71 -33 -45
+rect 33 -113 63 -45
+rect 129 -71 159 -45
+rect -159 -173 63 -113
+<< locali >>
+rect -323 123 -289 185
+rect -209 33 -175 49
+rect -209 -49 -175 -33
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+rect 175 33 209 49
+rect 175 -49 209 -33
+rect -323 -185 -289 -123
+rect -323 -219 -227 -185
+rect 227 -219 289 -185
+<< viali >>
+rect -209 -33 -175 33
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+rect 175 -33 209 33
+<< metal1 >>
+rect -215 33 -169 45
+rect -215 -33 -209 33
+rect -175 -33 -169 33
+rect -215 -45 -169 -33
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
+rect -119 -45 -73 -33
+rect -23 33 23 45
+rect -23 -33 -17 33
+rect 17 -33 23 33
+rect -23 -45 23 -33
+rect 73 33 119 45
+rect 73 -33 79 33
+rect 113 -33 119 33
+rect 73 -45 119 -33
+rect 169 33 215 45
+rect 169 -33 175 33
+rect 209 -33 215 33
+rect 169 -45 215 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -306 -202 306 202
+string parameters w 0.45 l 0.150 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag b/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag
new file mode 100644
index 0000000..47c6c0d
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_ZXAV3F.mag

@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< pwell >>
+rect -211 -255 211 255
+<< nmos >>
+rect -15 -45 15 45
+<< ndiff >>
+rect -73 33 -15 45
+rect -73 -33 -61 33
+rect -27 -33 -15 33
+rect -73 -45 -15 -33
+rect 15 33 73 45
+rect 15 -33 27 33
+rect 61 -33 73 33
+rect 15 -45 73 -33
+<< ndiffc >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< psubdiff >>
+rect 141 123 175 185
+rect 141 -185 175 -123
+rect -141 -219 -79 -185
+rect 79 -219 175 -185
+<< psubdiffcont >>
+rect 141 -123 175 123
+rect -79 -219 79 -185
+<< poly >>
+rect -33 67 15 133
+rect -15 45 15 67
+rect -15 -71 15 -45
+<< locali >>
+rect 141 123 175 185
+rect -61 33 -27 49
+rect -61 -49 -27 -33
+rect 27 33 61 49
+rect 27 -49 61 -33
+rect 141 -185 175 -123
+rect -141 -219 -79 -185
+rect 79 -219 175 -185
+<< viali >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< metal1 >>
+rect -67 33 -21 45
+rect -67 -33 -61 33
+rect -27 -33 -21 33
+rect -67 -45 -21 -33
+rect 21 33 67 45
+rect 21 -33 27 33
+rect 61 -33 67 33
+rect 21 -45 67 -33
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -202 158 202
+string parameters w 0.45 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 0 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_4757AC.mag b/mag/sky130_fd_pr__pfet_01v8_4757AC.mag
new file mode 100644
index 0000000..317fddb
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4757AC.mag

@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623181853
+<< error_p >>
+rect -29 231 29 237
+rect -29 197 -17 231
+rect -29 191 29 197
+<< nwell >>
+rect -211 -369 211 369
+<< pmos >>
+rect -15 -150 15 150
+<< pdiff >>
+rect -73 138 -15 150
+rect -73 -138 -61 138
+rect -27 -138 -15 138
+rect -73 -150 -15 -138
+rect 15 138 73 150
+rect 15 -138 27 138
+rect 61 -138 73 138
+rect 15 -150 73 -138
+<< pdiffc >>
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< nsubdiff >>
+rect -175 299 -79 333
+rect 79 299 175 333
+rect -175 237 -141 299
+rect 141 237 175 299
+rect -175 -299 -141 -237
+rect 141 -299 175 -237
+rect -175 -333 175 -299
+<< nsubdiffcont >>
+rect -79 299 79 333
+rect -175 -237 -141 237
+rect 141 -237 175 237
+<< poly >>
+rect -33 231 33 247
+rect -33 197 -17 231
+rect 17 197 33 231
+rect -33 181 33 197
+rect -15 150 15 181
+rect -15 -181 15 -150
+<< polycont >>
+rect -17 197 17 231
+<< locali >>
+rect -175 299 -79 333
+rect 79 299 175 333
+rect -175 237 -141 299
+rect 141 237 175 299
+rect -33 197 -17 231
+rect 17 197 33 231
+rect -61 138 -27 154
+rect -61 -154 -27 -138
+rect 27 138 61 154
+rect 27 -154 61 -138
+rect -175 -299 -141 -237
+rect 141 -299 175 -237
+rect -175 -333 175 -299
+<< viali >>
+rect -17 197 17 231
+rect -61 -138 -27 138
+rect 27 -138 61 138
+<< metal1 >>
+rect -29 231 29 237
+rect -29 197 -17 231
+rect 17 197 29 231
+rect -29 191 29 197
+rect -67 138 -21 150
+rect -67 -138 -61 138
+rect -27 -138 -21 138
+rect -67 -150 -21 -138
+rect 21 138 67 150
+rect 21 -138 27 138
+rect 61 -138 67 138
+rect 21 -150 67 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -316 158 316
+string parameters w 1.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_4798MH.mag b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag
new file mode 100644
index 0000000..5285d6f
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4798MH.mag

@@ -0,0 +1,93 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag b/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag
new file mode 100644
index 0000000..af53822
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4F35BC.mag

@@ -0,0 +1,111 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623451685
+<< nwell >>
+rect -359 -309 359 309
+<< pmos >>
+rect -159 -90 -129 90
+rect -63 -90 -33 90
+rect 33 -90 63 90
+rect 129 -90 159 90
+<< pdiff >>
+rect -221 78 -159 90
+rect -221 -78 -209 78
+rect -175 -78 -159 78
+rect -221 -90 -159 -78
+rect -129 78 -63 90
+rect -129 -78 -113 78
+rect -79 -78 -63 78
+rect -129 -90 -63 -78
+rect -33 78 33 90
+rect -33 -78 -17 78
+rect 17 -78 33 78
+rect -33 -90 33 -78
+rect 63 78 129 90
+rect 63 -78 79 78
+rect 113 -78 129 78
+rect 63 -90 129 -78
+rect 159 78 221 90
+rect 159 -78 175 78
+rect 209 -78 221 78
+rect 159 -90 221 -78
+<< pdiffc >>
+rect -209 -78 -175 78
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+rect 175 -78 209 78
+<< nsubdiff >>
+rect -323 239 -227 273
+rect 227 239 323 273
+rect -323 177 -289 239
+rect 289 177 323 239
+rect -323 -239 -289 -177
+rect 289 -239 323 -177
+<< nsubdiffcont >>
+rect -227 239 227 273
+rect -323 -177 -289 177
+rect 289 -177 323 177
+<< poly >>
+rect -63 159 159 208
+rect -159 90 -129 116
+rect -63 90 -33 159
+rect 33 90 63 116
+rect 129 90 159 159
+rect -159 -158 -129 -90
+rect -63 -116 -33 -90
+rect 33 -158 63 -90
+rect -159 -207 63 -158
+rect 129 -116 159 -90
+rect 129 -182 195 -116
+<< locali >>
+rect -323 239 -227 273
+rect 227 239 323 273
+rect -323 177 -289 239
+rect 289 177 323 239
+rect -209 78 -175 94
+rect -209 -94 -175 -78
+rect -113 78 -79 94
+rect -113 -94 -79 -78
+rect -17 78 17 94
+rect -17 -94 17 -78
+rect 79 78 113 94
+rect 79 -94 113 -78
+rect 175 78 209 94
+rect 175 -94 209 -78
+rect -323 -239 -289 -177
+rect 289 -239 323 -177
+<< viali >>
+rect -209 -78 -175 78
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+rect 175 -78 209 78
+<< metal1 >>
+rect -215 78 -169 90
+rect -215 -78 -209 78
+rect -175 -78 -169 78
+rect -215 -90 -169 -78
+rect -119 78 -73 90
+rect -119 -78 -113 78
+rect -79 -78 -73 78
+rect -119 -90 -73 -78
+rect -23 78 23 90
+rect -23 -78 -17 78
+rect 17 -78 23 78
+rect -23 -90 23 -78
+rect 73 78 119 90
+rect 73 -78 79 78
+rect 113 -78 119 78
+rect 73 -90 119 -78
+rect 169 78 215 90
+rect 169 -78 175 78
+rect 209 -78 215 78
+rect 169 -90 215 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -256 306 256
+string parameters w 0.9 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag b/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag
new file mode 100644
index 0000000..bc2dddd
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4F7GBC.mag

@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623450719
+<< nwell >>
+rect -211 -309 211 309
+<< pmos >>
+rect -15 -90 15 90
+<< pdiff >>
+rect -73 78 -15 90
+rect -73 -78 -61 78
+rect -27 -78 -15 78
+rect -73 -90 -15 -78
+rect 15 78 73 90
+rect 15 -78 27 78
+rect 61 -78 73 78
+rect 15 -90 73 -78
+<< pdiffc >>
+rect -61 -78 -27 78
+rect 27 -78 61 78
+<< nsubdiff >>
+rect -141 239 -79 273
+rect 79 239 175 273
+rect 141 177 175 239
+rect 141 -239 175 -177
+<< nsubdiffcont >>
+rect -79 239 79 273
+rect 141 -177 175 177
+<< poly >>
+rect -15 90 15 121
+rect -15 -121 15 -90
+rect -51 -187 15 -121
+<< locali >>
+rect -141 239 -79 273
+rect 79 239 175 273
+rect 141 177 175 239
+rect -61 78 -27 94
+rect -61 -94 -27 -78
+rect 27 78 61 94
+rect 27 -94 61 -78
+rect 141 -239 175 -177
+<< viali >>
+rect -61 -78 -27 78
+rect 27 -78 61 78
+<< metal1 >>
+rect -67 78 -21 90
+rect -67 -78 -61 78
+rect -27 -78 -21 78
+rect -67 -90 -21 -78
+rect 21 78 67 90
+rect 21 -78 27 78
+rect 61 -78 67 78
+rect 21 -90 67 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -256 158 256
+string parameters w 0.9 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag b/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag
new file mode 100644
index 0000000..98942cb
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_4ML9WA.mag

@@ -0,0 +1,189 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< nwell >>
+rect -2457 -634 2457 634
+<< pmos >>
+rect -2261 -486 -1861 414
+rect -1803 -486 -1403 414
+rect -1345 -486 -945 414
+rect -887 -486 -487 414
+rect -429 -486 -29 414
+rect 29 -486 429 414
+rect 487 -486 887 414
+rect 945 -486 1345 414
+rect 1403 -486 1803 414
+rect 1861 -486 2261 414
+<< pdiff >>
+rect -2319 402 -2261 414
+rect -2319 -474 -2307 402
+rect -2273 -474 -2261 402
+rect -2319 -486 -2261 -474
+rect -1861 402 -1803 414
+rect -1861 -474 -1849 402
+rect -1815 -474 -1803 402
+rect -1861 -486 -1803 -474
+rect -1403 402 -1345 414
+rect -1403 -474 -1391 402
+rect -1357 -474 -1345 402
+rect -1403 -486 -1345 -474
+rect -945 402 -887 414
+rect -945 -474 -933 402
+rect -899 -474 -887 402
+rect -945 -486 -887 -474
+rect -487 402 -429 414
+rect -487 -474 -475 402
+rect -441 -474 -429 402
+rect -487 -486 -429 -474
+rect -29 402 29 414
+rect -29 -474 -17 402
+rect 17 -474 29 402
+rect -29 -486 29 -474
+rect 429 402 487 414
+rect 429 -474 441 402
+rect 475 -474 487 402
+rect 429 -486 487 -474
+rect 887 402 945 414
+rect 887 -474 899 402
+rect 933 -474 945 402
+rect 887 -486 945 -474
+rect 1345 402 1403 414
+rect 1345 -474 1357 402
+rect 1391 -474 1403 402
+rect 1345 -486 1403 -474
+rect 1803 402 1861 414
+rect 1803 -474 1815 402
+rect 1849 -474 1861 402
+rect 1803 -486 1861 -474
+rect 2261 402 2319 414
+rect 2261 -474 2273 402
+rect 2307 -474 2319 402
+rect 2261 -486 2319 -474
+<< pdiffc >>
+rect -2307 -474 -2273 402
+rect -1849 -474 -1815 402
+rect -1391 -474 -1357 402
+rect -933 -474 -899 402
+rect -475 -474 -441 402
+rect -17 -474 17 402
+rect 441 -474 475 402
+rect 899 -474 933 402
+rect 1357 -474 1391 402
+rect 1815 -474 1849 402
+rect 2273 -474 2307 402
+<< nsubdiff >>
+rect -2387 -598 -2325 -564
+rect 2325 -598 2387 -564
+<< nsubdiffcont >>
+rect -2325 -598 2325 -564
+<< poly >>
+rect -2261 455 2261 511
+rect -2261 414 -1861 455
+rect -1803 414 -1403 455
+rect -1345 414 -945 455
+rect -887 414 -487 455
+rect -429 414 -29 455
+rect 29 414 429 455
+rect 487 414 887 455
+rect 945 414 1345 455
+rect 1403 414 1803 455
+rect 1861 414 2261 455
+rect -2261 -512 -1861 -486
+rect -1803 -512 -1403 -486
+rect -1345 -512 -945 -486
+rect -887 -512 -487 -486
+rect -429 -512 -29 -486
+rect 29 -512 429 -486
+rect 487 -512 887 -486
+rect 945 -512 1345 -486
+rect 1403 -512 1803 -486
+rect 1861 -512 2261 -486
+<< locali >>
+rect -2307 402 -2273 418
+rect -2307 -490 -2273 -474
+rect -1849 402 -1815 418
+rect -1849 -490 -1815 -474
+rect -1391 402 -1357 418
+rect -1391 -490 -1357 -474
+rect -933 402 -899 418
+rect -933 -490 -899 -474
+rect -475 402 -441 418
+rect -475 -490 -441 -474
+rect -17 402 17 418
+rect -17 -490 17 -474
+rect 441 402 475 418
+rect 441 -490 475 -474
+rect 899 402 933 418
+rect 899 -490 933 -474
+rect 1357 402 1391 418
+rect 1357 -490 1391 -474
+rect 1815 402 1849 418
+rect 1815 -490 1849 -474
+rect 2273 402 2307 418
+rect 2273 -490 2307 -474
+rect -2387 -598 -2325 -564
+rect 2325 -598 2387 -564
+<< viali >>
+rect -2307 -474 -2273 402
+rect -1849 -474 -1815 402
+rect -1391 -474 -1357 402
+rect -933 -474 -899 402
+rect -475 -474 -441 402
+rect -17 -474 17 402
+rect 441 -474 475 402
+rect 899 -474 933 402
+rect 1357 -474 1391 402
+rect 1815 -474 1849 402
+rect 2273 -474 2307 402
+<< metal1 >>
+rect -2313 402 -2267 414
+rect -2313 -474 -2307 402
+rect -2273 -474 -2267 402
+rect -2313 -486 -2267 -474
+rect -1855 402 -1809 414
+rect -1855 -474 -1849 402
+rect -1815 -474 -1809 402
+rect -1855 -486 -1809 -474
+rect -1397 402 -1351 414
+rect -1397 -474 -1391 402
+rect -1357 -474 -1351 402
+rect -1397 -486 -1351 -474
+rect -939 402 -893 414
+rect -939 -474 -933 402
+rect -899 -474 -893 402
+rect -939 -486 -893 -474
+rect -481 402 -435 414
+rect -481 -474 -475 402
+rect -441 -474 -435 402
+rect -481 -486 -435 -474
+rect -23 402 23 414
+rect -23 -474 -17 402
+rect 17 -474 23 402
+rect -23 -486 23 -474
+rect 435 402 481 414
+rect 435 -474 441 402
+rect 475 -474 481 402
+rect 435 -486 481 -474
+rect 893 402 939 414
+rect 893 -474 899 402
+rect 933 -474 939 402
+rect 893 -486 939 -474
+rect 1351 402 1397 414
+rect 1351 -474 1357 402
+rect 1391 -474 1397 402
+rect 1351 -486 1397 -474
+rect 1809 402 1855 414
+rect 1809 -474 1815 402
+rect 1849 -474 1855 402
+rect 1809 -486 1855 -474
+rect 2267 402 2313 414
+rect 2267 -474 2273 402
+rect 2307 -474 2313 402
+rect 2267 -486 2313 -474
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -2404 -581 2404 581
+string parameters w 4.5 l 2 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag b/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag
new file mode 100644
index 0000000..79465e7
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_6KD4CR.mag

@@ -0,0 +1,68 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< nwell >>
+rect -263 -264 263 264
+<< pmos >>
+rect -63 -45 -33 45
+rect 33 -45 63 45
+<< pdiff >>
+rect -125 33 -63 45
+rect -125 -33 -113 33
+rect -79 -33 -63 33
+rect -125 -45 -63 -33
+rect -33 33 33 45
+rect -33 -33 -17 33
+rect 17 -33 33 33
+rect -33 -45 33 -33
+rect 63 33 125 45
+rect 63 -33 79 33
+rect 113 -33 125 33
+rect 63 -45 125 -33
+<< pdiffc >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< nsubdiff >>
+rect -193 194 -131 228
+rect 131 194 193 228
+<< nsubdiffcont >>
+rect -131 194 131 228
+<< poly >>
+rect -63 45 -33 71
+rect 33 45 63 71
+rect -63 -105 -33 -45
+rect 33 -105 63 -45
+<< locali >>
+rect -193 194 -131 228
+rect 131 194 193 228
+rect -113 33 -79 49
+rect -113 -49 -79 -33
+rect -17 33 17 49
+rect -17 -49 17 -33
+rect 79 33 113 49
+rect 79 -49 113 -33
+<< viali >>
+rect -113 -33 -79 33
+rect -17 -33 17 33
+rect 79 -33 113 33
+<< metal1 >>
+rect -119 33 -73 45
+rect -119 -33 -113 33
+rect -79 -33 -73 33
+rect -119 -45 -73 -33
+rect -23 33 23 45
+rect -23 -33 -17 33
+rect 17 -33 23 33
+rect -23 -45 23 -33
+rect 73 33 119 45
+rect 73 -33 79 33
+rect 113 -33 119 33
+rect 73 -45 119 -33
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -211 210 211
+string parameters w 0.45 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_7779BR.mag b/mag/sky130_fd_pr__pfet_01v8_7779BR.mag
new file mode 100644
index 0000000..20b419a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7779BR.mag

@@ -0,0 +1,59 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623449341
+<< nwell >>
+rect -211 -264 211 264
+<< pmos >>
+rect -15 -45 15 45
+<< pdiff >>
+rect -73 33 -15 45
+rect -73 -33 -61 33
+rect -27 -33 -15 33
+rect -73 -45 -15 -33
+rect 15 33 73 45
+rect 15 -33 27 33
+rect 61 -33 73 33
+rect 15 -45 73 -33
+<< pdiffc >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< nsubdiff >>
+rect -141 194 -79 228
+rect 79 194 175 228
+rect 141 132 175 194
+rect 141 -194 175 -132
+<< nsubdiffcont >>
+rect -79 194 79 228
+rect 141 -132 175 132
+<< poly >>
+rect -15 45 15 81
+rect -15 -76 15 -45
+rect -33 -142 15 -76
+<< locali >>
+rect -141 194 -79 228
+rect 79 194 175 228
+rect 141 132 175 194
+rect -61 33 -27 49
+rect -61 -49 -27 -33
+rect 27 33 61 49
+rect 27 -49 61 -33
+rect 141 -194 175 -132
+<< viali >>
+rect -61 -33 -27 33
+rect 27 -33 61 33
+<< metal1 >>
+rect -67 33 -21 45
+rect -67 -33 -61 33
+rect -27 -33 -21 33
+rect -67 -45 -21 -33
+rect 21 33 67 45
+rect 21 -33 27 33
+rect 61 -33 67 33
+rect 21 -45 67 -33
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -211 158 211
+string parameters w 0.45 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag b/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag
new file mode 100644
index 0000000..bb965f5
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7KT7MH.mag

@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -311 -344 311 344
+<< pmos >>
+rect -111 -125 -81 125
+rect -15 -125 15 125
+rect 81 -125 111 125
+<< pdiff >>
+rect -173 113 -111 125
+rect -173 -113 -161 113
+rect -127 -113 -111 113
+rect -173 -125 -111 -113
+rect -81 113 -15 125
+rect -81 -113 -65 113
+rect -31 -113 -15 113
+rect -81 -125 -15 -113
+rect 15 113 81 125
+rect 15 -113 31 113
+rect 65 -113 81 113
+rect 15 -125 81 -113
+rect 111 113 173 125
+rect 111 -113 127 113
+rect 161 -113 173 113
+rect 111 -125 173 -113
+<< pdiffc >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< nsubdiff >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< nsubdiffcont >>
+rect -179 274 179 308
+rect -275 -212 -241 212
+rect 241 -212 275 212
+<< poly >>
+rect -111 125 -81 151
+rect -15 125 15 151
+rect 81 125 111 151
+rect -111 -156 -81 -125
+rect -15 -156 15 -125
+rect 81 -156 111 -125
+rect -111 -186 111 -156
+<< locali >>
+rect -275 274 -179 308
+rect 179 274 275 308
+rect -275 212 -241 274
+rect 241 212 275 274
+rect -161 113 -127 129
+rect -161 -129 -127 -113
+rect -65 113 -31 129
+rect -65 -129 -31 -113
+rect 31 113 65 129
+rect 31 -129 65 -113
+rect 127 113 161 129
+rect 127 -129 161 -113
+rect -275 -274 -241 -212
+rect 241 -274 275 -212
+<< viali >>
+rect -161 -113 -127 113
+rect -65 -113 -31 113
+rect 31 -113 65 113
+rect 127 -113 161 113
+<< metal1 >>
+rect -167 113 -121 125
+rect -167 -113 -161 113
+rect -127 -113 -121 113
+rect -167 -125 -121 -113
+rect -71 113 -25 125
+rect -71 -113 -65 113
+rect -31 -113 -25 113
+rect -71 -125 -25 -113
+rect 25 113 71 125
+rect 25 -113 31 113
+rect 65 -113 71 113
+rect 25 -125 71 -113
+rect 121 113 167 125
+rect 121 -113 127 113
+rect 161 -113 167 113
+rect 121 -125 167 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -258 -291 258 291
+string parameters w 1.25 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag b/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag
new file mode 100644
index 0000000..c605806
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_7T83YG.mag

@@ -0,0 +1,70 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623450397
+<< nwell >>
+rect -263 -309 263 309
+<< pmos >>
+rect -63 -90 -33 90
+rect 33 -90 63 90
+<< pdiff >>
+rect -125 78 -63 90
+rect -125 -78 -113 78
+rect -79 -78 -63 78
+rect -125 -90 -63 -78
+rect -33 78 33 90
+rect -33 -78 -17 78
+rect 17 -78 33 78
+rect -33 -90 33 -78
+rect 63 78 125 90
+rect 63 -78 79 78
+rect 113 -78 125 78
+rect 63 -90 125 -78
+<< pdiffc >>
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+<< nsubdiff >>
+rect -193 239 -131 273
+rect 131 239 193 273
+<< nsubdiffcont >>
+rect -131 239 131 273
+<< poly >>
+rect -63 90 -33 116
+rect 33 90 63 116
+rect -63 -121 -33 -90
+rect -99 -187 -33 -121
+rect 33 -121 63 -90
+rect 33 -187 99 -121
+<< locali >>
+rect -193 239 -131 273
+rect 131 239 193 273
+rect -113 78 -79 94
+rect -113 -94 -79 -78
+rect -17 78 17 94
+rect -17 -94 17 -78
+rect 79 78 113 94
+rect 79 -94 113 -78
+<< viali >>
+rect -113 -78 -79 78
+rect -17 -78 17 78
+rect 79 -78 113 78
+<< metal1 >>
+rect -119 78 -73 90
+rect -119 -78 -113 78
+rect -79 -78 -73 78
+rect -119 -90 -73 -78
+rect -23 78 23 90
+rect -23 -78 -17 78
+rect 17 -78 23 78
+rect -23 -90 23 -78
+rect 73 78 119 90
+rect 73 -78 79 78
+rect 113 -78 119 78
+rect 73 -90 119 -78
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -256 210 256
+string parameters w 0.9 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag b/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag
new file mode 100644
index 0000000..3b6ae8b
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_8DL6ZL.mag

@@ -0,0 +1,261 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622843784
+<< nwell >>
+rect -647 -369 647 369
+<< pmos >>
+rect -447 -150 -417 150
+rect -351 -150 -321 150
+rect -255 -150 -225 150
+rect -159 -150 -129 150
+rect -63 -150 -33 150
+rect 33 -150 63 150
+rect 129 -150 159 150
+rect 225 -150 255 150
+rect 321 -150 351 150
+rect 417 -150 447 150
+<< pdiff >>
+rect -509 138 -447 150
+rect -509 -138 -497 138
+rect -463 -138 -447 138
+rect -509 -150 -447 -138
+rect -417 138 -351 150
+rect -417 -138 -401 138
+rect -367 -138 -351 138
+rect -417 -150 -351 -138
+rect -321 138 -255 150
+rect -321 -138 -305 138
+rect -271 -138 -255 138
+rect -321 -150 -255 -138
+rect -225 138 -159 150
+rect -225 -138 -209 138
+rect -175 -138 -159 138
+rect -225 -150 -159 -138
+rect -129 138 -63 150
+rect -129 -138 -113 138
+rect -79 -138 -63 138
+rect -129 -150 -63 -138
+rect -33 138 33 150
+rect -33 -138 -17 138
+rect 17 -138 33 138
+rect -33 -150 33 -138
+rect 63 138 129 150
+rect 63 -138 79 138
+rect 113 -138 129 138
+rect 63 -150 129 -138
+rect 159 138 225 150
+rect 159 -138 175 138
+rect 209 -138 225 138
+rect 159 -150 225 -138
+rect 255 138 321 150
+rect 255 -138 271 138
+rect 305 -138 321 138
+rect 255 -150 321 -138
+rect 351 138 417 150
+rect 351 -138 367 138
+rect 401 -138 417 138
+rect 351 -150 417 -138
+rect 447 138 509 150
+rect 447 -138 463 138
+rect 497 -138 509 138
+rect 447 -150 509 -138
+<< pdiffc >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+<< nsubdiff >>
+rect -611 299 -515 333
+rect 515 299 611 333
+rect -611 237 -577 299
+rect 577 237 611 299
+rect -611 -299 -577 -237
+rect 577 -299 611 -237
+rect -611 -333 -515 -299
+rect 515 -333 611 -299
+<< nsubdiffcont >>
+rect -515 299 515 333
+rect -611 -237 -577 237
+rect 577 -237 611 237
+rect -515 -333 515 -299
+<< poly >>
+rect -447 150 -417 176
+rect -351 150 -321 176
+rect -255 150 -225 176
+rect -159 150 -129 176
+rect -63 150 -33 176
+rect 33 150 63 176
+rect 129 150 159 176
+rect 225 150 255 176
+rect 321 150 351 176
+rect 417 150 447 176
+rect -447 -181 -417 -150
+rect -351 -181 -321 -150
+rect -255 -181 -225 -150
+rect -159 -181 -129 -150
+rect -63 -181 -33 -150
+rect 33 -181 63 -150
+rect 129 -181 159 -150
+rect 225 -181 255 -150
+rect 321 -181 351 -150
+rect 417 -181 447 -150
+rect -465 -197 465 -181
+rect -465 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 465 -197
+rect -465 -247 465 -231
+<< polycont >>
+rect -449 -231 -415 -197
+rect -353 -231 -319 -197
+rect -257 -231 -223 -197
+rect -161 -231 -127 -197
+rect -65 -231 -31 -197
+rect 31 -231 65 -197
+rect 127 -231 161 -197
+rect 223 -231 257 -197
+rect 319 -231 353 -197
+rect 415 -231 449 -197
+<< locali >>
+rect -611 299 -515 333
+rect 515 299 611 333
+rect -611 237 -577 299
+rect 577 237 611 299
+rect -497 138 -463 154
+rect -497 -154 -463 -138
+rect -401 138 -367 154
+rect -401 -154 -367 -138
+rect -305 138 -271 154
+rect -305 -154 -271 -138
+rect -209 138 -175 154
+rect -209 -154 -175 -138
+rect -113 138 -79 154
+rect -113 -154 -79 -138
+rect -17 138 17 154
+rect -17 -154 17 -138
+rect 79 138 113 154
+rect 79 -154 113 -138
+rect 175 138 209 154
+rect 175 -154 209 -138
+rect 271 138 305 154
+rect 271 -154 305 -138
+rect 367 138 401 154
+rect 367 -154 401 -138
+rect 463 138 497 154
+rect 463 -154 497 -138
+rect -465 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 465 -197
+rect -611 -299 -577 -237
+rect 577 -299 611 -237
+rect -611 -333 -515 -299
+rect 515 -333 611 -299
+<< viali >>
+rect -497 -138 -463 138
+rect -401 -138 -367 138
+rect -305 -138 -271 138
+rect -209 -138 -175 138
+rect -113 -138 -79 138
+rect -17 -138 17 138
+rect 79 -138 113 138
+rect 175 -138 209 138
+rect 271 -138 305 138
+rect 367 -138 401 138
+rect 463 -138 497 138
+rect -449 -231 -415 -197
+rect -353 -231 -319 -197
+rect -257 -231 -223 -197
+rect -161 -231 -127 -197
+rect -65 -231 -31 -197
+rect 31 -231 65 -197
+rect 127 -231 161 -197
+rect 223 -231 257 -197
+rect 319 -231 353 -197
+rect 415 -231 449 -197
+<< metal1 >>
+rect -503 138 -457 150
+rect -503 -138 -497 138
+rect -463 -138 -457 138
+rect -503 -150 -457 -138
+rect -407 138 -361 150
+rect -407 -138 -401 138
+rect -367 -138 -361 138
+rect -407 -150 -361 -138
+rect -311 138 -265 150
+rect -311 -138 -305 138
+rect -271 -138 -265 138
+rect -311 -150 -265 -138
+rect -215 138 -169 150
+rect -215 -138 -209 138
+rect -175 -138 -169 138
+rect -215 -150 -169 -138
+rect -119 138 -73 150
+rect -119 -138 -113 138
+rect -79 -138 -73 138
+rect -119 -150 -73 -138
+rect -23 138 23 150
+rect -23 -138 -17 138
+rect 17 -138 23 138
+rect -23 -150 23 -138
+rect 73 138 119 150
+rect 73 -138 79 138
+rect 113 -138 119 138
+rect 73 -150 119 -138
+rect 169 138 215 150
+rect 169 -138 175 138
+rect 209 -138 215 138
+rect 169 -150 215 -138
+rect 265 138 311 150
+rect 265 -138 271 138
+rect 305 -138 311 138
+rect 265 -150 311 -138
+rect 361 138 407 150
+rect 361 -138 367 138
+rect 401 -138 407 138
+rect 361 -150 407 -138
+rect 457 138 503 150
+rect 457 -138 463 138
+rect 497 -138 503 138
+rect 457 -150 503 -138
+rect -464 -197 464 -188
+rect -464 -231 -449 -197
+rect -415 -231 -353 -197
+rect -319 -231 -257 -197
+rect -223 -231 -161 -197
+rect -127 -231 -65 -197
+rect -31 -231 31 -197
+rect 65 -231 127 -197
+rect 161 -231 223 -197
+rect 257 -231 319 -197
+rect 353 -231 415 -197
+rect 449 -231 464 -197
+rect -464 -240 464 -231
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -594 -316 594 316
+string parameters w 1.5 l 0.15 m 1 nf 10 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag b/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag
new file mode 100644
index 0000000..d32cad6
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_HRYSXS.mag

@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623162482
+<< nwell >>
+rect -216 -334 216 334
+<< pmos >>
+rect -20 -114 20 186
+<< pdiff >>
+rect -78 174 -20 186
+rect -78 -102 -66 174
+rect -32 -102 -20 174
+rect -78 -114 -20 -102
+rect 20 174 78 186
+rect 20 -102 32 174
+rect 66 -102 78 174
+rect 20 -114 78 -102
+<< pdiffc >>
+rect -66 -102 -32 174
+rect 32 -102 66 174
+<< nsubdiff >>
+rect -180 264 -84 298
+rect 84 264 180 298
+rect -180 201 -146 264
+rect 146 201 180 264
+rect -180 -264 -146 -201
+rect 146 -264 180 -201
+<< nsubdiffcont >>
+rect -84 264 84 298
+rect -180 -201 -146 201
+rect 146 -201 180 201
+<< poly >>
+rect -20 186 20 212
+rect -20 -145 20 -114
+rect -33 -211 33 -145
+<< locali >>
+rect -180 264 -84 298
+rect 84 264 180 298
+rect -180 201 -146 264
+rect 146 201 180 264
+rect -66 174 -32 190
+rect -66 -118 -32 -102
+rect 32 174 66 190
+rect 32 -118 66 -102
+rect -180 -264 -146 -201
+rect 146 -264 180 -201
+<< viali >>
+rect -66 -102 -32 174
+rect 32 -102 66 174
+<< metal1 >>
+rect -72 174 -26 186
+rect -72 -102 -66 174
+rect -32 -102 -26 174
+rect -72 -114 -26 -102
+rect 26 174 72 186
+rect 26 -102 32 174
+rect 66 -102 72 174
+rect 26 -114 72 -102
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -163 -281 163 281
+string parameters w 1.5 l 0.2 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag b/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag
new file mode 100644
index 0000000..f89ab31
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MJG8BZ.mag

@@ -0,0 +1,79 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -263 -314 263 314
+<< pmos >>
+rect -63 -95 -33 95
+rect 33 -95 63 95
+<< pdiff >>
+rect -125 83 -63 95
+rect -125 -83 -113 83
+rect -79 -83 -63 83
+rect -125 -95 -63 -83
+rect -33 83 33 95
+rect -33 -83 -17 83
+rect 17 -83 33 83
+rect -33 -95 33 -83
+rect 63 83 125 95
+rect 63 -83 79 83
+rect 113 -83 125 83
+rect 63 -95 125 -83
+<< pdiffc >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< nsubdiff >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< nsubdiffcont >>
+rect -131 244 131 278
+rect -227 -182 -193 182
+rect 193 -182 227 182
+<< poly >>
+rect -63 95 -33 121
+rect 33 95 63 121
+rect -63 -126 -33 -95
+rect 33 -126 63 -95
+rect -63 -192 63 -126
+<< locali >>
+rect -227 244 -131 278
+rect 131 244 227 278
+rect -227 182 -193 244
+rect 193 182 227 244
+rect -113 83 -79 99
+rect -113 -99 -79 -83
+rect -17 83 17 99
+rect -17 -99 17 -83
+rect 79 83 113 99
+rect 79 -99 113 -83
+rect -227 -244 -193 -182
+rect 193 -244 227 -182
+<< viali >>
+rect -113 -83 -79 83
+rect -17 -83 17 83
+rect 79 -83 113 83
+<< metal1 >>
+rect -119 83 -73 95
+rect -119 -83 -113 83
+rect -79 -83 -73 83
+rect -119 -95 -73 -83
+rect -23 83 23 95
+rect -23 -83 -17 83
+rect 17 -83 23 83
+rect -23 -95 23 -83
+rect 73 83 119 95
+rect 73 -83 79 83
+rect 113 -83 119 83
+rect 73 -95 119 -83
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -261 210 261
+string parameters w 0.95 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag b/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag
new file mode 100644
index 0000000..9bd363a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ND88ZC.mag

@@ -0,0 +1,419 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< nwell >>
+rect -1367 -369 1367 369
+<< pmos >>
+rect -1167 -150 -1137 150
+rect -1071 -150 -1041 150
+rect -975 -150 -945 150
+rect -879 -150 -849 150
+rect -783 -150 -753 150
+rect -687 -150 -657 150
+rect -591 -150 -561 150
+rect -495 -150 -465 150
+rect -399 -150 -369 150
+rect -303 -150 -273 150
+rect -207 -150 -177 150
+rect -111 -150 -81 150
+rect -15 -150 15 150
+rect 81 -150 111 150
+rect 177 -150 207 150
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+rect 369 -150 399 150
+rect 465 -150 495 150
+rect 561 -150 591 150
+rect 657 -150 687 150
+rect 753 -150 783 150
+rect 849 -150 879 150
+rect 945 -150 975 150
+rect 1041 -150 1071 150
+rect 1137 -150 1167 150
+<< pdiff >>
+rect -1229 138 -1167 150
+rect -1229 -138 -1217 138
+rect -1183 -138 -1167 138
+rect -1229 -150 -1167 -138
+rect -1137 138 -1071 150
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+rect -945 138 -879 150
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+rect 783 138 849 150
+rect 783 -138 799 138
+rect 833 -138 849 138
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+rect 1167 138 1229 150
+rect 1167 -138 1183 138
+rect 1217 -138 1229 138
+rect 1167 -150 1229 -138
+<< pdiffc >>
+rect -1217 -138 -1183 138
+rect -1121 -138 -1087 138
+rect -1025 -138 -991 138
+rect -929 -138 -895 138
+rect -833 -138 -799 138
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+rect -65 -138 -31 138
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+rect 319 -138 353 138
+rect 415 -138 449 138
+rect 511 -138 545 138
+rect 607 -138 641 138
+rect 703 -138 737 138
+rect 799 -138 833 138
+rect 895 -138 929 138
+rect 991 -138 1025 138
+rect 1087 -138 1121 138
+rect 1183 -138 1217 138
+<< nsubdiff >>
+rect -1297 299 -1235 333
+rect 1235 299 1331 333
+rect 1297 237 1331 299
+rect 1297 -299 1331 -237
+<< nsubdiffcont >>
+rect -1235 299 1235 333
+rect 1297 -237 1331 237
+<< poly >>
+rect -1167 150 -1137 176
+rect -1071 150 -1041 176
+rect -975 150 -945 176
+rect -879 150 -849 176
+rect -783 150 -753 176
+rect -687 150 -657 176
+rect -591 150 -561 176
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+rect -399 150 -369 176
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+rect -207 150 -177 176
+rect -111 150 -81 176
+rect -15 150 15 176
+rect 81 150 111 176
+rect 177 150 207 176
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+rect 465 150 495 176
+rect 561 150 591 176
+rect 657 150 687 176
+rect 753 150 783 176
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+rect 1137 150 1167 176
+rect -1167 -181 -1137 -150
+rect -1071 -181 -1041 -150
+rect -975 -181 -945 -150
+rect -879 -181 -849 -150
+rect -783 -181 -753 -150
+rect -687 -181 -657 -150
+rect -591 -181 -561 -150
+rect -495 -181 -465 -150
+rect -399 -181 -369 -150
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+rect -207 -181 -177 -150
+rect -111 -181 -81 -150
+rect -15 -181 15 -150
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+rect 177 -181 207 -150
+rect 273 -181 303 -150
+rect 369 -181 399 -150
+rect 465 -181 495 -150
+rect 561 -181 591 -150
+rect 657 -181 687 -150
+rect 753 -181 783 -150
+rect 849 -181 879 -150
+rect 945 -181 975 -150
+rect 1041 -181 1071 -150
+rect 1137 -181 1167 -150
+rect -1167 -247 1167 -181
+<< locali >>
+rect -1297 299 -1235 333
+rect 1235 299 1331 333
+rect 1297 237 1331 299
+rect -1217 138 -1183 154
+rect -1217 -154 -1183 -138
+rect -1121 138 -1087 154
+rect -1121 -154 -1087 -138
+rect -1025 138 -991 154
+rect -1025 -154 -991 -138
+rect -929 138 -895 154
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+rect -833 138 -799 154
+rect -833 -154 -799 -138
+rect -737 138 -703 154
+rect -737 -154 -703 -138
+rect -641 138 -607 154
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+rect -545 -154 -511 -138
+rect -449 138 -415 154
+rect -449 -154 -415 -138
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+rect -257 138 -223 154
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+rect -161 138 -127 154
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+rect -65 138 -31 154
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+rect 31 138 65 154
+rect 31 -154 65 -138
+rect 127 138 161 154
+rect 127 -154 161 -138
+rect 223 138 257 154
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+rect 319 138 353 154
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+rect 415 138 449 154
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+rect 511 138 545 154
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+rect 607 138 641 154
+rect 607 -154 641 -138
+rect 703 138 737 154
+rect 703 -154 737 -138
+rect 799 138 833 154
+rect 799 -154 833 -138
+rect 895 138 929 154
+rect 895 -154 929 -138
+rect 991 138 1025 154
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+rect 1087 138 1121 154
+rect 1087 -154 1121 -138
+rect 1183 138 1217 154
+rect 1183 -154 1217 -138
+rect 1297 -299 1331 -237
+<< viali >>
+rect -1217 -138 -1183 138
+rect -1121 -138 -1087 138
+rect -1025 -138 -991 138
+rect -929 -138 -895 138
+rect -833 -138 -799 138
+rect -737 -138 -703 138
+rect -641 -138 -607 138
+rect -545 -138 -511 138
+rect -449 -138 -415 138
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+rect -257 -138 -223 138
+rect -161 -138 -127 138
+rect -65 -138 -31 138
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+rect 511 -138 545 138
+rect 607 -138 641 138
+rect 703 -138 737 138
+rect 799 -138 833 138
+rect 895 -138 929 138
+rect 991 -138 1025 138
+rect 1087 -138 1121 138
+rect 1183 -138 1217 138
+<< metal1 >>
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+rect -1183 -138 -1177 138
+rect -1223 -150 -1177 -138
+rect -1127 138 -1081 150
+rect -1127 -138 -1121 138
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+rect -223 -138 -217 138
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+rect -71 -138 -65 138
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+rect 25 -138 31 138
+rect 65 -138 71 138
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+rect 121 138 167 150
+rect 121 -138 127 138
+rect 161 -138 167 138
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+rect 217 138 263 150
+rect 217 -138 223 138
+rect 257 -138 263 138
+rect 217 -150 263 -138
+rect 313 138 359 150
+rect 313 -138 319 138
+rect 353 -138 359 138
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+rect 409 138 455 150
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+rect 449 -138 455 138
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+rect 505 138 551 150
+rect 505 -138 511 138
+rect 545 -138 551 138
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+rect 601 138 647 150
+rect 601 -138 607 138
+rect 641 -138 647 138
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+rect 697 138 743 150
+rect 697 -138 703 138
+rect 737 -138 743 138
+rect 697 -150 743 -138
+rect 793 138 839 150
+rect 793 -138 799 138
+rect 833 -138 839 138
+rect 793 -150 839 -138
+rect 889 138 935 150
+rect 889 -138 895 138
+rect 929 -138 935 138
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+rect 985 138 1031 150
+rect 985 -138 991 138
+rect 1025 -138 1031 138
+rect 985 -150 1031 -138
+rect 1081 138 1127 150
+rect 1081 -138 1087 138
+rect 1121 -138 1127 138
+rect 1081 -150 1127 -138
+rect 1177 138 1223 150
+rect 1177 -138 1183 138
+rect 1217 -138 1223 138
+rect 1177 -150 1223 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1314 -316 1314 316
+string parameters w 1.5 l 0.15 m 1 nf 25 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag b/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag
new file mode 100644
index 0000000..bf825c4
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_NKZXKB.mag

@@ -0,0 +1,340 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623774805
+<< nwell >>
+rect -1127 -369 1127 369
+<< pmos >>
+rect -927 -150 -897 150
+rect -831 -150 -801 150
+rect -735 -150 -705 150
+rect -639 -150 -609 150
+rect -543 -150 -513 150
+rect -447 -150 -417 150
+rect -351 -150 -321 150
+rect -255 -150 -225 150
+rect -159 -150 -129 150
+rect -63 -150 -33 150
+rect 33 -150 63 150
+rect 129 -150 159 150
+rect 225 -150 255 150
+rect 321 -150 351 150
+rect 417 -150 447 150
+rect 513 -150 543 150
+rect 609 -150 639 150
+rect 705 -150 735 150
+rect 801 -150 831 150
+rect 897 -150 927 150
+<< pdiff >>
+rect -989 138 -927 150
+rect -989 -138 -977 138
+rect -943 -138 -927 138
+rect -989 -150 -927 -138
+rect -897 138 -831 150
+rect -897 -138 -881 138
+rect -847 -138 -831 138
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+rect -801 138 -735 150
+rect -801 -138 -785 138
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+rect -705 138 -639 150
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+rect -655 -138 -639 138
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+rect 543 138 609 150
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+rect 639 138 705 150
+rect 639 -138 655 138
+rect 689 -138 705 138
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+rect 735 138 801 150
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+rect 831 -150 897 -138
+rect 927 138 989 150
+rect 927 -138 943 138
+rect 977 -138 989 138
+rect 927 -150 989 -138
+<< pdiffc >>
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+rect -881 -138 -847 138
+rect -785 -138 -751 138
+rect -689 -138 -655 138
+rect -593 -138 -559 138
+rect -497 -138 -463 138
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+rect 559 -138 593 138
+rect 655 -138 689 138
+rect 751 -138 785 138
+rect 847 -138 881 138
+rect 943 -138 977 138
+<< nsubdiff >>
+rect -1057 299 -995 333
+rect 995 299 1057 333
+<< nsubdiffcont >>
+rect -995 299 995 333
+<< poly >>
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+rect -831 150 -801 176
+rect -735 150 -705 176
+rect -639 150 -609 176
+rect -543 150 -513 176
+rect -447 150 -417 176
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+rect -927 -181 -897 -150
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+rect -159 -181 -129 -150
+rect -63 -181 -33 -150
+rect -927 -247 -33 -181
+rect 33 -181 63 -150
+rect 129 -181 159 -150
+rect 225 -181 255 -150
+rect 321 -181 351 -150
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+rect 513 -181 543 -150
+rect 609 -181 639 -150
+rect 705 -181 735 -150
+rect 801 -181 831 -150
+rect 897 -181 927 -150
+rect 33 -247 927 -181
+<< locali >>
+rect -1057 299 -995 333
+rect 995 299 1057 333
+rect -977 138 -943 154
+rect -977 -154 -943 -138
+rect -881 138 -847 154
+rect -881 -154 -847 -138
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+rect -113 138 -79 154
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+rect -17 138 17 154
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+rect 79 138 113 154
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+rect 175 138 209 154
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+rect 559 138 593 154
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+rect 655 138 689 154
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+rect 751 138 785 154
+rect 751 -154 785 -138
+rect 847 138 881 154
+rect 847 -154 881 -138
+rect 943 138 977 154
+rect 943 -154 977 -138
+<< viali >>
+rect -977 -138 -943 138
+rect -881 -138 -847 138
+rect -785 -138 -751 138
+rect -689 -138 -655 138
+rect -593 -138 -559 138
+rect -497 -138 -463 138
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+rect -305 -138 -271 138
+rect -209 -138 -175 138
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+rect 367 -138 401 138
+rect 463 -138 497 138
+rect 559 -138 593 138
+rect 655 -138 689 138
+rect 751 -138 785 138
+rect 847 -138 881 138
+rect 943 -138 977 138
+<< metal1 >>
+rect -983 138 -937 150
+rect -983 -138 -977 138
+rect -943 -138 -937 138
+rect -983 -150 -937 -138
+rect -887 138 -841 150
+rect -887 -138 -881 138
+rect -847 -138 -841 138
+rect -887 -150 -841 -138
+rect -791 138 -745 150
+rect -791 -138 -785 138
+rect -751 -138 -745 138
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+rect -503 138 -457 150
+rect -503 -138 -497 138
+rect -463 -138 -457 138
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+rect -407 138 -361 150
+rect -407 -138 -401 138
+rect -367 -138 -361 138
+rect -407 -150 -361 -138
+rect -311 138 -265 150
+rect -311 -138 -305 138
+rect -271 -138 -265 138
+rect -311 -150 -265 -138
+rect -215 138 -169 150
+rect -215 -138 -209 138
+rect -175 -138 -169 138
+rect -215 -150 -169 -138
+rect -119 138 -73 150
+rect -119 -138 -113 138
+rect -79 -138 -73 138
+rect -119 -150 -73 -138
+rect -23 138 23 150
+rect -23 -138 -17 138
+rect 17 -138 23 138
+rect -23 -150 23 -138
+rect 73 138 119 150
+rect 73 -138 79 138
+rect 113 -138 119 138
+rect 73 -150 119 -138
+rect 169 138 215 150
+rect 169 -138 175 138
+rect 209 -138 215 138
+rect 169 -150 215 -138
+rect 265 138 311 150
+rect 265 -138 271 138
+rect 305 -138 311 138
+rect 265 -150 311 -138
+rect 361 138 407 150
+rect 361 -138 367 138
+rect 401 -138 407 138
+rect 361 -150 407 -138
+rect 457 138 503 150
+rect 457 -138 463 138
+rect 497 -138 503 138
+rect 457 -150 503 -138
+rect 553 138 599 150
+rect 553 -138 559 138
+rect 593 -138 599 138
+rect 553 -150 599 -138
+rect 649 138 695 150
+rect 649 -138 655 138
+rect 689 -138 695 138
+rect 649 -150 695 -138
+rect 745 138 791 150
+rect 745 -138 751 138
+rect 785 -138 791 138
+rect 745 -150 791 -138
+rect 841 138 887 150
+rect 841 -138 847 138
+rect 881 -138 887 138
+rect 841 -150 887 -138
+rect 937 138 983 150
+rect 937 -138 943 138
+rect 977 -138 983 138
+rect 937 -150 983 -138
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -1074 -316 1074 316
+string parameters w 1.5 l 0.15 m 1 nf 20 diffcov 100 polycov 100 guard 1 glc 1 grc 0 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag b/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag
new file mode 100644
index 0000000..f8474c2
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_XJXT7S.mag

@@ -0,0 +1,138 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623353110
+<< nwell >>
+rect -455 -344 455 344
+<< pmos >>
+rect -255 -125 -225 125
+rect -159 -125 -129 125
+rect -63 -125 -33 125
+rect 33 -125 63 125
+rect 129 -125 159 125
+rect 225 -125 255 125
+<< pdiff >>
+rect -317 113 -255 125
+rect -317 -113 -305 113
+rect -271 -113 -255 113
+rect -317 -125 -255 -113
+rect -225 113 -159 125
+rect -225 -113 -209 113
+rect -175 -113 -159 113
+rect -225 -125 -159 -113
+rect -129 113 -63 125
+rect -129 -113 -113 113
+rect -79 -113 -63 113
+rect -129 -125 -63 -113
+rect -33 113 33 125
+rect -33 -113 -17 113
+rect 17 -113 33 113
+rect -33 -125 33 -113
+rect 63 113 129 125
+rect 63 -113 79 113
+rect 113 -113 129 113
+rect 63 -125 129 -113
+rect 159 113 225 125
+rect 159 -113 175 113
+rect 209 -113 225 113
+rect 159 -125 225 -113
+rect 255 113 317 125
+rect 255 -113 271 113
+rect 305 -113 317 113
+rect 255 -125 317 -113
+<< pdiffc >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< nsubdiff >>
+rect -419 274 -323 308
+rect 323 274 419 308
+rect -419 212 -385 274
+rect 385 212 419 274
+rect -419 -274 -385 -212
+rect 385 -274 419 -212
+<< nsubdiffcont >>
+rect -323 274 323 308
+rect -419 -212 -385 212
+rect 385 -212 419 212
+<< poly >>
+rect -255 125 -225 151
+rect -159 125 -129 151
+rect -63 125 -33 151
+rect 33 125 63 151
+rect 129 125 159 151
+rect 225 125 255 151
+rect -255 -154 -225 -125
+rect -159 -154 -129 -125
+rect -63 -154 -33 -125
+rect 33 -154 63 -125
+rect 129 -154 159 -125
+rect 225 -154 255 -125
+<< locali >>
+rect -419 274 -323 308
+rect 323 274 419 308
+rect -419 212 -385 274
+rect 385 212 419 274
+rect -305 113 -271 129
+rect -305 -129 -271 -113
+rect -209 113 -175 129
+rect -209 -129 -175 -113
+rect -113 113 -79 129
+rect -113 -129 -79 -113
+rect -17 113 17 129
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+rect 79 113 113 129
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+rect 175 113 209 129
+rect 175 -129 209 -113
+rect 271 113 305 129
+rect 271 -129 305 -113
+rect -419 -274 -385 -212
+rect 385 -274 419 -212
+<< viali >>
+rect -305 -113 -271 113
+rect -209 -113 -175 113
+rect -113 -113 -79 113
+rect -17 -113 17 113
+rect 79 -113 113 113
+rect 175 -113 209 113
+rect 271 -113 305 113
+<< metal1 >>
+rect -311 113 -265 125
+rect -311 -113 -305 113
+rect -271 -113 -265 113
+rect -311 -125 -265 -113
+rect -215 113 -169 125
+rect -215 -113 -209 113
+rect -175 -113 -169 113
+rect -215 -125 -169 -113
+rect -119 113 -73 125
+rect -119 -113 -113 113
+rect -79 -113 -73 113
+rect -119 -125 -73 -113
+rect -23 113 23 125
+rect -23 -113 -17 113
+rect 17 -113 23 113
+rect -23 -125 23 -113
+rect 73 113 119 125
+rect 73 -113 79 113
+rect 113 -113 119 113
+rect 73 -125 119 -113
+rect 169 113 215 125
+rect 169 -113 175 113
+rect 209 -113 215 113
+rect 169 -125 215 -113
+rect 265 113 311 125
+rect 265 -113 271 113
+rect 305 -113 311 113
+rect 265 -125 311 -113
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -402 -291 402 291
+string parameters w 1.25 l 0.15 m 1 nf 6 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag b/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag
new file mode 100644
index 0000000..6535f8a
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ZP3U9B.mag

@@ -0,0 +1,108 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623431064
+<< nwell >>
+rect -359 -303 359 303
+<< pmos >>
+rect -159 -84 -129 84
+rect -63 -84 -33 84
+rect 33 -84 63 84
+rect 129 -84 159 84
+<< pdiff >>
+rect -221 72 -159 84
+rect -221 -72 -209 72
+rect -175 -72 -159 72
+rect -221 -84 -159 -72
+rect -129 72 -63 84
+rect -129 -72 -113 72
+rect -79 -72 -63 72
+rect -129 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 129 84
+rect 63 -72 79 72
+rect 113 -72 129 72
+rect 63 -84 129 -72
+rect 159 72 221 84
+rect 159 -72 175 72
+rect 209 -72 221 72
+rect 159 -84 221 -72
+<< pdiffc >>
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< nsubdiff >>
+rect -323 233 -227 267
+rect 227 233 323 267
+rect -323 171 -289 233
+rect 289 171 323 233
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< nsubdiffcont >>
+rect -227 233 227 267
+rect -323 -171 -289 171
+rect 289 -171 323 171
+<< poly >>
+rect -159 84 -129 110
+rect -63 84 -33 110
+rect 33 84 63 110
+rect 129 84 159 110
+rect -159 -110 -129 -84
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+rect 129 -110 159 -84
+<< locali >>
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+rect 227 233 323 267
+rect -323 171 -289 233
+rect 289 171 323 233
+rect -209 72 -175 88
+rect -209 -88 -175 -72
+rect -113 72 -79 88
+rect -113 -88 -79 -72
+rect -17 72 17 88
+rect -17 -88 17 -72
+rect 79 72 113 88
+rect 79 -88 113 -72
+rect 175 72 209 88
+rect 175 -88 209 -72
+rect -323 -233 -289 -171
+rect 289 -233 323 -171
+<< viali >>
+rect -209 -72 -175 72
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+rect 175 -72 209 72
+<< metal1 >>
+rect -215 72 -169 84
+rect -215 -72 -209 72
+rect -175 -72 -169 72
+rect -215 -84 -169 -72
+rect -119 72 -73 84
+rect -119 -72 -113 72
+rect -79 -72 -73 72
+rect -119 -84 -73 -72
+rect -23 72 23 84
+rect -23 -72 -17 72
+rect 17 -72 23 72
+rect -23 -84 23 -72
+rect 73 72 119 84
+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+rect 169 72 215 84
+rect 169 -72 175 72
+rect 209 -72 215 72
+rect 169 -84 215 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -306 -250 306 250
+string parameters w 0.84 l 0.15 m 1 nf 4 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag b/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag
new file mode 100644
index 0000000..0905923
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_ZPB9BB.mag

@@ -0,0 +1,78 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623427962
+<< nwell >>
+rect -263 -303 263 303
+<< pmos >>
+rect -63 -84 -33 84
+rect 33 -84 63 84
+<< pdiff >>
+rect -125 72 -63 84
+rect -125 -72 -113 72
+rect -79 -72 -63 72
+rect -125 -84 -63 -72
+rect -33 72 33 84
+rect -33 -72 -17 72
+rect 17 -72 33 72
+rect -33 -84 33 -72
+rect 63 72 125 84
+rect 63 -72 79 72
+rect 113 -72 125 72
+rect 63 -84 125 -72
+<< pdiffc >>
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+<< nsubdiff >>
+rect -227 233 -131 267
+rect 131 233 227 267
+rect -227 171 -193 233
+rect 193 171 227 233
+rect -227 -233 -193 -171
+rect 193 -233 227 -171
+<< nsubdiffcont >>
+rect -131 233 131 267
+rect -227 -171 -193 171
+rect 193 -171 227 171
+<< poly >>
+rect -63 84 -33 110
+rect 33 84 63 110
+rect -63 -110 -33 -84
+rect 33 -110 63 -84
+<< locali >>
+rect -227 233 -131 267
+rect 131 233 227 267
+rect -227 171 -193 233
+rect 193 171 227 233
+rect -113 72 -79 88
+rect -113 -88 -79 -72
+rect -17 72 17 88
+rect -17 -88 17 -72
+rect 79 72 113 88
+rect 79 -88 113 -72
+rect -227 -233 -193 -171
+rect 193 -233 227 -171
+<< viali >>
+rect -113 -72 -79 72
+rect -17 -72 17 72
+rect 79 -72 113 72
+<< metal1 >>
+rect -119 72 -73 84
+rect -119 -72 -113 72
+rect -79 -72 -73 72
+rect -119 -84 -73 -72
+rect -23 72 23 84
+rect -23 -72 -17 72
+rect 17 -72 23 72
+rect -23 -84 23 -72
+rect 73 72 119 84
+rect 73 -72 79 72
+rect 113 -72 119 72
+rect 73 -84 119 -72
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -210 -250 210 250
+string parameters w 0.84 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag b/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag
new file mode 100644
index 0000000..c74b7c5
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_lvt_8P223X.mag

@@ -0,0 +1,1253 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623863898
+<< nwell >>
+rect -2017 76 2017 1196
+rect -2018 -202 2017 76
+rect -2017 -1367 2017 -202
+<< pmoslvt >>
+rect -1821 47 -1731 947
+rect -1673 47 -1583 947
+rect -1525 47 -1435 947
+rect -1377 47 -1287 947
+rect -1229 47 -1139 947
+rect -1081 47 -991 947
+rect -933 47 -843 947
+rect -785 47 -695 947
+rect -637 47 -547 947
+rect -489 47 -399 947
+rect -341 47 -251 947
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+rect -45 47 45 947
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+rect 1139 47 1229 947
+rect 1287 47 1377 947
+rect 1435 47 1525 947
+rect 1583 47 1673 947
+rect 1731 47 1821 947
+rect -1821 -1219 -1731 -319
+rect -1673 -1219 -1583 -319
+rect -1525 -1219 -1435 -319
+rect -1377 -1219 -1287 -319
+rect -1229 -1219 -1139 -319
+rect -1081 -1219 -991 -319
+rect -933 -1219 -843 -319
+rect -785 -1219 -695 -319
+rect -637 -1219 -547 -319
+rect -489 -1219 -399 -319
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+rect -193 -1219 -103 -319
+rect -45 -1219 45 -319
+rect 103 -1219 193 -319
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+rect 399 -1219 489 -319
+rect 547 -1219 637 -319
+rect 695 -1219 785 -319
+rect 843 -1219 933 -319
+rect 991 -1219 1081 -319
+rect 1139 -1219 1229 -319
+rect 1287 -1219 1377 -319
+rect 1435 -1219 1525 -319
+rect 1583 -1219 1673 -319
+rect 1731 -1219 1821 -319
+<< pdiff >>
+rect -1879 935 -1821 947
+rect -1879 59 -1867 935
+rect -1833 59 -1821 935
+rect -1879 47 -1821 59
+rect -1731 935 -1673 947
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+rect 1477 -271 1650 -219
+rect 1782 -271 2017 -219
+rect -2017 -285 2017 -271
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8_lvt
+string FIXED_BBOX -1964 -1042 1964 1042
+string parameters w 4.5 l 0.45 m 2 nf 25 diffcov 100 polycov 100 guard 1 glc 0 grc 0 gtc 1 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.35 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_pr__res_high_po_5p73_GW5RGE.mag b/mag/sky130_fd_pr__res_high_po_5p73_GW5RGE.mag
new file mode 100644
index 0000000..1c515e4
--- /dev/null
+++ b/mag/sky130_fd_pr__res_high_po_5p73_GW5RGE.mag

@@ -0,0 +1,82 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623892191
+<< pwell >>
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+<< psubdiff >>
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+rect -2097 -2820 -2063 -2758
+rect 2063 -2820 2097 -2758
+rect -2097 -2854 -2001 -2820
+rect 2001 -2854 2097 -2820
+<< psubdiffcont >>
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+rect -2097 -2758 -2063 2758
+rect 2063 -2758 2097 2758
+rect -2001 -2854 2001 -2820
+<< xpolycontact >>
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+rect -573 2292 573 2724
+rect -573 -2724 573 -2292
+rect 821 2292 1967 2724
+rect 821 -2724 1967 -2292
+<< ppolyres >>
+rect -1967 -2292 -821 2292
+rect -573 -2292 573 2292
+rect 821 -2292 1967 2292
+<< locali >>
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+rect -2097 -2820 -2063 -2758
+rect 2063 -2820 2097 -2758
+rect -2097 -2854 -2001 -2820
+rect 2001 -2854 2097 -2820
+<< viali >>
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+rect -1951 -2706 -837 -2309
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+<< metal1 >>
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+rect -569 2706 569 2712
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+rect -1963 -2309 -825 -2303
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+rect -569 -2309 569 -2303
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+rect 1951 -2706 1963 -2309
+rect 825 -2712 1963 -2706
+<< res5p73 >>
+rect -1969 -2294 -819 2294
+rect -575 -2294 575 2294
+rect 819 -2294 1969 2294
+<< properties >>
+string gencell sky130_fd_pr__res_high_po_5p73
+string FIXED_BBOX -2080 -2837 2080 2837
+string parameters w 5.730 l 22.92 m 1 nx 3 wmin 5.730 lmin 0.50 rho 319.8 val 1.285k dummy 0 dw 0.0 term 19.188 sterm 0.0 caplen 0 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_high_po_0p35  sky130_fd_pr__res_high_po_0p69 sky130_fd_pr__res_high_po_1p41  sky130_fd_pr__res_high_po_2p85 sky130_fd_pr__res_high_po_5p73} full_metal 1 wmax 5.730 n_guard 0 hv_guard 0 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+string library sky130
+<< end >>

diff --git a/mag/sky130_fd_sc_hs__and2_1.mag b/mag/sky130_fd_sc_hs__and2_1.mag
new file mode 100644
index 0000000..1fed914
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__and2_1.mag

@@ -0,0 +1,254 @@
+magic
+tech sky130A
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+timestamp 1622592543
+<< checkpaint >>
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+<< nwell >>
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+<< scpmos >>
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+<< ndiffc >>
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+<< pdiffc >>
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+<< locali >>
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+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 and2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 94 65 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 127 94 161 128 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 223 242 257 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 1585064
+string GDS_START 1579992
+<< end >>

diff --git a/mag/sky130_fd_sc_hs__or2_1.mag b/mag/sky130_fd_sc_hs__or2_1.mag
new file mode 100644
index 0000000..ff8dfc0
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__or2_1.mag

@@ -0,0 +1,254 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622592543
+<< checkpaint >>
+rect -1298 -1309 1778 1975
+<< nwell >>
+rect -38 332 518 704
+<< pwell >>
+rect 1 49 479 248
+rect 0 0 480 49
+<< scpmos >>
+rect 122 368 152 536
+rect 206 368 236 536
+rect 364 368 394 592
+<< nmoslvt >>
+rect 125 112 155 222
+rect 250 112 280 222
+rect 366 74 396 222
+<< ndiff >>
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+rect 27 149 80 183
+rect 114 149 125 183
+rect 27 112 125 149
+rect 155 181 250 222
+rect 155 147 198 181
+rect 232 147 250 181
+rect 155 112 250 147
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+rect 396 210 453 222
+rect 396 176 407 210
+rect 441 176 453 210
+rect 396 120 453 176
+rect 396 86 407 120
+rect 441 86 453 120
+rect 396 74 453 86
+<< pdiff >>
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+rect 270 546 317 580
+rect 351 546 364 580
+rect 270 536 364 546
+rect 63 524 122 536
+rect 63 490 75 524
+rect 109 490 122 524
+rect 63 414 122 490
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+rect 394 463 407 497
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+rect 394 368 453 380
+<< ndiffc >>
+rect 80 149 114 183
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+rect 407 176 441 210
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+<< pdiffc >>
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+rect 75 490 109 524
+rect 75 380 109 414
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+rect 366 48 396 74
+<< polycont >>
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+rect 225 286 259 320
+rect 344 276 378 310
+<< locali >>
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+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+<< viali >>
+rect 31 649 65 683
+rect 127 649 161 683
+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 31 -17 65 17
+rect 127 -17 161 17
+rect 223 -17 257 17
+rect 319 -17 353 17
+rect 415 -17 449 17
+<< metal1 >>
+rect 0 683 480 715
+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 480 683
+rect 0 617 480 649
+rect 0 17 480 49
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 480 17
+rect 0 -49 480 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 or2_1
+flabel pwell s 0 0 480 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 480 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 480 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 480 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 223 316 257 350 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 415 390 449 424 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 464 449 498 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 415 538 449 572 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 480 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 1245662
+string GDS_START 1240892
+<< end >>

diff --git a/mag/sky130_fd_sc_hs__xor2_1.mag b/mag/sky130_fd_sc_hs__xor2_1.mag
new file mode 100644
index 0000000..053ed57
--- /dev/null
+++ b/mag/sky130_fd_sc_hs__xor2_1.mag

@@ -0,0 +1,367 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1622592543
+<< checkpaint >>
+rect -1298 -1309 2066 1975
+<< nwell >>
+rect -38 332 806 704
+<< pwell >>
+rect 17 49 754 261
+rect 0 0 768 49
+<< scpmos >>
+rect 128 392 158 592
+rect 212 392 242 592
+rect 422 368 452 592
+rect 536 368 566 592
+rect 636 368 666 592
+<< nmoslvt >>
+rect 164 125 194 235
+rect 323 125 353 235
+rect 425 87 455 235
+rect 503 87 533 235
+rect 617 87 647 235
+<< ndiff >>
+rect 43 182 164 235
+rect 43 148 51 182
+rect 85 148 119 182
+rect 153 148 164 182
+rect 43 125 164 148
+rect 194 192 323 235
+rect 194 158 205 192
+rect 239 158 278 192
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+rect 353 223 425 235
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+rect 353 125 380 133
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+rect 455 87 503 235
+rect 533 214 617 235
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+rect 578 180 617 214
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+rect 533 99 544 133
+rect 578 99 617 133
+rect 533 87 617 99
+rect 647 133 728 235
+rect 647 99 658 133
+rect 692 99 728 133
+rect 647 87 728 99
+<< pdiff >>
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+rect 69 546 81 580
+rect 115 546 128 580
+rect 69 509 128 546
+rect 69 475 81 509
+rect 115 475 128 509
+rect 69 438 128 475
+rect 69 404 81 438
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+rect 242 580 301 592
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+rect 666 463 689 497
+rect 723 463 735 497
+rect 666 414 735 463
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+<< ndiffc >>
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+rect 278 158 312 192
+rect 380 189 414 223
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+<< pdiffc >>
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+rect 689 380 723 414
+<< poly >>
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+rect 128 377 158 392
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+rect 164 51 194 125
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+<< polycont >>
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+rect 519 286 553 320
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+<< locali >>
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+rect 353 -17 415 17
+rect 449 -17 511 17
+rect 545 -17 607 17
+rect 641 -17 703 17
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+<< viali >>
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+rect 223 649 257 683
+rect 319 649 353 683
+rect 415 649 449 683
+rect 511 649 545 683
+rect 607 649 641 683
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+rect 223 -17 257 17
+rect 319 -17 353 17
+rect 415 -17 449 17
+rect 511 -17 545 17
+rect 607 -17 641 17
+rect 703 -17 737 17
+<< metal1 >>
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+rect 0 649 31 683
+rect 65 649 127 683
+rect 161 649 223 683
+rect 257 649 319 683
+rect 353 649 415 683
+rect 449 649 511 683
+rect 545 649 607 683
+rect 641 649 703 683
+rect 737 649 768 683
+rect 0 617 768 649
+rect 0 17 768 49
+rect 0 -17 31 17
+rect 65 -17 127 17
+rect 161 -17 223 17
+rect 257 -17 319 17
+rect 353 -17 415 17
+rect 449 -17 511 17
+rect 545 -17 607 17
+rect 641 -17 703 17
+rect 737 -17 768 17
+rect 0 -49 768 -17
+<< labels >>
+rlabel comment s 0 0 0 0 4 xor2_1
+flabel pwell s 0 0 768 49 0 FreeSans 200 0 0 0 VNB
+port 4 nsew ground bidirectional
+flabel nwell s 0 617 768 666 0 FreeSans 200 0 0 0 VPB
+port 5 nsew power bidirectional
+flabel metal1 s 0 617 768 666 0 FreeSans 340 0 0 0 VPWR
+port 6 nsew power bidirectional
+flabel metal1 s 0 0 768 49 0 FreeSans 340 0 0 0 VGND
+port 3 nsew ground bidirectional
+flabel locali s 31 242 65 276 0 FreeSans 340 0 0 0 A
+port 1 nsew signal input
+flabel locali s 511 316 545 350 0 FreeSans 340 0 0 0 B
+port 2 nsew signal input
+flabel locali s 511 94 545 128 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+flabel locali s 511 168 545 202 0 FreeSans 340 0 0 0 X
+port 7 nsew signal output
+<< properties >>
+string LEFsite unit
+string LEFclass CORE
+string FIXED_BBOX 0 0 768 666
+string GDS_FILE $PDKPATH/libs.ref/sky130_fd_sc_hs/gds/sky130_fd_sc_hs.gds
+string LEFsymmetry X Y
+string GDS_END 2405310
+string GDS_START 2399018
+<< end >>

diff --git a/mag/top_pll_v1.gds b/mag/top_pll_v1.gds
new file mode 100644
index 0000000..e338ebb
--- /dev/null
+++ b/mag/top_pll_v1.gds
Binary files differ

diff --git a/mag/top_pll_v1.mag b/mag/top_pll_v1.mag
new file mode 100644
index 0000000..5481914
--- /dev/null
+++ b/mag/top_pll_v1.mag

@@ -0,0 +1,537 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623956621
+<< nwell >>
+rect 0 2838 6183 2846
+rect 0 2608 3909 2838
+rect 3790 2062 3909 2608
+rect 6063 2012 6183 2838
+rect 13905 2752 20472 2846
+rect 13905 1955 14025 2752
+rect 18329 1955 20472 2752
+rect 18510 1923 20472 1955
+rect -3 -230 3909 546
+rect -3 -350 6063 -230
+rect 955 -370 2001 -350
+<< pwell >>
+rect 3790 706 3909 2062
+rect 2872 546 3909 706
+rect 13905 784 14901 854
+rect 18329 784 18510 1215
+rect 13905 653 18510 784
+rect 19367 653 20225 754
+rect 13905 -238 20472 653
+<< psubdiff >>
+rect 13461 -1919 13485 -1831
+rect 14493 -1919 14517 -1831
+<< nsubdiff >>
+rect 43 -212 67 -124
+rect 416 -212 440 -124
+rect 1252 -220 1276 -132
+rect 1625 -220 1649 -132
+rect 2420 -214 2446 -126
+rect 2795 -214 2819 -126
+<< psubdiffcont >>
+rect 13485 -1919 14493 -1831
+<< nsubdiffcont >>
+rect 67 -212 416 -124
+rect 1276 -220 1625 -132
+rect 2446 -214 2795 -126
+<< poly >>
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+rect 10374 2078 10395 2156
+rect 10657 2078 10680 2156
+rect 10374 2055 10680 2078
+rect 10354 385 10697 405
+rect 10354 280 10372 385
+rect 10671 280 10697 385
+rect 10354 269 10697 280
+<< polycont >>
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+rect 10395 2078 10657 2156
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+<< viali >>
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+rect 9699 2020 9723 2114
+rect 10374 2078 10395 2156
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+rect 13416 -1919 13485 -1831
+rect 13485 -1919 14493 -1831
+rect 14493 -1919 14548 -1831
+rect 13416 -1931 14548 -1919
+<< metal1 >>
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+rect 0 2808 6183 2816
+rect 0 2674 6294 2808
+rect 13869 2674 20472 2816
+rect 0 2578 3504 2674
+rect 3150 2150 3504 2578
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+rect 4963 2029 5581 2034
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+rect 10362 2179 10692 2185
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+rect 10342 263 10709 269
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+rect 2372 -106 2872 55
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+rect -1 -232 22 -112
+rect 2852 -232 2872 -112
+rect -1 -238 2872 -232
+rect -1 -407 499 -238
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+rect 13962 -1092 13972 -1056
+rect 13962 -1170 13973 -1092
+rect 14281 -1166 14682 -1086
+rect 14819 -1154 15043 -1098
+rect 13962 -1223 13972 -1170
+rect 13580 -1706 13842 -1507
+rect 13580 -1725 14356 -1706
+rect 19367 -1720 19612 -208
+rect 13288 -1896 13289 -1731
+rect 13768 -1804 14356 -1725
+rect 13404 -1810 14560 -1804
+rect 13404 -1931 13416 -1810
+rect 14548 -1931 14560 -1810
+rect 13404 -1937 14560 -1931
+rect 13768 -2069 14356 -1937
+rect 19278 -1964 19612 -1720
+rect 13768 -2215 13842 -2069
+rect 10227 -2717 10598 -2658
+rect 13760 -2695 13770 -2498
+rect 13951 -2599 13961 -2498
+rect 13951 -2677 13973 -2599
+rect 13951 -2695 13961 -2677
+rect 14281 -2683 14682 -2603
+rect 14816 -2673 15040 -2617
+<< via1 >>
+rect 3919 2034 4143 2090
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9420 2020 9699 2114
+rect 10395 2078 10657 2156
+rect 18520 1190 18728 1242
+rect 19587 1172 19999 1256
+rect -609 518 -513 715
+rect 3919 518 4143 574
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+rect 5919 518 6053 574
+rect 9434 325 9696 449
+rect 10372 280 10671 385
+rect -617 -1095 -505 -882
+rect 13797 -1223 13962 -1056
+rect 13770 -2695 13951 -2498
+<< metal2 >>
+rect 13173 2204 13734 2214
+rect 10395 2156 10657 2166
+rect 9420 2114 9699 2124
+rect 3919 2090 4143 2100
+rect 3919 2024 4143 2034
+rect 5180 2090 5404 2100
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+rect 5955 2091 6089 2101
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+rect 3988 1928 4074 2024
+rect 9420 2010 9699 2020
+rect 3738 1876 4074 1928
+rect 5955 1831 9647 1854
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+rect 6089 1775 9499 1812
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+rect 2159 858 2211 1750
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+rect 13173 1690 13734 1700
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+rect 5232 1555 5245 1611
+rect 5469 1609 10645 1611
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+rect 10634 1553 10645 1609
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+rect 19587 1256 19999 1266
+rect 18520 1242 18728 1252
+rect 18091 1190 18520 1241
+rect 18091 1189 18728 1190
+rect 18520 1180 18728 1189
+rect 19587 1162 19999 1172
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+rect 3988 584 4074 680
+rect -609 508 -513 518
+rect 3919 574 4143 584
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+rect 5180 574 5404 584
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+rect 5919 574 6053 584
+rect 5919 508 6053 518
+rect 9434 449 9696 459
+rect 9434 315 9696 325
+rect 10372 385 10671 395
+rect 10372 270 10671 280
+rect 13764 206 14377 369
+rect 14214 25 14377 206
+rect -617 -882 -505 -872
+rect -279 -954 161 -878
+rect -617 -1105 -505 -1095
+rect 13797 -1056 13962 -1046
+rect -405 -1940 -319 -1188
+rect 13797 -1233 13962 -1223
+rect 9937 -2546 10013 -1824
+rect 13770 -2498 13951 -2488
+rect 13770 -2705 13951 -2695
+<< via2 >>
+rect 5180 2034 5404 2090
+rect 5955 2035 6089 2091
+rect 9491 2043 9625 2099
+rect 10412 2078 10636 2134
+rect 5955 1756 6089 1812
+rect 9499 1775 9633 1831
+rect 13173 1700 13734 2204
+rect 5245 1555 5469 1611
+rect 10410 1553 10634 1609
+rect 19587 1172 19999 1256
+rect 5245 997 5469 1053
+rect 10410 999 10634 1055
+rect 5919 797 6053 853
+rect 9497 797 9631 853
+rect -609 518 -513 715
+rect 5180 518 5404 574
+rect 5919 518 6053 574
+rect 9497 359 9631 415
+rect 10412 306 10636 362
+rect -617 -1095 -505 -882
+rect 13797 -1223 13962 -1056
+rect 13770 -2695 13951 -2498
+<< metal3 >>
+rect 13136 4810 13764 4845
+rect 13136 4118 13170 4810
+rect 13714 4118 13764 4810
+rect 13136 2204 13764 4118
+rect 10402 2134 10646 2139
+rect 9470 2099 9672 2114
+rect 5170 2090 5414 2095
+rect 5170 2034 5180 2090
+rect 5404 2034 5414 2090
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+rect 9470 2043 9491 2099
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+rect 10402 2078 10412 2134
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+rect 9470 2034 9672 2043
+rect 5262 1616 5322 2029
+rect 5992 1817 6052 2030
+rect 9525 1836 9585 2034
+rect 9489 1831 9643 1836
+rect 5945 1812 6099 1817
+rect 5945 1756 5955 1812
+rect 6089 1756 6099 1812
+rect 9489 1775 9499 1831
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+rect 9489 1770 9643 1775
+rect 9525 1769 9585 1770
+rect 5945 1751 6099 1756
+rect 5992 1742 6052 1751
+rect 5235 1611 5479 1616
+rect 10494 1614 10554 2073
+rect 13136 1700 13173 2204
+rect 13734 1700 13764 2204
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+rect 19577 1256 20009 1261
+rect 19577 1172 19587 1256
+rect 19999 1172 20009 1256
+rect 19577 1167 20009 1172
+rect 5235 1053 5479 1058
+rect 5235 997 5245 1053
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+rect 10400 1055 10644 1060
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+rect 10634 999 10644 1055
+rect 10400 994 10644 999
+rect -627 715 -495 725
+rect -627 518 -609 715
+rect -513 518 -495 715
+rect 5262 579 5322 992
+rect 5956 858 6016 867
+rect 5909 853 6063 858
+rect 5909 797 5919 853
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+rect 5909 792 6063 797
+rect 9487 853 9641 858
+rect 9487 797 9497 853
+rect 9631 797 9641 853
+rect 9487 792 9641 797
+rect 5956 579 6016 792
+rect -627 -882 -495 518
+rect 5170 574 5414 579
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+rect 5909 574 6063 579
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+rect 9534 420 9594 792
+rect 9487 415 9641 420
+rect 9487 359 9497 415
+rect 9631 359 9641 415
+rect 10494 367 10554 994
+rect 9487 354 9641 359
+rect 10402 362 10646 367
+rect 10402 306 10412 362
+rect 10636 306 10646 362
+rect 10402 301 10646 306
+rect 16756 -71 16812 -15
+rect -627 -1095 -617 -882
+rect -505 -1095 -495 -882
+rect 13787 -1053 13972 -1051
+rect -627 -1100 -495 -1095
+rect 13785 -1259 13795 -1053
+rect 13965 -1259 13975 -1053
+rect 18944 -1835 19058 -1290
+rect 18937 -1939 18947 -1835
+rect 19055 -1939 19065 -1835
+rect 19758 -1841 19952 1167
+rect 19758 -1930 19773 -1841
+rect 19940 -1930 19952 -1841
+rect 13760 -2498 13961 -2493
+rect 13760 -2695 13770 -2498
+rect 13951 -2695 13961 -2498
+rect 13760 -2700 13961 -2695
+rect 18944 -2750 19058 -1939
+rect 19758 -1964 19952 -1930
+<< via3 >>
+rect 13170 4118 13714 4810
+rect 13795 -1056 13965 -1053
+rect 13795 -1223 13797 -1056
+rect 13797 -1223 13962 -1056
+rect 13962 -1223 13965 -1056
+rect 13795 -1259 13965 -1223
+rect 18947 -1939 19055 -1835
+rect 19773 -1930 19940 -1841
+rect 13770 -2695 13951 -2498
+<< metal4 >>
+rect 13169 4810 13715 4811
+rect 13169 4118 13170 4810
+rect 13714 4118 13715 4810
+rect 13169 4117 13715 4118
+rect 19686 4067 45340 4867
+rect 638 -1053 13971 -1048
+rect 638 -1259 13795 -1053
+rect 13965 -1259 13971 -1053
+rect 638 -1271 13971 -1259
+rect 18944 -1835 19952 -1831
+rect 18944 -1939 18947 -1835
+rect 19055 -1841 19952 -1835
+rect 19055 -1930 19773 -1841
+rect 19940 -1930 19952 -1841
+rect 19055 -1939 19952 -1930
+rect 18944 -1943 19952 -1939
+rect 638 -2498 13971 -2481
+rect 638 -2695 13770 -2498
+rect 13951 -2695 13971 -2498
+rect 638 -2704 13971 -2695
+use loop_filter  loop_filter_0
+timestamp 1623893910
+transform 1 0 15820 0 -1 9847
+box -16462 -24206 34360 5780
+use pfd_cp_interface  pfd_cp_interface_0
+timestamp 1623954650
+transform 1 0 3909 0 1 -230
+box 0 0 2154 3068
+use PFD  PFD_0
+timestamp 1623767380
+transform 1 0 0 0 1 1304
+box 0 -1304 3790 1304
+use charge_pump  charge_pump_0
+timestamp 1623940058
+transform 1 0 6183 0 1 -142
+box 0 -96 7722 2988
+use ring_osc  ring_osc_0
+timestamp 1623706675
+transform 1 0 14447 0 1 -174
+box -422 0 3882 2956
+use ring_osc_buffer  ring_osc_buffer_0
+timestamp 1623945368
+transform 1 0 18509 0 1 653
+box 0 0 1963 1270
+use div_by_5  div_by_5_0
+timestamp 1623948030
+transform -1 0 13250 0 1 -3418
+box -556 0 13892 3068
+use div_by_2  div_by_2_0
+timestamp 1623948030
+transform -1 0 18034 0 -1 -350
+box -1244 0 4228 3068
+<< labels >>
+rlabel metal2 2159 858 2211 1750 1 pfd_reset
+rlabel metal1 0 1956 210 2022 1 in_ref
+rlabel metal2 3988 1876 4074 2034 1 QA
+rlabel metal2 3988 574 4074 733 1 QB
+rlabel metal2 6053 755 9497 863 1 Down
+rlabel metal2 5469 971 10410 1079 1 nDown
+rlabel metal2 5469 1529 10410 1637 1 Up
+rlabel metal2 6089 1746 9499 1854 1 nUp
+rlabel metal1 8859 2012 8963 2633 1 biasp
+rlabel metal1 11133 2158 11217 2499 1 pswitch
+rlabel metal1 11118 80 11244 311 1 nswitch
+rlabel metal2 13764 206 14377 369 1 vco_vctrl
+rlabel metal3 16756 -71 16812 -15 1 vco_D0
+rlabel metal2 18091 1189 18520 1241 1 vco_out
+rlabel metal1 18878 1176 19279 1256 1 out_first_buffer
+rlabel via1 19587 1172 19999 1256 1 out_to_div
+rlabel metal1 20305 1172 20472 1250 1 out_to_pad
+rlabel metal1 14816 -2673 15040 -2617 1 out_div_2
+rlabel metal1 14819 -1154 15043 -1098 1 n_out_div_2
+rlabel metal1 14281 -1166 14682 -1086 1 n_out_buffer_div_2
+rlabel metal1 14281 -2683 14682 -2603 1 out_buffer_div_2
+rlabel metal1 13806 -2677 13973 -2599 1 out_by_2
+rlabel metal1 13806 -1170 13973 -1092 1 n_out_by_2
+rlabel metal2 -279 -954 161 -878 1 div_5_Q1_shift
+rlabel metal3 -627 -882 -495 518 1 out_div_by_5
+rlabel metal2 -405 -1940 -319 -1188 1 div_5_Q1
+rlabel metal1 6175 -1110 6996 -1051 1 div_5_Q0
+rlabel metal2 9937 -2546 10013 -1824 1 div_5_nQ0
+rlabel metal1 10227 -2717 10598 -2658 1 div_5_nQ2
+rlabel metal1 6405 304 8963 408 1 iref_cp
+rlabel metal1 0 2578 3504 2816 1 vdd
+rlabel metal1 18326 -208 19370 723 1 vss
+rlabel metal4 19686 4067 45340 4867 1 lf_vc
+<< end >>

diff --git a/mag/trans_gate.mag b/mag/trans_gate.mag
new file mode 100644
index 0000000..0a9f391
--- /dev/null
+++ b/mag/trans_gate.mag

@@ -0,0 +1,132 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1623610677
+<< nwell >>
+rect -53 635 569 723
+<< pwell >>
+rect -53 -811 569 -723
+<< psubdiff >>
+rect 55 -775 79 -741
+rect 437 -775 461 -741
+<< nsubdiff >>
+rect 55 653 79 687
+rect 437 653 461 687
+<< psubdiffcont >>
+rect 79 -775 437 -741
+<< nsubdiffcont >>
+rect 79 653 437 687
+<< poly >>
+rect 147 69 371 135
+rect 279 31 371 69
+rect 279 -37 291 31
+rect 359 -37 371 31
+rect 279 -53 371 -37
+rect 145 -69 237 -53
+rect 145 -137 157 -69
+rect 225 -137 237 -69
+rect 145 -171 237 -137
+rect 145 -237 369 -171
+<< polycont >>
+rect 291 -37 359 31
+rect 157 -137 225 -69
+<< locali >>
+rect 279 31 371 47
+rect 279 -37 291 31
+rect 359 -37 371 31
+rect 279 -53 371 -37
+rect 145 -69 237 -53
+rect 145 -137 157 -69
+rect 225 -137 237 -69
+rect 145 -153 237 -137
+<< viali >>
+rect -17 653 79 687
+rect 79 653 437 687
+rect 437 653 533 687
+rect -17 565 533 599
+rect 291 -37 359 31
+rect 157 -137 225 -69
+rect -17 -687 533 -653
+rect -17 -775 79 -741
+rect 79 -775 437 -741
+rect 437 -775 533 -741
+<< metal1 >>
+rect -53 687 569 693
+rect -53 653 -17 687
+rect 533 653 569 687
+rect -53 599 165 653
+rect 217 599 569 653
+rect -53 565 -17 599
+rect 533 565 569 599
+rect -53 559 165 565
+rect 217 559 569 565
+rect 45 462 329 508
+rect 45 404 137 462
+rect 283 404 329 462
+rect 45 -171 97 404
+rect 425 183 477 416
+rect 187 120 233 178
+rect 419 120 477 183
+rect 187 74 477 120
+rect 279 -53 291 37
+rect 359 -53 371 37
+rect 145 -143 157 -53
+rect 225 -143 237 -53
+rect 45 -217 329 -171
+rect 45 -341 97 -217
+rect 283 -263 329 -217
+rect 45 -513 91 -341
+rect 419 -343 477 74
+rect 425 -455 477 -343
+rect 419 -501 477 -455
+rect 187 -559 233 -513
+rect 379 -559 477 -501
+rect 187 -605 477 -559
+rect -53 -653 569 -647
+rect -53 -687 -17 -653
+rect 533 -687 569 -653
+rect -53 -741 299 -687
+rect 351 -741 569 -687
+rect -53 -775 -17 -741
+rect 533 -775 569 -741
+rect -53 -781 569 -775
+<< via1 >>
+rect 165 653 217 663
+rect 165 599 217 653
+rect 165 565 217 599
+rect 165 559 217 565
+rect 291 31 359 37
+rect 291 -37 359 31
+rect 291 -53 359 -37
+rect 157 -69 225 -53
+rect 157 -137 225 -69
+rect 157 -143 225 -137
+rect 299 -687 351 -653
+rect 299 -741 351 -687
+rect 299 -757 351 -741
+<< metal2 >>
+rect 157 663 225 673
+rect 157 559 165 663
+rect 217 559 225 663
+rect 157 -53 225 559
+rect 157 -153 225 -143
+rect 291 37 359 47
+rect 291 -653 359 -53
+rect 291 -757 299 -653
+rect 351 -757 359 -653
+rect 291 -766 359 -757
+rect 299 -767 351 -766
+use sky130_fd_pr__pfet_01v8_4798MH  sky130_fd_pr__pfet_01v8_4798MH_0
+timestamp 1623610677
+transform 1 0 258 0 1 291
+box -311 -344 311 344
+use sky130_fd_pr__nfet_01v8_BHR94T  sky130_fd_pr__nfet_01v8_BHR94T_0
+timestamp 1623610677
+transform 1 0 258 0 1 -388
+box -311 -335 311 335
+<< labels >>
+rlabel metal1 217 599 569 653 1 vdd
+rlabel metal1 -53 -741 299 -687 1 vss
+rlabel space 419 -605 477 416 1 out
+rlabel space 45 -513 97 508 1 in
+<< end >>

diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index ebc5e1b..ad60cec 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag

@@ -1,33 +1,15 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1620395479
-<< mvpsubdiff >>
-rect 345740 628255 345764 629032
-rect 371078 628255 371102 629032
-<< mvpsubdiffcont >>
-rect 345764 628255 371078 629032
-<< locali >>
-rect 345748 628255 345764 629032
-rect 371078 628255 371094 629032
-<< viali >>
-rect 357593 628300 359298 629000
+timestamp 1623979296
 << metal1 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 14755 659192 14765 659279
+rect 14990 659192 15000 659279
 << via1 >>
-rect 357538 629000 359388 629399
-rect 357538 628300 357593 629000
-rect 357593 628300 359298 629000
-rect 359298 628300 359388 629000
-rect 357538 628057 359388 628300
+rect 14765 659192 14990 659279
 << metal2 >>
-rect 357470 629399 359442 629457
-rect 357470 628057 357538 629399
-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
+rect 14765 659279 14990 659289
+rect 14765 659182 14990 659192
 rect 524 -800 636 480
 rect 1706 -800 1818 480
 rect 2888 -800 3000 480
@@ -523,133 +505,92 @@
 rect 582068 -800 582180 480
 rect 583250 -800 583362 480
 << via2 >>
-rect 357538 628057 359388 629399
+rect 14765 659192 14990 659279
 << metal3 >>
 rect 16194 702300 21194 704800
 rect 68194 702300 73194 704800
 rect 120194 702300 125194 704800
 rect 165594 702300 170594 704800
-rect 170894 690603 173094 704800
-rect -800 680242 1700 685242
-rect 170894 683764 173094 684327
-rect 173394 690603 175594 704800
+rect 170894 702300 173094 704800
+rect 173394 702300 175594 704800
 rect 175894 702300 180894 704800
 rect 217294 702300 222294 704800
-rect 173394 683764 175594 684327
-rect 222594 690636 224794 704800
-rect 222594 683913 224794 684360
-rect 225094 690636 227294 704800
+rect 222594 702300 224794 704800
+rect 225094 702300 227294 704800
 rect 227594 702300 232594 704800
-rect 225094 683913 227294 684360
-rect 318994 649497 323994 704800
-rect 324294 690618 326494 704800
-rect 326794 694292 328994 704800
-rect 329294 694292 334294 704800
+rect 318994 702300 323994 704800
+rect 324294 702300 326494 704800
+rect 326794 702300 328994 704800
+rect 329294 702300 334294 704800
 rect 413394 702300 418394 704800
 rect 465394 702300 470394 704800
-rect 326794 692092 334294 694292
-rect 324294 684038 326494 684344
-rect -800 643842 1660 648642
-rect 318994 642983 323994 643740
-rect 329294 649497 334294 692092
-rect 329294 642983 334294 643740
-rect 510594 690564 515394 704800
-rect -800 633842 1660 638642
-rect 510594 637598 515394 684332
-rect 510594 631116 515394 631780
-rect 520594 690564 525394 704800
+rect 510594 702340 515394 704800
+rect 520594 702340 525394 704800
 rect 566594 702300 571594 704800
-rect 520594 637598 525394 684332
+rect -800 683796 1700 685242
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+rect 5713 681296 5723 683796
+rect -800 680242 1700 681296
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-rect 560050 639784 560566 644584
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-rect 520594 631116 525394 631780
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-rect 357470 629399 359442 629457
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-rect 359388 628057 359442 629399
-rect 357470 627990 359442 628057
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-rect -800 505620 480 505732
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 rect 583520 584744 584800 584856
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+rect -800 559442 1660 564242
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+rect -800 511530 480 511642
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+rect -800 509166 480 509278
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 rect 583520 497686 584800 497798
 rect 583520 496504 584800 496616
 rect 583520 495322 584800 495434
 rect 583520 494140 584800 494252
-rect 573405 455628 573556 455740
-rect 576731 455628 584800 455740
-rect 537376 454446 584800 454558
+rect -800 468308 480 468420
+rect -800 467126 480 467238
+rect -800 465944 480 466056
+rect -800 464762 480 464874
+rect -800 463580 480 463692
+rect -800 462398 480 462510
+rect 583520 455628 584800 455740
+rect 583520 454446 584800 454558
 rect 583520 453264 584800 453376
 rect 583520 452082 584800 452194
 rect 583520 450900 584800 451012
 rect 583520 449718 584800 449830
+rect -800 425086 480 425198
+rect -800 423904 480 424016
+rect -800 422722 480 422834
+rect -800 421540 480 421652
+rect -800 420358 480 420470
+rect -800 419176 480 419288
 rect 583520 411206 584800 411318
 rect 583520 410024 584800 410136
 rect 583520 408842 584800 408954
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 rect 583520 406478 584800 406590
-rect 533497 405296 584800 405408
+rect 583520 405296 584800 405408
 rect -800 381864 480 381976
 rect -800 380682 480 380794
 rect -800 379500 480 379612
@@ -696,9 +637,7 @@
 rect 582340 225230 584800 230030
 rect -800 214888 1660 219688
 rect -800 204888 1660 209688
-rect 13406 191430 13991 196230
-rect 17427 191430 573605 196230
-rect 576629 191430 584800 196230
+rect 582340 191430 584800 196230
 rect 582340 181430 584800 186230
 rect -800 172888 1660 177688
 rect -800 162888 1660 167688
@@ -765,180 +704,32 @@
 rect -800 1544 480 1656
 rect 583520 1544 584800 1656
 << via3 >>
-rect 170894 684327 173094 690603
-rect 173394 684327 175594 690603
-rect 222594 684360 224794 690636
-rect 225094 684360 227294 690636
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-rect 13991 191430 17427 196230
-rect 573605 191430 576629 196230
+rect 3213 681296 5713 683796
+rect 3277 658981 5631 659464
 << metal4 >>
-rect 170628 690636 526162 690737
-rect 170628 690603 222594 690636
-rect 170628 684327 170894 690603
-rect 173094 684327 173394 690603
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-<< via4 >>
-rect 357559 643394 359314 649837
-rect 352028 615249 353603 617829
-rect 363412 615255 364987 617835
-rect 363414 597231 364992 601572
-<< metal5 >>
-rect 357521 649837 359350 649991
-rect 357521 643394 357559 649837
-rect 359314 643394 359350 649837
-rect 351918 617829 353747 617929
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-rect 363318 601572 365147 615255
-rect 363318 597231 363414 601572
-rect 364992 597231 365147 601572
-rect 363318 597052 365147 597231
+rect 3212 683796 5714 683797
+rect 3212 681331 3213 683796
+rect 3210 681296 3213 681331
+rect 5713 681296 5714 683796
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+rect 3245 659464 5710 678831
+rect 3245 658981 3277 659464
+rect 5631 658981 5710 659464
+rect 3245 658931 5710 658981
 << comment >>
 rect -100 704000 584100 704100
 rect -100 0 0 704000
 rect 584000 0 584100 704000
 rect -100 -100 584100 0
-use user_analog_proj_example  user_analog_proj_example_0
-timestamp 1620310959
-transform 1 0 345668 0 -1 627114
-box -59 -22 25476 8324
+use top_pll_v1  top_pll_v1_0
+timestamp 1623956621
+transform 1 0 14782 0 1 657248
+box -642 -3418 50180 34053
+use bias  bias_0
+timestamp 1623869799
+transform 1 0 250350 0 1 681360
+box -54 -412 44317 2238
 << labels >>
 flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
 port 0 nsew signal bidirectional
@@ -2296,10 +2087,6 @@
 port 676 nsew signal input
 flabel metal2 s 6434 -800 6546 480 0 FreeSans 1120 90 0 0 wbs_we_i
 port 677 nsew signal input
-flabel metal3 572152 640142 580220 644150 0 FreeSans 16000 0 0 0 VCCD1
-flabel metal3 567038 550960 577302 554546 0 FreeSans 16000 0 0 0 VDDA1
-flabel metal3 511190 664896 514962 676272 0 FreeSans 16000 90 0 0 VSSA1
-flabel metal3 561703 191929 571721 195859 0 FreeSans 16000 0 0 0 VSSD1
 << properties >>
 string FIXED_BBOX 0 0 584000 704000
 << end >>

diff --git a/skywater_setup.sh b/skywater_setup.sh
new file mode 100755
index 0000000..bfe93c6
--- /dev/null
+++ b/skywater_setup.sh

@@ -0,0 +1,137 @@
+#!/bin/bash
+
+echo "################# SkyWater130nm Enviroment Setup              #################"
+sudo apt-get update 
+sudo apt-get upgrade
+
+echo "################# Installing dependencies                     #################"
+sudo apt install git libtool automake autoconf texinfo libreadline-dev      \
+                     tcl8.6-dev tk8.6-dev libx11-dev libxaw7-dev xcb   \
+                     libxpm-dev bison flex libcairo2-dev m4 tcsh xterm wget \
+                     csh tcl-dev tk-dev ca-certificates qt5-default \
+                     libqt5designer5 libqt5multimedia5 libqt5multimediawidgets5 \
+                     libqt5opengl5 libqt5svg5 libqt5xmlpatterns5 libruby ruby ruby-dev \
+		     python3 python3-dev libz-dev -y
+
+version=$(lsb_release -cs)
+if [ $version == "focal" ]; then
+	echo "############################"
+	echo "Ubuntu 20.04. Installing adms"
+	echo "############################"
+	sudo apt install adms -y
+else
+	echo "#####################################"
+	echo "Ubuntu not 20.04. Not installing adms"
+	echo "#####################################"
+fi
+
+echo "################# Changing directory to $HOME       #################"
+cd
+
+echo "################# Creating directory for PDK & Tools          #################"
+mkdir skywater
+cd skywater
+
+echo "################# Installing ngspice                          #################"
+git clone https://git.code.sf.net/p/ngspice/ngspice
+cd ngspice
+if [ $version == "focal" ]; then
+	./autogen.sh --adms	
+	mkdir release
+	cd release
+	../configure --with-x --enable-xspice --enable-cider --enable-openmp --enable-pss --with-readline=yes --disable-debug
+	make -j4
+	sudo make install
+	cd $HOME/skywater
+else
+	./autogen.sh	
+	mkdir release
+	cd release
+	../configure --with-x --enable-xspice --enable-cider --enable-openmp --enable-pss --with-readline=yes --disable-debug
+	make -j4
+	sudo make install
+	cd $HOME/skywater
+fi
+
+echo "################# Installing XSCHEM                           #################"
+git clone https://github.com/StefanSchippers/xschem.git
+cd xschem
+./configure --prefix=/usr/local --user-conf-dir=~/.xschem \
+            --user-lib-path=~/share/xschem/xschem_library \
+            --sys-lib-path=/usr/local/share/xschem/xschem_library
+make -j4
+sudo make install
+cd $HOME/skywater
+
+echo "################# Cloning Google/Skywarter Symbols for Xschem #################"
+git clone https://github.com/StefanSchippers/xschem_sky130.git
+
+echo "################# Installing Magic                            #################"
+git clone git://opencircuitdesign.com/magic
+cd magic
+git checkout magic-8.3
+./configure
+make
+sudo make install
+cd $HOME/skywater
+
+echo "################# Installing klayout                          #################"
+
+if [ $version == "focal" ]; then
+	wget https://www.klayout.org/downloads/Ubuntu-20/klayout_0.26.11-1_amd64.deb
+else
+	wget https://www.klayout.org/downloads/Ubuntu-16/klayout_0.26.11-1_amd64.deb
+fi
+
+sudo dpkg -i ./klayout_0.26.11-1_amd64.deb
+sudo apt-get install -f -y
+rm klayout_0.26.11-1_amd64.deb
+
+echo "################# Installing netgen                           #################"
+git clone git://opencircuitdesign.com/netgen
+cd netgen
+git checkout netgen-1.5
+./configure
+make
+sudo make install
+cd $HOME/skywater
+
+echo "################# Cloning Google/Skywarter 130nm PDK          #################"
+git clone https://github.com/google/skywater-pdk.git
+cd skywater-pdk
+git submodule init libraries/sky130_fd_io/latest
+git submodule init libraries/sky130_fd_pr/latest
+git submodule init libraries/sky130_fd_sc_hd/latest
+git submodule init libraries/sky130_fd_sc_hdll/latest
+git submodule init libraries/sky130_fd_sc_hs/latest
+git submodule init libraries/sky130_fd_sc_ms/latest
+git submodule init libraries/sky130_fd_sc_ls/latest
+git submodule init libraries/sky130_fd_sc_lp/latest
+git submodule init libraries/sky130_fd_sc_hvl/latest
+git submodule update
+make timing
+cp -a libraries/sky130_fd_pr libraries/sky130_fd_pr_ngspice
+cd libraries/sky130_fd_pr_ngspice/latest
+patch -p2 < $HOME/skywater/xschem_sky130/sky130_fd_pr.patch
+cd $HOME/skywater
+cp ~/sky130-mpw2-fulgor/sky130.lib skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/
+
+echo "################# Installing Open PDKs                        #################"
+git clone git://opencircuitdesign.com/open_pdks
+cd open_pdks
+git checkout open_pdks-1.0
+mkdir -p $HOME/skywater/pdk/skywater130
+./configure --enable-sky130-pdk=$HOME/skywater/skywater-pdk/libraries --with-sky130-local-path=$HOME/skywater/pdk/skywater130 --enable-xschem-sky130=$HOME/skywater/xschem_sky130
+make
+sudo make install
+#cd $HOME/skywater/pdk/skywater130/sky130A/libs.tech/magic
+#sudo ln -s 1.* current
+#cd $HOME/skywater
+
+#echo "################# Copying sky130A.magicrc to magicrc          #################"
+#cp $HOME/skywater/pdk/skywater130/sky130A/libs.tech/magic/sky130A.magicrc $HOME/sky130-mpw2-fulgor/magicrc
+
+#echo "################# Installing Precheck                         #################"
+#git clone https://github.com/efabless/open_mpw_precheck.git
+#export TARGET_PATH="$HOME/caravel_fulgor_opamp"
+#export PDK_PATH="$HOME/skywater/pdk/skywater130"

diff --git a/xschem/DFF.sch b/xschem/DFF.sch
new file mode 100644
index 0000000..c834907
--- /dev/null
+++ b/xschem/DFF.sch

@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 100 -20 160 -20 { lab=CLK}
+N 140 20 160 20 { lab=Q}
+N 210 40 210 60 { lab=vss}
+N 210 -60 210 -40 { lab=D}
+N 140 260 160 260 { lab=P1}
+N 210 280 210 300 { lab=vss}
+N 210 180 210 200 { lab=D}
+N 140 20 140 100 { lab=Q}
+N 140 100 300 140 { lab=Q}
+N 300 140 300 240 { lab=Q}
+N 260 240 300 240 { lab=Q}
+N 120 220 160 220 { lab=P}
+N 120 140 120 220 { lab=P}
+N 120 140 300 100 { lab=P}
+N 300 -0 300 100 { lab=P}
+N 260 0 300 -0 { lab=P}
+N 260 500 280 500 { lab=P2}
+N 210 520 210 540 { lab=vss}
+N 260 740 280 740 { lab=Reset}
+N 210 760 210 780 { lab=vss}
+N 210 660 210 680 { lab=D}
+N 120 620 120 720 { lab=P2}
+N 120 720 160 720 { lab=P2}
+N 260 700 300 700 { lab=P1}
+N 300 620 300 700 { lab=P1}
+N 210 420 210 440 { lab=D}
+N 140 470 140 580 { lab=P1}
+N 140 260 140 470 { lab=P1}
+N 140 480 160 480 { lab=P1}
+N 140 580 300 620 { lab=P1}
+N 260 460 300 460 { lab=P}
+N 300 380 300 460 { lab=P}
+N 120 320 300 380 { lab=P}
+N 120 220 120 320 { lab=P}
+N 280 500 300 500 { lab=P2}
+N 300 500 300 580 { lab=P2}
+N 120 620 300 580 { lab=P2}
+N 300 240 380 240 { lab=Q}
+N 280 740 370 740 { lab=Reset}
+N 210 -70 210 -60 { lab=D}
+C {ipin.sym} 210 -70 1 0 {name=p1 lab=D}
+C {ipin.sym} 100 -20 0 0 {name=p2 lab=CLK}
+C {opin.sym} 380 240 0 0 {name=p3 lab=Q}
+C {lab_pin.sym} 210 60 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 140 220 0 0 {name=l2 sig_type=std_logic lab=P}
+C {lab_pin.sym} 210 300 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 180 1 0 {name=l5 sig_type=std_logic lab=D}
+C {lab_pin.sym} 210 540 1 1 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 660 3 1 {name=l7 sig_type=std_logic lab=D}
+C {lab_pin.sym} 210 420 1 0 {name=l8 sig_type=std_logic lab=D}
+C {lab_wire.sym} 290 700 0 0 {name=l9 sig_type=std_logic lab=P1}
+C {lab_wire.sym} 290 500 0 0 {name=l10 sig_type=std_logic lab=P2}
+C {ipin.sym} 370 740 2 0 {name=p4 lab=Reset}
+C {iopin.sym} 210 780 1 0 {name=p5 lab=vss}
+C {nor.sym} 210 0 0 0 {name=x1}
+C {nor.sym} 210 240 0 0 {name=x2}
+C {nor.sym} 210 480 0 1 {name=x3}
+C {nor.sym} 210 720 0 1 {name=x4}

diff --git a/xschem/DFF.sym b/xschem/DFF.sym
new file mode 100644
index 0000000..37d092d
--- /dev/null
+++ b/xschem/DFF.sym

@@ -0,0 +1,34 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -30 -30 30 {}
+L 4 30 -30 30 30 {}
+L 4 -50 -30 -30 -30 {}
+L 4 -50 0 -30 0 {}
+L 4 30 -30 50 -30 {}
+L 4 0 40 0 60 {}
+L 4 -30 -40 -30 -30 {}
+L 4 -30 -40 30 -40 {}
+L 4 30 -40 30 -30 {}
+L 4 -30 30 -30 40 {}
+L 4 -30 40 30 40 {}
+L 4 30 30 30 40 {}
+L 7 0 -60 0 -40 {}
+B 5 -52.5 -32.5 -47.5 -27.5 {name=D dir=in }
+B 5 -52.5 -2.5 -47.5 2.5 {name=CLK dir=in }
+B 5 47.5 -32.5 52.5 -27.5 {name=Q dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=Reset dir=in }
+B 5 -2.5 -62.5 2.5 -57.5 {name=vss dir=inout }
+T {@symname} 8.5 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {D} -25 -34 0 0 0.2 0.2 {}
+T {CLK} -25 -4 0 0 0.2 0.2 {}
+T {Q} 25 -34 0 1 0.2 0.2 {}
+T {Reset} -15 26 0 0 0.2 0.2 {}
+T {vss} -5 -54 0 1 0.2 0.2 {}

diff --git a/xschem/DFlipFlop.sch b/xschem/DFlipFlop.sch
new file mode 100644
index 0000000..f8435cd
--- /dev/null
+++ b/xschem/DFlipFlop.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 150 -210 210 -210 { lab=D_d}
+N 280 -290 280 -250 { lab=vdd}
+N 300 -90 300 -60 { lab=vss}
+N 570 -210 640 -210 { lab=Q}
+N 640 -210 650 -210 { lab=Q}
+N 150 -130 210 -130 { lab=nD_d}
+N 350 -130 390 -130 { lab=nA}
+N 350 -210 390 -210 { lab=A}
+N 390 -210 430 -210 { lab=A}
+N 390 -130 430 -130 { lab=nA}
+N 520 -90 520 -60 { lab=vss}
+N 500 -90 500 -60 { lab=nCLK}
+N 500 -280 500 -250 { lab=vdd}
+N 280 -90 280 -60 { lab=CLK}
+N 570 -130 640 -130 { lab=nQ}
+N 640 -130 650 -130 { lab=nQ}
+N -130 -170 -100 -170 { lab=D}
+N -100 -170 -60 -170 { lab=D}
+N 0 -260 0 -230 { lab=vdd}
+N 0 -110 0 -80 { lab=vss}
+N 60 -150 90 -150 { lab=nD_d}
+N 90 -150 90 -130 { lab=nD_d}
+N 90 -130 150 -130 { lab=nD_d}
+N 60 -190 90 -190 { lab=D_d}
+N 90 -210 90 -190 { lab=D_d}
+N 90 -210 150 -210 { lab=D_d}
+C {iopin.sym} 280 -290 3 0 {name=p1 lab=vdd}
+C {iopin.sym} 300 -60 1 0 {name=p3 lab=vss}
+C {opin.sym} 650 -210 0 0 {name=p7 lab=Q}
+C {lab_pin.sym} 520 -60 3 0 {name=l7 lab=vss}
+C {lab_pin.sym} 500 -280 1 0 {name=l8 lab=vdd}
+C {lab_wire.sym} 380 -130 0 1 {name=l19 lab=nA}
+C {opin.sym} 650 -130 0 0 {name=p2 lab=nQ}
+C {lab_wire.sym} 380 -210 0 1 {name=l1 lab=A}
+C {ipin.sym} -130 -170 0 0 {name=p6 lab=D}
+C {lab_wire.sym} 150 -210 0 0 {name=l27 lab=D_d}
+C {lab_wire.sym} 150 -130 0 0 {name=l28 lab=nD_d}
+C {ipin.sym} 280 -60 3 0 {name=p4 lab=CLK}
+C {ipin.sym} 500 -60 3 0 {name=p5 lab=nCLK}
+C {lab_pin.sym} 0 -260 1 0 {name=l2 lab=vdd}
+C {lab_pin.sym} 0 -80 3 0 {name=l3 lab=vss}
+C {clock_inverter.sym} 0 -170 0 0 {name=x1}
+C {latch_diff.sym} 280 -170 0 0 {name=x2}
+C {latch_diff.sym} 500 -170 0 0 {name=x3}

diff --git a/xschem/DFlipFlop.sym b/xschem/DFlipFlop.sym
new file mode 100644
index 0000000..3498bba
--- /dev/null
+++ b/xschem/DFlipFlop.sym

@@ -0,0 +1,40 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 -40 70 -40 {}
+L 4 50 40 70 40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -60 50 -60 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -10 -40 -0 {}
+L 4 -50 10 -40 -0 {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 30 -40 40 {}
+L 4 -50 50 -40 40 {}
+L 7 0 -80 0 -60 {}
+L 7 0 60 0 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
+B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=nCLK dir=in }
+T {@symname} 7 64 0 0 0.3 0.3 {}
+T {@name} -15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {Q} 45 -44 0 1 0.2 0.2 {}
+T {nQ} 45 36 0 1 0.2 0.2 {}
+T {vss} -6 85 1 1 0.2 0.2 {}
+T {D} -45 -44 0 0 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {nCLK} -35 36 0 0 0.2 0.2 {}

diff --git a/xschem/PFD.sch b/xschem/PFD.sch
new file mode 100644
index 0000000..e32e606
--- /dev/null
+++ b/xschem/PFD.sch

@@ -0,0 +1,40 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 30 60 30 130 { lab=Reset}
+N 30 100 90 100 { lab=Reset}
+N 30 130 30 140 { lab=Reset}
+N 80 230 240 230 { lab=Down}
+N 240 120 240 230 { lab=Down}
+N 190 120 240 120 { lab=Down}
+N 190 80 240 80 { lab=Up}
+N 240 -30 240 80 { lab=Up}
+N 80 -30 240 -30 { lab=Up}
+N -60 230 -20 230 { lab=vdd}
+N -60 -30 -20 -30 { lab=vdd}
+N 30 -100 30 -60 { lab=vss}
+N 30 260 30 290 { lab=vss}
+N 140 150 140 170 { lab=vss}
+N 140 30 140 50 { lab=vdd}
+N -60 200 -20 200 { lab=B}
+N -60 -0 -20 0 { lab=A}
+N 240 -30 320 -30 { lab=Up}
+N 240 230 320 230 { lab=Down}
+N 0 100 30 100 { lab=Reset}
+C {DFF.sym} 30 0 0 0 {name=x1}
+C {DFF.sym} 30 200 2 1 {name=x2}
+C {iopin.sym} -60 -30 2 0 {name=p1 lab=vdd}
+C {iopin.sym} 30 -100 3 0 {name=p2 lab=vss}
+C {ipin.sym} -60 0 0 0 {name=p3 lab=A}
+C {ipin.sym} -60 200 0 0 {name=p4 lab=B}
+C {opin.sym} 320 230 0 0 {name=p5 lab=Down}
+C {opin.sym} 320 -30 0 0 {name=p6 lab=Up}
+C {lab_pin.sym} 30 290 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -60 230 0 0 {name=l2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 140 170 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 30 1 0 {name=l4 sig_type=std_logic lab=vdd}
+C {iopin.sym} 0 100 2 0 {name=p7 lab=Reset}
+C {and_pfd.sym} 140 100 0 1 {name=x3}

diff --git a/xschem/PFD.sym b/xschem/PFD.sym
new file mode 100644
index 0000000..6c91f69
--- /dev/null
+++ b/xschem/PFD.sym

@@ -0,0 +1,48 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 50 -40 50 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 50 40 70 40 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 80 50 80 {}
+L 4 50 40 50 60 {}
+L 4 50 -60 50 -40 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -80 50 -60 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 40 60 {}
+L 4 40 60 40 80 {}
+L 7 20 -100 20 -80 {}
+L 7 -20 -100 -20 -80 {}
+L 7 0 80 0 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vss dir=inout }
+B 5 -22.5 -102.5 -17.5 -97.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Up dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=A dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=B dir=in }
+B 5 67.5 37.5 72.5 42.5 {name=Down dir=out }
+B 5 -2.5 97.5 2.5 102.5 {name=Reset dir=inout }
+T {@symname} 52.5 64 0 0 0.3 0.3 {}
+T {@name} -25 -2 0 0 0.2 0.2 {}
+T {vss} 6 -105 3 1 0.2 0.2 {}
+T {vdd} -34 -105 3 1 0.2 0.2 {}
+T {Up} 45 -44 0 1 0.2 0.2 {}
+T {A} -45 -44 0 0 0.2 0.2 {}
+T {B} -45 36 0 0 0.2 0.2 {}
+T {Down} 45 36 0 1 0.2 0.2 {}
+T {Reset} 14 115 1 1 0.2 0.2 {}
+T {Debug} 15 66 0 1 0.2 0.2 {}

diff --git a/xschem/PFD_pex_c.sym b/xschem/PFD_pex_c.sym
new file mode 100644
index 0000000..71929af
--- /dev/null
+++ b/xschem/PFD_pex_c.sym

@@ -0,0 +1,48 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 50 -40 50 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 50 40 70 40 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 80 50 80 {}
+L 4 50 40 50 60 {}
+L 4 50 -60 50 -40 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -60 -50 -40 {}
+L 4 50 -80 50 -60 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 40 60 {}
+L 4 40 60 40 80 {}
+L 7 20 -100 20 -80 {}
+L 7 -20 -100 -20 -80 {}
+L 7 0 80 0 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vss dir=inout }
+B 5 -22.5 -102.5 -17.5 -97.5 {name=vdd dir=inout }
+B 5 67.5 -42.5 72.5 -37.5 {name=Up dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=A dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=B dir=in }
+B 5 67.5 37.5 72.5 42.5 {name=Down dir=out }
+B 5 -2.5 97.5 2.5 102.5 {name=Reset dir=inout }
+T {@symname} 52.5 64 0 0 0.3 0.3 {}
+T {@name} -25 -2 0 0 0.2 0.2 {}
+T {vss} 6 -105 3 1 0.2 0.2 {}
+T {vdd} -34 -105 3 1 0.2 0.2 {}
+T {Up} 45 -44 0 1 0.2 0.2 {}
+T {A} -45 -44 0 0 0.2 0.2 {}
+T {B} -45 36 0 0 0.2 0.2 {}
+T {Down} 45 36 0 1 0.2 0.2 {}
+T {Reset} 14 115 1 1 0.2 0.2 {}
+T {Debug} 15 66 0 1 0.2 0.2 {}

diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
index 736a27c..20590e8 100644
--- a/xschem/analog_wrapper_tb.sch
+++ b/xschem/analog_wrapper_tb.sch

@@ -73,21 +73,21 @@
 N -60 -70 0 -70 { lab=#net26}
 N -60 -50 0 -50 { lab=#net27}
 C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1}
-C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
-C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
-C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
-C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
-C {devices/bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
-C {devices/bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
-C {devices/lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
-C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
-C {devices/lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
-C {devices/lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
-C {devices/lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
-C {devices/bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
-C {devices/bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
-C {devices/code_shown.sym} 920 -130 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+C {vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
+C {vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
+C {vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
+C {gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
+C {bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
+C {bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
+C {lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
+C {lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
+C {lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
+C {lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
+C {lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
+C {bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
+C {bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
+C {code_shown.sym} 920 -130 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
 .lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
 .include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 .control

diff --git a/xschem/and_pfd.sch b/xschem/and_pfd.sch
new file mode 100644
index 0000000..98b0aba
--- /dev/null
+++ b/xschem/and_pfd.sch

@@ -0,0 +1,173 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 60 160 60 220 { lab=#net1}
+N 60 20 60 100 { lab=out_nand}
+N 60 280 60 320 { lab=vss}
+N 60 320 260 320 { lab=vss}
+N 260 280 260 320 { lab=vss}
+N 260 170 260 220 { lab=#net2}
+N 260 20 260 100 { lab=out_nand}
+N 260 -80 260 -40 { lab=vdd}
+N 60 -80 260 -80 { lab=vdd}
+N 60 -80 60 -40 { lab=vdd}
+N 60 -10 260 -10 { lab=vdd}
+N 160 -80 160 -10 { lab=vdd}
+N 60 60 260 60 { lab=out_nand}
+N 60 130 150 130 { lab=vss}
+N 60 250 260 250 { lab=vss}
+N 160 250 160 320 { lab=vss}
+N 170 130 260 130 { lab=vss}
+N 260 160 260 170 { lab=#net2}
+N -40 130 20 130 { lab=A}
+N -40 250 20 250 { lab=B}
+N 300 250 360 250 { lab=A}
+N 300 130 360 130 { lab=B}
+N 300 -10 360 -10 { lab=B}
+N -40 -10 20 -10 { lab=A}
+N -40 -80 60 -80 { lab=vdd}
+N -40 320 60 320 { lab=vss}
+N 260 60 360 60 { lab=out_nand}
+N 490 30 490 100 { lab=out}
+N 420 0 450 0 { lab=out_nand}
+N 420 0 420 130 { lab=out_nand}
+N 420 130 450 130 { lab=out_nand}
+N 360 60 420 60 { lab=out_nand}
+N 260 320 490 320 { lab=vss}
+N 490 160 490 320 { lab=vss}
+N 490 -80 490 -30 { lab=vdd}
+N 260 -80 490 -80 { lab=vdd}
+N 490 60 600 60 { lab=out}
+N 490 0 560 0 { lab=vdd}
+N 560 -80 560 0 { lab=vdd}
+N 490 -80 560 -80 { lab=vdd}
+N 490 130 580 130 { lab=vss}
+N 580 130 580 320 { lab=vss}
+N 490 320 580 320 { lab=vss}
+N 150 130 170 130 { lab=vss}
+N 160 130 160 250 { lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 40 130 0 0 {name=M1
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 40 -10 0 0 {name=M2
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 40 250 0 0 {name=M3
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 280 130 0 1 {name=M4
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 280 250 0 1 {name=M5
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 280 -10 0 1 {name=M6
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -40 -80 2 0 {name=p1 lab=vdd}
+C {iopin.sym} -40 320 2 0 {name=p2 lab=vss}
+C {opin.sym} 600 60 0 0 {name=p3 lab=out}
+C {ipin.sym} -40 130 0 0 {name=p4 lab=A}
+C {ipin.sym} -40 250 0 0 {name=p5 lab=B}
+C {lab_pin.sym} -40 -10 0 0 {name=l1 sig_type=std_logic lab=A}
+C {lab_pin.sym} 360 -10 2 0 {name=l2 sig_type=std_logic lab=B}
+C {lab_pin.sym} 360 130 2 0 {name=l3 sig_type=std_logic lab=B}
+C {lab_pin.sym} 360 250 2 0 {name=l4 sig_type=std_logic lab=A}
+C {sky130_fd_pr/pfet_01v8.sym} 470 0 0 0 {name=M7
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 470 130 0 0 {name=M8
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 310 60 0 1 {name=l5 sig_type=std_logic lab=out_nand}

diff --git a/xschem/and_pfd.sym b/xschem/and_pfd.sym
new file mode 100644
index 0000000..833b9df
--- /dev/null
+++ b/xschem/and_pfd.sym

@@ -0,0 +1,32 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 30 0 50 0 {}
+L 4 -50 -20 -30 -20 {}
+L 4 -50 20 -30 20 {}
+L 4 -30 -30 -30 30 {}
+L 4 -30 -30 -0 -30 {}
+L 4 -30 30 -0 30 {}
+L 4 -3 30 2 30 {}
+L 4 -2 -30 2 -30 {}
+L 7 0 -50 0 -30 {}
+L 7 0 30 0 50 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 47.5 -2.5 52.5 2.5 {name=out dir=out }
+B 5 -52.5 -22.5 -47.5 -17.5 {name=A dir=in }
+B 5 -52.5 17.5 -47.5 22.5 {name=B dir=in }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+A 4 -0.5 0 30.10398644698074 274.7636416907262 170.4727166185477 {}
+T {@symname} 4 34 0 0 0.3 0.3 {}
+T {@name} -25 -12 0 0 0.2 0.2 {}
+T {vdd} -14 -55 3 1 0.2 0.2 {}
+T {out} 55 -14 0 1 0.2 0.2 {}
+T {A} -45 -34 0 0 0.2 0.2 {}
+T {B} -45 6 0 0 0.2 0.2 {}
+T {vss} -6 55 1 1 0.2 0.2 {}

diff --git a/xschem/bias.sch b/xschem/bias.sch
new file mode 100644
index 0000000..375151d
--- /dev/null
+++ b/xschem/bias.sch

@@ -0,0 +1,480 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 470 -700 470 -660 { lab=#net1}
+N 190 -860 190 -800 { lab=vdd}
+N 470 -860 470 -800 { lab=vdd}
+N 190 -700 190 -660 { lab=vbp1}
+N 270 -770 430 -770 { lab=vbp1}
+N 190 -710 270 -710 { lab=vbp1}
+N 270 -770 270 -710 { lab=vbp1}
+N 110 -630 190 -630 { lab=vdd}
+N 110 -770 190 -770 { lab=vdd}
+N 470 -770 550 -770 { lab=vdd}
+N 470 -630 550 -630 { lab=vdd}
+N 190 -740 190 -710 { lab=vbp1}
+N 230 -770 270 -770 { lab=vbp1}
+N 470 -600 470 -540 { lab=iref_0}
+N 190 -710 190 -700 { lab=vbp1}
+N 470 -740 470 -700 { lab=#net1}
+N 470 -540 470 -520 { lab=iref_0}
+N 740 -700 740 -660 { lab=#net2}
+N 740 -860 740 -800 { lab=vdd}
+N 740 -770 820 -770 { lab=vdd}
+N 740 -630 820 -630 { lab=vdd}
+N 740 -600 740 -540 { lab=iref_1}
+N 740 -740 740 -700 { lab=#net2}
+N 740 -540 740 -520 { lab=iref_1}
+N 640 -770 700 -770 { lab=vbp1}
+N 640 -630 700 -630 { lab=iref}
+N 990 -700 990 -660 { lab=#net3}
+N 990 -860 990 -800 { lab=vdd}
+N 990 -770 1070 -770 { lab=vdd}
+N 990 -630 1070 -630 { lab=vdd}
+N 990 -600 990 -540 { lab=iref_2}
+N 990 -740 990 -700 { lab=#net3}
+N 990 -540 990 -520 { lab=iref_2}
+N 890 -770 950 -770 { lab=vbp1}
+N 890 -630 950 -630 { lab=iref}
+N 1230 -700 1230 -660 { lab=#net4}
+N 1230 -860 1230 -800 { lab=vdd}
+N 1230 -770 1310 -770 { lab=vdd}
+N 1230 -630 1310 -630 { lab=vdd}
+N 1230 -600 1230 -540 { lab=iref_3}
+N 1230 -740 1230 -700 { lab=#net4}
+N 1230 -540 1230 -520 { lab=iref_3}
+N 1130 -770 1190 -770 { lab=vbp1}
+N 1130 -630 1190 -630 { lab=iref}
+N 1480 -700 1480 -660 { lab=#net5}
+N 1480 -860 1480 -800 { lab=vdd}
+N 1480 -770 1560 -770 { lab=vdd}
+N 1480 -630 1560 -630 { lab=vdd}
+N 1480 -600 1480 -540 { lab=iref_4}
+N 1480 -740 1480 -700 { lab=#net5}
+N 1480 -540 1480 -520 { lab=iref_4}
+N 1380 -770 1440 -770 { lab=vbp1}
+N 1380 -630 1440 -630 { lab=iref}
+N 470 -190 470 -150 { lab=#net6}
+N 470 -350 470 -290 { lab=vdd}
+N 470 -260 550 -260 { lab=vdd}
+N 470 -120 550 -120 { lab=vdd}
+N 470 -90 470 -30 { lab=iref_5}
+N 470 -230 470 -190 { lab=#net6}
+N 470 -30 470 -10 { lab=iref_5}
+N 740 -190 740 -150 { lab=#net7}
+N 740 -350 740 -290 { lab=vdd}
+N 740 -260 820 -260 { lab=vdd}
+N 740 -120 820 -120 { lab=vdd}
+N 740 -90 740 -30 { lab=iref_6}
+N 740 -230 740 -190 { lab=#net7}
+N 740 -30 740 -10 { lab=iref_6}
+N 640 -260 700 -260 { lab=vbp1}
+N 640 -120 700 -120 { lab=iref}
+N 990 -190 990 -150 { lab=#net8}
+N 990 -350 990 -290 { lab=vdd}
+N 990 -260 1070 -260 { lab=vdd}
+N 990 -120 1070 -120 { lab=vdd}
+N 990 -90 990 -30 { lab=iref_7}
+N 990 -230 990 -190 { lab=#net8}
+N 990 -30 990 -10 { lab=iref_7}
+N 890 -260 950 -260 { lab=vbp1}
+N 890 -120 950 -120 { lab=iref}
+N 1230 -190 1230 -150 { lab=#net9}
+N 1230 -350 1230 -290 { lab=vdd}
+N 1230 -260 1310 -260 { lab=vdd}
+N 1230 -120 1310 -120 { lab=vdd}
+N 1230 -90 1230 -30 { lab=iref_8}
+N 1230 -230 1230 -190 { lab=#net9}
+N 1230 -30 1230 -10 { lab=iref_8}
+N 1130 -260 1190 -260 { lab=vbp1}
+N 1130 -120 1190 -120 { lab=iref}
+N 1480 -190 1480 -150 { lab=#net10}
+N 1480 -350 1480 -290 { lab=vdd}
+N 1480 -260 1560 -260 { lab=vdd}
+N 1480 -120 1560 -120 { lab=vdd}
+N 1480 -90 1480 -30 { lab=iref_cp_9}
+N 1480 -230 1480 -190 { lab=#net10}
+N 1480 -30 1480 -10 { lab=iref_cp_9}
+N 1380 -260 1440 -260 { lab=vbp1}
+N 1380 -120 1440 -120 { lab=iref}
+N 370 -260 430 -260 { lab=vbp1}
+N 370 -120 430 -120 { lab=iref}
+N 230 -630 430 -630 { lab=iref}
+N 190 -600 190 -500 { lab=iref}
+N 190 -550 280 -550 { lab=iref}
+N 280 -630 280 -550 { lab=iref}
+C {lab_pin.sym} 110 -770 0 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 550 -770 2 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 470 -860 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 340 -770 0 0 {name=l5 sig_type=std_logic lab=vbp1}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 210 -630 0 1 {name=M1
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 210 -770 0 1 {name=M2
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -770 0 0 {name=M3
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -630 0 0 {name=M4
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {iopin.sym} 190 -500 1 0 {name=p8 lab=iref}
+C {iopin.sym} 190 -860 3 0 {name=p9 lab=vdd}
+C {lab_pin.sym} 550 -630 2 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 110 -630 0 0 {name=l9 sig_type=std_logic lab=vdd}
+C {opin.sym} 470 -520 1 0 {name=p1 lab=iref_0}
+C {lab_pin.sym} 820 -770 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 740 -860 1 0 {name=l3 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -770 0 0 {name=M5
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -630 0 0 {name=M6
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 820 -630 2 0 {name=l4 sig_type=std_logic lab=vdd}
+C {opin.sym} 740 -520 1 0 {name=p2 lab=iref_1}
+C {lab_wire.sym} 680 -770 0 0 {name=l10 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1070 -770 2 0 {name=l13 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -860 1 0 {name=l14 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -770 0 0 {name=M7
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -630 0 0 {name=M8
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1070 -630 2 0 {name=l15 sig_type=std_logic lab=vdd}
+C {opin.sym} 990 -520 1 0 {name=p3 lab=iref_2}
+C {lab_wire.sym} 930 -770 0 0 {name=l16 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1310 -770 2 0 {name=l18 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1230 -860 1 0 {name=l19 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -770 0 0 {name=M9
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -630 0 0 {name=M10
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1310 -630 2 0 {name=l20 sig_type=std_logic lab=vdd}
+C {opin.sym} 1230 -520 1 0 {name=p4 lab=iref_3}
+C {lab_wire.sym} 1170 -770 0 0 {name=l21 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1560 -770 2 0 {name=l23 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1480 -860 1 0 {name=l24 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -770 0 0 {name=M11
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -630 0 0 {name=M12
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1560 -630 2 0 {name=l25 sig_type=std_logic lab=vdd}
+C {opin.sym} 1480 -520 1 0 {name=p5 lab=iref_4}
+C {lab_wire.sym} 1420 -770 0 0 {name=l26 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 550 -260 2 0 {name=l28 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 470 -350 1 0 {name=l29 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -260 0 0 {name=M13
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 450 -120 0 0 {name=M14
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 550 -120 2 0 {name=l30 sig_type=std_logic lab=vdd}
+C {opin.sym} 470 -10 1 0 {name=p6 lab=iref_5}
+C {lab_pin.sym} 820 -260 2 0 {name=l31 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 740 -350 1 0 {name=l32 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -260 0 0 {name=M15
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 720 -120 0 0 {name=M16
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 820 -120 2 0 {name=l33 sig_type=std_logic lab=vdd}
+C {opin.sym} 740 -10 1 0 {name=p7 lab=iref_6}
+C {lab_wire.sym} 680 -260 0 0 {name=l34 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1070 -260 2 0 {name=l36 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -350 1 0 {name=l37 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -260 0 0 {name=M17
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 970 -120 0 0 {name=M18
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1070 -120 2 0 {name=l38 sig_type=std_logic lab=vdd}
+C {opin.sym} 990 -10 1 0 {name=p10 lab=iref_7}
+C {lab_wire.sym} 930 -260 0 0 {name=l39 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1310 -260 2 0 {name=l41 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1230 -350 1 0 {name=l42 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -260 0 0 {name=M19
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1210 -120 0 0 {name=M20
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1310 -120 2 0 {name=l43 sig_type=std_logic lab=vdd}
+C {opin.sym} 1230 -10 1 0 {name=p11 lab=iref_8}
+C {lab_wire.sym} 1170 -260 0 0 {name=l44 sig_type=std_logic lab=vbp1}
+C {lab_pin.sym} 1560 -260 2 0 {name=l46 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1480 -350 1 0 {name=l47 sig_type=std_logic lab=vdd}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -260 0 0 {name=M21
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 1460 -120 0 0 {name=M22
+L=0.45
+W=4.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {lab_pin.sym} 1560 -120 2 0 {name=l48 sig_type=std_logic lab=vdd}
+C {opin.sym} 1480 -10 1 0 {name=p12 lab=iref_9}
+C {lab_wire.sym} 1420 -260 0 0 {name=l49 sig_type=std_logic lab=vbp1}
+C {lab_wire.sym} 410 -260 0 0 {name=l51 sig_type=std_logic lab=vbp1}
+C {lab_wire.sym} 360 -630 0 0 {name=l1 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 670 -630 0 0 {name=l12 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 920 -630 0 0 {name=l17 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1170 -630 0 0 {name=l22 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1410 -630 0 0 {name=l27 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 400 -120 0 0 {name=l35 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 670 -120 0 0 {name=l40 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 920 -120 0 0 {name=l45 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1160 -120 0 0 {name=l50 sig_type=std_logic lab=iref}
+C {lab_wire.sym} 1410 -120 0 0 {name=l52 sig_type=std_logic lab=iref}

diff --git a/xschem/bias.sym b/xschem/bias.sym
new file mode 100644
index 0000000..f96b40f
--- /dev/null
+++ b/xschem/bias.sym

@@ -0,0 +1,56 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -110 -40 -10 {}
+L 4 40 -110 40 -10 {}
+L 4 -40 110 40 110 {}
+L 4 -40 -110 40 -110 {}
+L 4 40 -90 60 -90 {}
+L 4 40 -70 60 -70 {}
+L 4 40 -50 60 -50 {}
+L 4 40 -30 60 -30 {}
+L 4 40 -10 60 -10 {}
+L 4 40 10 60 10 {}
+L 4 40 30 60 30 {}
+L 4 40 50 60 50 {}
+L 4 40 70 60 70 {}
+L 4 40 90 60 90 {}
+L 4 40 -10 40 110 {}
+L 4 -40 -10 -40 110 {}
+L 7 0 -130 0 -110 {}
+L 7 -20 110 -20 130 {}
+L 7 20 110 20 130 {}
+B 5 -2.5 -132.5 2.5 -127.5 {name=vdd dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=iref dir=inout }
+B 5 17.5 127.5 22.5 132.5 {name=vss dir=inout }
+B 5 57.5 -92.5 62.5 -87.5 {name=iref_0 dir=out }
+B 5 57.5 -72.5 62.5 -67.5 {name=iref_1 dir=out }
+B 5 57.5 -52.5 62.5 -47.5 {name=iref_2 dir=out }
+B 5 57.5 -32.5 62.5 -27.5 {name=iref_3 dir=out }
+B 5 57.5 -12.5 62.5 -7.5 {name=iref_4 dir=out }
+B 5 57.5 7.5 62.5 12.5 {name=iref_5 dir=out }
+B 5 57.5 27.5 62.5 32.5 {name=iref_6 dir=out }
+B 5 57.5 47.5 62.5 52.5 {name=iref_7 dir=out }
+B 5 57.5 67.5 62.5 72.5 {name=iref_8 dir=out }
+B 5 57.5 87.5 62.5 92.5 {name=iref_9 dir=out }
+T {@symname} 34 114 0 0 0.3 0.3 {}
+T {@name} 5 -122 0 0 0.2 0.2 {}
+T {vdd} -14 -135 3 1 0.2 0.2 {}
+T {iref} -26 135 1 1 0.2 0.2 {}
+T {vss} 14 135 1 1 0.2 0.2 {}
+T {iref_0} 35 -94 0 1 0.2 0.2 {}
+T {iref_1} 35 -74 0 1 0.2 0.2 {}
+T {iref_2} 35 -54 0 1 0.2 0.2 {}
+T {iref_3} 35 -34 0 1 0.2 0.2 {}
+T {iref_4} 35 -14 0 1 0.2 0.2 {}
+T {iref_5} 35 6 0 1 0.2 0.2 {}
+T {iref_6} 35 26 0 1 0.2 0.2 {}
+T {iref_7} 35 46 0 1 0.2 0.2 {}
+T {iref_8} 35 66 0 1 0.2 0.2 {}
+T {iref_9} 35 86 0 1 0.2 0.2 {}

diff --git a/xschem/bias_pex_c.sym b/xschem/bias_pex_c.sym
new file mode 100644
index 0000000..29cf8e2
--- /dev/null
+++ b/xschem/bias_pex_c.sym

@@ -0,0 +1,56 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -110 -40 -10 {}
+L 4 40 -110 40 -10 {}
+L 4 -40 110 40 110 {}
+L 4 -40 -110 40 -110 {}
+L 4 40 -90 60 -90 {}
+L 4 40 -70 60 -70 {}
+L 4 40 -50 60 -50 {}
+L 4 40 -30 60 -30 {}
+L 4 40 -10 60 -10 {}
+L 4 40 10 60 10 {}
+L 4 40 30 60 30 {}
+L 4 40 50 60 50 {}
+L 4 40 70 60 70 {}
+L 4 40 90 60 90 {}
+L 4 40 -10 40 110 {}
+L 4 -40 -10 -40 110 {}
+L 7 0 -130 0 -110 {}
+L 7 -20 110 -20 130 {}
+L 7 20 110 20 130 {}
+B 5 -2.5 -132.5 2.5 -127.5 {name=vdd dir=inout }
+B 5 -22.5 127.5 -17.5 132.5 {name=iref dir=inout }
+B 5 17.5 127.5 22.5 132.5 {name=vss dir=inout }
+B 5 57.5 -92.5 62.5 -87.5 {name=iref_0 dir=out }
+B 5 57.5 -72.5 62.5 -67.5 {name=iref_1 dir=out }
+B 5 57.5 -52.5 62.5 -47.5 {name=iref_2 dir=out }
+B 5 57.5 -32.5 62.5 -27.5 {name=iref_3 dir=out }
+B 5 57.5 -12.5 62.5 -7.5 {name=iref_4 dir=out }
+B 5 57.5 7.5 62.5 12.5 {name=iref_5 dir=out }
+B 5 57.5 27.5 62.5 32.5 {name=iref_6 dir=out }
+B 5 57.5 47.5 62.5 52.5 {name=iref_7 dir=out }
+B 5 57.5 67.5 62.5 72.5 {name=iref_8 dir=out }
+B 5 57.5 87.5 62.5 92.5 {name=iref_9 dir=out }
+T {@symname} 34 114 0 0 0.3 0.3 {}
+T {@name} 5 -122 0 0 0.2 0.2 {}
+T {vdd} -14 -135 3 1 0.2 0.2 {}
+T {iref} -26 135 1 1 0.2 0.2 {}
+T {vss} 14 135 1 1 0.2 0.2 {}
+T {iref_0} 35 -94 0 1 0.2 0.2 {}
+T {iref_1} 35 -74 0 1 0.2 0.2 {}
+T {iref_2} 35 -54 0 1 0.2 0.2 {}
+T {iref_3} 35 -34 0 1 0.2 0.2 {}
+T {iref_4} 35 -14 0 1 0.2 0.2 {}
+T {iref_5} 35 6 0 1 0.2 0.2 {}
+T {iref_6} 35 26 0 1 0.2 0.2 {}
+T {iref_7} 35 46 0 1 0.2 0.2 {}
+T {iref_8} 35 66 0 1 0.2 0.2 {}
+T {iref_9} 35 86 0 1 0.2 0.2 {}

diff --git a/xschem/charge_pump.sch b/xschem/charge_pump.sch
new file mode 100644
index 0000000..7a02fd5
--- /dev/null
+++ b/xschem/charge_pump.sch

@@ -0,0 +1,277 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -30 190 -30 230 { lab=nswitch}
+N -100 190 -30 190 { lab=nswitch}
+N -30 190 30 190 { lab=nswitch}
+N -30 290 -30 320 { lab=vss}
+N -30 320 70 320 { lab=vss}
+N 70 220 70 320 { lab=vss}
+N 70 190 170 190 { lab=vss}
+N 170 190 170 320 { lab=vss}
+N 70 320 170 320 { lab=vss}
+N -130 190 -130 320 { lab=vss}
+N -130 320 -30 320 { lab=vss}
+N -30 260 70 260 { lab=vss}
+N -220 320 -130 320 { lab=vss}
+N -100 -150 30 -150 { lab=pswitch}
+N -30 -180 -30 -150 { lab=pswitch}
+N 70 -260 70 -180 { lab=vdd}
+N -30 -260 -30 -240 { lab=vdd}
+N -30 -210 70 -210 { lab=vdd}
+N 70 -150 170 -150 { lab=vdd}
+N 170 -260 170 -150 { lab=vdd}
+N 70 -260 170 -260 { lab=vdd}
+N -130 -260 -130 -150 { lab=vdd}
+N -130 -110 -130 -90 { lab=nUp}
+N -160 -40 -120 -40 { lab=nUp}
+N -130 130 -130 150 { lab=Down}
+N -170 70 -130 70 { lab=Down}
+N 70 0 170 0 { lab=out}
+N -230 -260 -130 -260 { lab=vdd}
+N -250 320 -220 320 { lab=vss}
+N -90 -210 -90 -200 { lab=Up}
+N -90 -210 -70 -210 { lab=Up}
+N -90 260 -70 260 { lab=nDown}
+N -120 260 -120 300 { lab=nDown}
+N -120 260 -90 260 { lab=nDown}
+N -130 -260 70 -260 { lab=vdd}
+N -210 190 -160 190 { lab=iref}
+N -220 -150 -160 -150 { lab=biasp}
+N 70 120 70 160 { lab=#net1}
+N 70 -0 70 60 { lab=out}
+N 70 -30 70 0 { lab=out}
+N 70 -120 70 -90 { lab=#net2}
+N -130 70 -100 70 { lab=Down}
+N -120 -40 -100 -40 { lab=nUp}
+N -130 -90 -130 -40 { lab=nUp}
+N -60 -10 -60 0 { lab=pswitch}
+N -60 0 20 0 { lab=pswitch}
+N 20 -80 20 0 { lab=pswitch}
+N -60 -80 20 -80 { lab=pswitch}
+N -60 -80 -60 -70 { lab=pswitch}
+N -30 -90 -30 -80 { lab=pswitch}
+N -60 -40 -40 -40 { lab=vdd}
+N -60 100 -60 110 { lab=nswitch}
+N -60 110 20 110 { lab=nswitch}
+N 20 30 20 110 { lab=nswitch}
+N -60 30 20 30 { lab=nswitch}
+N -60 30 -60 40 { lab=nswitch}
+N -130 70 -130 130 { lab=Down}
+N -60 70 -40 70 { lab=vss}
+N -30 110 -30 190 { lab=nswitch}
+N -30 -150 -30 -90 { lab=pswitch}
+N -40 140 -30 140 { lab=nswitch}
+N -40 -100 -30 -100 { lab=pswitch}
+N -690 220 -690 280 { lab=vss}
+N -740 190 -690 190 { lab=vss}
+N -650 190 -600 190 { lab=iref}
+N -620 120 -620 190 { lab=iref}
+N -690 120 -620 120 { lab=iref}
+N -690 80 -690 160 { lab=iref}
+N -820 320 -530 320 { lab=vss}
+N -690 280 -690 320 { lab=vss}
+N -440 220 -440 280 { lab=vss}
+N -440 190 -360 190 { lab=vss}
+N -440 -230 -440 -180 { lab=vdd}
+N -520 -150 -440 -150 { lab=vdd}
+N -530 190 -480 190 { lab=iref}
+N -400 -150 -340 -150 { lab=biasp}
+N -340 -150 -340 -90 { lab=biasp}
+N -440 -90 -340 -90 { lab=biasp}
+N -440 -120 -440 -90 { lab=biasp}
+N -440 -90 -440 -70 { lab=biasp}
+N -440 120 -440 160 { lab=biasp}
+N -340 -150 -320 -150 { lab=biasp}
+N -320 -150 -220 -150 { lab=biasp}
+N -540 -260 -240 -260 { lab=vdd}
+N -240 -260 -230 -260 { lab=vdd}
+N -440 -260 -440 -230 { lab=vdd}
+N -520 -260 -520 -150 { lab=vdd}
+N -360 320 -250 320 { lab=vss}
+N -520 320 -360 320 { lab=vss}
+N -530 320 -520 320 { lab=vss}
+N -440 280 -440 320 { lab=vss}
+N -600 190 -530 190 { lab=iref}
+N -440 -70 -440 120 { lab=biasp}
+N -790 190 -740 190 { lab=vss}
+N -790 190 -790 320 { lab=vss}
+N -360 190 -340 190 { lab=vss}
+N -340 190 -340 320 { lab=vss}
+N -340 -90 -340 -60 { lab=biasp}
+N 70 60 70 120 {}
+N 70 -90 70 -30 {}
+C {iopin.sym} -820 320 2 0 {name=p1 lab=vss}
+C {iopin.sym} -540 -260 2 0 {name=p2 lab=vdd}
+C {ipin.sym} -170 70 0 0 {name=p3 lab=Down}
+C {ipin.sym} -160 -40 0 0 {name=p4 lab=nUp}
+C {ipin.sym} -90 -200 3 0 {name=p5 lab=Up}
+C {ipin.sym} -120 300 2 0 {name=p6 lab=nDown}
+C {opin.sym} 170 0 0 0 {name=p7 lab=out}
+C {lab_wire.sym} 0 -150 0 0 {name=l4 sig_type=std_logic lab=pswitch}
+C {lab_wire.sym} 0 190 0 0 {name=l3 sig_type=std_logic lab=nswitch}
+C {sky130_fd_pr/pfet_01v8.sym} 50 -150 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 50 190 0 0 {name=M2
+L=0.15
+W=0.75
+nf=1 
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -130 -130 3 0 {name=M3
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -50 -210 0 0 {name=M4
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -130 170 1 0 {name=M5
+L=0.15
+W=0.75
+nf=1 
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -50 260 0 0 {name=M6
+L=0.15
+W=0.75
+nf=1 
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -80 -40 0 0 {name=M7
+L=2
+W=4.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} -40 70 2 0 {name=l8 lab=vss}
+C {lab_pin.sym} -40 -40 2 0 {name=l1 lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} -80 70 0 0 {name=M8
+L=1.5
+W=0.75
+nf=1 
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -40 140 2 0 {name=p8 lab=nswitch}
+C {iopin.sym} -40 -100 2 0 {name=p11 lab=pswitch}
+C {sky130_fd_pr/nfet_01v8.sym} -670 190 0 1 {name=M9
+L=0.15
+W=0.75
+nf=1 
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -460 190 0 0 {name=M10
+L=0.15
+W=0.75
+nf=1 
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -420 -150 0 1 {name=M11
+L=0.15
+W=1.5
+nf=1
+mult=25
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} -690 80 1 0 {name=p9 lab=iref}
+C {lab_pin.sym} -210 190 0 0 {name=l10 lab=iref}
+C {lab_wire.sym} -260 -150 0 0 {name=l2 sig_type=std_logic lab=biasp}
+C {iopin.sym} -340 -60 1 0 {name=p10 lab=biasp}

diff --git a/xschem/charge_pump.sym b/xschem/charge_pump.sym
new file mode 100644
index 0000000..177239c
--- /dev/null
+++ b/xschem/charge_pump.sym

@@ -0,0 +1,65 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -40 -60 40 {}
+L 4 70 -40 70 40 {}
+L 4 -80 -60 -60 -60 {}
+L 4 -80 -20 -60 -20 {}
+L 4 70 0 90 0 {}
+L 4 -80 20 -60 20 {}
+L 4 -80 60 -60 60 {}
+L 4 -60 -70 -60 -50 {}
+L 4 -60 50 -60 70 {}
+L 4 -60 60 -60 70 {}
+L 4 70 40 70 70 {}
+L 4 70 -60 70 -40 {}
+L 4 -60 -50 -60 -40 {}
+L 4 -60 40 -60 50 {}
+L 4 -60 -80 -60 -70 {}
+L 4 -60 -80 40 -80 {}
+L 4 70 -80 70 -60 {}
+L 4 -60 70 -60 80 {}
+L 4 -60 80 40 80 {}
+L 4 70 70 70 80 {}
+L 4 40 -80 70 -80 {}
+L 4 40 80 70 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 50 60 {}
+L 4 50 60 50 80 {}
+L 4 -40 -100 -40 -80 {}
+L 7 20 -100 20 -80 {}
+L 7 50 -100 50 -80 {}
+L 7 -30 80 -30 100 {}
+L 7 0 80 0 100 {}
+L 7 30 80 30 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vdd dir=inout }
+B 5 -82.5 -62.5 -77.5 -57.5 {name=Up dir=in }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=nUp dir=in }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -82.5 17.5 -77.5 22.5 {name=Down dir=in }
+B 5 -82.5 57.5 -77.5 62.5 {name=nDown dir=in }
+B 5 47.5 -102.5 52.5 -97.5 {name=vss dir=inout }
+B 5 -42.5 -102.5 -37.5 -97.5 {name=iref dir=in }
+B 5 -32.5 97.5 -27.5 102.5 {name=nswitch dir=inout }
+B 5 -2.5 97.5 2.5 102.5 {name=pswitch dir=inout }
+B 5 27.5 97.5 32.5 102.5 {name=biasp dir=inout }
+T {@symname} 80 84 0 0 0.3 0.3 {}
+T {@name} -35 -12 0 0 0.2 0.2 {}
+T {vdd} 6 -105 3 1 0.2 0.2 {}
+T {Up} -55 -74 0 0 0.2 0.2 {}
+T {nUp} -55 -34 0 0 0.2 0.2 {}
+T {out} 65 -14 0 1 0.2 0.2 {}
+T {Down} -55 6 0 0 0.2 0.2 {}
+T {nDown} -55 46 0 0 0.2 0.2 {}
+T {vss} 44 -85 1 1 0.2 0.2 {}
+T {iref} -54 -105 3 1 0.2 0.2 {}
+T {nswitch} -16 125 1 1 0.2 0.2 {}
+T {pswitch} 14 125 1 1 0.2 0.2 {}
+T {Debug} -15 66 0 0 0.2 0.2 {}
+T {biasp} 44 115 1 1 0.2 0.2 {}

diff --git a/xschem/charge_pump_pex_c.sym b/xschem/charge_pump_pex_c.sym
new file mode 100644
index 0000000..0030ebb
--- /dev/null
+++ b/xschem/charge_pump_pex_c.sym

@@ -0,0 +1,65 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -60 -40 -60 40 {}
+L 4 70 -40 70 40 {}
+L 4 -80 -60 -60 -60 {}
+L 4 -80 -20 -60 -20 {}
+L 4 70 0 90 0 {}
+L 4 -80 20 -60 20 {}
+L 4 -80 60 -60 60 {}
+L 4 -60 -70 -60 -50 {}
+L 4 -60 50 -60 70 {}
+L 4 -60 60 -60 70 {}
+L 4 70 40 70 70 {}
+L 4 70 -60 70 -40 {}
+L 4 -60 -50 -60 -40 {}
+L 4 -60 40 -60 50 {}
+L 4 -60 -80 -60 -70 {}
+L 4 -60 -80 40 -80 {}
+L 4 70 -80 70 -60 {}
+L 4 -60 70 -60 80 {}
+L 4 -60 80 40 80 {}
+L 4 70 70 70 80 {}
+L 4 40 -80 70 -80 {}
+L 4 40 80 70 80 {}
+L 4 -40 60 -40 80 {}
+L 4 -40 60 50 60 {}
+L 4 50 60 50 80 {}
+L 4 -40 -100 -40 -80 {}
+L 7 20 -100 20 -80 {}
+L 7 50 -100 50 -80 {}
+L 7 -30 80 -30 100 {}
+L 7 0 80 0 100 {}
+L 7 30 80 30 100 {}
+B 5 17.5 -102.5 22.5 -97.5 {name=vdd dir=inout }
+B 5 -82.5 -62.5 -77.5 -57.5 {name=Up dir=in }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=nUp dir=in }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -82.5 17.5 -77.5 22.5 {name=Down dir=in }
+B 5 -82.5 57.5 -77.5 62.5 {name=nDown dir=in }
+B 5 47.5 -102.5 52.5 -97.5 {name=vss dir=inout }
+B 5 -42.5 -102.5 -37.5 -97.5 {name=iref dir=in }
+B 5 -32.5 97.5 -27.5 102.5 {name=nswitch dir=inout }
+B 5 -2.5 97.5 2.5 102.5 {name=pswitch dir=inout }
+B 5 27.5 97.5 32.5 102.5 {name=biasp dir=inout }
+T {@symname} 80 84 0 0 0.3 0.3 {}
+T {@name} -35 -12 0 0 0.2 0.2 {}
+T {vdd} 6 -105 3 1 0.2 0.2 {}
+T {Up} -55 -74 0 0 0.2 0.2 {}
+T {nUp} -55 -34 0 0 0.2 0.2 {}
+T {out} 65 -14 0 1 0.2 0.2 {}
+T {Down} -55 6 0 0 0.2 0.2 {}
+T {nDown} -55 46 0 0 0.2 0.2 {}
+T {vss} 44 -85 1 1 0.2 0.2 {}
+T {iref} -54 -105 3 1 0.2 0.2 {}
+T {nswitch} -16 125 1 1 0.2 0.2 {}
+T {pswitch} 14 125 1 1 0.2 0.2 {}
+T {Debug} -15 66 0 0 0.2 0.2 {}
+T {biasp} 44 115 1 1 0.2 0.2 {}

diff --git a/xschem/clock_inverter.sch b/xschem/clock_inverter.sch
new file mode 100644
index 0000000..7d62fc3
--- /dev/null
+++ b/xschem/clock_inverter.sch

@@ -0,0 +1,41 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -430 0 -400 0 { lab=CLK}
+N -280 -200 -280 -170 { lab=vdd}
+N -280 -70 -280 -40 { lab=vss}
+N -280 180 -280 210 { lab=vss}
+N -280 50 -280 80 { lab=vdd}
+N -360 -120 -320 -120 { lab=CLK}
+N -400 0 -360 0 { lab=CLK}
+N -70 -200 -70 -170 { lab=vdd}
+N -70 -70 -70 -40 { lab=vss}
+N -360 130 -320 130 { lab=CLK}
+N -360 10 -360 130 { lab=CLK}
+N -360 -110 -360 10 { lab=CLK}
+N -360 -120 -360 -110 { lab=CLK}
+N -40 20 -40 50 { lab=vdd}
+N -40 230 -40 260 { lab=vss}
+N -190 130 -130 130 { lab=#net1}
+N 50 -120 140 -120 { lab=CLK_d}
+N 50 130 140 130 { lab=nCLK_d}
+N 20 -120 50 -120 { lab=CLK_d}
+N -190 -120 -110 -120 { lab=#net2}
+C {ipin.sym} -430 0 0 0 {name=p4 lab=CLK}
+C {iopin.sym} -280 -200 3 0 {name=p1 lab=vdd}
+C {lab_pin.sym} -280 -40 3 0 {name=l5 lab=vss}
+C {trans_gate.sym} -40 130 0 0 {name=x5}
+C {iopin.sym} -280 210 1 0 {name=p11 lab=vss}
+C {lab_pin.sym} -280 50 1 0 {name=l12 lab=vdd}
+C {lab_pin.sym} -70 -200 1 0 {name=l9 lab=vdd}
+C {lab_pin.sym} -70 -40 3 0 {name=l10 lab=vss}
+C {lab_pin.sym} -40 20 1 0 {name=l13 lab=vdd}
+C {lab_pin.sym} -40 260 3 0 {name=l14 lab=vss}
+C {opin.sym} 140 130 0 0 {name=p16 lab=nCLK_d}
+C {opin.sym} 140 -120 0 0 {name=p17 lab=CLK_d}
+C {inverter_cp_x1.sym} -50 -120 0 0 {name=x1}
+C {inverter_cp_x1.sym} -260 -120 0 0 {name=x2}
+C {inverter_cp_x1.sym} -260 130 0 0 {name=x3}

diff --git a/xschem/clock_inverter.sym b/xschem/clock_inverter.sym
new file mode 100644
index 0000000..971d7ed
--- /dev/null
+++ b/xschem/clock_inverter.sym

@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 40 -20 60 -20 {}
+L 4 -60 0 -40 0 {}
+L 4 40 20 60 20 {}
+L 4 -40 -40 40 -40 {}
+L 4 -40 40 40 40 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout }
+B 5 57.5 -22.5 62.5 -17.5 {name=CLK_d dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in }
+B 5 57.5 17.5 62.5 22.5 {name=nCLK_d dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=vss dir=inout }
+T {@symname} 9 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {vdd} -14 -65 3 1 0.2 0.2 {}
+T {CLK_d} 35 -24 0 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {nCLK_d} 35 16 0 1 0.2 0.2 {}
+T {vss} -6 65 1 1 0.2 0.2 {}

diff --git a/xschem/csvco.sch b/xschem/csvco.sch
new file mode 100644
index 0000000..5f70a27
--- /dev/null
+++ b/xschem/csvco.sch

@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -150 -210 -120 { lab=vdd}
+N -320 10 -280 10 { lab=vctrl}
+N -510 10 -470 10 { lab=vss}
+N -470 40 -470 80 { lab=vss}
+N -430 10 -390 10 { lab=vctrl}
+N -470 -130 -470 -100 { lab=vdd}
+N -500 -70 -470 -70 { lab=vdd}
+N -210 60 -210 100 { lab=vss}
+N -170 60 -170 70 { lab=D0}
+N -430 -70 -280 -70 { lab=vbp}
+N -470 -30 -420 -30 { lab=vbp}
+N -420 -30 -410 -30 { lab=vbp}
+N -410 -70 -410 -30 { lab=vbp}
+N -470 -30 -470 -20 { lab=vbp}
+N -470 -40 -470 -30 { lab=vbp}
+N -390 10 -320 10 { lab=vctrl}
+N -350 10 -350 70 { lab=vctrl}
+N -340 -30 -280 -30 { lab=out}
+N -140 -30 -70 -30 { lab=out1}
+N -70 -30 30 -30 { lab=out1}
+N -10 -70 30 -70 { lab=vbp}
+N -10 10 30 10 { lab=vctrl}
+N 100 -150 100 -120 { lab=vdd}
+N 100 60 100 100 { lab=vss}
+N 140 60 140 70 { lab=D0}
+N 170 -30 240 -30 { lab=out2}
+N 240 -30 340 -30 { lab=out2}
+N 300 -70 340 -70 { lab=vbp}
+N 300 10 340 10 { lab=vctrl}
+N 410 -150 410 -120 { lab=vdd}
+N 410 60 410 100 { lab=vss}
+N 450 60 450 70 { lab=D0}
+N 480 -30 540 -30 { lab=out}
+C {lab_pin.sym} -210 -150 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {ipin.sym} -350 70 3 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} -510 10 2 1 {name=l83 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} -450 10 0 1 {name=M1
+L=0.15
+W=1.5
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 80 3 1 {name=p84 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} -450 -70 0 1 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 -130 1 1 {name=p86 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -500 -70 2 1 {name=l87 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -350 -70 0 1 {name=l88 sig_type=std_logic lab=vbp}
+C {opin.sym} 540 -30 2 1 {name=p1 sig_type=std_logic lab=out}
+C {lab_pin.sym} -210 100 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {ipin.sym} -170 70 3 0 {name=p6 sig_type=std_logic lab=D0}
+C {lab_wire.sym} -340 -30 0 1 {name=l8 sig_type=std_logic lab=out}
+C {lab_wire.sym} -70 -30 0 1 {name=l12 sig_type=std_logic lab=out1}
+C {lab_pin.sym} -10 -70 0 0 {name=l32 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} -10 10 0 0 {name=l33 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 100 -150 1 0 {name=l34 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 100 100 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 70 3 0 {name=l46 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 300 -70 0 0 {name=l36 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} 300 10 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 410 -150 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 100 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 70 3 0 {name=l47 sig_type=std_logic lab=D0}
+C {lab_wire.sym} 240 -30 0 1 {name=l48 sig_type=std_logic lab=out2}
+C {csvco_branch.sym} -210 -30 0 0 {name=x1}
+C {csvco_branch.sym} 100 -30 0 0 {name=x2}
+C {csvco_branch.sym} 410 -30 0 0 {name=x3}

diff --git a/xschem/csvco.sym b/xschem/csvco.sym
new file mode 100644
index 0000000..52a2546
--- /dev/null
+++ b/xschem/csvco.sym

@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {D0} -66.5 27.5 0 0 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}

diff --git a/xschem/csvco_branch.sch b/xschem/csvco_branch.sch
new file mode 100644
index 0000000..5c911f0
--- /dev/null
+++ b/xschem/csvco_branch.sch

@@ -0,0 +1,92 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 540 -300 540 -270 { lab=vdd_inv}
+N 540 -70 580 -70 { lab=vss}
+N 440 -220 500 -220 { lab=in}
+N 630 -220 700 -220 { lab=out}
+N 540 -350 540 -300 { lab=vdd_inv}
+N 540 -440 540 -410 { lab=vdd}
+N 540 -380 570 -380 { lab=vdd}
+N 540 -170 540 -100 { lab=vss_inv}
+N 540 -40 540 0 { lab=vss}
+N 460 -70 500 -70 { lab=vctrl}
+N 580 -190 580 -150 { lab=vss}
+N 580 -280 580 -250 { lab=vdd}
+N 700 -220 760 -220 { lab=out}
+N 900 -220 1440 -220 { lab=out}
+N 760 -220 900 -220 { lab=out}
+N 460 -380 500 -380 { lab=vbp}
+N 1440 -220 1490 -220 { lab=out}
+N 1070 -220 1070 -180 { lab=out}
+N 1000 -150 1030 -150 { lab=D0}
+N 1070 -150 1110 -150 { lab=vss}
+N 1070 -120 1070 -80 { lab=#net1}
+N 1070 -20 1070 20 { lab=vss}
+C {lab_pin.sym} 580 -70 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 520 -380 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 570 -380 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {ipin.sym} 460 -70 0 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 580 -150 3 0 {name=l127 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 580 -280 1 0 {name=l139 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 640 -220 0 1 {name=l106 sig_type=std_logic lab=out}
+C {ipin.sym} 460 -380 0 0 {name=p1 sig_type=std_logic lab=vbp}
+C {iopin.sym} 540 -440 3 0 {name=p6 sig_type=std_logic lab=vdd}
+C {iopin.sym} 540 0 1 0 {name=p7 sig_type=std_logic lab=vss}
+C {ipin.sym} 440 -220 0 0 {name=p8 sig_type=std_logic lab=in}
+C {opin.sym} 1490 -220 0 0 {name=p9 sig_type=std_logic lab=out}
+C {lab_wire.sym} 540 -340 3 0 {name=l1 sig_type=std_logic lab=vdd_inv}
+C {lab_wire.sym} 540 -160 3 0 {name=l4 sig_type=std_logic lab=vss_inv}
+C {sky130_fd_pr/nfet_01v8.sym} 520 -70 0 0 {name=M2
+L=0.15
+W=1.5
+nf=1 
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1050 -150 0 0 {name=M4
+L=0.15
+W=0.42
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 1000 -150 0 0 {name=p3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 1110 -150 2 0 {name=l8 sig_type=std_logic lab=vss}
+C {inverter_csvco.sym} 560 -220 0 0 {name=x1}
+C {capa.sym} 1070 -50 0 0 {name=C1
+m=1
+value=5.78f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1070 20 3 0 {name=l5 sig_type=std_logic lab=vss}

diff --git a/xschem/csvco_branch.sym b/xschem/csvco_branch.sym
new file mode 100644
index 0000000..0289106
--- /dev/null
+++ b/xschem/csvco_branch.sym

@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 -70 -50 70 {}
+L 4 -50 70 50 70 {}
+L 4 50 -70 50 70 {}
+L 4 -50 -70 50 -70 {}
+L 4 40 70 40 90 {}
+L 7 0 -90 0 -70 {}
+L 7 0 70 0 90 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=vbp sig_type=std_logic dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=in sig_type=std_logic dir=in }
+B 5 67.5 -2.5 72.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=vctrl sig_type=std_logic dir=in }
+B 5 -2.5 87.5 2.5 92.5 {name=vss sig_type=std_logic dir=inout }
+B 5 37.5 87.5 42.5 92.5 {name=D0 sig_type=std_logic dir=in }
+T {@symname} 58 54 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -4 -65 3 1 0.2 0.2 {}
+T {vbp} -45 -44 0 0 0.2 0.2 {}
+T {in} -45 -4 0 0 0.2 0.2 {}
+T {out} 45 -4 0 1 0.2 0.2 {}
+T {vctrl} -45 36 0 0 0.2 0.2 {}
+T {vss} 4 65 1 1 0.2 0.2 {}
+T {D0} 36 65 3 0 0.2 0.2 {}

diff --git a/xschem/csvco_pex_c.sym b/xschem/csvco_pex_c.sym
new file mode 100644
index 0000000..b24a424
--- /dev/null
+++ b/xschem/csvco_pex_c.sym

@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 0 -50 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
+T {D0} -73.5 26 0 0 0.2 0.2 {}

diff --git a/xschem/dff_pfd_pex_c.sym b/xschem/dff_pfd_pex_c.sym
new file mode 100644
index 0000000..f100e2b
--- /dev/null
+++ b/xschem/dff_pfd_pex_c.sym

@@ -0,0 +1,34 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -30 -30 -30 30 {}
+L 4 30 -30 30 30 {}
+L 4 -50 -30 -30 -30 {}
+L 4 -50 0 -30 0 {}
+L 4 30 -30 50 -30 {}
+L 4 0 40 0 60 {}
+L 4 -30 -40 -30 -30 {}
+L 4 -30 -40 30 -40 {}
+L 4 30 -40 30 -30 {}
+L 4 -30 30 -30 40 {}
+L 4 -30 40 30 40 {}
+L 4 30 30 30 40 {}
+L 7 0 -60 0 -40 {}
+B 5 -52.5 -32.5 -47.5 -27.5 {name=vdd dir=in }
+B 5 -52.5 -2.5 -47.5 2.5 {name=CLK dir=in }
+B 5 47.5 -32.5 52.5 -27.5 {name=Q dir=out }
+B 5 -2.5 57.5 2.5 62.5 {name=Reset dir=in }
+B 5 -2.5 -62.5 2.5 -57.5 {name=vss dir=inout }
+T {@symname} 8.5 44 0 0 0.3 0.3 {}
+T {@name} 15 -52 0 0 0.2 0.2 {}
+T {D} -25 -34 0 0 0.2 0.2 {}
+T {CLK} -25 -4 0 0 0.2 0.2 {}
+T {Q} 25 -34 0 1 0.2 0.2 {}
+T {Reset} -15 26 0 0 0.2 0.2 {}
+T {vss} -5 -54 0 1 0.2 0.2 {}

diff --git a/xschem/div_by_2.sch b/xschem/div_by_2.sch
new file mode 100644
index 0000000..db07f51
--- /dev/null
+++ b/xschem/div_by_2.sch

@@ -0,0 +1,71 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 130 20 160 20 { lab=CLK}
+N 560 -40 630 -40 { lab=out_div}
+N 1080 -120 1090 -120 { lab=CLK_2}
+N 160 20 200 20 { lab=CLK}
+N 380 0 420 0 { lab=CLK_d}
+N 380 40 420 40 { lab=nCLK_d}
+N 490 80 490 110 { lab=vss}
+N 490 -120 490 -80 { lab=vdd}
+N 560 40 600 40 { lab=nout_div}
+N 600 40 640 40 { lab=nout_div}
+N 320 40 380 40 { lab=nCLK_d}
+N 320 0 380 0 { lab=CLK_d}
+N 260 -80 260 -40 { lab=vdd}
+N 260 80 260 110 { lab=vss}
+N 380 -40 420 -40 { lab=nout_div}
+N 1030 -120 1080 -120 { lab=CLK_2}
+N 740 -210 740 -170 { lab=vdd}
+N 740 -70 740 -40 { lab=vss}
+N 740 40 740 80 { lab=vdd}
+N 740 180 740 210 { lab=vss}
+N 640 130 700 130 { lab=nout_div}
+N 640 40 640 130 { lab=nout_div}
+N 640 -120 700 -120 { lab=out_div}
+N 640 -120 640 -40 { lab=out_div}
+N 630 -40 640 -40 { lab=out_div}
+N 830 -120 900 -120 { lab=o1}
+N 1080 130 1090 130 { lab=nCLK_2}
+N 1030 130 1080 130 { lab=nCLK_2}
+N 830 130 900 130 { lab=o2}
+N 940 -210 940 -170 { lab=vdd}
+N 940 -70 940 -40 { lab=vss}
+N 940 40 940 80 { lab=vdd}
+N 940 180 940 210 { lab=vss}
+N 670 130 670 200 { lab=nout_div}
+N 870 130 870 200 { lab=o2}
+N 860 -190 860 -120 { lab=o1}
+N 670 -190 670 -120 { lab=out_div}
+C {ipin.sym} 130 20 0 0 {name=p4 lab=CLK}
+C {opin.sym} 1090 -120 0 0 {name=p7 lab=CLK_2}
+C {lab_wire.sym} 380 0 0 0 {name=l20 lab=CLK_d}
+C {lab_wire.sym} 380 40 0 0 {name=l21 lab=nCLK_d}
+C {iopin.sym} 490 110 1 0 {name=p2 lab=vss}
+C {iopin.sym} 490 -120 3 0 {name=p5 lab=vdd}
+C {opin.sym} 1090 130 0 0 {name=p1 lab=nCLK_2}
+C {lab_pin.sym} 260 -80 1 0 {name=l3 lab=vdd}
+C {lab_pin.sym} 260 110 3 0 {name=l6 lab=vss}
+C {lab_pin.sym} 380 -40 0 0 {name=l1 lab=nout_div}
+C {DFlipFlop.sym} 490 0 0 0 {name=x1}
+C {clock_inverter.sym} 260 20 0 0 {name=x2}
+C {inverter_min_x2.sym} 760 -120 0 0 {name=x3}
+C {inverter_min_x4.sym} 960 -120 0 0 {name=x4}
+C {lab_pin.sym} 740 -210 1 0 {name=l2 lab=vdd}
+C {lab_pin.sym} 740 -40 3 0 {name=l4 lab=vss}
+C {lab_pin.sym} 740 40 1 0 {name=l5 lab=vdd}
+C {lab_pin.sym} 740 210 3 0 {name=l7 lab=vss}
+C {lab_pin.sym} 940 -210 1 0 {name=l8 lab=vdd}
+C {lab_pin.sym} 940 -40 3 0 {name=l9 lab=vss}
+C {lab_pin.sym} 940 40 1 0 {name=l10 lab=vdd}
+C {lab_pin.sym} 940 210 3 0 {name=l11 lab=vss}
+C {iopin.sym} 670 200 1 0 {name=p3 lab=nout_div}
+C {iopin.sym} 870 200 1 0 {name=p6 lab=o2}
+C {iopin.sym} 860 -190 3 0 {name=p8 lab=o1}
+C {iopin.sym} 670 -190 3 0 {name=p9 lab=out_div}
+C {inverter_min_x2.sym} 760 130 0 0 {name=x5}
+C {inverter_min_x4.sym} 960 130 0 0 {name=x6}

diff --git a/xschem/div_by_2.sym b/xschem/div_by_2.sym
new file mode 100644
index 0000000..e00042c
--- /dev/null
+++ b/xschem/div_by_2.sym

@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 20 70 20 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -40 -50 0 {}
+L 4 -40 -60 40 -60 {}
+L 4 50 -40 50 20 {}
+L 4 50 20 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -0 -50 40 {}
+L 4 -50 -10 -40 0 {}
+L 4 -50 10 -40 0 {}
+L 4 50 -20 70 -20 {}
+L 4 50 -40 50 -20 {}
+L 4 50 -20 50 40 {}
+L 4 40 -60 50 -60 {}
+L 4 50 -60 50 -40 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 -50 -60 -40 -60 {}
+L 4 -40 40 -40 60 {}
+L 4 -40 40 40 40 {}
+L 4 40 40 40 60 {}
+L 7 20 -80 20 -60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 -30 60 -30 80 {}
+L 7 -10 60 -10 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 67.5 17.5 72.5 22.5 {name=nCLK_2 dir=out }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -22.5 72.5 -17.5 {name=CLK_2 dir=out }
+B 5 -32.5 77.5 -27.5 82.5 {name=out_div dir=inout }
+B 5 -12.5 77.5 -7.5 82.5 {name=nout_div dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=o1 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=o2 dir=inout }
+T {@symname} 46 64 0 0 0.3 0.3 {}
+T {@name} -15 -42 0 0 0.2 0.2 {}
+T {nCLK_2} 45 6 0 1 0.2 0.2 {}
+T {vss} 25 -86 3 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {vdd} -24 -65 1 1 0.2 0.2 {}
+T {CLK_2} 45 -24 0 1 0.2 0.2 {}
+T {Debug} 15 46 0 1 0.2 0.2 {}
+T {out_div} -35 106 1 1 0.2 0.2 {}
+T {nout_div} -15 106 1 1 0.2 0.2 {}
+T {o1} 5 86 1 1 0.2 0.2 {}
+T {o2} 25 86 1 1 0.2 0.2 {}

diff --git a/xschem/div_by_2_pex_c.sym b/xschem/div_by_2_pex_c.sym
new file mode 100644
index 0000000..ebe7cd4
--- /dev/null
+++ b/xschem/div_by_2_pex_c.sym

@@ -0,0 +1,58 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 20 70 20 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 -40 -50 0 {}
+L 4 -40 -60 40 -60 {}
+L 4 50 -40 50 20 {}
+L 4 50 20 50 40 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -0 -50 40 {}
+L 4 -50 -10 -40 0 {}
+L 4 -50 10 -40 0 {}
+L 4 50 -20 70 -20 {}
+L 4 50 -40 50 -20 {}
+L 4 50 -20 50 40 {}
+L 4 40 -60 50 -60 {}
+L 4 50 -60 50 -40 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 -50 60 {}
+L 4 -50 -60 -50 -40 {}
+L 4 -50 -60 -40 -60 {}
+L 4 -40 40 -40 60 {}
+L 4 -40 40 40 40 {}
+L 4 40 40 40 60 {}
+L 7 20 -80 20 -60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 -30 60 -30 80 {}
+L 7 -10 60 -10 80 {}
+L 7 10 60 10 80 {}
+L 7 30 60 30 80 {}
+B 5 67.5 17.5 72.5 22.5 {name=nCLK_2 dir=out }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 -22.5 72.5 -17.5 {name=CLK_2 dir=out }
+B 5 -32.5 77.5 -27.5 82.5 {name=out_div dir=inout }
+B 5 -12.5 77.5 -7.5 82.5 {name=nout_div dir=inout }
+B 5 7.5 77.5 12.5 82.5 {name=o1 dir=inout }
+B 5 27.5 77.5 32.5 82.5 {name=o2 dir=inout }
+T {@symname} 46 64 0 0 0.3 0.3 {}
+T {@name} -15 -42 0 0 0.2 0.2 {}
+T {nCLK_2} 45 6 0 1 0.2 0.2 {}
+T {vss} 25 -86 3 1 0.2 0.2 {}
+T {CLK} -35 -4 0 0 0.2 0.2 {}
+T {vdd} -24 -65 1 1 0.2 0.2 {}
+T {CLK_2} 45 -24 0 1 0.2 0.2 {}
+T {Debug} 15 46 0 1 0.2 0.2 {}
+T {out_div} -35 106 1 1 0.2 0.2 {}
+T {nout_div} -15 106 1 1 0.2 0.2 {}
+T {o1} 5 86 1 1 0.2 0.2 {}
+T {o2} 25 86 1 1 0.2 0.2 {}

diff --git a/xschem/div_by_5.sch b/xschem/div_by_5.sch
new file mode 100644
index 0000000..b4f028e
--- /dev/null
+++ b/xschem/div_by_5.sch

@@ -0,0 +1,97 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 -660 0 -620 { lab=vdd}
+N 0 -460 0 -430 { lab=vss}
+N -120 -540 -70 -540 { lab=CLK}
+N -120 -500 -70 -500 { lab=nCLK}
+N 390 -660 390 -620 { lab=vdd}
+N 390 -460 390 -430 { lab=vss}
+N 270 -540 320 -540 { lab=CLK}
+N 270 -500 320 -500 { lab=nCLK}
+N 800 -660 800 -620 { lab=vdd}
+N 800 -460 800 -430 { lab=vss}
+N 680 -540 730 -540 { lab=CLK}
+N 680 -500 730 -500 { lab=nCLK}
+N 870 -580 920 -580 { lab=Q0}
+N 70 -500 100 -500 { lab=nQ2}
+N 870 -500 920 -500 { lab=nQ0}
+N -100 -640 -100 -580 { lab=D2}
+N -100 -580 -70 -580 { lab=D2}
+N 70 -580 100 -580 { lab=Q2}
+N 460 -500 490 -500 { lab=nQ1}
+N 460 -580 490 -580 { lab=Q1}
+N 700 -580 730 -580 { lab=D0}
+N 290 -580 320 -580 { lab=D1}
+N -120 -810 -120 -760 { lab=Q0}
+N -80 -810 -80 -760 { lab=Q1}
+N 270 -630 270 -580 { lab=D1}
+N 270 -580 290 -580 { lab=D1}
+N 290 -800 290 -750 { lab=Q1}
+N 250 -800 250 -750 { lab=Q0}
+N 680 -640 680 -580 { lab=D0}
+N 680 -580 700 -580 { lab=D0}
+N 700 -810 700 -760 { lab=nQ2}
+N 660 -810 660 -760 { lab=nQ0}
+N 1190 -460 1190 -430 { lab=vss}
+N 1190 -660 1190 -620 { lab=vdd}
+N 1070 -500 1120 -500 { lab=CLK}
+N 1070 -540 1120 -540 { lab=nCLK}
+N 1090 -580 1120 -580 { lab=Q1}
+N 1260 -580 1370 -580 { lab=Q1_shift}
+N 1340 -620 1370 -620 { lab=Q1}
+N 1490 -600 1550 -600 { lab=CLK_5}
+N 1260 -500 1320 -500 { lab=nQ1_shift}
+N 1330 -550 1370 -550 { lab=Q1_shift}
+N 1330 -580 1330 -550 { lab=Q1_shift}
+C {iopin.sym} 0 -660 3 0 {name=p5 lab=vdd}
+C {iopin.sym} 0 -430 1 0 {name=p6 lab=vss}
+C {ipin.sym} -120 -540 0 0 {name=p8 lab=CLK}
+C {lab_pin.sym} 270 -540 0 0 {name=l9 lab=CLK}
+C {lab_pin.sym} 270 -500 0 0 {name=l10 lab=nCLK}
+C {lab_pin.sym} 680 -540 0 0 {name=l11 lab=CLK}
+C {lab_pin.sym} 680 -500 0 0 {name=l12 lab=nCLK}
+C {opin.sym} 1550 -600 0 0 {name=p15 lab=CLK_5}
+C {lab_pin.sym} 390 -660 1 0 {name=l29 lab=vdd}
+C {lab_pin.sym} 800 -660 1 0 {name=l30 lab=vdd}
+C {lab_pin.sym} 390 -430 3 0 {name=l31 lab=vss}
+C {lab_pin.sym} 800 -430 3 0 {name=l32 lab=vss}
+C {lab_pin.sym} -120 -810 1 0 {name=l13 lab=Q0}
+C {lab_wire.sym} 100 -580 0 0 {name=l15 lab=Q2}
+C {lab_pin.sym} -100 -580 0 0 {name=l16 lab=D2}
+C {lab_wire.sym} 490 -500 0 0 {name=l14 lab=nQ1}
+C {sky130_stdcells/and2_1.sym} -100 -700 1 0 {name=x8 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} -80 -810 1 0 {name=l17 lab=Q1}
+C {sky130_stdcells/xor2_1.sym} 270 -690 1 0 {name=x9 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 270 -580 0 0 {name=l19 lab=D1}
+C {lab_pin.sym} 290 -800 1 0 {name=l22 lab=Q1}
+C {lab_pin.sym} 250 -800 1 0 {name=l27 lab=Q0}
+C {sky130_stdcells/and2_1.sym} 680 -700 1 0 {name=x10 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 680 -580 0 0 {name=l33 lab=D0}
+C {lab_pin.sym} 700 -810 1 0 {name=l34 lab=nQ2}
+C {lab_pin.sym} 660 -810 1 0 {name=l35 lab=nQ0}
+C {lab_pin.sym} 1190 -430 3 0 {name=l36 lab=vss}
+C {lab_pin.sym} 1190 -660 1 0 {name=l37 lab=vdd}
+C {lab_pin.sym} 1070 -500 2 1 {name=l38 lab=CLK}
+C {lab_pin.sym} 1070 -540 2 1 {name=l39 lab=nCLK}
+C {lab_pin.sym} 1090 -580 0 0 {name=l40 lab=Q1}
+C {sky130_stdcells/or2_1.sym} 1430 -600 0 0 {name=x12 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hs__ }
+C {lab_pin.sym} 1340 -620 0 0 {name=l41 lab=Q1}
+C {lab_wire.sym} 1330 -580 0 0 {name=l44 lab=Q1_shift}
+C {ipin.sym} -120 -500 0 0 {name=p1 lab=nCLK}
+C {lab_wire.sym} 1320 -500 0 0 {name=l1 lab=nQ1_shift}
+C {DFlipFlop.sym} 0 -540 0 0 {name=x1}
+C {DFlipFlop.sym} 390 -540 0 0 {name=x2}
+C {DFlipFlop.sym} 800 -540 0 0 {name=x3}
+C {DFlipFlop.sym} 1190 -540 0 0 {name=x4}
+C {noconn.sym} 490 -500 2 0 {name=l2}
+C {noconn.sym} 1320 -500 2 0 {name=l3}
+C {noconn.sym} 100 -580 2 0 {name=l4}
+C {iopin.sym} 100 -500 0 0 {name=p2 lab=nQ2}
+C {iopin.sym} 490 -580 0 0 {name=p3 lab=Q1}
+C {iopin.sym} 920 -580 0 0 {name=p4 lab=Q0}
+C {iopin.sym} 920 -500 0 0 {name=p7 lab=nQ0}
+C {iopin.sym} 1370 -550 0 0 {name=p9 lab=Q1_shift}

diff --git a/xschem/div_by_5.sym b/xschem/div_by_5.sym
new file mode 100644
index 0000000..c0eb1b7
--- /dev/null
+++ b/xschem/div_by_5.sym

@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 60 0 80 0 {}
+L 4 -80 -20 -60 -20 {}
+L 4 -60 -40 -60 -20 {}
+L 4 -50 -60 50 -60 {}
+L 4 60 -40 60 40 {}
+L 4 -50 60 50 60 {}
+L 4 -60 -20 -60 40 {}
+L 4 -60 -30 -50 -20 {}
+L 4 -60 -10 -50 -20 {}
+L 4 -80 20 -60 20 {}
+L 4 -60 -40 -60 20 {}
+L 4 -60 20 -60 40 {}
+L 4 -60 10 -50 20 {}
+L 4 -60 30 -50 20 {}
+L 4 60 40 60 60 {}
+L 4 -60 40 -60 60 {}
+L 4 -60 -60 -60 -40 {}
+L 4 60 -60 60 -40 {}
+L 4 50 60 60 60 {}
+L 4 -60 60 -50 60 {}
+L 4 -60 -60 -50 -60 {}
+L 4 50 -60 60 -60 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 50 40 {}
+L 4 -50 40 -50 60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 20 -80 20 -60 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+L 7 20 60 20 80 {}
+L 7 40 60 40 80 {}
+L 7 0 60 0 80 {}
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=CLK_5 dir=out }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=CLK dir=in }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=nCLK dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=nQ2 dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=Q1 dir=inout }
+B 5 17.5 77.5 22.5 82.5 {name=nQ0 dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=Q0 dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=Q1_shift dir=inout }
+T {@symname} 66 64 0 0 0.3 0.3 {}
+T {@name} -5 -32 0 0 0.2 0.2 {}
+T {vdd} -34 -85 3 1 0.2 0.2 {}
+T {CLK_5} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -45 -24 0 0 0.2 0.2 {}
+T {vss} 14 -65 1 1 0.2 0.2 {}
+T {nCLK} -45 16 0 0 0.2 0.2 {}
+T {nQ2} -26 85 1 1 0.2 0.2 {}
+T {Q1} -6 85 1 1 0.2 0.2 {}
+T {nQ0} 34 85 1 1 0.2 0.2 {}
+T {Q0} 54 85 1 1 0.2 0.2 {}
+T {Q1_shift} 14 105 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}

diff --git a/xschem/div_by_5_pex_c.sym b/xschem/div_by_5_pex_c.sym
new file mode 100644
index 0000000..b637808
--- /dev/null
+++ b/xschem/div_by_5_pex_c.sym

@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 60 0 80 0 {}
+L 4 -80 -20 -60 -20 {}
+L 4 -60 -40 -60 -20 {}
+L 4 -50 -60 50 -60 {}
+L 4 60 -40 60 40 {}
+L 4 -50 60 50 60 {}
+L 4 -60 -20 -60 40 {}
+L 4 -60 -30 -50 -20 {}
+L 4 -60 -10 -50 -20 {}
+L 4 -80 20 -60 20 {}
+L 4 -60 -40 -60 20 {}
+L 4 -60 20 -60 40 {}
+L 4 -60 10 -50 20 {}
+L 4 -60 30 -50 20 {}
+L 4 60 40 60 60 {}
+L 4 -60 40 -60 60 {}
+L 4 -60 -60 -60 -40 {}
+L 4 60 -60 60 -40 {}
+L 4 50 60 60 60 {}
+L 4 -60 60 -50 60 {}
+L 4 -60 -60 -50 -60 {}
+L 4 50 -60 60 -60 {}
+L 4 50 40 50 60 {}
+L 4 -50 40 50 40 {}
+L 4 -50 40 -50 60 {}
+L 7 -20 -80 -20 -60 {}
+L 7 20 -80 20 -60 {}
+L 7 -40 60 -40 80 {}
+L 7 -20 60 -20 80 {}
+L 7 20 60 20 80 {}
+L 7 40 60 40 80 {}
+L 7 0 60 0 80 {}
+B 5 -22.5 -82.5 -17.5 -77.5 {name=vdd dir=inout }
+B 5 77.5 -2.5 82.5 2.5 {name=CLK_5 dir=out }
+B 5 -82.5 -22.5 -77.5 -17.5 {name=CLK dir=in }
+B 5 17.5 -82.5 22.5 -77.5 {name=vss dir=inout }
+B 5 -82.5 17.5 -77.5 22.5 {name=nCLK dir=in }
+B 5 -42.5 77.5 -37.5 82.5 {name=nQ2 dir=inout }
+B 5 -22.5 77.5 -17.5 82.5 {name=Q1 dir=inout }
+B 5 17.5 77.5 22.5 82.5 {name=nQ0 dir=inout }
+B 5 37.5 77.5 42.5 82.5 {name=Q0 dir=inout }
+B 5 -2.5 77.5 2.5 82.5 {name=Q1_shift dir=inout }
+T {@symname} 66 64 0 0 0.3 0.3 {}
+T {@name} -5 -32 0 0 0.2 0.2 {}
+T {vdd} -34 -85 3 1 0.2 0.2 {}
+T {CLK_5} 45 -4 0 1 0.2 0.2 {}
+T {CLK} -45 -24 0 0 0.2 0.2 {}
+T {vss} 14 -65 1 1 0.2 0.2 {}
+T {nCLK} -45 16 0 0 0.2 0.2 {}
+T {nQ2} -26 85 1 1 0.2 0.2 {}
+T {Q1} -6 85 1 1 0.2 0.2 {}
+T {nQ0} 34 85 1 1 0.2 0.2 {}
+T {Q0} 54 85 1 1 0.2 0.2 {}
+T {Q1_shift} 14 105 1 1 0.2 0.2 {}
+T {Debug} -15 46 0 0 0.2 0.2 {}

diff --git a/xschem/example_por.sch b/xschem/example_por.sch
index cf6e0c3..b09dbeb 100644
--- a/xschem/example_por.sch
+++ b/xschem/example_por.sch

@@ -289,9 +289,9 @@
 C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
 C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
 C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt }
-C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
-C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
-C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
-C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
+C {iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
+C {iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
+C {opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
+C {opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
+C {opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
+C {iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}

diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
index 664018f..0e88178 100644
--- a/xschem/example_por_tb.sch
+++ b/xschem/example_por_tb.sch

@@ -28,18 +28,18 @@
 N -330 60 -280 60 {}
 N -330 -110 -210 -110 {}
 C {example_por.sym} -10 -20 0 0 {name=x1}
-C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
-C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
-C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
-C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
-C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
-C {devices/code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
+C {gnd.sym} -100 60 0 0 {name=l1 lab=GND}
+C {vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
+C {vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
+C {opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
+C {opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
+C {opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
+C {opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
+C {opin.sym} 180 10 0 0 {name=p5 lab=por_l}
+C {code_shown.sym} -470 140 0 0 {name=s1 only_toplevel=false value=".param mc_mm_switch=0
 .lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
 .include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
-C {devices/code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
+C {code_shown.sym} -470 250 0 0 {name=s2 only_toplevel=false value=".control
 tran 1u 20m
 plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
 .endc"}

diff --git a/xschem/inverter_cp_x1.sch b/xschem/inverter_cp_x1.sch
new file mode 100644
index 0000000..c9fe522
--- /dev/null
+++ b/xschem/inverter_cp_x1.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=1.25
+nf=1 
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}

diff --git a/xschem/inverter_cp_x1.sym b/xschem/inverter_cp_x1.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_cp_x1.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_cp_x2.sch b/xschem/inverter_cp_x2.sch
new file mode 100644
index 0000000..734bbdd
--- /dev/null
+++ b/xschem/inverter_cp_x2.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=1.25
+nf=1 
+mult=6
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}

diff --git a/xschem/inverter_cp_x2.sym b/xschem/inverter_cp_x2.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_cp_x2.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_csvco.sch b/xschem/inverter_csvco.sch
new file mode 100644
index 0000000..5d55284
--- /dev/null
+++ b/xschem/inverter_csvco.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vbulkp}
+N 250 90 350 90 { lab=vbulkn}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.2
+W=0.75
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.2
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 350 90 0 0 {name=p5 lab=vbulkn}
+C {iopin.sym} 350 -90 0 0 {name=p6 lab=vbulkp}

diff --git a/xschem/inverter_csvco.sym b/xschem/inverter_csvco.sym
new file mode 100644
index 0000000..611d998
--- /dev/null
+++ b/xschem/inverter_csvco.sym

@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+L 7 20 -30 20 -10 {}
+L 7 20 10 20 30 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+B 5 17.5 -32.5 22.5 -27.5 {name=vbulkp dir=inout }
+B 5 17.5 27.5 22.5 32.5 {name=vbulkn dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 34 10 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
+T {vbulkp} 6 -55 3 1 0.2 0.2 {}
+T {vbulkn} 14 55 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_csvco_pex_c.sym b/xschem/inverter_csvco_pex_c.sym
new file mode 100644
index 0000000..0fbd461
--- /dev/null
+++ b/xschem/inverter_csvco_pex_c.sym

@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primative
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+L 7 20 -30 20 -10 {}
+L 7 20 10 20 30 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+B 5 17.5 -32.5 22.5 -27.5 {name=vbulkp dir=inout }
+B 5 17.5 27.5 22.5 32.5 {name=vbulkn dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 34 10 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}
+T {vbulkp} 6 -55 3 1 0.2 0.2 {}
+T {vbulkn} 14 55 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_min_x2.sch b/xschem/inverter_min_x2.sch
new file mode 100644
index 0000000..e986f76
--- /dev/null
+++ b/xschem/inverter_min_x2.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1 
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}

diff --git a/xschem/inverter_min_x2.sym b/xschem/inverter_min_x2.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min_x2.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_min_x2_pex_c.sym b/xschem/inverter_min_x2_pex_c.sym
new file mode 100644
index 0000000..0c2e821
--- /dev/null
+++ b/xschem/inverter_min_x2_pex_c.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_min_x4.sch b/xschem/inverter_min_x4.sch
new file mode 100644
index 0000000..6f8dda8
--- /dev/null
+++ b/xschem/inverter_min_x4.sch

@@ -0,0 +1,50 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 250 -60 250 60 { lab=out}
+N 250 0 340 -0 { lab=out}
+N 160 90 210 90 { lab=in}
+N 160 -90 160 90 { lab=in}
+N 160 -90 210 -90 { lab=in}
+N 100 -0 160 -0 { lab=in}
+N 250 -180 250 -120 { lab=vdd}
+N 250 120 250 180 { lab=vss}
+N 250 -90 350 -90 { lab=vdd}
+N 250 90 350 90 { lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
+L=0.15
+W=0.84
+nf=1
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
+C {opin.sym} 340 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
+L=0.15
+W=0.42
+nf=1 
+mult=4
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}

diff --git a/xschem/inverter_min_x4.sym b/xschem/inverter_min_x4.sym
new file mode 100644
index 0000000..cdda9c9
--- /dev/null
+++ b/xschem/inverter_min_x4.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/inverter_min_x4_pex_c.sym b/xschem/inverter_min_x4_pex_c.sym
new file mode 100644
index 0000000..0c2e821
--- /dev/null
+++ b/xschem/inverter_min_x4_pex_c.sym

@@ -0,0 +1,27 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -40 40 40 0 {}
+L 4 -40 -40 40 0 {}
+L 4 -40 -40 -40 40 {}
+L 7 -20 -50 -20 -30 {}
+L 7 -20 30 -20 50 {}
+B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
+B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
+A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} -16 30 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -34 -55 3 1 0.2 0.2 {}
+T {out} 67 -13 0 1 0.2 0.2 {}
+T {in} -56 -14 0 0 0.2 0.2 {}
+T {vss} -22 54 1 1 0.2 0.2 {}

diff --git a/xschem/latch_diff.sch b/xschem/latch_diff.sch
new file mode 100644
index 0000000..3458830
--- /dev/null
+++ b/xschem/latch_diff.sch

@@ -0,0 +1,120 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 60 80 60 100 { lab=#net1}
+N 60 100 180 100 { lab=#net1}
+N 180 100 180 120 { lab=#net1}
+N 180 100 300 100 { lab=#net1}
+N 300 80 300 100 { lab=#net1}
+N 60 -40 60 20 { lab=nQ}
+N 60 -140 60 -100 { lab=vdd}
+N 60 -140 300 -140 { lab=vdd}
+N 300 -140 300 -100 { lab=vdd}
+N 300 -40 300 20 { lab=Q}
+N 60 50 300 50 { lab=vss}
+N 60 -10 130 -10 { lab=nQ}
+N 130 -10 220 -70 { lab=nQ}
+N 220 -70 260 -70 { lab=nQ}
+N 100 -70 130 -70 { lab=Q}
+N 130 -70 230 -10 { lab=Q}
+N 230 -10 300 -10 { lab=Q}
+N -10 -70 60 -70 { lab=vdd}
+N -10 -140 -10 -70 { lab=vdd}
+N -10 -140 60 -140 { lab=vdd}
+N 300 -70 370 -70 { lab=vdd}
+N 370 -140 370 -70 { lab=vdd}
+N 300 -140 370 -140 { lab=vdd}
+N -10 -10 60 -10 { lab=nQ}
+N 300 -10 370 -10 { lab=Q}
+N -10 50 20 50 { lab=D}
+N 340 50 370 50 { lab=nD}
+N -10 150 140 150 { lab=CLK}
+N 180 180 180 210 { lab=vss}
+N 180 150 220 150 { lab=vss}
+N -30 210 180 210 { lab=vss}
+N -30 -140 -10 -140 { lab=vdd}
+N -30 -10 -10 -10 { lab=nQ}
+N -30 50 -10 50 { lab=D}
+N -30 150 -10 150 { lab=CLK}
+C {sky130_fd_pr/nfet_01v8.sym} 160 150 0 0 {name=M3
+L=0.15
+W=1.25
+nf=1 
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -30 -140 2 0 {name=p1 lab=vdd}
+C {iopin.sym} -30 210 2 0 {name=p2 lab=vss}
+C {ipin.sym} -30 50 0 0 {name=p4 lab=D}
+C {opin.sym} -30 -10 2 0 {name=p5 lab=nQ}
+C {ipin.sym} -30 150 0 0 {name=p3 lab=CLK}
+C {lab_pin.sym} 220 150 2 0 {name=l6 lab=vss}
+C {ipin.sym} 370 50 2 0 {name=p6 lab=nD}
+C {opin.sym} 370 -10 0 0 {name=p7 lab=Q}
+C {lab_wire.sym} 160 50 0 1 {name=l1 lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 80 -70 0 1 {name=M4
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 280 -70 0 0 {name=M5
+L=0.15
+W=0.95
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 40 50 0 0 {name=M1
+L=0.15
+W=0.95
+nf=1 
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 320 50 0 1 {name=M2
+L=0.15
+W=0.95
+nf=1 
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}

diff --git a/xschem/latch_diff.sym b/xschem/latch_diff.sym
new file mode 100644
index 0000000..34bb3fc
--- /dev/null
+++ b/xschem/latch_diff.sym

@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 40 70 40 {}
+L 4 50 -40 70 -40 {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 40 -50 40 {}
+L 4 0 60 0 80 {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 -50 60 50 60 {}
+L 4 -50 -60 50 -60 {}
+L 7 0 -80 0 -60 {}
+L 7 20 60 20 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
+B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
+B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
+B 5 -72.5 37.5 -67.5 42.5 {name=nD dir=in }
+B 5 -2.5 77.5 2.5 82.5 {name=CLK dir=in }
+B 5 17.5 77.5 22.5 82.5 {name=vss dir=inout }
+T {@symname} 7 -76 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -14 -85 3 1 0.2 0.2 {}
+T {nQ} 45 36 0 1 0.2 0.2 {}
+T {Q} 45 -44 0 1 0.2 0.2 {}
+T {D} -45 -44 0 0 0.2 0.2 {}
+T {nD} -45 36 0 0 0.2 0.2 {}
+T {CLK} -14 45 0 0 0.2 0.2 {}
+T {vss} 34 85 1 1 0.2 0.2 {}

diff --git a/xschem/loop_filter.sch b/xschem/loop_filter.sch
new file mode 100644
index 0000000..65afdf2
--- /dev/null
+++ b/xschem/loop_filter.sch

@@ -0,0 +1,51 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 420 100 420 150 { lab=vc_pex}
+N 420 210 420 250 { lab=vss}
+N 420 -110 420 -80 { lab=in}
+N 420 120 470 120 { lab=vc_pex}
+N 650 210 650 230 { lab=vss}
+N 650 -80 650 150 { lab=in}
+N 650 -100 650 -80 { lab=in}
+N 420 -100 650 -100 { lab=in}
+N 380 40 460 40 { lab=vss}
+N 360 0 360 10 { lab=#net1}
+N 360 0 480 0 { lab=#net1}
+N 480 0 480 10 { lab=#net1}
+N 420 -20 420 0 { lab=#net1}
+N 340 -50 390 -50 { lab=vss}
+N 360 70 360 90 { lab=vc_pex}
+N 360 90 480 90 { lab=vc_pex}
+N 480 70 480 90 { lab=vc_pex}
+N 420 90 420 100 { lab=vc_pex}
+N 390 -50 400 -50 {}
+C {iopin.sym} 420 -110 3 0 {name=p2 lab=in}
+C {iopin.sym} 420 250 1 0 {name=p3 lab=vss}
+C {iopin.sym} 470 120 0 0 {name=p1 lab=vc_pex}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 420 180 0 0 {name=C1 model=cap_mim_m3_1 W=25 L=25 MF=25 spiceprefix=X}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 650 180 0 0 {name=C2 model=cap_mim_m3_1 W=20 L=20 MF=9 spiceprefix=X}
+C {lab_pin.sym} 650 230 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/res_high_po_1p41.sym} 360 40 0 1 {name=R2
+W=5.73
+L=22.92
+model=res_high_po_5p73
+spiceprefix=X
+mult=1}
+C {lab_pin.sym} 420 40 3 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 340 -50 0 0 {name=l9 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/res_high_po_1p41.sym} 480 40 0 0 {name=R1
+W=5.73
+L=22.92
+model=res_high_po_5p73
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/res_high_po_1p41.sym} 420 -50 0 0 {name=R3
+W=5.73
+L=22.92
+model=res_high_po_5p73
+spiceprefix=X
+mult=1}

diff --git a/xschem/loop_filter.sym b/xschem/loop_filter.sym
new file mode 100644
index 0000000..cffe115
--- /dev/null
+++ b/xschem/loop_filter.sym

@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}

diff --git a/xschem/loop_filter_pex_c.sym b/xschem/loop_filter_pex_c.sym
new file mode 100644
index 0000000..a7d0cd0
--- /dev/null
+++ b/xschem/loop_filter_pex_c.sym

@@ -0,0 +1,24 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 40 -50 40 50 {}
+L 4 -40 -50 -40 50 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 7 0 50 0 70 {}
+L 7 0 -70 0 -50 {}
+L 7 40 0 60 0 {}
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -2.5 -72.5 2.5 -67.5 {name=in dir=inout }
+B 5 57.5 -2.5 62.5 2.5 {name=vc_pex dir=inout }
+T {@symname} 52.5 34 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vss} -6 75 1 1 0.2 0.2 {}
+T {in} -14 -75 3 1 0.2 0.2 {}
+T {vc_pex} 75 -14 0 1 0.2 0.2 {}

diff --git a/xschem/nor.sch b/xschem/nor.sch
new file mode 100644
index 0000000..07b6bfa
--- /dev/null
+++ b/xschem/nor.sch

@@ -0,0 +1,131 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 210 80 210 130 { lab=out}
+N 210 80 420 80 { lab=out}
+N 420 80 420 130 { lab=out}
+N 420 30 420 80 { lab=out}
+N 210 -80 210 -30 { lab=#net1}
+N 210 30 210 80 { lab=out}
+N 420 -80 420 -30 { lab=#net2}
+N 210 -180 210 -140 { lab=vdd}
+N 210 -180 420 -180 { lab=vdd}
+N 420 -180 420 -140 { lab=vdd}
+N 420 190 420 230 { lab=vss}
+N 210 230 420 230 { lab=vss}
+N 210 190 210 230 { lab=vss}
+N 210 160 420 160 { lab=vss}
+N 320 160 320 230 { lab=vss}
+N 210 -110 320 -110 { lab=vdd}
+N 320 -110 420 -110 { lab=vdd}
+N 320 -180 320 -110 { lab=vdd}
+N 350 0 420 0 { lab=vdd}
+N 210 0 280 0 { lab=vdd}
+N 100 230 210 230 { lab=vss}
+N 100 -180 210 -180 { lab=vdd}
+N 100 0 170 -0 { lab=B}
+N 100 -110 170 -110 { lab=A}
+N 100 160 170 160 { lab=A}
+N 460 -110 520 -110 { lab=B}
+N 460 0 520 0 { lab=A}
+N 460 160 520 160 { lab=B}
+N 420 80 520 80 { lab=out}
+N 320 -110 320 0 { lab=vdd}
+N 280 -0 320 0 { lab=vdd}
+N 320 0 350 -0 { lab=vdd}
+C {sky130_fd_pr/nfet_01v8.sym} 190 160 0 0 {name=M1
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 440 160 0 1 {name=M2
+L=0.15
+W=0.45
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 100 -110 0 0 {name=p1 lab=A}
+C {ipin.sym} 100 0 0 0 {name=p2 lab=B}
+C {lab_pin.sym} 100 160 0 0 {name=l1 sig_type=std_logic lab=A}
+C {iopin.sym} 100 -180 2 0 {name=p3 lab=vdd}
+C {opin.sym} 520 80 0 0 {name=p4 lab=out}
+C {iopin.sym} 100 230 2 0 {name=p5 lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 190 0 0 0 {name=M4
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 520 0 2 0 {name=l2 sig_type=std_logic lab=A}
+C {lab_pin.sym} 520 160 2 0 {name=l3 sig_type=std_logic lab=B}
+C {lab_pin.sym} 520 -110 2 0 {name=l4 sig_type=std_logic lab=B}
+C {sky130_fd_pr/pfet_01v8.sym} 190 -110 0 0 {name=M3
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 440 -110 0 1 {name=M5
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 440 0 0 1 {name=M6
+L=0.15
+W=0.9
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}

diff --git a/xschem/nor.sym b/xschem/nor.sym
new file mode 100644
index 0000000..cf80fc8
--- /dev/null
+++ b/xschem/nor.sym

@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -20 -30 -20 {}
+L 4 -50 20 -30 20 {}
+L 4 30 0 50 0 {}
+L 7 0 -40 0 -20 {}
+L 7 0 20 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout }
+B 5 -52.5 -22.5 -47.5 -17.5 {name=A dir=in }
+B 5 -52.5 17.5 -47.5 22.5 {name=B dir=in }
+B 5 47.5 -2.5 52.5 2.5 {name=out dir=out }
+B 5 -2.5 37.5 2.5 42.5 {name=vss dir=inout }
+A 4 -60 -0 36.05551275463989 303.6900675259798 112.6198649480405 {}
+A 4 -35 35 65.19202405202648 32.47119229084849 61.92751306414704 {}
+A 4 25 -0.5 5.024937810560445 354.2894068625004 360 {}
+A 4 -35 -35 65.19202405202648 265.6012946450045 61.92751306414704 {}
+T {@symname} 14.5 7 0 0 0.3 0.3 {}
+T {@name} -17 -7 0 0 0.2 0.2 {}
+T {vdd} -14 -45 3 1 0.2 0.2 {}
+T {A} -47 -30 0 0 0.2 0.2 {}
+T {B} -47 10 0 0 0.2 0.2 {}
+T {out} 47 -10 0 1 0.2 0.2 {}
+T {vss} -6 45 1 1 0.2 0.2 {}

diff --git a/xschem/pfd_cp_interface.sch b/xschem/pfd_cp_interface.sch
new file mode 100644
index 0000000..37d1f7b
--- /dev/null
+++ b/xschem/pfd_cp_interface.sch

@@ -0,0 +1,64 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -220 -200 -220 -170 { lab=vdd}
+N -220 -70 -220 -40 { lab=vss}
+N -220 40 -220 70 { lab=vdd}
+N -220 170 -220 200 { lab=vss}
+N -290 -120 -260 -120 { lab=QA}
+N -290 120 -260 120 { lab=QB}
+N -30 -200 -30 -170 { lab=vdd}
+N -30 -70 -30 -40 { lab=vss}
+N 20 0 20 30 { lab=vdd}
+N -130 120 -70 120 { lab=nQB}
+N 20 220 20 250 { lab=vss}
+N -130 -120 -70 -120 { lab=nQA}
+N 110 120 170 120 { lab=nDown}
+N 60 -120 170 -120 { lab=Up}
+N 210 170 210 200 { lab=vss}
+N 210 40 210 70 { lab=vdd}
+N 210 -70 210 -40 { lab=vss}
+N 210 -200 210 -170 { lab=vdd}
+N 300 -120 360 -120 { lab=nUp}
+N 300 120 360 120 { lab=Down}
+N 130 120 130 250 { lab=nDown}
+N 130 -250 130 -120 { lab=Up}
+N 360 -120 420 -120 { lab=nUp}
+N 360 120 420 120 { lab=Down}
+N 130 250 420 250 { lab=nDown}
+N 130 -250 420 -250 { lab=Up}
+N -360 120 -290 120 { lab=QB}
+N -360 -120 -290 -120 { lab=QA}
+C {lab_wire.sym} 110 -120 0 0 {name=l20 sig_type=std_logic lab=Up}
+C {lab_wire.sym} 350 120 0 0 {name=l21 sig_type=std_logic lab=Down}
+C {trans_gate.sym} 20 120 0 0 {name=x5}
+C {iopin.sym} -220 -200 3 0 {name=p7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -220 -40 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 40 1 0 {name=l10 sig_type=std_logic lab=vdd}
+C {iopin.sym} -220 200 1 0 {name=p11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -200 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 20 0 1 0 {name=l19 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -30 -40 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 20 250 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 200 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 40 1 0 {name=l24 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 210 -40 3 0 {name=l25 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 210 -200 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 350 -120 0 0 {name=l29 sig_type=std_logic lab=nUp}
+C {lab_wire.sym} 160 120 0 0 {name=l30 sig_type=std_logic lab=nDown}
+C {lab_wire.sym} -90 120 0 0 {name=l33 sig_type=std_logic lab=nQB}
+C {lab_wire.sym} -90 -120 0 0 {name=l34 sig_type=std_logic lab=nQA}
+C {inverter_cp_x1.sym} -10 -120 0 0 {name=x3}
+C {ipin.sym} -360 -120 0 0 {name=p1 lab=QA}
+C {ipin.sym} -360 120 0 0 {name=p2 lab=QB}
+C {opin.sym} 420 250 0 0 {name=p3 lab=nDown}
+C {opin.sym} 420 120 0 0 {name=p4 lab=Down}
+C {opin.sym} 420 -120 0 0 {name=p5 lab=nUp}
+C {opin.sym} 420 -250 0 0 {name=p6 lab=Up}
+C {inverter_cp_x1.sym} -200 120 0 0 {name=x1}
+C {inverter_cp_x1.sym} -200 -120 0 0 {name=x2}
+C {inverter_cp_x2.sym} 230 -120 0 0 {name=x4}
+C {inverter_cp_x2.sym} 230 120 0 0 {name=x6}

diff --git a/xschem/pfd_cp_interface.sym b/xschem/pfd_cp_interface.sym
new file mode 100644
index 0000000..fc77e91
--- /dev/null
+++ b/xschem/pfd_cp_interface.sym

@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 50 -60 70 -60 {}
+L 4 -70 -40 -50 -40 {}
+L 4 50 -20 70 -20 {}
+L 4 50 20 70 20 {}
+L 4 -70 40 -50 40 {}
+L 4 50 60 70 60 {}
+L 4 -50 80 50 80 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 50 -80 50 -60 {}
+L 7 0 -100 0 -80 {}
+L 7 0 80 0 100 {}
+B 5 67.5 -62.5 72.5 -57.5 {name=Up dir=out }
+B 5 -2.5 -102.5 2.5 -97.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=QA dir=in }
+B 5 67.5 -22.5 72.5 -17.5 {name=nUp dir=out }
+B 5 67.5 17.5 72.5 22.5 {name=Down dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=QB dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss sig_type=std_logic dir=inout }
+B 5 67.5 57.5 72.5 62.5 {name=nDown dir=out }
+T {@symname} 10 84 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {Up} 45 -64 0 1 0.2 0.2 {}
+T {vdd} -14 -105 3 1 0.2 0.2 {}
+T {QA} -45 -44 0 0 0.2 0.2 {}
+T {nUp} 45 -24 0 1 0.2 0.2 {}
+T {Down} 45 16 0 1 0.2 0.2 {}
+T {QB} -45 36 0 0 0.2 0.2 {}
+T {vss} -6 105 1 1 0.2 0.2 {}
+T {nDown} 45 56 0 1 0.2 0.2 {}

diff --git a/xschem/pfd_cp_interface_pex_c.sym b/xschem/pfd_cp_interface_pex_c.sym
new file mode 100644
index 0000000..dcaecae
--- /dev/null
+++ b/xschem/pfd_cp_interface_pex_c.sym

@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -60 -50 60 {}
+L 4 50 -60 50 60 {}
+L 4 50 -60 70 -60 {}
+L 4 -70 -40 -50 -40 {}
+L 4 50 -20 70 -20 {}
+L 4 50 20 70 20 {}
+L 4 -70 40 -50 40 {}
+L 4 50 60 70 60 {}
+L 4 -50 80 50 80 {}
+L 4 -50 -80 50 -80 {}
+L 4 -50 -80 -50 -60 {}
+L 4 -50 60 -50 80 {}
+L 4 50 60 50 80 {}
+L 4 50 -80 50 -60 {}
+L 7 0 -100 0 -80 {}
+L 7 0 80 0 100 {}
+B 5 67.5 -62.5 72.5 -57.5 {name=Up dir=out }
+B 5 -2.5 -102.5 2.5 -97.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=QA dir=in }
+B 5 67.5 -22.5 72.5 -17.5 {name=nUp dir=out }
+B 5 67.5 17.5 72.5 22.5 {name=Down dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=QB dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss sig_type=std_logic dir=inout }
+B 5 67.5 57.5 72.5 62.5 {name=nDown dir=out }
+T {@symname} 10 84 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {Up} 45 -64 0 1 0.2 0.2 {}
+T {vdd} -14 -105 3 1 0.2 0.2 {}
+T {QA} -45 -44 0 0 0.2 0.2 {}
+T {nUp} 45 -24 0 1 0.2 0.2 {}
+T {Down} 45 16 0 1 0.2 0.2 {}
+T {QB} -45 36 0 0 0.2 0.2 {}
+T {vss} -6 105 1 1 0.2 0.2 {}
+T {nDown} 45 56 0 1 0.2 0.2 {}

diff --git a/xschem/ring_osc_buffer.sch b/xschem/ring_osc_buffer.sch
new file mode 100644
index 0000000..18e1f4e
--- /dev/null
+++ b/xschem/ring_osc_buffer.sch

@@ -0,0 +1,35 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 780 -210 820 -210 { lab=o1}
+N 690 -290 690 -260 { lab=vdd}
+N 690 -160 690 -130 { lab=vss}
+N 990 -290 990 -260 { lab=vdd}
+N 990 -160 990 -130 { lab=vss}
+N 620 -210 650 -210 { lab=in_vco}
+N 820 -210 950 -210 { lab=o1}
+N 1080 -210 1210 -210 { lab=out_div}
+N 1320 -290 1320 -260 { lab=vdd}
+N 1320 -160 1320 -130 { lab=vss}
+N 1210 -210 1280 -210 { lab=out_div}
+N 1410 -210 1450 -210 { lab=out_pad}
+N 570 -210 620 -210 { lab=in_vco}
+N 1180 -210 1180 -140 { lab=out_div}
+N 880 -260 880 -210 { lab=o1}
+C {iopin.sym} 690 -290 3 0 {name=p16 sig_type=std_logic lab=vdd}
+C {iopin.sym} 690 -130 1 0 {name=p40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 990 -290 1 0 {name=l48 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 990 -130 3 0 {name=l49 sig_type=std_logic lab=vss}
+C {ipin.sym} 570 -210 0 0 {name=p60 sig_type=std_logic lab=in_vco}
+C {lab_wire.sym} 810 -210 0 0 {name=l61 sig_type=std_logic lab=o1}
+C {lab_pin.sym} 1320 -290 1 0 {name=l74 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 1320 -130 3 0 {name=l84 sig_type=std_logic lab=vss}
+C {opin.sym} 1450 -210 2 1 {name=p86 sig_type=std_logic lab=out_pad}
+C {inverter_min_x2.sym} 710 -210 0 0 {name=x1}
+C {inverter_min_x4.sym} 1010 -210 0 0 {name=x2}
+C {opin.sym} 1180 -140 3 1 {name=p1 sig_type=std_logic lab=out_div}
+C {iopin.sym} 880 -260 3 0 {name=p2 sig_type=std_logic lab=o1}
+C {inverter_min_x4.sym} 1340 -210 0 0 {name=x3}

diff --git a/xschem/ring_osc_buffer.sym b/xschem/ring_osc_buffer.sym
new file mode 100644
index 0000000..587bc9c
--- /dev/null
+++ b/xschem/ring_osc_buffer.sym

@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 -60 0 -40 0 {}
+L 4 40 -20 60 -20 {}
+L 4 40 20 60 20 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 4 -30 40 -30 50 {}
+L 4 -30 30 30 30 {}
+L 4 30 40 30 50 {}
+L 4 -30 30 -30 40 {}
+L 4 30 30 30 40 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 -40 50 {}
+L 4 -40 -50 -40 -40 {}
+L 4 40 -50 40 -40 {}
+L 7 -20 -70 -20 -50 {}
+L 7 20 -70 20 -50 {}
+L 7 0 50 0 70 {}
+B 5 -22.5 -72.5 -17.5 -67.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in_vco sig_type=std_logic dir=in }
+B 5 57.5 -22.5 62.5 -17.5 {name=out_pad sig_type=std_logic dir=out }
+B 5 57.5 17.5 62.5 22.5 {name=out_div sig_type=std_logic dir=out }
+B 5 17.5 -72.5 22.5 -67.5 {name=vss sig_type=std_logic dir=inout }
+B 5 -2.5 67.5 2.5 72.5 {name=o1 sig_type=std_logic dir=inout }
+T {@symname} 44.5 54 0 0 0.3 0.3 {}
+T {@name} -15 -12 0 0 0.2 0.2 {}
+T {vdd} -34 -75 3 1 0.2 0.2 {}
+T {in_vco} -75 -14 0 0 0.2 0.2 {}
+T {out_pad} 85 -34 0 1 0.2 0.2 {}
+T {out_div} 85 6 0 1 0.2 0.2 {}
+T {vss} 6 -75 3 1 0.2 0.2 {}
+T {Debug} 15 36 0 1 0.2 0.2 {}
+T {o1} 14 75 1 1 0.2 0.2 {}

diff --git a/xschem/ring_osc_buffer_pex_c.sym b/xschem/ring_osc_buffer_pex_c.sym
new file mode 100644
index 0000000..6b44152
--- /dev/null
+++ b/xschem/ring_osc_buffer_pex_c.sym

@@ -0,0 +1,43 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -40 -40 -40 40 {}
+L 4 40 -40 40 40 {}
+L 4 -60 0 -40 0 {}
+L 4 40 -20 60 -20 {}
+L 4 40 20 60 20 {}
+L 4 -40 -50 40 -50 {}
+L 4 -40 50 40 50 {}
+L 4 -30 40 -30 50 {}
+L 4 -30 30 30 30 {}
+L 4 30 40 30 50 {}
+L 4 -30 30 -30 40 {}
+L 4 30 30 30 40 {}
+L 4 40 40 40 50 {}
+L 4 -40 40 -40 50 {}
+L 4 -40 -50 -40 -40 {}
+L 4 40 -50 40 -40 {}
+L 7 -20 -70 -20 -50 {}
+L 7 20 -70 20 -50 {}
+L 7 0 50 0 70 {}
+B 5 -22.5 -72.5 -17.5 -67.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -62.5 -2.5 -57.5 2.5 {name=in_vco sig_type=std_logic dir=in }
+B 5 57.5 -22.5 62.5 -17.5 {name=out_pad sig_type=std_logic dir=out }
+B 5 57.5 17.5 62.5 22.5 {name=out_div sig_type=std_logic dir=out }
+B 5 17.5 -72.5 22.5 -67.5 {name=vss sig_type=std_logic dir=inout }
+B 5 -2.5 67.5 2.5 72.5 {name=o1 sig_type=std_logic dir=inout }
+T {@symname} 44.5 54 0 0 0.3 0.3 {}
+T {@name} -15 -12 0 0 0.2 0.2 {}
+T {vdd} -34 -75 3 1 0.2 0.2 {}
+T {in_vco} -75 -14 0 0 0.2 0.2 {}
+T {out_pad} 85 -34 0 1 0.2 0.2 {}
+T {out_div} 85 6 0 1 0.2 0.2 {}
+T {vss} 6 -75 3 1 0.2 0.2 {}
+T {Debug} 15 36 0 1 0.2 0.2 {}
+T {o1} 14 75 1 1 0.2 0.2 {}

diff --git a/xschem/simulations/.spiceinit b/xschem/simulations/.spiceinit
new file mode 100644
index 0000000..0c7a371
--- /dev/null
+++ b/xschem/simulations/.spiceinit

@@ -0,0 +1,5 @@
+set ngbehavior=hsa 
+set ng_nomodcheck 
+set numthreads=8 
+set filetype=ascii 
+set outputpath=~sky130-mpw2-fulgorring_osc

diff --git a/xschem/simulations/DFF.spice b/xschem/simulations/DFF.spice
new file mode 100644
index 0000000..2de16a7
--- /dev/null
+++ b/xschem/simulations/DFF.spice

@@ -0,0 +1,43 @@
+**.subckt DFF D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+**.ends
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/DFlipFlop.spice b/xschem/simulations/DFlipFlop.spice
new file mode 100644
index 0000000..dfdb429
--- /dev/null
+++ b/xschem/simulations/DFlipFlop.spice

@@ -0,0 +1,93 @@
+**.subckt DFlipFlop vdd vss Q nQ D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+**.ends
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/PFD.spice b/xschem/simulations/PFD.spice
new file mode 100644
index 0000000..65e94d9
--- /dev/null
+++ b/xschem/simulations/PFD.spice

@@ -0,0 +1,96 @@
+**.subckt PFD vdd vss A B Down Up Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+**.ends
+
+* expanding   symbol:  DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF  D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding   symbol:  and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd  vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/PFD_pex_c.spice b/xschem/simulations/PFD_pex_c.spice
new file mode 100644
index 0000000..c9ccf62
--- /dev/null
+++ b/xschem/simulations/PFD_pex_c.spice

@@ -0,0 +1,251 @@
+* NGSPICE file created from PFD.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_159_n90# a_n129_n90# 0.06fF
+C1 a_159_n90# w_n359_n309# 0.09fF
+C2 a_159_n90# a_n33_n90# 0.09fF
+C3 a_159_n90# a_63_n90# 0.26fF
+C4 a_n63_n116# a_n159_n207# 0.12fF
+C5 a_n221_n90# a_159_n90# 0.04fF
+C6 a_n129_n90# w_n359_n309# 0.06fF
+C7 a_n129_n90# a_n33_n90# 0.26fF
+C8 a_n129_n90# a_63_n90# 0.09fF
+C9 a_n33_n90# w_n359_n309# 0.05fF
+C10 a_63_n90# w_n359_n309# 0.06fF
+C11 a_n33_n90# a_63_n90# 0.26fF
+C12 a_n221_n90# a_n129_n90# 0.26fF
+C13 a_n221_n90# w_n359_n309# 0.09fF
+C14 a_n221_n90# a_n33_n90# 0.09fF
+C15 a_n221_n90# a_63_n90# 0.06fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n125_n45# a_n33_n45# 0.13fF
+C1 a_n125_n45# a_63_n45# 0.05fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_33_n71# a_n129_71# 0.04fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 out A 0.06fF
+C1 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C2 out vdd 0.11fF
+C3 B out 0.40fF
+C4 A vdd 0.09fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C6 B A 0.24fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C2 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 nor_pfd_2/B vdd 0.02fF
+C4 Q nor_pfd_2/B 2.22fF
+C5 Reset nor_pfd_2/B 0.43fF
+C6 vdd nor_pfd_2/A -0.01fF
+C7 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C8 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C9 Q nor_pfd_2/A 1.38fF
+C10 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C11 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C12 Q vdd 0.08fF
+C13 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C14 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C15 Reset Q 0.14fF
+C16 nor_pfd_3/A vdd 0.09fF
+C17 nor_pfd_3/A Q 0.98fF
+C18 CLK Q 0.04fF
+C19 Reset nor_pfd_3/A 0.12fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 vdd vss 16.42fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 2.77fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 nor_pfd_3/A vss 3.16fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n33_n45# a_159_n45# 0.05fF
+C2 a_63_n45# a_159_n45# 0.13fF
+C3 a_n129_n45# a_n221_n45# 0.13fF
+C4 a_n33_n45# a_n221_n45# 0.05fF
+C5 a_63_n45# a_n221_n45# 0.03fF
+C6 a_n159_n173# a_n63_n71# 0.10fF
+C7 a_n221_n45# a_159_n45# 0.02fF
+C8 a_n129_n45# a_n33_n45# 0.13fF
+C9 a_n129_n45# a_63_n45# 0.05fF
+C10 a_n33_n45# a_63_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n99_n187# a_33_n187# 0.04fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_63_n90# a_n125_n90# 0.09fF
+C3 a_n125_n90# a_n33_n90# 0.26fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 A B 0.33fF
+C1 B a_656_410# 0.30fF
+C2 out a_656_410# 0.20fF
+C3 A a_656_410# 0.04fF
+C4 vdd out 0.10fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C6 vdd A 0.05fF
+C7 vdd a_656_410# 0.20fF
+C8 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C9 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD_pex_c vss vdd Up A B Down Reset
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C1 Down vdd 0.08fF
+C2 vdd Reset 0.02fF
+C3 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C4 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C5 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C6 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C7 Down Up 0.06fF
+C8 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C9 Up vdd 1.62fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 vdd vss 44.73fF
+C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 Down vss 4.18fF
+C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 Reset vss 5.05fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C34 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C35 Up vss 2.76fF
+C36 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C37 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+

diff --git a/xschem/analog_wrapper_tb.spice b/xschem/simulations/analog_wrapper_tb.spice
similarity index 100%
rename from xschem/analog_wrapper_tb.spice
rename to xschem/simulations/analog_wrapper_tb.spice


diff --git a/xschem/simulations/and_pfd.spice b/xschem/simulations/and_pfd.spice
new file mode 100644
index 0000000..60e45db
--- /dev/null
+++ b/xschem/simulations/and_pfd.spice

@@ -0,0 +1,33 @@
+**.subckt and_pfd vdd vss out A B
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/bias_pex_c.spice b/xschem/simulations/bias_pex_c.spice
new file mode 100644
index 0000000..0caf87b
--- /dev/null
+++ b/xschem/simulations/bias_pex_c.spice

@@ -0,0 +1,157 @@
+* NGSPICE file created from bias.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+C0 a_n1879_n1219# w_n2018_n202# 0.25fF
+C1 a_n1731_n1219# w_n2018_n202# 19.90fF
+C2 a_n2017_n1317# w_n2018_n202# 0.16fF
+C3 a_n2017_n61# w_n2018_n202# 1.37fF
+C4 a_n1731_n1219# a_n1879_n1219# 19.29fF
+C5 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C6 a_n1731_n1219# a_n2017_n1317# 4.73fF
+C7 a_n2017_n61# a_n1879_n1219# 0.16fF
+C8 a_n1731_n1219# a_n2017_n61# 5.23fF
+C9 a_n2017_n61# a_n2017_n1317# 2.88fF
+C10 a_n1879_n1219# VSUBS 1.53fF
+C11 a_n2017_n1317# VSUBS 5.03fF
+C12 a_n1731_n1219# VSUBS 2.60fF
+C13 a_n2017_n61# VSUBS 5.10fF
+C14 w_n2018_n202# VSUBS 37.43fF
+.ends
+
+.subckt bias_pex_c vdd iref vss iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 vss iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 vss iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+C0 iref iref_2 -0.01fF
+C1 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
+C2 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
+C3 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vdd 0.24fF
+C4 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C5 iref_7 iref_6 0.05fF
+C6 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
+C8 iref m1_20168_984# 0.07fF
+C9 iref iref_5 0.05fF
+C10 iref iref_9 -0.01fF
+C11 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
+C13 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
+C14 iref_7 iref_8 0.05fF
+C15 iref_3 iref_4 0.05fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# iref_2 0.24fF
+C17 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C18 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
+C19 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
+C20 iref iref_8 -0.03fF
+C21 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C22 iref_6 iref_5 0.05fF
+C23 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# m1_20168_984# 0.01fF
+C24 iref_2 iref_3 0.05fF
+C25 iref vdd -0.07fF
+C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C27 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
+C28 iref iref_1 -0.02fF
+C29 iref_2 iref_1 0.05fF
+C30 iref iref_4 0.30fF
+C31 iref_8 iref_9 0.05fF
+C32 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# -0.15fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vdd 0.24fF
+C34 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C35 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C36 m1_20168_984# vdd 0.25fF
+C37 iref_0 iref_1 0.05fF
+C38 iref vss 32.42fF
+C39 iref_4 vss 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vss 2.60fF
+C41 iref_3 vss 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vss 2.60fF
+C43 iref_2 vss -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vss 2.60fF
+C45 iref_1 vss -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vss 2.60fF
+C47 m1_20168_984# vss 56.92fF
+C48 vdd vss 416.01fF
+C49 iref_0 vss 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vss 2.60fF
+C51 iref_9 vss -1.13fF
+C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vss 2.60fF
+C53 iref_7 vss -1.38fF
+C54 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vss 2.60fF
+C55 iref_8 vss -1.19fF
+C56 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vss 2.60fF
+C57 iref_6 vss -1.00fF
+C58 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vss 2.60fF
+C59 iref_5 vss 1.40fF
+C60 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vss 2.60fF
+.ends
+

diff --git a/xschem/simulations/charge_pump.spice b/xschem/simulations/charge_pump.spice
new file mode 100644
index 0000000..3958f73
--- /dev/null
+++ b/xschem/simulations/charge_pump.spice

@@ -0,0 +1,48 @@
+**.subckt charge_pump vss vdd Down nUp Up nDown out nswitch pswitch iref biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/charge_pump_pex_c.spice b/xschem/simulations/charge_pump_pex_c.spice
new file mode 100644
index 0000000..90a1be4
--- /dev/null
+++ b/xschem/simulations/charge_pump_pex_c.spice

@@ -0,0 +1,692 @@
+* NGSPICE file created from charge_pump.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 a_1803_n486# w_n2457_n634# 0.02fF
+C1 a_2261_n486# w_n2457_n634# 0.02fF
+C2 w_n2457_n634# a_n487_n486# 0.02fF
+C3 a_n945_n486# w_n2457_n634# 0.02fF
+C4 a_n29_n486# w_n2457_n634# 0.02fF
+C5 a_n1403_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_n2319_n486# 0.02fF
+C7 w_n2457_n634# a_887_n486# 0.02fF
+C8 a_n1861_n486# w_n2457_n634# 0.02fF
+C9 w_n2457_n634# a_1345_n486# 0.02fF
+C10 a_429_n486# w_n2457_n634# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_303_n75# a_111_n75# 0.08fF
+C1 a_n657_n75# a_n465_n75# 0.08fF
+C2 a_n273_n75# a_n81_n75# 0.08fF
+C3 a_n1229_n75# a_n1041_n75# 0.08fF
+C4 a_687_n75# a_591_n75# 0.22fF
+C5 a_687_n75# a_303_n75# 0.03fF
+C6 a_n657_n75# a_n1041_n75# 0.03fF
+C7 a_n1229_n75# a_n1137_n75# 0.22fF
+C8 a_591_n75# a_975_n75# 0.03fF
+C9 a_n465_n75# a_n369_n75# 0.22fF
+C10 a_n561_n75# a_n177_n75# 0.03fF
+C11 a_207_n75# a_399_n75# 0.08fF
+C12 a_399_n75# a_15_n75# 0.03fF
+C13 a_207_n75# a_n177_n75# 0.03fF
+C14 a_n1229_n75# a_n945_n75# 0.05fF
+C15 a_15_n75# a_n177_n75# 0.08fF
+C16 a_n657_n75# a_n945_n75# 0.05fF
+C17 a_n465_n75# a_n273_n75# 0.08fF
+C18 a_111_n75# a_399_n75# 0.05fF
+C19 a_111_n75# a_n177_n75# 0.05fF
+C20 a_687_n75# a_399_n75# 0.05fF
+C21 a_n465_n75# a_n81_n75# 0.03fF
+C22 a_495_n75# a_879_n75# 0.03fF
+C23 a_303_n75# a_n81_n75# 0.03fF
+C24 a_591_n75# a_879_n75# 0.05fF
+C25 a_n369_n75# a_n177_n75# 0.08fF
+C26 a_n273_n75# a_n177_n75# 0.22fF
+C27 a_783_n75# a_1071_n75# 0.05fF
+C28 a_687_n75# a_783_n75# 0.22fF
+C29 a_n1041_n75# a_n1137_n75# 0.22fF
+C30 a_975_n75# a_783_n75# 0.08fF
+C31 a_n81_n75# a_n177_n75# 0.22fF
+C32 a_495_n75# a_591_n75# 0.22fF
+C33 a_n945_n75# a_n1041_n75# 0.22fF
+C34 a_303_n75# a_495_n75# 0.08fF
+C35 a_n561_n75# a_n753_n75# 0.08fF
+C36 a_1167_n75# a_783_n75# 0.03fF
+C37 a_n561_n75# a_n849_n75# 0.05fF
+C38 a_n945_n75# a_n1137_n75# 0.08fF
+C39 a_n849_n75# a_n753_n75# 0.22fF
+C40 a_303_n75# a_591_n75# 0.05fF
+C41 a_207_n75# a_15_n75# 0.08fF
+C42 a_n465_n75# a_n177_n75# 0.05fF
+C43 a_207_n75# a_111_n75# 0.22fF
+C44 a_495_n75# a_399_n75# 0.22fF
+C45 a_111_n75# a_15_n75# 0.22fF
+C46 a_591_n75# a_399_n75# 0.08fF
+C47 a_303_n75# a_399_n75# 0.22fF
+C48 a_n561_n75# a_n657_n75# 0.22fF
+C49 a_n849_n75# a_n1229_n75# 0.03fF
+C50 a_n657_n75# a_n753_n75# 0.22fF
+C51 a_879_n75# a_783_n75# 0.22fF
+C52 a_n657_n75# a_n849_n75# 0.08fF
+C53 a_687_n75# a_1071_n75# 0.03fF
+C54 a_n561_n75# a_n369_n75# 0.08fF
+C55 a_n753_n75# a_n369_n75# 0.03fF
+C56 a_975_n75# a_1071_n75# 0.22fF
+C57 a_687_n75# a_975_n75# 0.05fF
+C58 a_n369_n75# a_15_n75# 0.03fF
+C59 a_n561_n75# a_n273_n75# 0.05fF
+C60 a_1167_n75# a_1071_n75# 0.22fF
+C61 a_1167_n75# a_975_n75# 0.08fF
+C62 a_495_n75# a_783_n75# 0.05fF
+C63 a_n273_n75# a_15_n75# 0.05fF
+C64 a_591_n75# a_783_n75# 0.08fF
+C65 a_n81_n75# a_207_n75# 0.05fF
+C66 a_n273_n75# a_111_n75# 0.03fF
+C67 a_n81_n75# a_15_n75# 0.22fF
+C68 a_n657_n75# a_n369_n75# 0.05fF
+C69 a_n81_n75# a_111_n75# 0.08fF
+C70 a_n561_n75# a_n465_n75# 0.22fF
+C71 a_n465_n75# a_n753_n75# 0.05fF
+C72 a_n849_n75# a_n465_n75# 0.03fF
+C73 a_n657_n75# a_n273_n75# 0.03fF
+C74 a_879_n75# a_1071_n75# 0.08fF
+C75 a_687_n75# a_879_n75# 0.08fF
+C76 a_n753_n75# a_n1041_n75# 0.05fF
+C77 a_783_n75# a_399_n75# 0.03fF
+C78 a_n849_n75# a_n1041_n75# 0.08fF
+C79 a_975_n75# a_879_n75# 0.22fF
+C80 a_n753_n75# a_n1137_n75# 0.03fF
+C81 a_n273_n75# a_n369_n75# 0.22fF
+C82 a_495_n75# a_207_n75# 0.05fF
+C83 a_n849_n75# a_n1137_n75# 0.05fF
+C84 a_n561_n75# a_n945_n75# 0.03fF
+C85 a_1167_n75# a_879_n75# 0.05fF
+C86 a_n945_n75# a_n753_n75# 0.08fF
+C87 a_n369_n75# a_n81_n75# 0.05fF
+C88 a_591_n75# a_207_n75# 0.03fF
+C89 a_n849_n75# a_n945_n75# 0.22fF
+C90 a_303_n75# a_207_n75# 0.22fF
+C91 a_495_n75# a_111_n75# 0.03fF
+C92 a_303_n75# a_15_n75# 0.05fF
+C93 a_687_n75# a_495_n75# 0.08fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n989_n150# a_n897_n150# 0.43fF
+C1 a_639_n150# a_447_n150# 0.16fF
+C2 a_n513_n150# a_n609_n150# 0.43fF
+C3 a_n417_n150# a_n801_n150# 0.07fF
+C4 a_n989_n150# a_n801_n150# 0.16fF
+C5 a_543_n150# a_735_n150# 0.16fF
+C6 a_735_n150# a_351_n150# 0.07fF
+C7 a_543_n150# a_159_n150# 0.07fF
+C8 a_n513_n150# a_n225_n150# 0.10fF
+C9 a_351_n150# a_159_n150# 0.16fF
+C10 a_447_n150# a_735_n150# 0.10fF
+C11 a_447_n150# a_159_n150# 0.10fF
+C12 a_63_n150# a_255_n150# 0.16fF
+C13 a_639_n150# a_831_n150# 0.16fF
+C14 a_927_n150# a_831_n150# 0.43fF
+C15 a_63_n150# a_n321_n150# 0.07fF
+C16 a_n321_n150# a_n705_n150# 0.07fF
+C17 a_n513_n150# a_n129_n150# 0.07fF
+C18 a_639_n150# a_255_n150# 0.07fF
+C19 a_n513_n150# a_n897_n150# 0.07fF
+C20 a_n609_n150# a_n321_n150# 0.10fF
+C21 a_255_n150# a_n33_n150# 0.10fF
+C22 a_n33_n150# a_n321_n150# 0.10fF
+C23 a_n513_n150# a_n801_n150# 0.10fF
+C24 a_831_n150# a_735_n150# 0.43fF
+C25 a_n321_n150# a_n225_n150# 0.43fF
+C26 a_n513_n150# a_n417_n150# 0.43fF
+C27 a_n927_n247# a_33_n247# 0.09fF
+C28 a_255_n150# a_159_n150# 0.43fF
+C29 a_n609_n150# a_n705_n150# 0.43fF
+C30 a_63_n150# a_n33_n150# 0.43fF
+C31 a_639_n150# a_927_n150# 0.10fF
+C32 a_63_n150# a_n225_n150# 0.10fF
+C33 a_255_n150# a_n129_n150# 0.07fF
+C34 a_543_n150# a_351_n150# 0.16fF
+C35 a_n321_n150# a_n129_n150# 0.16fF
+C36 a_n609_n150# a_n225_n150# 0.07fF
+C37 a_543_n150# a_447_n150# 0.43fF
+C38 a_447_n150# a_351_n150# 0.43fF
+C39 a_63_n150# a_159_n150# 0.43fF
+C40 a_n33_n150# a_n225_n150# 0.16fF
+C41 a_639_n150# a_735_n150# 0.43fF
+C42 a_927_n150# a_735_n150# 0.16fF
+C43 a_n321_n150# a_n417_n150# 0.43fF
+C44 a_n33_n150# a_159_n150# 0.16fF
+C45 a_63_n150# a_n129_n150# 0.16fF
+C46 a_n705_n150# a_n897_n150# 0.16fF
+C47 a_n225_n150# a_159_n150# 0.07fF
+C48 a_n609_n150# a_n897_n150# 0.10fF
+C49 a_n705_n150# a_n801_n150# 0.43fF
+C50 a_n33_n150# a_n129_n150# 0.43fF
+C51 a_n609_n150# a_n801_n150# 0.16fF
+C52 a_831_n150# a_543_n150# 0.10fF
+C53 a_n129_n150# a_n225_n150# 0.43fF
+C54 a_n417_n150# a_n705_n150# 0.10fF
+C55 a_n989_n150# a_n705_n150# 0.10fF
+C56 a_n609_n150# a_n417_n150# 0.16fF
+C57 a_255_n150# a_543_n150# 0.10fF
+C58 a_831_n150# a_447_n150# 0.07fF
+C59 a_255_n150# a_351_n150# 0.43fF
+C60 a_n989_n150# a_n609_n150# 0.07fF
+C61 a_n33_n150# a_n417_n150# 0.07fF
+C62 a_n129_n150# a_159_n150# 0.10fF
+C63 a_255_n150# a_447_n150# 0.16fF
+C64 a_n225_n150# a_n417_n150# 0.16fF
+C65 a_n513_n150# a_n321_n150# 0.16fF
+C66 a_63_n150# a_351_n150# 0.10fF
+C67 a_n897_n150# a_n801_n150# 0.43fF
+C68 a_639_n150# a_543_n150# 0.43fF
+C69 a_63_n150# a_447_n150# 0.07fF
+C70 a_639_n150# a_351_n150# 0.10fF
+C71 a_927_n150# a_543_n150# 0.07fF
+C72 a_n129_n150# a_n417_n150# 0.10fF
+C73 a_n33_n150# a_351_n150# 0.07fF
+C74 a_n513_n150# a_n705_n150# 0.16fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n989_n75# a_n801_n75# 0.08fF
+C1 a_927_n75# a_735_n75# 0.08fF
+C2 a_63_n75# a_447_n75# 0.03fF
+C3 a_n225_n75# a_n33_n75# 0.08fF
+C4 a_n129_n75# a_n417_n75# 0.05fF
+C5 a_n801_n75# a_n705_n75# 0.22fF
+C6 a_351_n75# a_n33_n75# 0.03fF
+C7 a_927_n75# a_831_n75# 0.22fF
+C8 a_n989_n75# a_n609_n75# 0.03fF
+C9 a_159_n75# a_543_n75# 0.03fF
+C10 a_63_n75# a_n225_n75# 0.05fF
+C11 a_735_n75# a_543_n75# 0.08fF
+C12 a_63_n75# a_351_n75# 0.05fF
+C13 a_n705_n75# a_n609_n75# 0.22fF
+C14 a_n129_n75# a_255_n75# 0.03fF
+C15 a_831_n75# a_543_n75# 0.05fF
+C16 a_n513_n75# a_n705_n75# 0.08fF
+C17 a_n33_n75# a_n417_n75# 0.03fF
+C18 a_255_n75# a_159_n75# 0.22fF
+C19 a_n321_n75# a_n609_n75# 0.05fF
+C20 a_447_n75# a_639_n75# 0.08fF
+C21 a_n513_n75# a_n321_n75# 0.08fF
+C22 a_n225_n75# a_n321_n75# 0.22fF
+C23 a_n33_n75# a_255_n75# 0.05fF
+C24 a_n705_n75# a_n417_n75# 0.05fF
+C25 a_639_n75# a_351_n75# 0.05fF
+C26 a_63_n75# a_255_n75# 0.08fF
+C27 a_639_n75# a_927_n75# 0.05fF
+C28 a_n801_n75# a_n609_n75# 0.08fF
+C29 a_n321_n75# a_n417_n75# 0.22fF
+C30 a_n801_n75# a_n513_n75# 0.05fF
+C31 a_639_n75# a_543_n75# 0.22fF
+C32 a_n513_n75# a_n609_n75# 0.22fF
+C33 a_n225_n75# a_n609_n75# 0.03fF
+C34 a_447_n75# a_351_n75# 0.22fF
+C35 a_n129_n75# a_159_n75# 0.05fF
+C36 a_n927_n101# a_33_n101# 0.08fF
+C37 a_n513_n75# a_n225_n75# 0.05fF
+C38 a_639_n75# a_255_n75# 0.03fF
+C39 a_n801_n75# a_n417_n75# 0.03fF
+C40 a_n129_n75# a_n33_n75# 0.22fF
+C41 a_831_n75# a_735_n75# 0.22fF
+C42 a_447_n75# a_543_n75# 0.22fF
+C43 a_n417_n75# a_n609_n75# 0.08fF
+C44 a_n33_n75# a_159_n75# 0.08fF
+C45 a_63_n75# a_n129_n75# 0.08fF
+C46 a_n513_n75# a_n417_n75# 0.22fF
+C47 a_n897_n75# a_n989_n75# 0.22fF
+C48 a_n225_n75# a_n417_n75# 0.08fF
+C49 a_63_n75# a_159_n75# 0.22fF
+C50 a_351_n75# a_543_n75# 0.08fF
+C51 a_447_n75# a_255_n75# 0.08fF
+C52 a_n897_n75# a_n705_n75# 0.08fF
+C53 a_927_n75# a_543_n75# 0.03fF
+C54 a_63_n75# a_n33_n75# 0.22fF
+C55 a_n321_n75# a_n129_n75# 0.08fF
+C56 a_351_n75# a_255_n75# 0.22fF
+C57 a_639_n75# a_735_n75# 0.22fF
+C58 a_n321_n75# a_n33_n75# 0.05fF
+C59 a_255_n75# a_543_n75# 0.05fF
+C60 a_n989_n75# a_n705_n75# 0.05fF
+C61 a_639_n75# a_831_n75# 0.08fF
+C62 a_n897_n75# a_n801_n75# 0.22fF
+C63 a_63_n75# a_n321_n75# 0.03fF
+C64 a_n897_n75# a_n609_n75# 0.05fF
+C65 a_n321_n75# a_n705_n75# 0.03fF
+C66 a_447_n75# a_159_n75# 0.05fF
+C67 a_447_n75# a_735_n75# 0.05fF
+C68 a_n897_n75# a_n513_n75# 0.03fF
+C69 a_n513_n75# a_n129_n75# 0.03fF
+C70 a_n225_n75# a_n129_n75# 0.22fF
+C71 a_447_n75# a_831_n75# 0.03fF
+C72 a_n225_n75# a_159_n75# 0.03fF
+C73 a_351_n75# a_159_n75# 0.08fF
+C74 a_351_n75# a_735_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n1103_n44# a_n1461_n44# 0.04fF
+C1 a_1045_n44# a_687_n44# 0.04fF
+C2 a_n29_n44# a_329_n44# 0.04fF
+C3 a_n1103_n44# a_n745_n44# 0.04fF
+C4 a_1403_n44# a_1761_n44# 0.04fF
+C5 a_n1461_n44# a_n1819_n44# 0.04fF
+C6 a_687_n44# a_329_n44# 0.04fF
+C7 a_n387_n44# a_n29_n44# 0.04fF
+C8 a_n387_n44# a_n745_n44# 0.04fF
+C9 a_1403_n44# a_1045_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_975_n150# a_783_n150# 0.16fF
+C1 w_n1367_n369# a_1071_n150# 0.07fF
+C2 a_n561_n150# a_n177_n150# 0.07fF
+C3 a_591_n150# a_879_n150# 0.10fF
+C4 a_111_n150# a_207_n150# 0.43fF
+C5 a_n753_n150# a_n849_n150# 0.43fF
+C6 a_n273_n150# a_n657_n150# 0.07fF
+C7 a_687_n150# a_303_n150# 0.07fF
+C8 a_n465_n150# a_n849_n150# 0.07fF
+C9 a_n177_n150# a_207_n150# 0.07fF
+C10 a_687_n150# a_399_n150# 0.10fF
+C11 a_n561_n150# a_n273_n150# 0.10fF
+C12 a_207_n150# a_303_n150# 0.43fF
+C13 a_15_n150# a_n369_n150# 0.07fF
+C14 a_n753_n150# a_n369_n150# 0.07fF
+C15 a_399_n150# a_207_n150# 0.16fF
+C16 a_n81_n150# a_207_n150# 0.10fF
+C17 a_n657_n150# a_n849_n150# 0.16fF
+C18 a_n1041_n150# a_n849_n150# 0.16fF
+C19 a_n369_n150# a_n465_n150# 0.43fF
+C20 a_591_n150# a_303_n150# 0.10fF
+C21 a_n1229_n150# a_n849_n150# 0.07fF
+C22 a_399_n150# a_591_n150# 0.16fF
+C23 a_n561_n150# a_n849_n150# 0.10fF
+C24 a_687_n150# a_495_n150# 0.16fF
+C25 a_1167_n150# a_879_n150# 0.10fF
+C26 a_975_n150# a_1071_n150# 0.43fF
+C27 a_n945_n150# a_n849_n150# 0.43fF
+C28 a_n657_n150# a_n369_n150# 0.10fF
+C29 a_207_n150# a_495_n150# 0.10fF
+C30 a_783_n150# a_1071_n150# 0.10fF
+C31 a_n561_n150# a_n369_n150# 0.16fF
+C32 a_111_n150# a_n177_n150# 0.10fF
+C33 a_111_n150# a_303_n150# 0.16fF
+C34 a_591_n150# a_495_n150# 0.43fF
+C35 a_879_n150# w_n1367_n369# 0.04fF
+C36 a_111_n150# a_399_n150# 0.10fF
+C37 a_687_n150# a_975_n150# 0.10fF
+C38 a_111_n150# a_n81_n150# 0.16fF
+C39 a_n1137_n150# a_n849_n150# 0.10fF
+C40 a_111_n150# a_n273_n150# 0.07fF
+C41 a_879_n150# a_495_n150# 0.07fF
+C42 a_n177_n150# a_n81_n150# 0.43fF
+C43 a_399_n150# a_303_n150# 0.43fF
+C44 a_687_n150# a_783_n150# 0.43fF
+C45 a_n81_n150# a_303_n150# 0.07fF
+C46 a_n177_n150# a_n273_n150# 0.43fF
+C47 a_n753_n150# a_n465_n150# 0.10fF
+C48 a_1167_n150# w_n1367_n369# 0.14fF
+C49 a_591_n150# a_975_n150# 0.07fF
+C50 a_111_n150# a_495_n150# 0.07fF
+C51 a_n81_n150# a_n273_n150# 0.16fF
+C52 a_n753_n150# a_n657_n150# 0.43fF
+C53 a_n753_n150# a_n1041_n150# 0.10fF
+C54 a_591_n150# a_783_n150# 0.16fF
+C55 a_495_n150# a_303_n150# 0.16fF
+C56 a_n657_n150# a_n465_n150# 0.16fF
+C57 a_879_n150# a_975_n150# 0.43fF
+C58 a_n561_n150# a_n753_n150# 0.16fF
+C59 a_399_n150# a_495_n150# 0.43fF
+C60 a_n945_n150# a_n753_n150# 0.16fF
+C61 a_n561_n150# a_n465_n150# 0.43fF
+C62 a_879_n150# a_783_n150# 0.43fF
+C63 a_n657_n150# a_n1041_n150# 0.07fF
+C64 a_n177_n150# a_n369_n150# 0.16fF
+C65 a_15_n150# a_207_n150# 0.16fF
+C66 a_687_n150# a_1071_n150# 0.07fF
+C67 a_n1229_n150# a_n1041_n150# 0.16fF
+C68 a_1167_n150# a_975_n150# 0.16fF
+C69 a_n561_n150# a_n657_n150# 0.43fF
+C70 a_n81_n150# a_n369_n150# 0.10fF
+C71 a_n945_n150# a_n657_n150# 0.10fF
+C72 a_n945_n150# a_n1041_n150# 0.43fF
+C73 a_n273_n150# a_n369_n150# 0.43fF
+C74 a_1167_n150# a_783_n150# 0.07fF
+C75 a_n945_n150# a_n1229_n150# 0.10fF
+C76 a_n1137_n150# a_n753_n150# 0.07fF
+C77 a_n561_n150# a_n945_n150# 0.07fF
+C78 a_399_n150# a_783_n150# 0.07fF
+C79 a_975_n150# w_n1367_n369# 0.05fF
+C80 a_879_n150# a_1071_n150# 0.16fF
+C81 a_15_n150# a_111_n150# 0.43fF
+C82 a_n1137_n150# a_n1041_n150# 0.43fF
+C83 a_n1137_n150# a_n1229_n150# 0.43fF
+C84 a_687_n150# a_591_n150# 0.43fF
+C85 a_15_n150# a_n177_n150# 0.16fF
+C86 a_783_n150# a_495_n150# 0.10fF
+C87 a_15_n150# a_303_n150# 0.10fF
+C88 a_1167_n150# a_1071_n150# 0.43fF
+C89 a_n945_n150# a_n1137_n150# 0.16fF
+C90 a_591_n150# a_207_n150# 0.07fF
+C91 a_n177_n150# a_n465_n150# 0.10fF
+C92 a_15_n150# a_399_n150# 0.07fF
+C93 a_15_n150# a_n81_n150# 0.43fF
+C94 a_687_n150# a_879_n150# 0.16fF
+C95 a_15_n150# a_n273_n150# 0.10fF
+C96 a_n81_n150# a_n465_n150# 0.07fF
+C97 a_n273_n150# a_n465_n150# 0.16fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump_pex_c vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 out vdd 6.70fF
+C1 biasp pswitch 3.02fF
+C2 nswitch pswitch 0.06fF
+C3 nUp pswitch 5.66fF
+C4 vdd biasp 2.64fF
+C5 nswitch vdd 0.07fF
+C6 nswitch nDown 0.48fF
+C7 nDown Down 0.13fF
+C8 iref biasp 0.80fF
+C9 nswitch iref 1.83fF
+C10 nUp Up 0.15fF
+C11 vdd pswitch 3.89fF
+C12 nswitch out 1.43fF
+C13 out nUp 0.31fF
+C14 pswitch Up 0.86fF
+C15 nswitch biasp 0.03fF
+C16 out pswitch 5.12fF
+C17 nswitch Down 2.26fF
+C18 Down nUp 0.25fF
+C19 vdd vss 35.71fF
+C20 nswitch vss 6.13fF
+C21 Down vss 4.77fF
+C22 nDown vss 1.11fF
+C23 Up vss 1.17fF
+C24 biasp vss 1.10fF
+C25 iref vss 10.11fF
+C26 out vss -3.12fF
+C27 pswitch vss 3.28fF
+C28 nUp vss 5.85fF
+.ends
+

diff --git a/xschem/simulations/clock_inverter.spice b/xschem/simulations/clock_inverter.spice
new file mode 100644
index 0000000..babdc08
--- /dev/null
+++ b/xschem/simulations/clock_inverter.spice

@@ -0,0 +1,47 @@
+**.subckt clock_inverter CLK vdd vss nCLK_d CLK_d
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+**.ends
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/csvco.spice b/xschem/simulations/csvco.spice
new file mode 100644
index 0000000..828d217
--- /dev/null
+++ b/xschem/simulations/csvco.spice

@@ -0,0 +1,62 @@
+**.subckt csvco vctrl vss vdd out D0
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x4 vdd vbp out out1 vctrl vss D0 csvco_branch
+x5 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x6 vdd vbp out2 out vctrl vss D0 csvco_branch
+**.ends
+
+* expanding   symbol:  ring_osc/sch/csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/ring_osc/sch/csvco_branch.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/ring_osc/sch/csvco_branch.sch
+.subckt csvco_branch  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding   symbol:  inverter_csvco/sch/inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/csvco_branch.spice b/xschem/simulations/csvco_branch.spice
new file mode 100644
index 0000000..c6afb0c
--- /dev/null
+++ b/xschem/simulations/csvco_branch.spice

@@ -0,0 +1,41 @@
+**.subckt csvco_branch vctrl vbp vdd vss in out D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+**.ends
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/csvco_pex_c.spice b/xschem/simulations/csvco_pex_c.spice
new file mode 100644
index 0000000..4241239
--- /dev/null
+++ b/xschem/simulations/csvco_pex_c.spice

@@ -0,0 +1,314 @@
+* NGSPICE file created from ring_osc.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_15_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# a_n73_n150# 0.01fF
+C1 a_n33_181# w_n211_n369# 0.05fF
+C2 w_n211_n369# a_n73_n150# 0.20fF
+C3 a_15_n150# a_n33_181# 0.01fF
+C4 a_15_n150# a_n73_n150# 0.51fF
+C5 a_15_n150# w_n211_n369# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n150# a_n321_n150# 0.10fF
+C1 a_n129_n150# a_n225_n150# 0.43fF
+C2 a_447_n150# a_n465_172# 0.01fF
+C3 a_63_n150# a_159_n150# 0.43fF
+C4 a_n509_n150# a_n417_n150# 0.43fF
+C5 a_n509_n150# a_n465_172# 0.01fF
+C6 a_n465_172# a_159_n150# 0.10fF
+C7 a_n33_n150# a_n129_n150# 0.43fF
+C8 a_n225_n150# a_n509_n150# 0.10fF
+C9 a_n225_n150# a_159_n150# 0.07fF
+C10 a_255_n150# a_n129_n150# 0.07fF
+C11 a_n129_n150# a_n321_n150# 0.16fF
+C12 a_447_n150# a_351_n150# 0.43fF
+C13 a_63_n150# a_n465_172# 0.10fF
+C14 a_255_n150# a_447_n150# 0.16fF
+C15 a_63_n150# a_n225_n150# 0.10fF
+C16 a_n465_172# a_n417_n150# 0.10fF
+C17 a_351_n150# a_159_n150# 0.16fF
+C18 a_n33_n150# a_159_n150# 0.16fF
+C19 a_n225_n150# a_n417_n150# 0.16fF
+C20 a_n321_n150# a_n509_n150# 0.16fF
+C21 a_n225_n150# a_n465_172# 0.10fF
+C22 a_255_n150# a_159_n150# 0.43fF
+C23 a_351_n150# a_63_n150# 0.10fF
+C24 a_63_n150# a_n33_n150# 0.43fF
+C25 a_255_n150# a_63_n150# 0.16fF
+C26 a_n33_n150# a_n417_n150# 0.07fF
+C27 a_63_n150# a_n321_n150# 0.07fF
+C28 a_351_n150# a_n465_172# 0.10fF
+C29 a_n129_n150# a_n509_n150# 0.07fF
+C30 a_n33_n150# a_n465_172# 0.10fF
+C31 a_n129_n150# a_159_n150# 0.10fF
+C32 a_255_n150# a_n465_172# 0.10fF
+C33 a_n33_n150# a_n225_n150# 0.16fF
+C34 a_n321_n150# a_n417_n150# 0.43fF
+C35 a_n321_n150# a_n465_172# 0.10fF
+C36 a_n225_n150# a_n321_n150# 0.43fF
+C37 a_447_n150# a_159_n150# 0.10fF
+C38 a_63_n150# a_n129_n150# 0.16fF
+C39 a_351_n150# a_n33_n150# 0.07fF
+C40 a_n129_n150# a_n417_n150# 0.10fF
+C41 a_n129_n150# a_n465_172# 0.10fF
+C42 a_447_n150# a_63_n150# 0.07fF
+C43 a_255_n150# a_351_n150# 0.43fF
+C44 a_255_n150# a_n33_n150# 0.10fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n321_n150# a_n129_n150# 0.16fF
+C1 w_n647_n369# a_n129_n150# 0.02fF
+C2 w_n647_n369# a_351_n150# 0.07fF
+C3 a_n417_n150# a_n129_n150# 0.10fF
+C4 a_n465_n247# a_63_n150# 0.08fF
+C5 a_159_n150# w_n647_n369# 0.04fF
+C6 a_159_n150# a_n129_n150# 0.10fF
+C7 a_n321_n150# a_n33_n150# 0.10fF
+C8 w_n647_n369# a_n33_n150# 0.02fF
+C9 a_159_n150# a_351_n150# 0.16fF
+C10 a_255_n150# a_447_n150# 0.16fF
+C11 a_n417_n150# a_n33_n150# 0.07fF
+C12 a_255_n150# a_63_n150# 0.16fF
+C13 a_n129_n150# a_n33_n150# 0.43fF
+C14 a_n33_n150# a_351_n150# 0.07fF
+C15 a_n225_n150# a_n321_n150# 0.43fF
+C16 a_n225_n150# w_n647_n369# 0.04fF
+C17 a_159_n150# a_n33_n150# 0.16fF
+C18 a_n417_n150# a_n225_n150# 0.16fF
+C19 a_n225_n150# a_n129_n150# 0.43fF
+C20 w_n647_n369# a_447_n150# 0.14fF
+C21 a_n321_n150# a_63_n150# 0.07fF
+C22 w_n647_n369# a_63_n150# 0.02fF
+C23 a_255_n150# a_n465_n247# 0.08fF
+C24 a_159_n150# a_n225_n150# 0.07fF
+C25 a_n321_n150# a_n509_n150# 0.16fF
+C26 w_n647_n369# a_n509_n150# 0.14fF
+C27 a_351_n150# a_447_n150# 0.43fF
+C28 a_n129_n150# a_63_n150# 0.16fF
+C29 a_63_n150# a_351_n150# 0.10fF
+C30 a_n417_n150# a_n509_n150# 0.43fF
+C31 a_n129_n150# a_n509_n150# 0.07fF
+C32 a_n225_n150# a_n33_n150# 0.16fF
+C33 a_159_n150# a_447_n150# 0.10fF
+C34 a_159_n150# a_63_n150# 0.43fF
+C35 a_n321_n150# a_n465_n247# 0.08fF
+C36 a_n465_n247# w_n647_n369# 0.47fF
+C37 a_63_n150# a_n33_n150# 0.43fF
+C38 a_n417_n150# a_n465_n247# 0.08fF
+C39 a_n465_n247# a_n129_n150# 0.08fF
+C40 a_n465_n247# a_351_n150# 0.08fF
+C41 a_159_n150# a_n465_n247# 0.08fF
+C42 a_255_n150# w_n647_n369# 0.05fF
+C43 a_n225_n150# a_63_n150# 0.10fF
+C44 a_n225_n150# a_n509_n150# 0.10fF
+C45 a_255_n150# a_n129_n150# 0.07fF
+C46 a_n465_n247# a_n33_n150# 0.08fF
+C47 a_255_n150# a_351_n150# 0.43fF
+C48 a_63_n150# a_447_n150# 0.07fF
+C49 a_255_n150# a_159_n150# 0.43fF
+C50 a_n321_n150# w_n647_n369# 0.05fF
+C51 a_n225_n150# a_n465_n247# 0.08fF
+C52 a_n417_n150# a_n321_n150# 0.43fF
+C53 a_255_n150# a_n33_n150# 0.10fF
+C54 a_n417_n150# w_n647_n369# 0.07fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_n73_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out in 0.11fF
+C1 out vbulkp 0.08fF
+C2 vdd in 0.01fF
+C3 vdd vbulkp 0.04fF
+C4 vss in 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out inverter_csvco_0/vss vss vdd
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vbp vdd 1.21fF
+C1 out inverter_csvco_0/vss 0.03fF
+C2 D0 inverter_csvco_0/vss 0.02fF
+C3 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C4 out in 0.06fF
+C5 out D0 0.09fF
+C6 vdd cap_vco_0/t 0.04fF
+C7 inverter_csvco_0/vdd vdd 1.89fF
+C8 inverter_csvco_0/vdd in 0.01fF
+C9 out cap_vco_0/t 0.70fF
+C10 inverter_csvco_0/vdd out 0.02fF
+C11 inverter_csvco_0/vdd vbp 0.75fF
+C12 in inverter_csvco_0/vss 0.01fF
+C13 vctrl inverter_csvco_0/vss 0.87fF
+C14 out vss 0.93fF
+C15 inverter_csvco_0/vdd vss 0.26fF
+C16 in vss 0.69fF
+C17 D0 vss -0.67fF
+C18 vbp vss 0.13fF
+C19 vdd vss 9.58fF
+C20 cap_vco_0/t vss 7.22fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt csvco_pex_c vdd out_vco vctrl vss D0
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ csvco_branch_0/inverter_csvco_0/vss vss vdd csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss vss vdd csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco csvco_branch_2/inverter_csvco_0/vss vss vdd csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+C0 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C1 csvco_branch_2/in out_vco 0.58fF
+C2 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C3 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C4 csvco_branch_2/vbp vdd 1.49fF
+C5 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C6 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C7 out_vco csvco_branch_1/in 0.76fF
+C8 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C9 vctrl csvco_branch_2/vbp 0.06fF
+C10 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C11 csvco_branch_1/inverter_csvco_0/vdd vdd 0.19fF
+C12 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C13 vctrl D0 4.41fF
+C14 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C15 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C16 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C17 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C18 csvco_branch_2/in vss 1.60fF
+C19 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C20 vdd vss 31.40fF
+C21 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C22 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C23 csvco_branch_1/in vss 1.58fF
+C24 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C25 out_vco vss 0.67fF
+C26 D0 vss -1.21fF
+C27 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+

diff --git a/xschem/current_test.spice b/xschem/simulations/current_test.spice
similarity index 100%
rename from xschem/current_test.spice
rename to xschem/simulations/current_test.spice


diff --git a/xschem/simulations/dff_pfd_pex_c.spice b/xschem/simulations/dff_pfd_pex_c.spice
new file mode 100644
index 0000000..a49bac6
--- /dev/null
+++ b/xschem/simulations/dff_pfd_pex_c.spice

@@ -0,0 +1,116 @@
+* NGSPICE file created from dff_pfd.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 w_n359_n309# a_159_n90# 0.09fF
+C1 a_n33_n90# w_n359_n309# 0.05fF
+C2 a_n33_n90# a_159_n90# 0.09fF
+C3 a_n221_n90# a_63_n90# 0.06fF
+C4 a_63_n90# w_n359_n309# 0.06fF
+C5 a_n129_n90# a_n221_n90# 0.26fF
+C6 a_63_n90# a_159_n90# 0.26fF
+C7 a_63_n90# a_n33_n90# 0.26fF
+C8 a_n129_n90# w_n359_n309# 0.06fF
+C9 a_n129_n90# a_159_n90# 0.06fF
+C10 a_n129_n90# a_n33_n90# 0.26fF
+C11 a_n159_n207# a_n63_n116# 0.12fF
+C12 a_n221_n90# w_n359_n309# 0.09fF
+C13 a_n221_n90# a_159_n90# 0.04fF
+C14 a_n221_n90# a_n33_n90# 0.09fF
+C15 a_n129_n90# a_63_n90# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_33_n71# a_n129_71# 0.04fF
+C2 a_n125_n45# a_n33_n45# 0.13fF
+C3 a_n125_n45# a_63_n45# 0.05fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
+C1 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C2 A vdd 0.09fF
+C3 A B 0.24fF
+C4 A out 0.06fF
+C5 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C6 vdd out 0.11fF
+C7 B out 0.40fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd_pex_c vdd CLK Q Reset vss
+Xnor_pfd_0 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd CLK Q nor_pfd
+Xnor_pfd_1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss vdd nor_pfd_3/A Reset nor_pfd
+C0 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C1 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C2 nor_pfd_3/A vdd 0.09fF
+C3 Q nor_pfd_2/B 2.22fF
+C4 Q nor_pfd_2/A 1.38fF
+C5 Q Reset 0.14fF
+C6 Q CLK 0.04fF
+C7 nor_pfd_2/B vdd 0.02fF
+C8 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C9 vdd nor_pfd_2/A -0.01fF
+C10 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C11 nor_pfd_3/A Reset 0.12fF
+C12 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C13 Q vdd 0.08fF
+C14 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C15 Q nor_pfd_3/A 0.98fF
+C16 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C17 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C18 nor_pfd_2/B Reset 0.43fF
+C19 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 Reset vss 1.48fF
+C23 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C25 nor_pfd_2/A vss 2.56fF
+C26 nor_pfd_2/B vss 1.42fF
+C27 vdd vss 16.42fF
+C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C29 Q vss 0.26fF
+C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C31 nor_pfd_3/A vss 3.16fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+

diff --git a/xschem/simulations/div_by_2.spice b/xschem/simulations/div_by_2.spice
new file mode 100644
index 0000000..4347632
--- /dev/null
+++ b/xschem/simulations/div_by_2.spice

@@ -0,0 +1,149 @@
+**.subckt div_by_2 CLK CLK_2 vss vdd nCLK_2 nout_div o2 o1 out_div
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+**.ends
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/div_by_2_pex_c.spice b/xschem/simulations/div_by_2_pex_c.spice
new file mode 100644
index 0000000..54bb1f2
--- /dev/null
+++ b/xschem/simulations/div_by_2_pex_c.spice

@@ -0,0 +1,448 @@
+* NGSPICE file created from div_by_2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH_div2 VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_15_n125# w_n311_n344# 0.09fF
+C2 a_n15_n156# a_n111_n156# 0.02fF
+C3 a_111_n125# w_n311_n344# 0.14fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_n81_n125# w_n311_n344# 0.09fF
+C7 a_15_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_n173_n125# 0.14fF
+C9 a_111_n125# a_n81_n125# 0.13fF
+C10 a_n15_n156# a_81_n156# 0.02fF
+C11 a_15_n125# a_n173_n125# 0.13fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T_div2 a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n15_n151# a_81_n151# 0.02fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n81_n125# a_n173_n125# 0.36fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n111_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate_div2 m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH_div2
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T_div2
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_45_n513# m1_187_n605# 0.36fF
+C2 vdd m1_187_n605# 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH_div2 VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_n81_n125# w_n311_n344# 0.09fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 w_n311_n344# a_n173_n125# 0.14fF
+C7 a_111_n125# a_n173_n125# 0.08fF
+C8 a_111_n125# w_n311_n344# 0.14fF
+C9 a_15_n125# a_n81_n125# 0.36fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM_div2 w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_15_n125# a_n173_n125# 0.13fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1_div2 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH_div2
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM_div2
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter_div2 vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out CLK CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate_div2
+Xinverter_cp_x1_0 CLK inverter_cp_x1_0/out vss vdd inverter_cp_x1_div2
+Xinverter_cp_x1_1 CLK inverter_cp_x1_2/in vss vdd inverter_cp_x1_div2
+Xinverter_cp_x1_2 inverter_cp_x1_2/in CLK_d vss vdd inverter_cp_x1_div2
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 inverter_cp_x1_2/in CLK_d 0.12fF
+C2 CLK inverter_cp_x1_0/out 0.31fF
+C3 vdd CLK_d 0.03fF
+C4 vdd inverter_cp_x1_0/out 0.28fF
+C5 vdd nCLK_d 0.03fF
+C6 nCLK_d inverter_cp_x1_0/out 0.11fF
+C7 CLK inverter_cp_x1_2/in 0.31fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ_div2 VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n125_n95# 0.11fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 a_63_n95# a_n125_n95# 0.10fF
+C3 a_63_n95# w_n263_n314# 0.11fF
+C4 a_n33_n95# a_n125_n95# 0.28fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854_div2 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_n129_n213# a_n81_n125# 0.10fF
+C3 a_n173_n125# a_n81_n125# 0.36fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_n173_n125# a_n129_n213# 0.02fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_111_n125# a_n129_n213# 0.01fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX_div2 a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n125_n95# a_n33_n95# 0.88fF
+C2 a_n125_n95# a_n81_n183# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff_div2 m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ_div2
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ_div2
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854_div2
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX_div2
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX_div2
+C0 Q m1_657_280# 0.94fF
+C1 Q nD 0.05fF
+C2 D Q 0.05fF
+C3 nQ Q 0.93fF
+C4 vdd Q 0.16fF
+C5 CLK m1_657_280# 0.24fF
+C6 nQ m1_657_280# 1.41fF
+C7 nQ nD 0.05fF
+C8 D nQ 0.05fF
+C9 vdd nQ 0.16fF
+C10 D vss 0.53fF
+C11 Q vss -0.55fF
+C12 m1_657_280# vss 1.88fF
+C13 nD vss 0.16fF
+C14 CLK vss 0.87fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop_div2 vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in nQ Q latch_diff_1/m1_657_280#
++ latch_diff_1/nD vdd clock_inverter_0/inverter_cp_x1_0/out CLK latch_diff_0/D nCLK
++ D latch_diff_0/nD latch_diff_0/m1_657_280#
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in vdd clock_inverter_0/inverter_cp_x1_0/out
++ D latch_diff_0/D latch_diff_0/nD clock_inverter_div2
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff_div2
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff_div2
+C0 latch_diff_1/nD vdd 0.02fF
+C1 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C2 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C3 latch_diff_1/nD Q 0.01fF
+C4 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C5 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C6 latch_diff_1/D nQ 0.11fF
+C7 latch_diff_1/nD latch_diff_0/D 0.04fF
+C8 latch_diff_1/D vdd 0.03fF
+C9 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C10 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C11 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C12 latch_diff_0/nD latch_diff_1/D 0.41fF
+C13 latch_diff_1/D latch_diff_0/D 0.11fF
+C14 latch_diff_1/D latch_diff_1/nD 0.33fF
+C15 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C16 nQ latch_diff_1/nD 0.08fF
+C17 latch_diff_0/nD vdd 0.14fF
+C18 vdd latch_diff_0/D 0.09fF
+C19 Q vss -0.92fF
+C20 latch_diff_1/m1_657_280# vss 0.64fF
+C21 nCLK vss 0.83fF
+C22 nQ vss 0.57fF
+C23 latch_diff_1/D vss -0.30fF
+C24 latch_diff_0/m1_657_280# vss 0.72fF
+C25 CLK vss 0.83fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_div2 VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_129_n110# a_33_n110# 0.02fF
+C1 w_n359_n303# a_63_n84# 0.06fF
+C2 a_159_n84# a_n221_n84# 0.04fF
+C3 a_n159_n110# a_n63_n110# 0.02fF
+C4 w_n359_n303# a_n33_n84# 0.05fF
+C5 a_n129_n84# a_63_n84# 0.09fF
+C6 a_n33_n84# a_n129_n84# 0.24fF
+C7 w_n359_n303# a_n221_n84# 0.08fF
+C8 a_159_n84# w_n359_n303# 0.08fF
+C9 a_n63_n110# a_33_n110# 0.02fF
+C10 a_n221_n84# a_n129_n84# 0.24fF
+C11 a_159_n84# a_n129_n84# 0.05fF
+C12 a_n33_n84# a_63_n84# 0.24fF
+C13 a_n221_n84# a_63_n84# 0.05fF
+C14 a_159_n84# a_63_n84# 0.24fF
+C15 w_n359_n303# a_n129_n84# 0.06fF
+C16 a_n221_n84# a_n33_n84# 0.09fF
+C17 a_159_n84# a_n33_n84# 0.09fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_div2 w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n129_n42# a_63_n42# 0.05fF
+C1 a_n221_n42# a_n33_n42# 0.05fF
+C2 a_n129_n42# a_159_n42# 0.03fF
+C3 a_n221_n42# a_63_n42# 0.03fF
+C4 a_n33_n42# a_63_n42# 0.12fF
+C5 a_n221_n42# a_159_n42# 0.02fF
+C6 a_n33_n42# a_159_n42# 0.05fF
+C7 a_n129_n42# a_n221_n42# 0.12fF
+C8 a_n63_n68# a_33_n68# 0.02fF
+C9 a_129_n68# a_33_n68# 0.02fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_n129_n42# a_n33_n42# 0.12fF
+C12 a_n63_n68# a_n159_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_div2 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_div2
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_div2
+C0 out in 0.67fF
+C1 vdd in 0.33fF
+C2 out vdd 0.62fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_div2 a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_n63_n68# 0.02fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_n125_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_div2 VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_63_n84# 0.24fF
+C1 a_n33_n84# w_n263_n303# 0.07fF
+C2 a_n33_n84# a_n125_n84# 0.24fF
+C3 w_n263_n303# a_63_n84# 0.10fF
+C4 a_n125_n84# a_63_n84# 0.09fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 w_n263_n303# a_n125_n84# 0.10fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_div2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_div2
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_div2
+C0 in vdd 0.01fF
+C1 out vdd 0.15fF
+C2 out in 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2_pex_c nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+XDFlipFlop_0 vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_1/nD
++ vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/D
++ DFlipFlop_0/nCLK nout_div DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/latch_diff_0/m1_657_280#
++ DFlipFlop_div2
+Xinverter_min_x4_1 o2 nCLK_2 vss vdd inverter_min_x4_div2
+Xinverter_min_x4_0 o1 CLK_2 vss vdd inverter_min_x4_div2
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in vdd clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter_div2
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2_div2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2_div2
+C0 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C1 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C2 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C3 o1 out_div 0.01fF
+C4 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C5 vdd out_div 0.03fF
+C6 vdd o2 0.14fF
+C7 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C8 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C9 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C10 DFlipFlop_0/nCLK vdd 0.30fF
+C11 vdd nCLK_2 0.08fF
+C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C13 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C14 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C15 vdd o1 0.14fF
+C16 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C17 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C18 nout_div out_div 0.22fF
+C19 o1 CLK_2 0.11fF
+C20 vdd DFlipFlop_0/CLK 0.40fF
+C21 vdd CLK_2 0.08fF
+C22 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C23 DFlipFlop_0/nCLK nout_div 0.43fF
+C24 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C25 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C26 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C27 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C29 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C30 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C31 vdd nout_div 0.16fF
+C32 o2 nCLK_2 0.11fF
+C33 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C34 nout_div DFlipFlop_0/CLK 0.42fF
+C35 DFlipFlop_0/CLK vss 1.03fF
+C36 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
+C44 out_div vss -1.37fF
+C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C46 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C47 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C52 nout_div vss 4.86fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+

diff --git a/xschem/simulations/div_by_5.spice b/xschem/simulations/div_by_5.spice
new file mode 100644
index 0000000..bfac654
--- /dev/null
+++ b/xschem/simulations/div_by_5.spice

@@ -0,0 +1,118 @@
+**.subckt div_by_5 vdd vss CLK CLK_5 nCLK nQ2 Q1 Q0 nQ0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+**.ends
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/div_by_5_pex_c.spice b/xschem/simulations/div_by_5_pex_c.spice
new file mode 100644
index 0000000..f087166
--- /dev/null
+++ b/xschem/simulations/div_by_5_pex_c.spice

@@ -0,0 +1,595 @@
+* NGSPICE file created from div_by_5.ext - technology: sky130A
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 X a_194_125# 0.29fF
+C1 a_194_125# A 0.18fF
+C2 a_194_125# B 0.57fF
+C3 X VPWR 0.07fF
+C4 X VGND 0.28fF
+C5 VPWR A 0.15fF
+C6 A VGND 0.31fF
+C7 a_355_368# a_194_125# 0.51fF
+C8 VPWR B 0.09fF
+C9 B VGND 0.10fF
+C10 VPWR a_355_368# 0.37fF
+C11 a_194_125# a_158_392# 0.06fF
+C12 VPWR a_194_125# 0.33fF
+C13 a_194_125# VGND 0.25fF
+C14 X B 0.13fF
+C15 A B 0.28fF
+C16 VPWR VPB 0.06fF
+C17 X a_355_368# 0.17fF
+C18 a_355_368# A 0.02fF
+C19 VPWR VGND 0.01fF
+C20 a_355_368# B 0.08fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# w_n311_n344# 0.14fF
+C2 a_n173_n125# a_n81_n125# 0.36fF
+C3 a_81_n156# a_n15_n156# 0.02fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# w_n311_n344# 0.14fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n111_n156# a_n15_n156# 0.02fF
+C8 w_n311_n344# a_n81_n125# 0.09fF
+C9 a_15_n125# a_111_n125# 0.36fF
+C10 a_15_n125# w_n311_n344# 0.09fF
+C11 a_n173_n125# a_111_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_81_n151# a_n15_n151# 0.02fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_n15_n151# a_n111_n151# 0.02fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_15_n125# a_n173_n125# 0.13fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# m1_45_n513# 0.36fF
+C1 vdd m1_45_n513# 0.69fF
+C2 vdd m1_187_n605# 0.55fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_15_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_15_n125# a_n81_n125# 0.36fF
+C3 w_n311_n344# a_15_n125# 0.09fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n344# 0.14fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 a_n173_n125# w_n311_n344# 0.14fF
+C9 w_n311_n344# a_n81_n125# 0.09fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n81_n125# a_111_n125# 0.13fF
+C2 a_111_n125# a_15_n125# 0.36fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.21fF
+C1 CLK inverter_cp_x1_2/in 0.31fF
+C2 CLK_d vdd 0.03fF
+C3 nCLK_d vdd 0.03fF
+C4 CLK vdd 0.36fF
+C5 CLK_d inverter_cp_x1_2/in 0.12fF
+C6 inverter_cp_x1_0/out vdd 0.28fF
+C7 inverter_cp_x1_0/out nCLK_d 0.11fF
+C8 inverter_cp_x1_0/out CLK 0.31fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 CLK vss 3.03fF
+C12 inverter_cp_x1_0/out vss 1.97fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_63_n95# 0.11fF
+C1 a_n125_n95# a_63_n95# 0.10fF
+C2 a_n33_n95# w_n263_n314# 0.08fF
+C3 a_n125_n95# a_n33_n95# 0.28fF
+C4 a_n33_n95# a_63_n95# 0.28fF
+C5 a_n125_n95# w_n263_n314# 0.11fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n129_n213# 0.02fF
+C1 a_n81_n125# a_n173_n125# 0.36fF
+C2 a_n129_n213# a_111_n125# 0.01fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_15_n125# a_n129_n213# 0.10fF
+C6 a_n81_n125# a_15_n125# 0.36fF
+C7 a_15_n125# a_n173_n125# 0.13fF
+C8 a_15_n125# a_111_n125# 0.36fF
+C9 a_n81_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n81_n183# 0.16fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ D 0.05fF
+C1 nQ nD 0.05fF
+C2 nQ Q 0.93fF
+C3 nQ vdd 0.16fF
+C4 nQ m1_657_280# 1.41fF
+C5 D Q 0.05fF
+C6 nD Q 0.05fF
+C7 vdd Q 0.16fF
+C8 m1_657_280# CLK 0.24fF
+C9 Q m1_657_280# 0.94fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D vdd
++ CLK clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/nD latch_diff_1/D 0.41fF
+C1 latch_diff_1/nD Q 0.01fF
+C2 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C3 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C4 latch_diff_1/nD vdd 0.02fF
+C5 latch_diff_0/D latch_diff_1/D 0.11fF
+C6 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
+C7 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
+C8 latch_diff_1/nD latch_diff_1/D 0.33fF
+C9 vdd latch_diff_1/D 0.03fF
+C10 latch_diff_1/nD nQ 0.08fF
+C11 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C12 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C13 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C14 vdd latch_diff_0/nD 0.14fF
+C15 latch_diff_1/nD latch_diff_0/D 0.04fF
+C16 nQ latch_diff_1/D 0.11fF
+C17 latch_diff_0/D vdd 0.09fF
+C18 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.72fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.30fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 D vss 3.27fF
+C30 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 X VGND 0.15fF
+C1 A VGND 0.21fF
+C2 VPWR a_56_136# 0.57fF
+C3 B X 0.02fF
+C4 B A 0.08fF
+C5 a_56_136# VGND 0.06fF
+C6 VPWR VPB 0.04fF
+C7 B a_56_136# 0.30fF
+C8 VPWR B 0.02fF
+C9 a_56_136# X 0.26fF
+C10 a_56_136# A 0.17fF
+C11 VPWR X 0.20fF
+C12 VPWR A 0.07fF
+C13 B VGND 0.03fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 B a_63_368# 0.14fF
+C1 A B 0.10fF
+C2 VGND X 0.16fF
+C3 VGND a_63_368# 0.27fF
+C4 VPWR X 0.18fF
+C5 VPWR a_63_368# 0.29fF
+C6 a_152_368# a_63_368# 0.03fF
+C7 A VPWR 0.05fF
+C8 VGND B 0.11fF
+C9 X a_63_368# 0.33fF
+C10 B VPWR 0.01fF
+C11 A X 0.02fF
+C12 VPB VPWR 0.04fF
+C13 A a_63_368# 0.28fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5_pex_c vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280#
++ DFlipFlop_0/D DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 DFlipFlop_1/latch_diff_0/nD Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280#
++ DFlipFlop_1/D DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280#
++ DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD Q1_shift DFlipFlop_3/latch_diff_1/nD
++ DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C1 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C2 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C3 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C4 nQ0 vdd 0.11fF
+C5 DFlipFlop_0/D Q0 0.39fF
+C6 DFlipFlop_1/D vdd 0.25fF
+C7 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C8 vdd CLK_5 0.15fF
+C9 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C10 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C11 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C12 Q0 CLK 0.08fF
+C13 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C14 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C15 DFlipFlop_1/D nQ0 0.12fF
+C16 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C17 DFlipFlop_3/nQ vdd 0.02fF
+C18 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C19 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C20 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C21 DFlipFlop_2/nQ nCLK 0.09fF
+C22 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C23 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C24 CLK nQ2 0.17fF
+C25 DFlipFlop_0/D vdd 0.19fF
+C26 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C27 CLK vdd 0.41fF
+C28 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C29 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C30 Q1 DFlipFlop_0/Q 0.13fF
+C31 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C32 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C33 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C34 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C35 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C36 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C37 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C38 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C39 nQ0 CLK 0.19fF
+C40 DFlipFlop_2/nQ vdd 0.02fF
+C41 Q1 Q1_shift 0.36fF
+C42 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C43 DFlipFlop_1/D CLK 0.21fF
+C44 Q1 DFlipFlop_2/D 0.10fF
+C45 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C46 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C47 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C48 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C49 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C50 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C51 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C52 DFlipFlop_3/nQ CLK 0.01fF
+C53 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C54 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C55 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C56 DFlipFlop_0/Q Q0 0.21fF
+C57 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C58 nCLK DFlipFlop_0/Q 0.11fF
+C59 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C60 sky130_fd_sc_hs__xor2_1_0/a_355_368# Q0 0.03fF
+C61 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C62 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C63 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C64 DFlipFlop_2/D Q0 0.25fF
+C65 DFlipFlop_2/D nCLK 0.41fF
+C66 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
+C67 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C68 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C69 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C70 DFlipFlop_0/Q nQ2 0.09fF
+C71 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C72 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C73 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C74 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C75 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C76 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C77 DFlipFlop_2/nQ CLK 0.13fF
+C78 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C79 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
+C80 Q1 Q0 9.65fF
+C81 Q1 nCLK -0.01fF
+C82 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C83 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C84 Q1_shift vdd 0.10fF
+C85 DFlipFlop_2/D vdd 0.07fF
+C86 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C87 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C88 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C89 Q1 nQ2 0.07fF
+C90 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C91 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C92 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C93 Q1 vdd 9.49fF
+C94 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C95 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C96 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C97 nCLK Q0 0.20fF
+C98 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C99 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C100 DFlipFlop_3/nQ Q1_shift 0.04fF
+C101 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
+C102 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C103 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C104 Q1 nQ0 0.06fF
+C105 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C106 Q1 DFlipFlop_1/D 0.03fF
+C107 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
+C108 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C109 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C110 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C111 DFlipFlop_0/Q CLK 0.08fF
+C112 Q0 nQ2 0.23fF
+C113 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C114 nCLK nQ2 0.10fF
+C115 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C116 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C117 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C118 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C119 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C120 Q1 DFlipFlop_3/nQ 0.10fF
+C121 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C122 Q0 vdd 5.33fF
+C123 nCLK vdd 0.34fF
+C124 DFlipFlop_2/D CLK 0.14fF
+C125 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C126 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C127 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C128 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
+C129 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C130 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C131 Q1 DFlipFlop_0/D 0.13fF
+C132 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C133 nQ0 Q0 0.33fF
+C134 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C135 nQ0 nCLK 0.09fF
+C136 DFlipFlop_1/D Q0 0.07fF
+C137 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C138 DFlipFlop_1/D nCLK 0.14fF
+C139 Q1 CLK -0.10fF
+C140 vdd nQ2 0.04fF
+C141 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C142 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C143 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C144 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C145 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C146 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C147 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C148 Q1 DFlipFlop_2/nQ 0.31fF
+C149 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C150 nQ0 nQ2 0.03fF
+C151 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C152 nCLK DFlipFlop_3/nQ 0.02fF
+C153 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C154 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C155 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C156 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -1.63fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 Q1 vss 1.26fF
+C170 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/D vss 5.34fF
+C180 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C183 Q0 vss 0.53fF
+C184 nQ0 vss 1.84fF
+C185 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/D vss 3.72fF
+C191 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 4.92fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 4.85fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/D vss 4.04fF
+C204 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+

diff --git a/xschem/example_por_tb.spice b/xschem/simulations/example_por_tb.spice
similarity index 100%
rename from xschem/example_por_tb.spice
rename to xschem/simulations/example_por_tb.spice


diff --git a/xschem/simulations/inverter_cp_x1.spice b/xschem/simulations/inverter_cp_x1.spice
new file mode 100644
index 0000000..e7fa406
--- /dev/null
+++ b/xschem/simulations/inverter_cp_x1.spice

@@ -0,0 +1,14 @@
+**.subckt inverter_cp_x1 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/inverter_cp_x2.spice b/xschem/simulations/inverter_cp_x2.spice
new file mode 100644
index 0000000..7b8d413
--- /dev/null
+++ b/xschem/simulations/inverter_cp_x2.spice

@@ -0,0 +1,14 @@
+**.subckt inverter_cp_x2 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/inverter_csvco.spice b/xschem/simulations/inverter_csvco.spice
new file mode 100644
index 0000000..ccb62c1
--- /dev/null
+++ b/xschem/simulations/inverter_csvco.spice

@@ -0,0 +1,16 @@
+**.subckt inverter_csvco vss in out vdd vbulkn vbulkp
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/inverter_csvco_pex_c.spice b/xschem/simulations/inverter_csvco_pex_c.spice
new file mode 100644
index 0000000..8a84801
--- /dev/null
+++ b/xschem/simulations/inverter_csvco_pex_c.spice

@@ -0,0 +1,37 @@
+* NGSPICE file created from inverter_csvco.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 w_n216_n334# a_n78_n114# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco_pex_c vdd out in vss vbulkp vbulkn
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd vbulkp 0.04fF
+C1 in vss 0.01fF
+C2 in out 0.11fF
+C3 vbulkp out 0.08fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+

diff --git a/xschem/simulations/inverter_min_x2.spice b/xschem/simulations/inverter_min_x2.spice
new file mode 100644
index 0000000..4f0dc98
--- /dev/null
+++ b/xschem/simulations/inverter_min_x2.spice

@@ -0,0 +1,14 @@
+**.subckt inverter_min_x2 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/inverter_min_x2_pex_c.spice b/xschem/simulations/inverter_min_x2_pex_c.spice
new file mode 100644
index 0000000..fef0f8e
--- /dev/null
+++ b/xschem/simulations/inverter_min_x2_pex_c.spice

@@ -0,0 +1,47 @@
+* NGSPICE file created from inverter_min_x2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_inv2 a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n125_n42# a_63_n42# 0.05fF
+C1 a_63_n42# a_n33_n42# 0.12fF
+C2 a_n125_n42# a_n33_n42# 0.12fF
+C3 a_33_n68# a_n63_n68# 0.02fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_inv2 VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n33_n84# a_n125_n84# 0.24fF
+C1 a_63_n84# a_n33_n84# 0.24fF
+C2 a_n125_n84# w_n263_n303# 0.10fF
+C3 a_63_n84# w_n263_n303# 0.10fF
+C4 a_33_n110# a_n63_n110# 0.02fF
+C5 a_63_n84# a_n125_n84# 0.09fF
+C6 a_n33_n84# w_n263_n303# 0.07fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_pex_c vdd out in vss
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_inv2
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_inv2
+C0 out vdd 0.15fF
+C1 out in 0.30fF
+C2 vdd in 0.01fF
+C3 out vss 0.66fF
+C4 in vss 0.72fF
+C5 vdd vss 2.93fF
+.ends
+

diff --git a/xschem/simulations/inverter_min_x4.spice b/xschem/simulations/inverter_min_x4.spice
new file mode 100644
index 0000000..3c9ede2
--- /dev/null
+++ b/xschem/simulations/inverter_min_x4.spice

@@ -0,0 +1,14 @@
+**.subckt inverter_min_x4 vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/inverter_min_x4_pex_c.spice b/xschem/simulations/inverter_min_x4_pex_c.spice
new file mode 100644
index 0000000..379107d
--- /dev/null
+++ b/xschem/simulations/inverter_min_x4_pex_c.spice

@@ -0,0 +1,79 @@
+* NGSPICE file created from inverter_min_x4.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_inv4 VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n221_n84# 0.24fF
+C1 w_n359_n303# a_n33_n84# 0.05fF
+C2 a_159_n84# a_n33_n84# 0.09fF
+C3 a_63_n84# a_n221_n84# 0.05fF
+C4 a_159_n84# w_n359_n303# 0.08fF
+C5 a_33_n110# a_n63_n110# 0.02fF
+C6 a_129_n110# a_33_n110# 0.02fF
+C7 a_63_n84# a_n129_n84# 0.09fF
+C8 a_n221_n84# a_n33_n84# 0.09fF
+C9 w_n359_n303# a_n221_n84# 0.08fF
+C10 a_159_n84# a_n221_n84# 0.04fF
+C11 a_n129_n84# a_n33_n84# 0.24fF
+C12 a_n159_n110# a_n63_n110# 0.02fF
+C13 w_n359_n303# a_n129_n84# 0.06fF
+C14 a_159_n84# a_n129_n84# 0.05fF
+C15 a_63_n84# a_n33_n84# 0.24fF
+C16 a_63_n84# w_n359_n303# 0.06fF
+C17 a_159_n84# a_63_n84# 0.24fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_inv4 w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_63_n42# a_n33_n42# 0.12fF
+C1 a_n129_n42# a_n33_n42# 0.12fF
+C2 a_33_n68# a_n63_n68# 0.02fF
+C3 a_n129_n42# a_63_n42# 0.05fF
+C4 a_n159_n68# a_n63_n68# 0.02fF
+C5 a_159_n42# a_n221_n42# 0.02fF
+C6 a_33_n68# a_129_n68# 0.02fF
+C7 a_n221_n42# a_n33_n42# 0.05fF
+C8 a_159_n42# a_n33_n42# 0.05fF
+C9 a_n221_n42# a_63_n42# 0.03fF
+C10 a_n129_n42# a_n221_n42# 0.12fF
+C11 a_159_n42# a_63_n42# 0.12fF
+C12 a_n129_n42# a_159_n42# 0.03fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_pex_c vdd out in vss
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_inv4
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_inv4
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+

diff --git a/xschem/simulations/latch_diff.spice b/xschem/simulations/latch_diff.spice
new file mode 100644
index 0000000..ebb2734
--- /dev/null
+++ b/xschem/simulations/latch_diff.spice

@@ -0,0 +1,26 @@
+**.subckt latch_diff vdd vss D nQ CLK nD Q
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/latch_diff_pex_c.spice b/xschem/simulations/latch_diff_pex_c.spice
new file mode 100644
index 0000000..f7aa001
--- /dev/null
+++ b/xschem/simulations/latch_diff_pex_c.spice

@@ -0,0 +1,73 @@
+* NGSPICE file created from latch_diff.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# w_n263_n314# 0.08fF
+C1 a_n125_n95# w_n263_n314# 0.11fF
+C2 a_63_n95# w_n263_n314# 0.11fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 a_63_n95# a_n33_n95# 0.28fF
+C5 a_63_n95# a_n125_n95# 0.10fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_111_n125# 0.36fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_n81_n125# a_111_n125# 0.13fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_n81_n125# a_n173_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.05fF
+C7 a_15_n125# w_n311_n335# 0.05fF
+C8 a_n81_n125# w_n311_n335# 0.05fF
+C9 a_n173_n125# w_n311_n335# 0.05fF
+C10 a_n129_n213# w_n311_n335# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n33_n95# a_n81_n183# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff vss vdd Q nQ D nD CLK
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nQ m1_657_280# 1.41fF
+C1 vdd Q 0.16fF
+C2 nQ Q 0.93fF
+C3 Q nD 0.05fF
+C4 Q D 0.05fF
+C5 nQ vdd 0.16fF
+C6 CLK m1_657_280# 0.20fF
+C7 Q m1_657_280# 0.94fF
+C8 nQ nD 0.05fF
+C9 nQ D 0.05fF
+C10 D vss 0.53fF
+C11 nD vss 0.16fF
+C12 m1_657_280# vss 1.88fF
+C13 CLK vss 0.54fF
+C14 Q vss 1.08fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.30fF
+.ends
+

diff --git a/xschem/simulations/loop_filter.spice b/xschem/simulations/loop_filter.spice
new file mode 100644
index 0000000..d5a3534
--- /dev/null
+++ b/xschem/simulations/loop_filter.spice

@@ -0,0 +1,12 @@
+**.subckt loop_filter in vss vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+XC1 vc_pex vss sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+XC2 in vss sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+XR2 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR1 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 net1 in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/loop_filter_pex_c.spice b/xschem/simulations/loop_filter_pex_c.spice
new file mode 100644
index 0000000..69a804d
--- /dev/null
+++ b/xschem/simulations/loop_filter_pex_c.spice

@@ -0,0 +1,115 @@
+* NGSPICE file created from loop_filter.ext - technology: sky130A
+
+.subckt sky130_fd_pr__res_high_po_5p73_GW5RGE w_n2133_n2890# a_n573_2292# a_821_n2724#
++ a_821_2292# a_n1967_2292# a_n573_n2724# a_n1967_n2724#
+X0 a_n1967_n2724# a_n1967_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+X1 a_n573_n2724# a_n573_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+X2 a_821_n2724# a_821_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_n2724# a_n1967_n2724# 0.19fF
+C1 a_821_2292# a_n573_2292# 0.19fF
+C2 a_821_n2724# a_n573_n2724# 0.19fF
+C3 a_n1967_2292# a_n573_2292# 0.19fF
+C4 a_821_n2724# w_n2133_n2890# 1.76fF
+C5 a_821_2292# w_n2133_n2890# 1.76fF
+C6 a_n573_n2724# w_n2133_n2890# 1.53fF
+C7 a_n573_2292# w_n2133_n2890# 1.53fF
+C8 a_n1967_n2724# w_n2133_n2890# 1.76fF
+C9 a_n1967_2292# w_n2133_n2890# 1.76fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS c1_n6369_n6300# m3_2169_n6400# m3_n2150_n6400#
++ c1_2269_n6300# c1_n2050_n6300# m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_n6400# c1_n2050_n6300# 121.67fF
+C1 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C2 m3_n2150_n6400# c1_2269_n6300# 4.84fF
+C3 m3_n6469_n6400# c1_n6369_n6300# 121.67fF
+C4 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C5 m3_2169_n6400# m3_n2150_n6400# 39.69fF
+C6 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C7 m3_n6469_n6400# c1_n2050_n6300# 4.84fF
+C8 m3_n2150_n6400# m3_n6469_n6400# 39.69fF
+C9 c1_2269_n6300# VSUBS 0.16fF
+C10 c1_n2050_n6300# VSUBS 0.16fF
+C11 c1_n6369_n6300# VSUBS 0.16fF
+C12 m3_2169_n6400# VSUBS 26.86fF
+C13 m3_n2150_n6400# VSUBS 26.86fF
+C14 m3_n6469_n6400# VSUBS 26.86fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MA89VW VSUBS c1_2769_n13100# m3_n2650_n13200# m3_n13288_n13200#
++ m3_n7969_n13200# m3_2669_n13200# c1_n2550_n13100# c1_n7869_n13100# m3_7988_n13200#
++ c1_n13188_n13100# c1_8088_n13100#
+X0 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n13288_n13200# c1_n13188_n13100# 305.88fF
+C1 m3_n2650_n13200# c1_n2550_n13100# 305.88fF
+C2 c1_8088_n13100# m3_7988_n13200# 305.88fF
+C3 c1_2769_n13100# c1_8088_n13100# 4.15fF
+C4 m3_n2650_n13200# m3_2669_n13200# 81.90fF
+C5 m3_n13288_n13200# c1_n7869_n13100# 10.12fF
+C6 c1_2769_n13100# c1_n2550_n13100# 4.15fF
+C7 m3_n7969_n13200# c1_n2550_n13100# 10.12fF
+C8 m3_n2650_n13200# c1_2769_n13100# 10.12fF
+C9 m3_n7969_n13200# c1_n7869_n13100# 305.88fF
+C10 c1_n7869_n13100# c1_n13188_n13100# 4.15fF
+C11 m3_7988_n13200# m3_2669_n13200# 81.90fF
+C12 m3_n2650_n13200# m3_n7969_n13200# 81.90fF
+C13 c1_8088_n13100# m3_2669_n13200# 10.12fF
+C14 c1_2769_n13100# m3_2669_n13200# 305.88fF
+C15 c1_n7869_n13100# c1_n2550_n13100# 4.15fF
+C16 m3_n7969_n13200# m3_n13288_n13200# 81.90fF
+C17 c1_8088_n13100# VSUBS 0.23fF
+C18 c1_2769_n13100# VSUBS 0.23fF
+C19 c1_n2550_n13100# VSUBS 0.23fF
+C20 c1_n7869_n13100# VSUBS 0.23fF
+C21 c1_n13188_n13100# VSUBS 0.23fF
+C22 m3_7988_n13200# VSUBS 63.09fF
+C23 m3_2669_n13200# VSUBS 63.09fF
+C24 m3_n2650_n13200# VSUBS 63.09fF
+C25 m3_n7969_n13200# VSUBS 63.09fF
+C26 m3_n13288_n13200# VSUBS 63.09fF
+.ends
+
+.subckt loop_filter_pex_c vss in vc_pex
+Xsky130_fd_pr__res_high_po_5p73_GW5RGE_0 vss vc_pex m1_166_166# vc_pex in m1_166_166#
++ m1_166_166# sky130_fd_pr__res_high_po_5p73_GW5RGE
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 vss in vss vss in in vss sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+Xsky130_fd_pr__cap_mim_m3_1_MA89VW_0 vss vc_pex vss vss vss vss vc_pex vc_pex vss
++ vc_pex vc_pex sky130_fd_pr__cap_mim_m3_1_MA89VW
+C0 vc_pex vss -869.21fF
+C1 in vss -532.70fF
+C2 m1_166_166# vss 5.01fF
+.ends
+

diff --git a/xschem/simulations/loop_filter_real.spice b/xschem/simulations/loop_filter_real.spice
new file mode 100644
index 0000000..16522de
--- /dev/null
+++ b/xschem/simulations/loop_filter_real.spice

@@ -0,0 +1,9 @@
+**.subckt loop_filter_real vss vctrl
+*.iopin vss
+*.iopin vctrl
+C1 net2 vss 'C1' m=1 
+C2 net1 vss 'C2' m=1 
+XR1 net2 vctrl __UNCONNECTED_PIN__0 sky130_fd_pr__res_xhigh_po_1p41 W=1.41 L=1 mult=1 m=1
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/nor.spice b/xschem/simulations/nor.spice
new file mode 100644
index 0000000..520e5fd
--- /dev/null
+++ b/xschem/simulations/nor.spice

@@ -0,0 +1,27 @@
+**.subckt nor A B vdd out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/pfd_cp_interface.spice b/xschem/simulations/pfd_cp_interface.spice
new file mode 100644
index 0000000..5e4088b
--- /dev/null
+++ b/xschem/simulations/pfd_cp_interface.spice

@@ -0,0 +1,69 @@
+**.subckt pfd_cp_interface vdd vss QA QB nDown Down nUp Up
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+**.ends
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/pfd_cp_interface_pex_c.spice b/xschem/simulations/pfd_cp_interface_pex_c.spice
new file mode 100644
index 0000000..d7391c5
--- /dev/null
+++ b/xschem/simulations/pfd_cp_interface_pex_c.spice

@@ -0,0 +1,258 @@
+* NGSPICE file created from pfd_cp_interface.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8_pci a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_63_n125# a_255_n125# 0.13fF
+C1 a_159_n125# a_255_n125# 0.36fF
+C2 a_n317_n125# a_n33_n125# 0.08fF
+C3 a_n33_n125# a_63_n125# 0.36fF
+C4 a_n129_n125# a_255_n125# 0.06fF
+C5 a_n33_n125# a_159_n125# 0.13fF
+C6 a_n33_n125# a_n225_n125# 0.13fF
+C7 a_n129_n125# a_n33_n125# 0.36fF
+C8 a_129_n151# a_225_n151# 0.02fF
+C9 a_n33_n125# a_255_n125# 0.08fF
+C10 a_n255_n151# a_n159_n151# 0.02fF
+C11 a_33_n151# a_n63_n151# 0.02fF
+C12 a_n317_n125# a_63_n125# 0.06fF
+C13 a_n159_n151# a_n63_n151# 0.02fF
+C14 a_129_n151# a_33_n151# 0.02fF
+C15 a_63_n125# a_159_n125# 0.36fF
+C16 a_n317_n125# a_n225_n125# 0.36fF
+C17 a_63_n125# a_n225_n125# 0.08fF
+C18 a_n317_n125# a_n129_n125# 0.13fF
+C19 a_n129_n125# a_63_n125# 0.13fF
+C20 a_159_n125# a_n225_n125# 0.06fF
+C21 a_n129_n125# a_159_n125# 0.08fF
+C22 a_n129_n125# a_n225_n125# 0.36fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S_pci VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_n317_n125# 0.36fF
+C1 a_33_n154# a_129_n154# 0.02fF
+C2 a_n129_n125# a_159_n125# 0.08fF
+C3 a_n129_n125# w_n455_n344# 0.04fF
+C4 a_n159_n154# a_n63_n154# 0.02fF
+C5 a_n33_n125# a_n317_n125# 0.08fF
+C6 a_n129_n125# a_63_n125# 0.13fF
+C7 a_255_n125# a_159_n125# 0.36fF
+C8 a_n225_n125# a_n33_n125# 0.13fF
+C9 a_255_n125# w_n455_n344# 0.11fF
+C10 a_n255_n154# a_n159_n154# 0.02fF
+C11 a_63_n125# a_255_n125# 0.13fF
+C12 a_n129_n125# a_255_n125# 0.06fF
+C13 w_n455_n344# a_n317_n125# 0.11fF
+C14 a_n225_n125# a_159_n125# 0.06fF
+C15 a_n225_n125# w_n455_n344# 0.06fF
+C16 a_63_n125# a_n317_n125# 0.06fF
+C17 a_n129_n125# a_n317_n125# 0.13fF
+C18 a_n225_n125# a_63_n125# 0.08fF
+C19 a_159_n125# a_n33_n125# 0.13fF
+C20 w_n455_n344# a_n33_n125# 0.05fF
+C21 a_n225_n125# a_n129_n125# 0.36fF
+C22 a_63_n125# a_n33_n125# 0.36fF
+C23 a_n63_n154# a_33_n154# 0.02fF
+C24 a_n129_n125# a_n33_n125# 0.36fF
+C25 w_n455_n344# a_159_n125# 0.06fF
+C26 a_225_n154# a_129_n154# 0.02fF
+C27 a_255_n125# a_n33_n125# 0.08fF
+C28 a_63_n125# a_159_n125# 0.36fF
+C29 a_63_n125# w_n455_n344# 0.04fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2_pci in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8_pci
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S_pci
+C0 in vdd 0.04fF
+C1 in out 0.85fF
+C2 out vdd 0.29fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH_pci VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 w_n311_n344# a_15_n125# 0.09fF
+C1 a_81_n156# a_n15_n156# 0.02fF
+C2 a_n173_n125# w_n311_n344# 0.14fF
+C3 w_n311_n344# a_111_n125# 0.14fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 w_n311_n344# a_n81_n125# 0.09fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_15_n125# a_n81_n125# 0.36fF
+C9 a_n111_n156# a_n15_n156# 0.02fF
+C10 a_n173_n125# a_n81_n125# 0.36fF
+C11 a_111_n125# a_n81_n125# 0.13fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T_pci a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_81_n151# a_n15_n151# 0.02fF
+C1 a_15_n125# a_n81_n125# 0.36fF
+C2 a_n173_n125# a_15_n125# 0.13fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n15_n151# a_n111_n151# 0.02fF
+C5 a_n173_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n173_n125# a_111_n125# 0.08fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate_pci in out vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss out in in vdd vss vss out sky130_fd_pr__pfet_01v8_4798MH_pci
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd out in in vdd out sky130_fd_pr__nfet_01v8_BHR94T_pci
+C0 out vdd 0.55fF
+C1 out in 0.36fF
+C2 in vdd 0.69fF
+C3 out vss 0.97fF
+C4 in vss 1.35fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH_pci VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n81_n125# w_n311_n344# 0.09fF
+C4 a_15_n125# w_n311_n344# 0.09fF
+C5 a_n173_n125# w_n311_n344# 0.14fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_111_n125# 0.14fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM_pci w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 a_111_n125# a_n173_n125# 0.08fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1_pci in out vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH_pci
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM_pci
+C0 out in 0.32fF
+C1 out vdd 0.10fF
+C2 in vdd 0.02fF
+C3 out vss 0.84fF
+C4 in vss 1.06fF
+C5 vdd vss 3.13fF
+.ends
+
+.subckt pfd_cp_interface_pex_c Up vdd QA nUp Down QB vss nDown 
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2_pci
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2_pci
+Xtrans_gate_0 trans_gate_0/in nDown vss vdd trans_gate_pci
+Xinverter_cp_x1_0 QB trans_gate_0/in vss vdd inverter_cp_x1_pci
+Xinverter_cp_x1_1 QA inverter_cp_x1_2/in vss vdd inverter_cp_x1_pci
+Xinverter_cp_x1_2 inverter_cp_x1_2/in Up vss vdd inverter_cp_x1_pci
+C0 nDown vdd 0.80fF
+C1 nDown Down 0.23fF
+C2 vdd inverter_cp_x1_2/in 0.40fF
+C3 Up inverter_cp_x1_2/in 0.12fF
+C4 Down vdd 0.09fF
+C5 nDown trans_gate_0/in 0.11fF
+C6 vdd Up 0.60fF
+C7 nUp vdd 0.14fF
+C8 nUp Up 0.20fF
+C9 vdd trans_gate_0/in 0.24fF
+C10 Down trans_gate_0/in 0.12fF
+C11 inverter_cp_x1_2/in vss 1.95fF
+C12 QA vss 1.17fF
+C13 trans_gate_0/in vss 1.97fF
+C14 QB vss 1.17fF
+C15 vdd vss 27.67fF
+C16 nUp vss 1.32fF
+C17 Up vss 2.60fF
+C18 Down vss 1.26fF
+C19 nDown vss 3.02fF
+.ends
+

diff --git a/xschem/simulations/ring_osc_buffer.spice b/xschem/simulations/ring_osc_buffer.spice
new file mode 100644
index 0000000..f4cf772
--- /dev/null
+++ b/xschem/simulations/ring_osc_buffer.spice

@@ -0,0 +1,47 @@
+**.subckt ring_osc_buffer vdd vss in_vco out_pad out_div o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+**.ends
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/ring_osc_buffer_pex_c.spice b/xschem/simulations/ring_osc_buffer_pex_c.spice
new file mode 100644
index 0000000..09b7e3a
--- /dev/null
+++ b/xschem/simulations/ring_osc_buffer_pex_c.spice

@@ -0,0 +1,140 @@
+* NGSPICE file created from ring_osc_buffer.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n33_n84# 0.24fF
+C1 a_n129_n84# w_n359_n303# 0.06fF
+C2 a_63_n84# a_159_n84# 0.24fF
+C3 a_n63_n110# a_n159_n110# 0.02fF
+C4 a_n221_n84# a_159_n84# 0.04fF
+C5 a_159_n84# a_n33_n84# 0.09fF
+C6 w_n359_n303# a_159_n84# 0.08fF
+C7 a_n63_n110# a_33_n110# 0.02fF
+C8 a_n129_n84# a_159_n84# 0.05fF
+C9 a_63_n84# a_n221_n84# 0.05fF
+C10 a_129_n110# a_33_n110# 0.02fF
+C11 a_63_n84# a_n33_n84# 0.24fF
+C12 a_63_n84# w_n359_n303# 0.06fF
+C13 a_n221_n84# a_n33_n84# 0.09fF
+C14 a_n221_n84# w_n359_n303# 0.08fF
+C15 a_63_n84# a_n129_n84# 0.09fF
+C16 a_n129_n84# a_n221_n84# 0.24fF
+C17 w_n359_n303# a_n33_n84# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D_ro_buff w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n221_n42# a_159_n42# 0.02fF
+C1 a_33_n68# a_129_n68# 0.02fF
+C2 a_n159_n68# a_n63_n68# 0.02fF
+C3 a_n221_n42# a_n129_n42# 0.12fF
+C4 a_n33_n42# a_159_n42# 0.05fF
+C5 a_63_n42# a_159_n42# 0.12fF
+C6 a_n33_n42# a_n129_n42# 0.12fF
+C7 a_63_n42# a_n129_n42# 0.05fF
+C8 a_n129_n42# a_159_n42# 0.03fF
+C9 a_n221_n42# a_n33_n42# 0.05fF
+C10 a_n221_n42# a_63_n42# 0.03fF
+C11 a_33_n68# a_n63_n68# 0.02fF
+C12 a_63_n42# a_n33_n42# 0.12fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4_ro_buff in out vss vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B_ro_buff
+Xsky130_fd_pr__nfet_01v8_DXA56D_ro_buff_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D_ro_buff
+C0 out vdd 0.62fF
+C1 in out 0.67fF
+C2 in vdd 0.33fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_63_n42# a_n125_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_n125_n84# 0.10fF
+C1 w_n263_n303# a_n33_n84# 0.07fF
+C2 w_n263_n303# a_63_n84# 0.10fF
+C3 a_n63_n110# a_33_n110# 0.02fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
+C5 a_n125_n84# a_63_n84# 0.09fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2_ro_buff in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK_ro_buff
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB_ro_buff
+C0 in vdd 0.01fF
+C1 out vdd 0.15fF
+C2 out in 0.30fF
+C3 out vss 0.66fF
+C4 in vss 0.72fF
+C5 vdd vss 2.93fF
+.ends
+
+.subckt ring_osc_buffer_pex_c vdd in_vco out_pad out_div vss o1
+Xinverter_min_x4_1 out_div out_pad vss vdd inverter_min_x4_ro_buff
+Xinverter_min_x4_0 o1 out_div vss vdd inverter_min_x4_ro_buff
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2_ro_buff
+C0 out_div out_pad 0.15fF
+C1 o1 vdd 0.09fF
+C2 out_div o1 0.11fF
+C3 vdd out_pad 0.10fF
+C4 out_div vdd 0.17fF
+C5 in_vco vss 0.83fF
+C6 vdd vss 14.54fF
+C7 o1 vss 2.72fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
+.ends
+

diff --git a/xschem/simulations/tb_DFF.spice b/xschem/simulations/tb_DFF.spice
new file mode 100644
index 0000000..c72a0f5
--- /dev/null
+++ b/xschem/simulations/tb_DFF.spice

@@ -0,0 +1,57 @@
+**.subckt tb_DFF
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0 
+C1 Up vss 10f m=1
+x2 Up vdd Q net3 net2 net4 vss net1 pfd_cp_interface_pex_c
+x1 vdd A Q B vss dff_pfd_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = 1.8
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/dff_pfd_pex_c.spice
+
+.ic v(net3) = 0.0
+.ic v(net4) = 0.0
+.ic v(Q) = 0.0
+
+* Data to save
+.save all
+
+* Simulation
+.control
+	tran 0.1ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_DFF_nor_tran.raw
+	plot v(A)+2 v(B)+2 v(Q)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_PFD.spice b/xschem/simulations/tb_PFD.spice
new file mode 100644
index 0000000..7ca5a31
--- /dev/null
+++ b/xschem/simulations/tb_PFD.spice

@@ -0,0 +1,146 @@
+**.subckt tb_PFD
+x1 vss vdd QA A B QB Reset PFD
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0 
+x2 net4 vdd QA net3 net2 QB vss net1 pfd_cp_interface_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 400ns
+	write tb_PFD_tran.raw
+ 	plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD  vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding   symbol:  DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF  D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding   symbol:  and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd  vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_PFD_pex.spice b/xschem/simulations/tb_PFD_pex.spice
new file mode 100644
index 0000000..76570e4
--- /dev/null
+++ b/xschem/simulations/tb_PFD_pex.spice

@@ -0,0 +1,56 @@
+**.subckt tb_PFD_pex
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vdiv B vss PULSE(0 {vin} 0 1p 1p {1.05*Tref/2} {1.05*Tref}) DC {vin} AC 0 
+Vref1 A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+x2 net4 vdd QA net3 net2 QB vss net1 pfd_cp_interface_pex_c
+x1 vss vdd QA A B QB Reset PFD_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+.option RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+	tran 0.001ns 400ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_PFD_pex_tran.raw
+ 	plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_cap_cp.spice b/xschem/simulations/tb_cap_cp.spice
new file mode 100644
index 0000000..67593e1
--- /dev/null
+++ b/xschem/simulations/tb_cap_cp.spice

@@ -0,0 +1,65 @@
+**.subckt tb_cap_cp
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+XM1 vss vdd vss vss sky130_fd_pr__nfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM2 vss vdd vss vss sky130_fd_pr__pfet_01v8 L=0.3 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/sky130-mpw2-fulgor/PFD/sch/simulations/PFD_pex_c.spice
+.include ~/sky130-mpw2-fulgor/pfd_cp_interface/sch/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all @M.XM1.msky130_fd_pr__nfet_01v8[cgs] @M.XM2.msky130_fd_pr__pfet_01v8[cgs] @M.XM1.msky130_fd_pr__nfet_01v8[cgd] @M.XM2.msky130_fd_pr__pfet_01v8[cgd] @M.XM1.msky130_fd_pr__nfet_01v8[cgb] @M.XM2.msky130_fd_pr__pfet_01v8[cgb] @M.XM1.msky130_fd_pr__nfet_01v8[cgg] @M.XM2.msky130_fd_pr__pfet_01v8[cgg]
+
+
+* Simulation
+.control
+	op
+	echo .
+	echo ---- Cgs ----
+	print @M.XM1.msky130_fd_pr__nfet_01v8[cgs]
+	print @M.XM2.msky130_fd_pr__pfet_01v8[cgs]
+	echo .
+	echo ---- Cgd ----
+	print @M.XM1.msky130_fd_pr__nfet_01v8[cgd]
+	print @M.XM2.msky130_fd_pr__pfet_01v8[cgd]
+	echo .
+	echo ---- Cgs ----
+	print @M.XM1.msky130_fd_pr__nfet_01v8[cgb]
+	print @M.XM2.msky130_fd_pr__pfet_01v8[cgb]
+	echo .
+	echo ---- Cgs ----
+	print @M.XM1.msky130_fd_pr__nfet_01v8[cgg]
+	print @M.XM2.msky130_fd_pr__pfet_01v8[cgg]
+
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_charge_pump.spice b/xschem/simulations/tb_charge_pump.spice
new file mode 100644
index 0000000..49eab40
--- /dev/null
+++ b/xschem/simulations/tb_charge_pump.spice

@@ -0,0 +1,235 @@
+**.subckt tb_charge_pump
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref net2 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+Vdiv net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+C1 net3 vss 33.5p m=1
+R1 vctrl net3 2k m=1
+C2 vctrl vss 6.7p m=1
+vout cp_out vctrl 0
+x1 vss vdd net16 net17 net18 net19 Reset PFD
+x5 vdd net4 net2 vss inverter_cp_x2
+x6 vdd QA net4 vss inverter_cp_x2
+x7 vdd net5 net1 vss inverter_cp_x2
+x8 vdd QB net5 vss inverter_cp_x2
+x3 Up vdd QA nUp Down QB vss nDown pfd_cp_interface_pex_c
+x2 vdd Up nUp cp_out Down nDown vss iref_cp nswitch pswitch biasp charge_pump_pex_c
+I0 net6 vss 100u
+x4 vdd net6 vss iref_cp net7 net8 net9 net10 net11 net12 net13 net14 net15 bias_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/caravel_analog_fulgor/xschem/simulations/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+.ic v(vctrl) = 0.0
+
+* Simulation
+.control
+	op
+	echo .
+	echo ---- M1 bias ----
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M2 bias ----
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M3 bias ----
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M4 bias ----
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M5 bias ----
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[id]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vds]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vdsat]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vgs]
+	echo ---- M6 bias ----
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[id]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vds]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vdsat]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vgs]
+	echo ---- M7 bias ----
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[id]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vds]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vgs]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgs]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgs]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgd]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgd]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgb]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgb]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgg]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgg]
+
+	reset
+
+
+	tran 0.01ns 400ns
+	write tb_cp_gate_switched_tran.raw
+	plot i(v.x2.vm1) i(v.x2.vm2)
+	plot v(vctrl) v(nDown)+2 v(Down)+4 v(nUp)+6 v(Up)+8 v(QB)+10 v(QA)+12
+	plot v(pswitch) v(nswitch) xlimit 4ns 44ns
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD  vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding   symbol:  inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+
+* expanding   symbol:  DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF  D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding   symbol:  and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd  vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_csvco.spice b/xschem/simulations/tb_csvco.spice
new file mode 100644
index 0000000..51cc484
--- /dev/null
+++ b/xschem/simulations/tb_csvco.spice

@@ -0,0 +1,236 @@
+**.subckt tb_csvco
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+VD0 D0 vss DC {vd0} 
+x3 vdd out_ro D0 vctrl vss csvco
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco  vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding   symbol:  csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_csvco_pex_c.spice b/xschem/simulations/tb_csvco_pex_c.spice
new file mode 100644
index 0000000..04776d5
--- /dev/null
+++ b/xschem/simulations/tb_csvco_pex_c.spice

@@ -0,0 +1,172 @@
+**.subckt tb_csvco_pex_c
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+VD0 D0 vss DC {vd0} 
+x3 vdd out_ro vctrl vss D0 csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_div_by_2.spice b/xschem/simulations/tb_div_by_2.spice
new file mode 100644
index 0000000..519a0ce
--- /dev/null
+++ b/xschem/simulations/tb_div_by_2.spice

@@ -0,0 +1,212 @@
+**.subckt tb_div_by_2
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+x1 nout vss A vdd out out_div net3 net4 net5 div_by_2
+x2 vdd net2 net1 vss inverter_min_x2_pex_c
+x3 vdd A net2 vss inverter_min_x4_pex_c
+C1 nout vss 10f m=1
+C2 out vss 10f m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_2_tran.raw
+	plot v(out) v(A) v(nout)+2 v(A)+2
+	plot v(out_div) v(out)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2  nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_div_by_2_pex_c.spice b/xschem/simulations/tb_div_by_2_pex_c.spice
new file mode 100644
index 0000000..e5c61d7
--- /dev/null
+++ b/xschem/simulations/tb_div_by_2_pex_c.spice

@@ -0,0 +1,76 @@
+**.subckt tb_div_by_2_pex_c
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+x1 nout vss A vdd out net9 net10 net11 net12 div_by_2_pex_c
+Vref net2 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+x3 vdd net3 net2 vss inverter_min_x2_pex_c
+x4 vdd A net3 vss inverter_min_x4_pex_c
+x2 vdd net1 out vss nout net4 net5 net7 net8 net6 div_by_5_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(out) = 0.0
+.ic v(nout) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_2_tran.raw
+	plot v(out) v(A) v(nout)+2 v(A)+2
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_div_by_5.spice b/xschem/simulations/tb_div_by_5.spice
new file mode 100644
index 0000000..630f57f
--- /dev/null
+++ b/xschem/simulations/tb_div_by_5.spice

@@ -0,0 +1,246 @@
+**.subckt tb_div_by_5
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref CLK vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+C2 clk_10 vss 10f m=1
+x2 nclk_2 vss CLK vdd clk_2 net1 net2 net3 net4 div_by_2
+x1 vdd clk_10 clk_2 vss nclk_2 net5 net6 net7 net8 net9 div_by_5
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(CLK) = 0.0
+.ic v(x1.q2) = 0.0
+.ic v(x1.q1) = 0.0
+.ic v(x1.q1_shift) = 0.0
+.ic v(x1.q0) = 0.0
+.ic v(x1.x1.a) = 0.0
+.ic v(x1.x1.D_d) = 0.0
+.ic v(x1.x1.nD_d) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 600ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_5_tran.raw
+	plot v(clk_10) v(clk) v(clk_2) v(clk_2)+3 v(clk)+6
+	plot v(x1.Q2) v(x1.Q1)+2 v(clk_Q0)+4 v(x1.Q1_shift)+6 v(clk_10)+8
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2  nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5  vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_div_by_5_pex_c.spice b/xschem/simulations/tb_div_by_5_pex_c.spice
new file mode 100644
index 0000000..3ab0cfe
--- /dev/null
+++ b/xschem/simulations/tb_div_by_5_pex_c.spice

@@ -0,0 +1,73 @@
+**.subckt tb_div_by_5_pex_c
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+x1 nclk_2 vss A vdd clk_2 net14 net15 net16 net17 div_by_2_pex_c
+Vref net1 vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+x3 vdd net2 net1 vss inverter_min_x2_pex_c
+x4 vdd A net2 vss inverter_min_x4_pex_c
+x5 vss vdd net10 net11 clk_5 net9 net8 PFD_pex_c
+x2 vdd clk_5 clk_2_buf vss nclk_2_buf net3 net4 net6 net7 net5 div_by_5_pex_c
+x6 vdd net12 clk_2 vss inverter_min_x2_pex_c
+x7 vdd clk_2_buf net12 vss inverter_min_x4_pex_c
+x8 vdd net13 nclk_2 vss inverter_min_x2_pex_c
+x9 vdd nclk_2_buf net13 vss inverter_min_x4_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_5)
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	write tb_div_by_5_tran.raw
+	plot v(clk_2) v(A) v(nclk_2)+2 v(A)+2
+	plot v(clk_5) v(clk_2_buf) v(A)
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_inverter_csvco.spice b/xschem/simulations/tb_inverter_csvco.spice
new file mode 100644
index 0000000..039f534
--- /dev/null
+++ b/xschem/simulations/tb_inverter_csvco.spice

@@ -0,0 +1,96 @@
+**.subckt tb_inverter_csvco
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+VIN in vss PULSE(0 {vin} 0 1p 1p {T/2} {T}) DC {vin} AC 0 
+C1 out vss 10f m=1
+x1 vdd out in vss vdd vss inverter_csvco
+x2 vdd out_pex_c in vss vdd vss inverter_csvco_pex_c
+C2 out_pex_c vss 10f m=1
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0
+.param vin = vdd
+.param T   = 100n
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Initial Conditions
+.ic v(out) = 0.0
+.ic v(out_wp) = 0.0
+.ic v(out_wp_rc) = 0.0
+.ic v(out_pex_c) = 0.0
+
+* Data to save
+.save all  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgs]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgs]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgd]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgd]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[csb]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[csb]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[cdb]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[cdb]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgg]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgg]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgb]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgb]
+
+* Simulation
+.control
+	set filetype = ascii
+	op
+	write tb_inverter_min.raw
+	echo .
+	echo ------ OP Results -----
+	print all
+
+	reset
+
+	dc vin 0 1.8 0.01
+	setplot dc1
+	plot v(in) v(out) v(out_pex_c)
+	write tb_inverter_min_dc.raw
+
+	reset
+
+	tran 1ns 1us
+	meas tran tpLH trig v(in) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	meas tran tpHL trig v(in) val=0.9 rise=5 targ v(out) val=0.9 fall=4
+	meas tran tpLHc trig v(in) val=0.9 fall=5 targ v(out_pex_c) val=0.9 rise=5
+	meas tran tpHLc trig v(in) val=0.9 rise=5 targ v(out_pex_c) val=0.9 fall=4
+	let tp = (0.5*(tpLH + tpHL))
+	let tp_c = (0.5*(tpLHc + tpHLc))
+	echo .
+	echo ---- tp Ideal ----
+	print tpLH tpHL tp
+	echo .
+	echo ---- tp PEX C ----
+	print tpLHc tpHLc tp_c
+	write tb_inverter_tran.raw
+	plot v(in) v(out) v(out_pex_c)+2
+
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_loop_filter.spice b/xschem/simulations/tb_loop_filter.spice
new file mode 100644
index 0000000..5d54826
--- /dev/null
+++ b/xschem/simulations/tb_loop_filter.spice

@@ -0,0 +1,66 @@
+**.subckt tb_loop_filter
+VSS vss GND {vss} 
+vdd vdd vss {vdd} 
+Vref A vss PULSE(0 1.0 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+x1 vss A vc loop_filter
+x2 vss A vc_pex loop_filter_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 5e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param R1 = 1.6k
+.param C1 = 33.5p
+.param C2 = 6.7p
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+
+* Data to save
+
+
+* Simulation
+.control
+
+	tran 0.01ns 200ns
+	meas tran t1 when v(vc)=0.63
+	meas tran t2 when v(vc_pex)=0.63
+	let R = t1/0.5p
+	let Rpex = t2/05.p
+	print R Rpex
+	plot v(vc) v(vc_pex)
+.endc
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter  vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+XC1 vc_pex vss sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+XC2 in vss sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+XR2 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR1 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 net1 in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_top_pll_v1.spice b/xschem/simulations/tb_top_pll_v1.spice
new file mode 100644
index 0000000..d199d64
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1.spice

@@ -0,0 +1,688 @@
+**.subckt tb_top_pll_v1
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+VD0 D0 vss {vd0} 
+I0 net1 vss {iref} 
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 top_pll_v1
+x2 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  top_pll_v1.sym # of pins=33
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sch
+.subckt top_pll_v1  iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x4 vss vco_vctrl lf_vc loop_filter
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_pad out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+.ends
+
+
+* expanding   symbol:  bias.sym # of pins=13
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
+.subckt bias  vdd iref vss iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
+*.iopin iref
+*.iopin vdd
+*.opin iref_0
+*.opin iref_1
+*.opin iref_2
+*.opin iref_3
+*.opin iref_4
+*.opin iref_5
+*.opin iref_6
+*.opin iref_7
+*.opin iref_8
+*.opin iref_9
+XM1 iref iref vbp1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM2 vbp1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM3 net1 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM4 iref_0 iref net1 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM5 net2 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM6 iref_1 iref net2 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM7 net3 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM8 iref_2 iref net3 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM9 net4 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM10 iref_3 iref net4 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM11 net5 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM12 iref_4 iref net5 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM13 net6 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM14 iref_5 iref net6 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM15 net7 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM16 iref_6 iref net7 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM17 net8 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM18 iref_7 iref net8 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM19 net9 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM20 iref_8 iref net9 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM21 net10 vbp1 vdd vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+XM22 iref_9 iref net10 vdd sky130_fd_pr__pfet_01v8_lvt L=0.45 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=25 m=25 
+.ends
+
+
+* expanding   symbol:  PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD  vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding   symbol:  charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump  vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+.ends
+
+
+* expanding   symbol:  pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface  Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding   symbol:  loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter  vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+XC1 vc_pex vss sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+XC2 in vss sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+XR2 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR1 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 net1 in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding   symbol:  csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco  vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding   symbol:  ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer  vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5  vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding   symbol:  div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2  nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF  D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding   symbol:  and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd  vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+
+* expanding   symbol:  csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/and2/sky130_fd_sc_hs__and2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/xor2/sky130_fd_sc_hs__xor2_1.spice
+.include ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest/cells/or2/sky130_fd_sc_hs__or2_1.spice
+
+**** end user architecture code
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_top_pll_v1_pex_c.spice b/xschem/simulations/tb_top_pll_v1_pex_c.spice
new file mode 100644
index 0000000..efd712e
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1_pex_c.spice

@@ -0,0 +1,85 @@
+**.subckt tb_top_pll_v1_pex_c
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+VD0 D0 vss {vd0} 
+I0 net1 vss {iref} 
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 top_pll_v1_pex_c
+x9 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v1_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice b/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice
new file mode 100644
index 0000000..4da7253
--- /dev/null
+++ b/xschem/simulations/tb_top_pll_v1_pex_no_integration.spice

@@ -0,0 +1,149 @@
+**.subckt tb_top_pll_v1_pex_no_integration
+VSS vss GND {vss} 
+VDD vdd vss {vdd} 
+Vref A vss PULSE(0 {vin} 0 1p 1p {Tref/2} {Tref}) DC {vin} AC 0 
+VD0 D0 vss {vd0} 
+I0 net1 vss {iref} 
+x2 vdd net1 vss iref_cp net2 net3 net4 net5 net6 net7 net8 net9 net10 bias_pex_c
+x1 iref_cp vss vdd vco_out vctrl Up QB nUp A out_to_pad Down nDown QA D0 lf_vc vco_buffer_out biasp
++ pswitch pfd_reset nswitch out_by_2 out_to_div out_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1
++ out_buffer_div_2 n_out_buffer_div_2 div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2 top_pll_v1_pex_no_integration
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14
++ v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  top_pll_v1_pex_no_integration.sym # of pins=33
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1_pex_no_integration.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1_pex_no_integration.sch
+.subckt top_pll_v1_pex_no_integration  iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref
++ out_to_pad Down nDown pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2
++ out_to_div out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2
++ div_5_Q0 n_out_div_2 div_5_nQ2 out_div_2
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD_pex_c
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c
+x5 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5_pex_c
+x6 vss vco_vctrl lf_vc loop_filter_pex_c
+x7 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x8 vdd vco_out out_to_pad out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x4 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+.ends
+
+.GLOBAL GND
+**** begin user architecture code
+
+**** end user architecture code
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/tb_vco.spice b/xschem/simulations/tb_vco.spice
new file mode 100644
index 0000000..b0f1ef8
--- /dev/null
+++ b/xschem/simulations/tb_vco.spice

@@ -0,0 +1,227 @@
+**.subckt tb_vco vctrl D0 D1 D2 D3
+*.ipin vctrl
+*.ipin D0
+*.ipin D1
+*.ipin D2
+*.ipin D3
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+C1 out vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+x5 vdd out out4 vss inverter_min_x2
+x4 vdd out4 out3 vss inverter_min_x2
+XM1 net2 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 net2 vdd vss vss sky130_fd_pr__nfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM10 net1 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM13 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM14 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 net1 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+C4 net7 vss 1f m=1
+XM15 out1 D0 net7 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+C2 net8 vss 2f m=1
+C3 net9 vss 4f m=1
+C5 net10 vss 8f m=1
+C6 net11 vss 1f m=1
+C7 net12 vss 2f m=1
+C8 net13 vss 4f m=1
+C9 net14 vss 8f m=1
+C10 net15 vss 1f m=1
+C11 net16 vss 2f m=1
+C12 net17 vss 4f m=1
+C13 net18 vss 8f m=1
+VD0 D0 vss DC {vd0} 
+VD1 D1 vss DC {vd1} 
+VD2 D2 vss DC {vd2} 
+VD3 D3 vss DC {vd3} 
+XM9 net5 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM12 net6 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 net3 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM5 net4 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM16 out1 D1 net8 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM17 out1 D2 net9 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM18 out1 D3 net10 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM19 out2 D0 net11 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM20 out2 D1 net12 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM21 out2 D2 net13 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM22 out2 D3 net14 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM23 out3 D0 net15 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM24 out3 D1 net16 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM25 out3 D2 net17 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM26 out3 D3 net18 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net5 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 net6 vss vdd vdd sky130_fd_pr__pfet_01v8 L=0.6 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 net1 out1 out3 net2 vdd vss inverter_csvco_pex_c
+x2 net5 out2 out1 net3 vdd vss inverter_csvco_pex_c
+x3 net6 out3 out2 net4 vdd vss inverter_csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vctrl = 1.0
+.param vd0 = 0.0
+.param vd1 = 0.0
+.param vd2 = 0.0
+.param vd3 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Data to save
+.save all  @M.XM7.msky130_fd_pr__pfet_01v8[id]  @M.XM7.msky130_fd_pr__pfet_01v8[vds]  @M.XM7.msky130_fd_pr__pfet_01v8[vdsat]  @M.XM10.msky130_fd_pr__pfet_01v8[id]  @M.XM10.msky130_fd_pr__pfet_01v8[vds]  @M.XM10.msky130_fd_pr__pfet_01v8[vdsat]  @M.XM13.msky130_fd_pr__pfet_01v8[id]  @M.XM13.msky130_fd_pr__pfet_01v8[vds]  @M.XM13.msky130_fd_pr__pfet_01v8[vdsat]  @M.XM1.msky130_fd_pr__nfet_01v8[id]  @M.XM1.msky130_fd_pr__nfet_01v8[vds]  @M.XM1.msky130_fd_pr__nfet_01v8[vdsat]  @M.XM4.msky130_fd_pr__nfet_01v8[id]  @M.XM4.msky130_fd_pr__nfet_01v8[vds]  @M.XM4.msky130_fd_pr__nfet_01v8[vdsat]  @M.XM14.msky130_fd_pr__nfet_01v8[id]  @M.XM14.msky130_fd_pr__pfet_01v8[vds]  @M.XM14.msky130_fd_pr__pfet_01v8[vdsat]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]  @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]  @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
+
+.ic v(out1) = vdd/2
+.ic v(out2) = vdd/2
+.ic v(out3) = vdd/2
+.ic v(out4) = 0.0
+.ic v(out) = 0.0
+
+* Simulation
+.control
+op
+write tb_vco.raw
+
+echo ----- M1 -----
+print @M.XM1.msky130_fd_pr__nfet_01v8[id]
+print @M.XM1.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM1.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M4 -----
+print @M.XM4.msky130_fd_pr__nfet_01v8[id]
+print @M.XM4.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM4.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M14 -----
+print @M.XM14.msky130_fd_pr__nfet_01v8[id]
+print @M.XM14.msky130_fd_pr__nfet_01v8[vds]
+print @M.XM14.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- M7 -----
+print @M.XM7.msky130_fd_pr__pfet_01v8[id]
+print @M.XM7.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- M10 -----
+print @M.XM10.msky130_fd_pr__pfet_01v8[id]
+print @M.XM10.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM10.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- M13 -----
+print @M.XM13.msky130_fd_pr__pfet_01v8[id]
+print @M.XM13.msky130_fd_pr__pfet_01v8[vds]
+print @M.XM13.msky130_fd_pr__pfet_01v8[vdsat]
+
+echo ----- Inverter NMOS -----
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]
+print @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
+
+echo ----- Inverter PMOS -----
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
+print @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
+
+alterparam vctrl = 0.0
+reset
+
+let i = 0
+while i <= 1.9
+	tran 0.01ns 50ns
+	meas tran To trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	let T = To/10.0
+	let f = 1/T
+	echo .
+	echo --- VCO ----
+	print T f
+	let i = i + 0.3
+	alterparam vctrl = $&i
+	reset
+end
+*plot v(tran1.out) v(tran1.vctrl)
+*plot v(tran2.out) v(tran2.vctrl)
+*plot v(tran3.out) v(tran3.vctrl)
+*plot v(tran4.out) v(tran4.vctrl)
+*plot v(tran5.out) v(tran5.vctrl)
+*plot v(tran6.out) v(tran6.vctrl)
+*plot v(tran7.out) v(tran7.vctrl)
+print tran7.f tran6.f tran5.f tran4.f tran3.f tran2.f tran1.f
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/threshold_test_tb.spice b/xschem/simulations/threshold_test_tb.spice
similarity index 100%
rename from xschem/threshold_test_tb.spice
rename to xschem/simulations/threshold_test_tb.spice


diff --git a/xschem/simulations/top_pll_v1.spice b/xschem/simulations/top_pll_v1.spice
new file mode 100644
index 0000000..07fe011
--- /dev/null
+++ b/xschem/simulations/top_pll_v1.spice

@@ -0,0 +1,511 @@
+**.subckt top_pll_v1 vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset cp_nswitch cp_pswitch
+*+ cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_pad out_to_div out_by_2 n_out_by_2
+*+ out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift div_5_nQ0 div_5_Q0
+*+ div_5_nQ2 out_div_by_5
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump
+x3 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface
+x4 vss vco_vctrl lf_vc loop_filter
+x5 vdd vco_out vco_D0 vco_vctrl vss csvco
+x6 vdd vco_out out_to_pad out_to_div vss out_first_buffer ring_osc_buffer
+x7 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5
+x8 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2
+**.ends
+
+* expanding   symbol:  PFD.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+.subckt PFD  vss vdd Up A B Down Reset
+*.iopin vdd
+*.iopin vss
+*.ipin A
+*.ipin B
+*.opin Down
+*.opin Up
+*.iopin Reset
+x1 vdd A Up Reset vss DFF
+x2 vdd B Down Reset vss DFF
+x3 vdd Reset Up Down vss and_pfd
+.ends
+
+
+* expanding   symbol:  charge_pump.sym # of pins=11
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+.subckt charge_pump  vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
+*.iopin vss
+*.iopin vdd
+*.ipin Down
+*.ipin nUp
+*.ipin Up
+*.ipin nDown
+*.opin out
+*.iopin nswitch
+*.iopin pswitch
+*.ipin iref
+*.iopin biasp
+XM1 out pswitch vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM2 out nswitch vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM3 pswitch nUp biasp vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 pswitch Up vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM5 nswitch Down iref vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM6 nswitch nDown vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM7 pswitch nUp pswitch vdd sky130_fd_pr__pfet_01v8 L=2 W=4.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM8 nswitch Down nswitch vss sky130_fd_pr__nfet_01v8 L=1.5 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM9 iref iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM10 biasp iref vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+XM11 biasp biasp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=25 m=25 
+.ends
+
+
+* expanding   symbol:  pfd_cp_interface.sym # of pins=8
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+.subckt pfd_cp_interface  Up vdd QA nUp Down QB vss nDown
+*.iopin vdd
+*.iopin vss
+*.ipin QA
+*.ipin QB
+*.opin nDown
+*.opin Down
+*.opin nUp
+*.opin Up
+x5 vdd nDown nQB vss trans_gate
+x3 vdd Up nQA vss inverter_cp_x1
+x1 vdd nQB QB vss inverter_cp_x1
+x2 vdd nQA QA vss inverter_cp_x1
+x4 vdd nUp Up vss inverter_cp_x2
+x6 vdd Down nDown vss inverter_cp_x2
+.ends
+
+
+* expanding   symbol:  loop_filter.sym # of pins=3
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+.subckt loop_filter  vss in vc_pex
+*.iopin in
+*.iopin vss
+*.iopin vc_pex
+XC1 vc_pex vss sky130_fd_pr__cap_mim_m3_1 W=25 L=25 MF=25 m=25
+XC2 in vss sky130_fd_pr__cap_mim_m3_1 W=20 L=20 MF=9 m=9
+XR2 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR1 vc_pex net1 vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+XR3 net1 in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
+.ends
+
+
+* expanding   symbol:  csvco.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+.subckt csvco  vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd vbp out out1 vctrl vss D0 csvco_branch
+x2 vdd vbp out1 out2 vctrl vss D0 csvco_branch
+x3 vdd vbp out2 out vctrl vss D0 csvco_branch
+.ends
+
+
+* expanding   symbol:  ring_osc_buffer.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+.subckt ring_osc_buffer  vdd in_vco out_pad out_div vss o1
+*.iopin vdd
+*.iopin vss
+*.ipin in_vco
+*.opin out_pad
+*.opin out_div
+*.iopin o1
+x1 vdd o1 in_vco vss inverter_min_x2
+x2 vdd out_div o1 vss inverter_min_x4
+x3 vdd out_pad out_div vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  div_by_5.sym # of pins=10
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+.subckt div_by_5  vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
+*.iopin vdd
+*.iopin vss
+*.ipin CLK
+*.opin CLK_5
+*.ipin nCLK
+*.iopin nQ2
+*.iopin Q1
+*.iopin Q0
+*.iopin nQ0
+*.iopin Q1_shift
+x8 Q1 Q0 vss vss vdd vdd D2 sky130_fd_sc_hs__and2_1
+x9 Q1 Q0 vss vss vdd vdd D1 sky130_fd_sc_hs__xor2_1
+x10 nQ2 nQ0 vss vss vdd vdd D0 sky130_fd_sc_hs__and2_1
+x12 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+x1 vdd Q2 nQ2 vss D2 CLK nCLK DFlipFlop
+x2 vdd Q1 nQ1 vss D1 CLK nCLK DFlipFlop
+x3 vdd Q0 nQ0 vss D0 CLK nCLK DFlipFlop
+x4 vdd Q1_shift nQ1_shift vss Q1 nCLK CLK DFlipFlop
+.ends
+
+
+* expanding   symbol:  div_by_2.sym # of pins=9
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+.subckt div_by_2  nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
+*.ipin CLK
+*.opin CLK_2
+*.iopin vss
+*.iopin vdd
+*.opin nCLK_2
+*.iopin nout_div
+*.iopin o2
+*.iopin o1
+*.iopin out_div
+x1 vdd out_div nout_div vss nout_div CLK_d nCLK_d DFlipFlop
+x2 vdd CLK_d CLK nCLK_d vss clock_inverter
+x3 vdd o1 out_div vss inverter_min_x2
+x4 vdd CLK_2 o1 vss inverter_min_x4
+x5 vdd o2 nout_div vss inverter_min_x2
+x6 vdd nCLK_2 o2 vss inverter_min_x4
+.ends
+
+
+* expanding   symbol:  DFF.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+.subckt DFF  D CLK Q Reset vss
+*.ipin D
+*.ipin CLK
+*.opin Q
+*.ipin Reset
+*.iopin vss
+x1 D CLK Q P vss nor
+x2 D P P1 Q vss nor
+x3 D P P2 P1 vss nor
+x4 D P1 Reset P2 vss nor
+.ends
+
+
+* expanding   symbol:  and_pfd.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+.subckt and_pfd  vdd out A B vss
+*.iopin vdd
+*.iopin vss
+*.opin out
+*.ipin A
+*.ipin B
+XM1 out_nand A net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out_nand A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out_nand B net2 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out_nand B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 out out_nand vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 out out_nand vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  trans_gate.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+.subckt trans_gate  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x1.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+.subckt inverter_cp_x1  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+.ends
+
+
+* expanding   symbol:  inverter_cp_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+.subckt inverter_cp_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+
+* expanding   symbol:  csvco_branch.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+.subckt csvco_branch  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=10 m=10 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  DFlipFlop.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+.subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
+*.iopin vdd
+*.iopin vss
+*.opin Q
+*.opin nQ
+*.ipin D
+*.ipin CLK
+*.ipin nCLK
+x1 vdd D_d D nD_d vss clock_inverter
+x2 vdd nA A D_d nD_d CLK vss latch_diff
+x3 vdd nQ Q A nA nCLK vss latch_diff
+.ends
+
+
+* expanding   symbol:  clock_inverter.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+.subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
+*.ipin CLK
+*.iopin vdd
+*.iopin vss
+*.opin nCLK_d
+*.opin CLK_d
+x5 vdd nCLK_d net1 vss trans_gate
+x1 vdd CLK_d net2 vss inverter_cp_x1
+x2 vdd net2 CLK vss inverter_cp_x1
+x3 vdd net1 CLK vss inverter_cp_x1
+.ends
+
+
+* expanding   symbol:  nor.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+.subckt nor  vdd A B out vss
+*.ipin A
+*.ipin B
+*.iopin vdd
+*.opin out
+*.iopin vss
+XM1 out A vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out B vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.45 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out B net1 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM5 net2 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 out A net2 vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.9 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+
+* expanding   symbol:  latch_diff.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+.subckt latch_diff  vdd nQ Q D nD CLK vss
+*.iopin vdd
+*.iopin vss
+*.ipin D
+*.opin nQ
+*.ipin CLK
+*.ipin nD
+*.opin Q
+XM3 net1 CLK vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM4 nQ Q vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 Q nQ vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 nQ D net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 Q nD net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.95 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/top_pll_v1_pex_c.spice b/xschem/simulations/top_pll_v1_pex_c.spice
new file mode 100644
index 0000000..56417a9
--- /dev/null
+++ b/xschem/simulations/top_pll_v1_pex_c.spice

@@ -0,0 +1,2591 @@
+* NGSPICE file created from top_pll_v1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__res_high_po_5p73_GW5RGE w_n2133_n2890# a_n573_2292# a_821_n2724#
++ a_821_2292# a_n1967_2292# a_n573_n2724# a_n1967_n2724#
+X0 a_n1967_n2724# a_n1967_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+X1 a_n573_n2724# a_n573_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+X2 a_821_n2724# a_821_2292# w_n2133_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+C0 a_n573_2292# a_821_2292# 0.19fF
+C1 a_n573_2292# a_n1967_2292# 0.19fF
+C2 a_n573_n2724# a_n1967_n2724# 0.19fF
+C3 a_821_n2724# a_n573_n2724# 0.19fF
+C4 a_821_n2724# w_n2133_n2890# 1.76fF
+C5 a_821_2292# w_n2133_n2890# 1.76fF
+C6 a_n573_n2724# w_n2133_n2890# 1.53fF
+C7 a_n573_2292# w_n2133_n2890# 1.53fF
+C8 a_n1967_n2724# w_n2133_n2890# 1.76fF
+C9 a_n1967_2292# w_n2133_n2890# 1.76fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS c1_n6369_n6300# m3_2169_n6400# m3_n2150_n6400#
++ c1_2269_n6300# c1_n2050_n6300# m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+C0 m3_n2150_n6400# m3_n6469_n6400# 39.69fF
+C1 m3_n2150_n6400# c1_n2050_n6300# 121.67fF
+C2 c1_n2050_n6300# m3_n6469_n6400# 4.84fF
+C3 m3_n2150_n6400# c1_2269_n6300# 4.84fF
+C4 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C5 c1_n6369_n6300# m3_n6469_n6400# 121.67fF
+C6 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
+C7 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C8 m3_2169_n6400# m3_n2150_n6400# 39.69fF
+C9 c1_2269_n6300# VSUBS 0.16fF
+C10 c1_n2050_n6300# VSUBS 0.16fF
+C11 c1_n6369_n6300# VSUBS 0.16fF
+C12 m3_2169_n6400# VSUBS 26.86fF
+C13 m3_n2150_n6400# VSUBS 26.86fF
+C14 m3_n6469_n6400# VSUBS 26.86fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MA89VW VSUBS c1_2769_n13100# m3_n2650_n13200# m3_n13288_n13200#
++ m3_n7969_n13200# m3_2669_n13200# c1_n2550_n13100# c1_n7869_n13100# m3_7988_n13200#
++ c1_n13188_n13100# c1_8088_n13100#
+X0 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_8088_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n7869_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n2550_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_2769_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+C0 m3_n7969_n13200# m3_n13288_n13200# 81.90fF
+C1 m3_7988_n13200# c1_8088_n13100# 305.88fF
+C2 c1_n7869_n13100# m3_n13288_n13200# 10.12fF
+C3 m3_2669_n13200# c1_2769_n13100# 305.88fF
+C4 m3_2669_n13200# c1_8088_n13100# 10.12fF
+C5 c1_8088_n13100# c1_2769_n13100# 4.15fF
+C6 m3_2669_n13200# m3_n2650_n13200# 81.90fF
+C7 c1_n7869_n13100# c1_n13188_n13100# 4.15fF
+C8 c1_n2550_n13100# c1_2769_n13100# 4.15fF
+C9 m3_2669_n13200# m3_7988_n13200# 81.90fF
+C10 m3_n2650_n13200# c1_2769_n13100# 10.12fF
+C11 m3_n13288_n13200# c1_n13188_n13100# 305.88fF
+C12 m3_n7969_n13200# c1_n2550_n13100# 10.12fF
+C13 c1_n7869_n13100# m3_n7969_n13200# 305.88fF
+C14 m3_n2650_n13200# m3_n7969_n13200# 81.90fF
+C15 c1_n7869_n13100# c1_n2550_n13100# 4.15fF
+C16 m3_n2650_n13200# c1_n2550_n13100# 305.88fF
+C17 c1_8088_n13100# VSUBS 0.23fF
+C18 c1_2769_n13100# VSUBS 0.23fF
+C19 c1_n2550_n13100# VSUBS 0.23fF
+C20 c1_n7869_n13100# VSUBS 0.23fF
+C21 c1_n13188_n13100# VSUBS 0.23fF
+C22 m3_7988_n13200# VSUBS 63.09fF
+C23 m3_2669_n13200# VSUBS 63.09fF
+C24 m3_n2650_n13200# VSUBS 63.09fF
+C25 m3_n7969_n13200# VSUBS 63.09fF
+C26 m3_n13288_n13200# VSUBS 63.09fF
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xsky130_fd_pr__res_high_po_5p73_GW5RGE_0 vss vc_pex m1_166_166# vc_pex in m1_166_166#
++ m1_166_166# sky130_fd_pr__res_high_po_5p73_GW5RGE
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 vss in vss vss in in vss sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+Xsky130_fd_pr__cap_mim_m3_1_MA89VW_0 vss vc_pex vss vss vss vss vc_pex vc_pex vss
++ vc_pex vc_pex sky130_fd_pr__cap_mim_m3_1_MA89VW
+C0 vc_pex vss -1790.18fF
+C1 in vss -256.75fF
+C2 m1_166_166# vss 5.01fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+C0 w_n2457_n634# a_n945_n486# 0.02fF
+C1 w_n2457_n634# a_1803_n486# 0.02fF
+C2 w_n2457_n634# a_n487_n486# 0.02fF
+C3 w_n2457_n634# a_429_n486# 0.02fF
+C4 w_n2457_n634# a_887_n486# 0.02fF
+C5 w_n2457_n634# a_n2319_n486# 0.02fF
+C6 w_n2457_n634# a_n29_n486# 0.02fF
+C7 a_2261_n486# w_n2457_n634# 0.02fF
+C8 w_n2457_n634# a_n1861_n486# 0.02fF
+C9 a_n1403_n486# w_n2457_n634# 0.02fF
+C10 w_n2457_n634# a_1345_n486# 0.02fF
+C11 a_2261_n486# VSUBS 0.03fF
+C12 a_1803_n486# VSUBS 0.03fF
+C13 a_1345_n486# VSUBS 0.03fF
+C14 a_887_n486# VSUBS 0.03fF
+C15 a_429_n486# VSUBS 0.03fF
+C16 a_n29_n486# VSUBS 0.03fF
+C17 a_n487_n486# VSUBS 0.03fF
+C18 a_n945_n486# VSUBS 0.03fF
+C19 a_n1403_n486# VSUBS 0.03fF
+C20 a_n1861_n486# VSUBS 0.03fF
+C21 a_n2319_n486# VSUBS 0.03fF
+C22 a_n2261_n512# VSUBS 4.27fF
+C23 w_n2457_n634# VSUBS 21.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_591_n75# a_207_n75# 0.03fF
+C1 a_n657_n75# a_n1041_n75# 0.03fF
+C2 a_n465_n75# a_n561_n75# 0.22fF
+C3 a_n945_n75# a_n849_n75# 0.22fF
+C4 a_303_n75# a_591_n75# 0.05fF
+C5 a_1071_n75# a_687_n75# 0.03fF
+C6 a_n177_n75# a_n273_n75# 0.22fF
+C7 a_399_n75# a_495_n75# 0.22fF
+C8 a_n753_n75# a_n1041_n75# 0.05fF
+C9 a_n561_n75# a_n369_n75# 0.08fF
+C10 a_879_n75# a_495_n75# 0.03fF
+C11 a_n1229_n75# a_n1041_n75# 0.08fF
+C12 a_15_n75# a_n369_n75# 0.03fF
+C13 a_n1137_n75# a_n849_n75# 0.05fF
+C14 a_399_n75# a_783_n75# 0.03fF
+C15 a_879_n75# a_783_n75# 0.22fF
+C16 a_303_n75# a_687_n75# 0.03fF
+C17 a_591_n75# a_687_n75# 0.22fF
+C18 a_n945_n75# a_n1041_n75# 0.22fF
+C19 a_879_n75# a_975_n75# 0.22fF
+C20 a_n177_n75# a_n465_n75# 0.05fF
+C21 a_495_n75# a_783_n75# 0.05fF
+C22 a_n753_n75# a_n657_n75# 0.22fF
+C23 a_399_n75# a_15_n75# 0.03fF
+C24 a_n465_n75# a_n273_n75# 0.08fF
+C25 a_n177_n75# a_n369_n75# 0.08fF
+C26 a_399_n75# a_111_n75# 0.05fF
+C27 a_n1137_n75# a_n1041_n75# 0.22fF
+C28 a_n561_n75# a_n657_n75# 0.22fF
+C29 a_879_n75# a_1071_n75# 0.08fF
+C30 a_n273_n75# a_n369_n75# 0.22fF
+C31 a_1167_n75# a_879_n75# 0.05fF
+C32 a_975_n75# a_783_n75# 0.08fF
+C33 a_n81_n75# a_15_n75# 0.22fF
+C34 a_n753_n75# a_n561_n75# 0.08fF
+C35 a_495_n75# a_111_n75# 0.03fF
+C36 a_n945_n75# a_n657_n75# 0.05fF
+C37 a_n81_n75# a_111_n75# 0.08fF
+C38 a_n465_n75# a_n849_n75# 0.03fF
+C39 a_399_n75# a_207_n75# 0.08fF
+C40 a_399_n75# a_303_n75# 0.22fF
+C41 a_399_n75# a_591_n75# 0.08fF
+C42 a_n945_n75# a_n753_n75# 0.08fF
+C43 a_1071_n75# a_783_n75# 0.05fF
+C44 a_879_n75# a_591_n75# 0.05fF
+C45 a_1167_n75# a_783_n75# 0.03fF
+C46 a_n945_n75# a_n1229_n75# 0.05fF
+C47 a_495_n75# a_207_n75# 0.05fF
+C48 a_n81_n75# a_207_n75# 0.05fF
+C49 a_n465_n75# a_n369_n75# 0.22fF
+C50 a_1071_n75# a_975_n75# 0.22fF
+C51 a_1167_n75# a_975_n75# 0.08fF
+C52 a_n945_n75# a_n561_n75# 0.03fF
+C53 a_n849_n75# a_n1041_n75# 0.08fF
+C54 a_n177_n75# a_n81_n75# 0.22fF
+C55 a_303_n75# a_495_n75# 0.08fF
+C56 a_591_n75# a_495_n75# 0.22fF
+C57 a_303_n75# a_n81_n75# 0.03fF
+C58 a_n753_n75# a_n1137_n75# 0.03fF
+C59 a_n81_n75# a_n273_n75# 0.08fF
+C60 a_n273_n75# a_n657_n75# 0.03fF
+C61 a_n1137_n75# a_n1229_n75# 0.22fF
+C62 a_15_n75# a_111_n75# 0.22fF
+C63 a_399_n75# a_687_n75# 0.05fF
+C64 a_591_n75# a_783_n75# 0.08fF
+C65 a_879_n75# a_687_n75# 0.08fF
+C66 a_1167_n75# a_1071_n75# 0.22fF
+C67 a_591_n75# a_975_n75# 0.03fF
+C68 a_n177_n75# a_n561_n75# 0.03fF
+C69 a_495_n75# a_687_n75# 0.08fF
+C70 a_n945_n75# a_n1137_n75# 0.08fF
+C71 a_207_n75# a_15_n75# 0.08fF
+C72 a_n849_n75# a_n657_n75# 0.08fF
+C73 a_n273_n75# a_n561_n75# 0.05fF
+C74 a_n177_n75# a_15_n75# 0.08fF
+C75 a_207_n75# a_111_n75# 0.22fF
+C76 a_303_n75# a_15_n75# 0.05fF
+C77 a_n177_n75# a_111_n75# 0.05fF
+C78 a_303_n75# a_111_n75# 0.08fF
+C79 a_n465_n75# a_n81_n75# 0.03fF
+C80 a_n465_n75# a_n657_n75# 0.08fF
+C81 a_n273_n75# a_15_n75# 0.05fF
+C82 a_n753_n75# a_n849_n75# 0.22fF
+C83 a_687_n75# a_783_n75# 0.22fF
+C84 a_n273_n75# a_111_n75# 0.03fF
+C85 a_n849_n75# a_n1229_n75# 0.03fF
+C86 a_n81_n75# a_n369_n75# 0.05fF
+C87 a_n657_n75# a_n369_n75# 0.05fF
+C88 a_975_n75# a_687_n75# 0.05fF
+C89 a_n753_n75# a_n465_n75# 0.05fF
+C90 a_n849_n75# a_n561_n75# 0.05fF
+C91 a_n177_n75# a_207_n75# 0.03fF
+C92 a_303_n75# a_207_n75# 0.22fF
+C93 a_n753_n75# a_n369_n75# 0.03fF
+C94 a_1167_n75# w_n1367_n285# 0.10fF
+C95 a_1071_n75# w_n1367_n285# 0.07fF
+C96 a_975_n75# w_n1367_n285# 0.06fF
+C97 a_879_n75# w_n1367_n285# 0.05fF
+C98 a_783_n75# w_n1367_n285# 0.04fF
+C99 a_687_n75# w_n1367_n285# 0.04fF
+C100 a_591_n75# w_n1367_n285# 0.04fF
+C101 a_495_n75# w_n1367_n285# 0.04fF
+C102 a_399_n75# w_n1367_n285# 0.04fF
+C103 a_303_n75# w_n1367_n285# 0.04fF
+C104 a_207_n75# w_n1367_n285# 0.04fF
+C105 a_111_n75# w_n1367_n285# 0.04fF
+C106 a_15_n75# w_n1367_n285# 0.04fF
+C107 a_n81_n75# w_n1367_n285# 0.04fF
+C108 a_n177_n75# w_n1367_n285# 0.04fF
+C109 a_n273_n75# w_n1367_n285# 0.04fF
+C110 a_n369_n75# w_n1367_n285# 0.04fF
+C111 a_n465_n75# w_n1367_n285# 0.04fF
+C112 a_n561_n75# w_n1367_n285# 0.04fF
+C113 a_n657_n75# w_n1367_n285# 0.04fF
+C114 a_n753_n75# w_n1367_n285# 0.04fF
+C115 a_n849_n75# w_n1367_n285# 0.04fF
+C116 a_n945_n75# w_n1367_n285# 0.04fF
+C117 a_n1041_n75# w_n1367_n285# 0.04fF
+C118 a_n1137_n75# w_n1367_n285# 0.04fF
+C119 a_n1229_n75# w_n1367_n285# 0.04fF
+C120 a_n1167_n101# w_n1367_n285# 2.55fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+C0 a_n225_n75# a_159_n75# 0.03fF
+C1 a_n609_n75# a_n513_n75# 0.22fF
+C2 a_n609_n75# a_n225_n75# 0.03fF
+C3 a_n33_n75# a_351_n75# 0.03fF
+C4 a_n417_n75# a_n801_n75# 0.03fF
+C5 a_447_n75# a_159_n75# 0.05fF
+C6 a_n513_n75# a_n225_n75# 0.05fF
+C7 a_543_n75# a_447_n75# 0.22fF
+C8 a_n417_n75# a_n321_n75# 0.22fF
+C9 a_n989_n75# a_n897_n75# 0.22fF
+C10 a_735_n75# a_351_n75# 0.03fF
+C11 a_n417_n75# a_n33_n75# 0.03fF
+C12 a_159_n75# a_n129_n75# 0.05fF
+C13 a_n897_n75# a_n705_n75# 0.08fF
+C14 a_n513_n75# a_n129_n75# 0.03fF
+C15 a_n225_n75# a_n129_n75# 0.22fF
+C16 a_n321_n75# a_63_n75# 0.03fF
+C17 a_n609_n75# a_n897_n75# 0.05fF
+C18 a_255_n75# a_159_n75# 0.22fF
+C19 a_543_n75# a_255_n75# 0.05fF
+C20 a_n513_n75# a_n897_n75# 0.03fF
+C21 a_n321_n75# a_n33_n75# 0.05fF
+C22 a_159_n75# a_351_n75# 0.08fF
+C23 a_63_n75# a_n33_n75# 0.22fF
+C24 a_255_n75# a_447_n75# 0.08fF
+C25 a_543_n75# a_351_n75# 0.08fF
+C26 a_639_n75# a_927_n75# 0.05fF
+C27 a_447_n75# a_351_n75# 0.22fF
+C28 a_n989_n75# a_n801_n75# 0.08fF
+C29 a_n417_n75# a_n705_n75# 0.05fF
+C30 a_639_n75# a_735_n75# 0.22fF
+C31 a_639_n75# a_831_n75# 0.08fF
+C32 a_255_n75# a_n129_n75# 0.03fF
+C33 a_n801_n75# a_n705_n75# 0.22fF
+C34 a_n417_n75# a_n609_n75# 0.08fF
+C35 a_n417_n75# a_n513_n75# 0.22fF
+C36 a_n417_n75# a_n225_n75# 0.08fF
+C37 a_n609_n75# a_n801_n75# 0.08fF
+C38 a_n321_n75# a_n705_n75# 0.03fF
+C39 a_n513_n75# a_n801_n75# 0.05fF
+C40 a_n609_n75# a_n321_n75# 0.05fF
+C41 a_927_n75# a_735_n75# 0.08fF
+C42 a_255_n75# a_351_n75# 0.22fF
+C43 a_33_n101# a_n927_n101# 0.08fF
+C44 a_543_n75# a_639_n75# 0.22fF
+C45 a_n513_n75# a_n321_n75# 0.08fF
+C46 a_n225_n75# a_n321_n75# 0.22fF
+C47 a_927_n75# a_831_n75# 0.22fF
+C48 a_159_n75# a_63_n75# 0.22fF
+C49 a_n225_n75# a_63_n75# 0.05fF
+C50 a_639_n75# a_447_n75# 0.08fF
+C51 a_159_n75# a_n33_n75# 0.08fF
+C52 a_735_n75# a_831_n75# 0.22fF
+C53 a_n417_n75# a_n129_n75# 0.05fF
+C54 a_447_n75# a_63_n75# 0.03fF
+C55 a_n225_n75# a_n33_n75# 0.08fF
+C56 a_543_n75# a_927_n75# 0.03fF
+C57 a_n897_n75# a_n801_n75# 0.22fF
+C58 a_n321_n75# a_n129_n75# 0.08fF
+C59 a_n989_n75# a_n705_n75# 0.05fF
+C60 a_543_n75# a_735_n75# 0.08fF
+C61 a_n129_n75# a_63_n75# 0.08fF
+C62 a_n989_n75# a_n609_n75# 0.03fF
+C63 a_543_n75# a_831_n75# 0.05fF
+C64 a_255_n75# a_639_n75# 0.03fF
+C65 a_447_n75# a_735_n75# 0.05fF
+C66 a_n129_n75# a_n33_n75# 0.22fF
+C67 a_255_n75# a_63_n75# 0.08fF
+C68 a_447_n75# a_831_n75# 0.03fF
+C69 a_n609_n75# a_n705_n75# 0.22fF
+C70 a_639_n75# a_351_n75# 0.05fF
+C71 a_255_n75# a_n33_n75# 0.05fF
+C72 a_n513_n75# a_n705_n75# 0.08fF
+C73 a_63_n75# a_351_n75# 0.05fF
+C74 a_543_n75# a_159_n75# 0.03fF
+C75 a_927_n75# w_n1127_n285# 0.04fF
+C76 a_831_n75# w_n1127_n285# 0.04fF
+C77 a_735_n75# w_n1127_n285# 0.04fF
+C78 a_639_n75# w_n1127_n285# 0.04fF
+C79 a_543_n75# w_n1127_n285# 0.04fF
+C80 a_447_n75# w_n1127_n285# 0.04fF
+C81 a_351_n75# w_n1127_n285# 0.04fF
+C82 a_255_n75# w_n1127_n285# 0.04fF
+C83 a_159_n75# w_n1127_n285# 0.04fF
+C84 a_63_n75# w_n1127_n285# 0.04fF
+C85 a_n33_n75# w_n1127_n285# 0.04fF
+C86 a_n129_n75# w_n1127_n285# 0.04fF
+C87 a_n225_n75# w_n1127_n285# 0.04fF
+C88 a_n321_n75# w_n1127_n285# 0.04fF
+C89 a_n417_n75# w_n1127_n285# 0.04fF
+C90 a_n513_n75# w_n1127_n285# 0.04fF
+C91 a_n609_n75# w_n1127_n285# 0.04fF
+C92 a_n705_n75# w_n1127_n285# 0.04fF
+C93 a_n801_n75# w_n1127_n285# 0.04fF
+C94 a_n897_n75# w_n1127_n285# 0.04fF
+C95 a_n989_n75# w_n1127_n285# 0.04fF
+C96 a_33_n101# w_n1127_n285# 0.99fF
+C97 a_n927_n101# w_n1127_n285# 0.99fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_639_n150# 0.07fF
+C1 a_n33_n150# a_351_n150# 0.07fF
+C2 a_447_n150# a_63_n150# 0.07fF
+C3 a_n513_n150# a_n609_n150# 0.43fF
+C4 a_n129_n150# a_63_n150# 0.16fF
+C5 a_735_n150# a_927_n150# 0.16fF
+C6 a_831_n150# a_543_n150# 0.10fF
+C7 a_n33_n150# a_63_n150# 0.43fF
+C8 a_n321_n150# a_63_n150# 0.07fF
+C9 a_831_n150# a_447_n150# 0.07fF
+C10 a_63_n150# a_n225_n150# 0.10fF
+C11 a_639_n150# a_351_n150# 0.10fF
+C12 a_n417_n150# a_n705_n150# 0.10fF
+C13 a_n801_n150# a_n705_n150# 0.43fF
+C14 a_n417_n150# a_n801_n150# 0.07fF
+C15 a_255_n150# a_351_n150# 0.43fF
+C16 a_159_n150# a_543_n150# 0.07fF
+C17 a_33_n247# a_n927_n247# 0.09fF
+C18 a_735_n150# a_639_n150# 0.43fF
+C19 a_n989_n150# a_n609_n150# 0.07fF
+C20 a_159_n150# a_447_n150# 0.10fF
+C21 a_n897_n150# a_n705_n150# 0.16fF
+C22 a_n897_n150# a_n801_n150# 0.43fF
+C23 a_543_n150# a_447_n150# 0.43fF
+C24 a_831_n150# a_927_n150# 0.43fF
+C25 a_255_n150# a_63_n150# 0.16fF
+C26 a_n129_n150# a_159_n150# 0.10fF
+C27 a_n417_n150# a_n129_n150# 0.10fF
+C28 a_n33_n150# a_159_n150# 0.16fF
+C29 a_n417_n150# a_n33_n150# 0.07fF
+C30 a_n321_n150# a_n705_n150# 0.07fF
+C31 a_n417_n150# a_n321_n150# 0.43fF
+C32 a_159_n150# a_n225_n150# 0.07fF
+C33 a_n417_n150# a_n225_n150# 0.16fF
+C34 a_735_n150# a_351_n150# 0.07fF
+C35 a_831_n150# a_639_n150# 0.16fF
+C36 a_927_n150# a_543_n150# 0.07fF
+C37 a_351_n150# a_63_n150# 0.10fF
+C38 a_n129_n150# a_n33_n150# 0.43fF
+C39 a_n129_n150# a_n321_n150# 0.16fF
+C40 a_n513_n150# a_n705_n150# 0.16fF
+C41 a_n513_n150# a_n417_n150# 0.43fF
+C42 a_255_n150# a_159_n150# 0.43fF
+C43 a_n513_n150# a_n801_n150# 0.10fF
+C44 a_n129_n150# a_n225_n150# 0.43fF
+C45 a_639_n150# a_543_n150# 0.43fF
+C46 a_n33_n150# a_n321_n150# 0.10fF
+C47 a_n609_n150# a_n705_n150# 0.43fF
+C48 a_255_n150# a_543_n150# 0.10fF
+C49 a_n33_n150# a_n225_n150# 0.16fF
+C50 a_n417_n150# a_n609_n150# 0.16fF
+C51 a_639_n150# a_447_n150# 0.16fF
+C52 a_n609_n150# a_n801_n150# 0.16fF
+C53 a_n321_n150# a_n225_n150# 0.43fF
+C54 a_n897_n150# a_n513_n150# 0.07fF
+C55 a_255_n150# a_447_n150# 0.16fF
+C56 a_n897_n150# a_n609_n150# 0.10fF
+C57 a_831_n150# a_735_n150# 0.43fF
+C58 a_n513_n150# a_n129_n150# 0.07fF
+C59 a_255_n150# a_n129_n150# 0.07fF
+C60 a_159_n150# a_351_n150# 0.16fF
+C61 a_n989_n150# a_n705_n150# 0.10fF
+C62 a_n989_n150# a_n801_n150# 0.16fF
+C63 a_n513_n150# a_n321_n150# 0.16fF
+C64 a_255_n150# a_n33_n150# 0.10fF
+C65 a_351_n150# a_543_n150# 0.16fF
+C66 a_927_n150# a_639_n150# 0.10fF
+C67 a_n513_n150# a_n225_n150# 0.10fF
+C68 a_n897_n150# a_n989_n150# 0.43fF
+C69 a_n609_n150# a_n321_n150# 0.10fF
+C70 a_351_n150# a_447_n150# 0.43fF
+C71 a_735_n150# a_543_n150# 0.16fF
+C72 a_n609_n150# a_n225_n150# 0.07fF
+C73 a_159_n150# a_63_n150# 0.43fF
+C74 a_735_n150# a_447_n150# 0.10fF
+C75 a_927_n150# VSUBS 0.03fF
+C76 a_831_n150# VSUBS 0.03fF
+C77 a_735_n150# VSUBS 0.03fF
+C78 a_639_n150# VSUBS 0.03fF
+C79 a_543_n150# VSUBS 0.03fF
+C80 a_447_n150# VSUBS 0.03fF
+C81 a_351_n150# VSUBS 0.03fF
+C82 a_255_n150# VSUBS 0.03fF
+C83 a_159_n150# VSUBS 0.03fF
+C84 a_63_n150# VSUBS 0.03fF
+C85 a_n33_n150# VSUBS 0.03fF
+C86 a_n129_n150# VSUBS 0.03fF
+C87 a_n225_n150# VSUBS 0.03fF
+C88 a_n321_n150# VSUBS 0.03fF
+C89 a_n417_n150# VSUBS 0.03fF
+C90 a_n513_n150# VSUBS 0.03fF
+C91 a_n609_n150# VSUBS 0.03fF
+C92 a_n705_n150# VSUBS 0.03fF
+C93 a_n801_n150# VSUBS 0.03fF
+C94 a_n897_n150# VSUBS 0.03fF
+C95 a_n989_n150# VSUBS 0.03fF
+C96 a_33_n247# VSUBS 1.04fF
+C97 a_n927_n247# VSUBS 1.04fF
+C98 w_n1127_n369# VSUBS 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+C0 a_n745_n44# a_n387_n44# 0.04fF
+C1 a_1761_n44# a_1403_n44# 0.04fF
+C2 a_1045_n44# a_687_n44# 0.04fF
+C3 a_n1461_n44# a_n1103_n44# 0.04fF
+C4 a_1403_n44# a_1045_n44# 0.04fF
+C5 a_n387_n44# a_n29_n44# 0.04fF
+C6 a_n1819_n44# a_n1461_n44# 0.04fF
+C7 a_329_n44# a_687_n44# 0.04fF
+C8 a_n745_n44# a_n1103_n44# 0.04fF
+C9 a_n29_n44# a_329_n44# 0.04fF
+C10 a_1761_n44# w_n1957_n254# 0.04fF
+C11 a_1403_n44# w_n1957_n254# 0.04fF
+C12 a_1045_n44# w_n1957_n254# 0.04fF
+C13 a_687_n44# w_n1957_n254# 0.04fF
+C14 a_329_n44# w_n1957_n254# 0.04fF
+C15 a_n29_n44# w_n1957_n254# 0.04fF
+C16 a_n387_n44# w_n1957_n254# 0.04fF
+C17 a_n745_n44# w_n1957_n254# 0.04fF
+C18 a_n1103_n44# w_n1957_n254# 0.04fF
+C19 a_n1461_n44# w_n1957_n254# 0.04fF
+C20 a_n1819_n44# w_n1957_n254# 0.04fF
+C21 a_n1761_n132# w_n1957_n254# 3.23fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_1071_n150# a_1167_n150# 0.43fF
+C1 a_n849_n150# a_n1229_n150# 0.07fF
+C2 a_n1041_n150# a_n945_n150# 0.43fF
+C3 a_687_n150# a_591_n150# 0.43fF
+C4 a_399_n150# a_15_n150# 0.07fF
+C5 a_111_n150# a_207_n150# 0.43fF
+C6 a_303_n150# a_15_n150# 0.10fF
+C7 a_n465_n150# a_n273_n150# 0.16fF
+C8 a_n1041_n150# a_n753_n150# 0.10fF
+C9 a_n945_n150# a_n753_n150# 0.16fF
+C10 a_879_n150# a_495_n150# 0.07fF
+C11 a_n369_n150# a_n273_n150# 0.43fF
+C12 a_n657_n150# a_n273_n150# 0.07fF
+C13 a_111_n150# a_n273_n150# 0.07fF
+C14 a_n273_n150# a_n561_n150# 0.10fF
+C15 a_783_n150# a_975_n150# 0.16fF
+C16 a_n81_n150# a_207_n150# 0.10fF
+C17 a_399_n150# a_495_n150# 0.43fF
+C18 a_687_n150# a_783_n150# 0.43fF
+C19 a_n369_n150# a_15_n150# 0.07fF
+C20 a_879_n150# w_n1367_n369# 0.04fF
+C21 a_1071_n150# a_783_n150# 0.10fF
+C22 a_111_n150# a_15_n150# 0.43fF
+C23 a_n1137_n150# a_n1229_n150# 0.43fF
+C24 a_207_n150# a_591_n150# 0.07fF
+C25 a_1167_n150# a_783_n150# 0.07fF
+C26 a_303_n150# a_495_n150# 0.16fF
+C27 a_n1137_n150# a_n849_n150# 0.10fF
+C28 a_303_n150# a_399_n150# 0.43fF
+C29 a_n1041_n150# a_n657_n150# 0.07fF
+C30 a_591_n150# a_783_n150# 0.16fF
+C31 a_n81_n150# a_n273_n150# 0.16fF
+C32 a_n945_n150# a_n657_n150# 0.10fF
+C33 a_n465_n150# a_n177_n150# 0.10fF
+C34 a_n753_n150# a_n465_n150# 0.10fF
+C35 a_n945_n150# a_n561_n150# 0.07fF
+C36 a_n369_n150# a_n177_n150# 0.16fF
+C37 a_n81_n150# a_15_n150# 0.43fF
+C38 a_n753_n150# a_n369_n150# 0.07fF
+C39 a_n753_n150# a_n657_n150# 0.43fF
+C40 a_111_n150# a_n177_n150# 0.10fF
+C41 a_111_n150# a_495_n150# 0.07fF
+C42 a_n177_n150# a_n561_n150# 0.07fF
+C43 a_111_n150# a_399_n150# 0.10fF
+C44 a_n753_n150# a_n561_n150# 0.16fF
+C45 a_879_n150# a_975_n150# 0.43fF
+C46 a_n1041_n150# a_n1229_n150# 0.16fF
+C47 a_687_n150# a_879_n150# 0.16fF
+C48 a_n945_n150# a_n1229_n150# 0.10fF
+C49 a_n1041_n150# a_n849_n150# 0.16fF
+C50 a_1071_n150# a_879_n150# 0.16fF
+C51 a_111_n150# a_303_n150# 0.16fF
+C52 a_n945_n150# a_n849_n150# 0.43fF
+C53 a_1167_n150# a_879_n150# 0.10fF
+C54 a_687_n150# a_495_n150# 0.16fF
+C55 a_687_n150# a_399_n150# 0.10fF
+C56 a_n465_n150# a_n369_n150# 0.43fF
+C57 a_n465_n150# a_n657_n150# 0.16fF
+C58 a_591_n150# a_879_n150# 0.10fF
+C59 a_n81_n150# a_n177_n150# 0.43fF
+C60 a_207_n150# a_15_n150# 0.16fF
+C61 a_n465_n150# a_n561_n150# 0.43fF
+C62 a_975_n150# w_n1367_n369# 0.05fF
+C63 a_n849_n150# a_n753_n150# 0.43fF
+C64 a_n369_n150# a_n657_n150# 0.10fF
+C65 a_303_n150# a_687_n150# 0.07fF
+C66 a_591_n150# a_495_n150# 0.43fF
+C67 a_n369_n150# a_n561_n150# 0.16fF
+C68 a_591_n150# a_399_n150# 0.16fF
+C69 a_1071_n150# w_n1367_n369# 0.07fF
+C70 a_n657_n150# a_n561_n150# 0.43fF
+C71 a_303_n150# a_n81_n150# 0.07fF
+C72 a_1167_n150# w_n1367_n369# 0.14fF
+C73 a_15_n150# a_n273_n150# 0.10fF
+C74 a_303_n150# a_591_n150# 0.10fF
+C75 a_n1041_n150# a_n1137_n150# 0.43fF
+C76 a_n81_n150# a_n465_n150# 0.07fF
+C77 a_n849_n150# a_n465_n150# 0.07fF
+C78 a_783_n150# a_879_n150# 0.43fF
+C79 a_n945_n150# a_n1137_n150# 0.16fF
+C80 a_207_n150# a_n177_n150# 0.07fF
+C81 a_207_n150# a_495_n150# 0.10fF
+C82 a_207_n150# a_399_n150# 0.16fF
+C83 a_n81_n150# a_n369_n150# 0.10fF
+C84 a_111_n150# a_n81_n150# 0.16fF
+C85 a_n849_n150# a_n657_n150# 0.16fF
+C86 a_783_n150# a_495_n150# 0.10fF
+C87 a_399_n150# a_783_n150# 0.07fF
+C88 a_n1137_n150# a_n753_n150# 0.07fF
+C89 a_n849_n150# a_n561_n150# 0.10fF
+C90 a_303_n150# a_207_n150# 0.43fF
+C91 a_687_n150# a_975_n150# 0.10fF
+C92 a_n177_n150# a_n273_n150# 0.43fF
+C93 a_1071_n150# a_975_n150# 0.43fF
+C94 a_1071_n150# a_687_n150# 0.07fF
+C95 a_1167_n150# a_975_n150# 0.16fF
+C96 a_n177_n150# a_15_n150# 0.16fF
+C97 a_591_n150# a_975_n150# 0.07fF
+C98 a_1167_n150# VSUBS 0.03fF
+C99 a_1071_n150# VSUBS 0.03fF
+C100 a_975_n150# VSUBS 0.03fF
+C101 a_879_n150# VSUBS 0.03fF
+C102 a_783_n150# VSUBS 0.03fF
+C103 a_687_n150# VSUBS 0.03fF
+C104 a_591_n150# VSUBS 0.03fF
+C105 a_495_n150# VSUBS 0.03fF
+C106 a_399_n150# VSUBS 0.03fF
+C107 a_303_n150# VSUBS 0.03fF
+C108 a_207_n150# VSUBS 0.03fF
+C109 a_111_n150# VSUBS 0.03fF
+C110 a_15_n150# VSUBS 0.03fF
+C111 a_n81_n150# VSUBS 0.03fF
+C112 a_n177_n150# VSUBS 0.03fF
+C113 a_n273_n150# VSUBS 0.03fF
+C114 a_n369_n150# VSUBS 0.03fF
+C115 a_n465_n150# VSUBS 0.03fF
+C116 a_n561_n150# VSUBS 0.03fF
+C117 a_n657_n150# VSUBS 0.03fF
+C118 a_n753_n150# VSUBS 0.03fF
+C119 a_n849_n150# VSUBS 0.03fF
+C120 a_n945_n150# VSUBS 0.03fF
+C121 a_n1041_n150# VSUBS 0.03fF
+C122 a_n1137_n150# VSUBS 0.03fF
+C123 a_n1229_n150# VSUBS 0.03fF
+C124 a_n1167_n247# VSUBS 2.63fF
+C125 w_n1367_n369# VSUBS 7.85fF
+.ends
+
+.subckt charge_pump nswitch pswitch vdd nUp vss Down biasp w_2544_775# out iref nDown
++ Up w_6648_570#
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+C0 nswitch Down 2.27fF
+C1 pswitch vdd 3.98fF
+C2 nDown Down 0.13fF
+C3 nswitch biasp 0.03fF
+C4 nswitch nDown 0.31fF
+C5 nswitch out 1.28fF
+C6 nUp Down 0.25fF
+C7 Up nUp 0.15fF
+C8 pswitch Up 0.70fF
+C9 nswitch iref 1.91fF
+C10 nswitch pswitch 0.06fF
+C11 nswitch vdd 0.07fF
+C12 iref biasp 0.80fF
+C13 pswitch biasp 3.11fF
+C14 out nUp 0.31fF
+C15 pswitch out 4.91fF
+C16 vdd biasp 2.64fF
+C17 vdd out 6.66fF
+C18 pswitch nUp 5.66fF
+C19 vdd vss 35.71fF
+C20 Down vss 4.77fF
+C21 Up vss 1.17fF
+C22 nswitch vss 6.39fF
+C23 nDown vss 1.11fF
+C24 biasp vss 8.73fF
+C25 iref vss 10.12fF
+C26 out vss -3.49fF
+C27 pswitch vss 3.45fF
+C28 nUp vss 5.85fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n111_n156# a_n15_n156# 0.02fF
+C1 a_111_n125# w_n311_n344# 0.14fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_n173_n125# w_n311_n344# 0.14fF
+C4 a_81_n156# a_n15_n156# 0.02fF
+C5 w_n311_n344# a_15_n125# 0.09fF
+C6 a_n81_n125# a_n173_n125# 0.36fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_111_n125# a_n173_n125# 0.08fF
+C9 a_111_n125# a_15_n125# 0.36fF
+C10 a_n173_n125# a_15_n125# 0.13fF
+C11 a_n81_n125# w_n311_n344# 0.09fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n173_n125# a_111_n125# 0.08fF
+C3 a_n111_n151# a_n15_n151# 0.02fF
+C4 a_n15_n151# a_81_n151# 0.02fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_15_n125# a_111_n125# 0.36fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_187_n605# vdd 0.55fF
+C1 m1_187_n605# m1_45_n513# 0.36fF
+C2 vdd m1_45_n513# 0.69fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n173_n125# 0.13fF
+C1 w_n311_n344# a_n173_n125# 0.14fF
+C2 a_15_n125# w_n311_n344# 0.09fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_111_n125# a_15_n125# 0.36fF
+C5 a_111_n125# w_n311_n344# 0.14fF
+C6 a_n81_n125# a_n173_n125# 0.36fF
+C7 a_n81_n125# a_15_n125# 0.36fF
+C8 a_n81_n125# w_n311_n344# 0.09fF
+C9 a_n81_n125# a_111_n125# 0.13fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_15_n125# a_n81_n125# 0.36fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 in out 0.32fF
+C1 vdd out 0.10fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd inverter_cp_x1_2/in 0.21fF
+C1 vdd inverter_cp_x1_0/out 0.28fF
+C2 vdd nCLK_d 0.03fF
+C3 CLK_d inverter_cp_x1_2/in 0.12fF
+C4 CLK inverter_cp_x1_2/in 0.31fF
+C5 CLK inverter_cp_x1_0/out 0.31fF
+C6 inverter_cp_x1_0/out nCLK_d 0.11fF
+C7 CLK_d vdd 0.03fF
+C8 vdd CLK 0.36fF
+C9 CLK_d vss 0.96fF
+C10 inverter_cp_x1_2/in vss 2.01fF
+C11 CLK vss 3.03fF
+C12 inverter_cp_x1_0/out vss 1.97fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# w_n263_n314# 0.11fF
+C1 a_n125_n95# a_n33_n95# 0.28fF
+C2 w_n263_n314# a_63_n95# 0.11fF
+C3 a_n33_n95# a_63_n95# 0.28fF
+C4 a_n125_n95# a_63_n95# 0.10fF
+C5 w_n263_n314# a_n33_n95# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_n81_n125# a_n129_n213# 0.10fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_111_n125# a_n173_n125# 0.08fF
+C4 a_n129_n213# a_111_n125# 0.01fF
+C5 a_15_n125# a_111_n125# 0.36fF
+C6 a_n129_n213# a_n173_n125# 0.02fF
+C7 a_n81_n125# a_111_n125# 0.13fF
+C8 a_15_n125# a_n173_n125# 0.13fF
+C9 a_n129_n213# a_15_n125# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n33_n95# a_n125_n95# 0.88fF
+C1 a_n33_n95# a_n81_n183# 0.10fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 nD Q 0.05fF
+C1 m1_657_280# nQ 1.41fF
+C2 nQ Q 0.93fF
+C3 vdd nQ 0.16fF
+C4 D nQ 0.05fF
+C5 m1_657_280# Q 0.94fF
+C6 m1_657_280# CLK 0.24fF
+C7 nD nQ 0.05fF
+C8 vdd Q 0.16fF
+C9 D Q 0.05fF
+C10 D vss 0.53fF
+C11 m1_657_280# vss 1.88fF
+C12 nD vss 0.16fF
+C13 CLK vss 0.87fF
+C14 Q vss -0.55fF
+C15 nQ vss 1.16fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ Q D latch_diff_1/m1_657_280# latch_diff_0/D latch_diff_1/nD vdd CLK clock_inverter_0/inverter_cp_x1_0/out
++ nCLK latch_diff_0/nD
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C1 latch_diff_1/nD Q 0.01fF
+C2 nQ latch_diff_1/nD 0.08fF
+C3 latch_diff_1/D vdd 0.03fF
+C4 latch_diff_0/nD vdd 0.14fF
+C5 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
+C6 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C7 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
+C8 latch_diff_0/D vdd 0.09fF
+C9 latch_diff_1/nD latch_diff_1/D 0.33fF
+C10 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C11 latch_diff_1/nD latch_diff_0/D 0.04fF
+C12 nQ latch_diff_1/D 0.11fF
+C13 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C14 latch_diff_0/nD latch_diff_0/m1_657_280# 0.38fF
+C15 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
+C16 latch_diff_0/nD latch_diff_1/D 0.41fF
+C17 latch_diff_1/nD vdd 0.02fF
+C18 latch_diff_0/D latch_diff_1/D 0.11fF
+C19 latch_diff_1/m1_657_280# vss 0.64fF
+C20 nCLK vss 0.83fF
+C21 Q vss -0.92fF
+C22 nQ vss 0.57fF
+C23 latch_diff_0/m1_657_280# vss 0.72fF
+C24 CLK vss 0.83fF
+C25 latch_diff_1/D vss -0.30fF
+C26 latch_diff_1/nD vss 1.83fF
+C27 latch_diff_0/D vss 1.29fF
+C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C29 D vss 3.27fF
+C30 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# a_159_n84# 0.04fF
+C1 a_159_n84# a_63_n84# 0.24fF
+C2 a_33_n110# a_129_n110# 0.02fF
+C3 a_n33_n84# a_159_n84# 0.09fF
+C4 a_n221_n84# a_63_n84# 0.05fF
+C5 w_n359_n303# a_159_n84# 0.08fF
+C6 a_n33_n84# a_n221_n84# 0.09fF
+C7 a_33_n110# a_n63_n110# 0.02fF
+C8 a_n129_n84# a_159_n84# 0.05fF
+C9 a_n159_n110# a_n63_n110# 0.02fF
+C10 a_n221_n84# w_n359_n303# 0.08fF
+C11 a_n33_n84# a_63_n84# 0.24fF
+C12 a_n129_n84# a_n221_n84# 0.24fF
+C13 w_n359_n303# a_63_n84# 0.06fF
+C14 a_n129_n84# a_63_n84# 0.09fF
+C15 a_n33_n84# w_n359_n303# 0.05fF
+C16 a_n33_n84# a_n129_n84# 0.24fF
+C17 a_n129_n84# w_n359_n303# 0.06fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_n63_n68# 0.02fF
+C1 a_n63_n68# a_n159_n68# 0.02fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_159_n42# a_63_n42# 0.12fF
+C4 a_n221_n42# a_63_n42# 0.03fF
+C5 a_n33_n42# a_159_n42# 0.05fF
+C6 a_n129_n42# a_63_n42# 0.05fF
+C7 a_n33_n42# a_n221_n42# 0.05fF
+C8 a_n221_n42# a_159_n42# 0.02fF
+C9 a_n33_n42# a_n129_n42# 0.12fF
+C10 a_159_n42# a_n129_n42# 0.03fF
+C11 a_n221_n42# a_n129_n42# 0.12fF
+C12 a_129_n68# a_33_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in vdd 0.33fF
+C1 in out 0.67fF
+C2 vdd out 0.62fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_33_n68# a_n63_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_n125_n42# a_63_n42# 0.05fF
+C3 a_n33_n42# a_63_n42# 0.12fF
+C4 a_63_n42# w_n263_n252# 0.09fF
+C5 a_n33_n42# w_n263_n252# 0.07fF
+C6 a_n125_n42# w_n263_n252# 0.09fF
+C7 a_33_n68# w_n263_n252# 0.05fF
+C8 a_n63_n68# w_n263_n252# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 w_n263_n303# a_63_n84# 0.10fF
+C1 a_n125_n84# a_63_n84# 0.09fF
+C2 a_n125_n84# w_n263_n303# 0.10fF
+C3 a_n33_n84# a_63_n84# 0.24fF
+C4 w_n263_n303# a_n33_n84# 0.07fF
+C5 a_n125_n84# a_n33_n84# 0.24fF
+C6 a_n63_n110# a_33_n110# 0.02fF
+C7 a_63_n84# VSUBS 0.03fF
+C8 a_n33_n84# VSUBS 0.03fF
+C9 a_n125_n84# VSUBS 0.03fF
+C10 a_33_n110# VSUBS 0.05fF
+C11 a_n63_n110# VSUBS 0.05fF
+C12 w_n263_n303# VSUBS 1.74fF
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+C0 out vdd 0.15fF
+C1 in vdd 0.01fF
+C2 in out 0.30fF
+C3 vdd vss 2.93fF
+C4 out vss 0.66fF
+C5 in vss 0.72fF
+.ends
+
+.subckt div_by_2 nout_div clock_inverter_0/inverter_cp_x1_2/in vdd CLK_2 nCLK_2 o1
++ out_div vss o2 clock_inverter_0/inverter_cp_x1_0/out CLK
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nout_div out_div nout_div DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ DFlipFlop_0/latch_diff_1/nD vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
+Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+C0 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C1 vdd out_div 0.03fF
+C2 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C3 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
+C4 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C5 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C7 o1 out_div 0.01fF
+C8 o1 vdd 0.14fF
+C9 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C10 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C11 nCLK_2 vdd 0.08fF
+C12 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C13 o2 vdd 0.14fF
+C14 out_div nout_div 0.22fF
+C15 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C16 vdd nout_div 0.16fF
+C17 CLK_2 vdd 0.08fF
+C18 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
+C19 nCLK_2 o2 0.11fF
+C20 CLK_2 o1 0.11fF
+C21 DFlipFlop_0/CLK vdd 0.40fF
+C22 DFlipFlop_0/nCLK vdd 0.30fF
+C23 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
+C24 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C25 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C26 DFlipFlop_0/CLK nout_div 0.42fF
+C27 DFlipFlop_0/latch_diff_1/nD nout_div 1.18fF
+C28 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C29 DFlipFlop_0/nCLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.46fF
+C30 DFlipFlop_0/nCLK nout_div 0.43fF
+C31 DFlipFlop_0/latch_diff_0/D nout_div 0.09fF
+C32 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C33 DFlipFlop_0/latch_diff_0/nD nout_div 0.07fF
+C34 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C35 o2 vss 2.21fF
+C36 nCLK_2 vss 1.08fF
+C37 o1 vss 2.21fF
+C38 CLK_2 vss 1.08fF
+C39 DFlipFlop_0/CLK vss 1.03fF
+C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C41 CLK vss 3.27fF
+C42 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C43 DFlipFlop_0/nCLK vss 1.76fF
+C44 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
+C45 out_div vss -0.77fF
+C46 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
+C48 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C51 nout_div vss 4.41fF
+C52 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
+C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C54 vdd vss 64.43fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n33_181# a_15_n150# 0.01fF
+C2 a_n73_n150# w_n211_n369# 0.20fF
+C3 a_n33_181# w_n211_n369# 0.05fF
+C4 a_n33_181# a_n73_n150# 0.01fF
+C5 w_n211_n369# a_15_n150# 0.20fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_255_n150# a_63_n150# 0.16fF
+C1 a_n225_n150# a_n465_172# 0.10fF
+C2 a_n129_n150# a_n465_172# 0.10fF
+C3 a_n33_n150# a_159_n150# 0.16fF
+C4 a_n417_n150# a_n321_n150# 0.43fF
+C5 a_255_n150# a_n465_172# 0.10fF
+C6 a_351_n150# a_159_n150# 0.16fF
+C7 a_n465_172# a_63_n150# 0.10fF
+C8 a_447_n150# a_159_n150# 0.10fF
+C9 a_n509_n150# a_n321_n150# 0.16fF
+C10 a_n321_n150# a_n33_n150# 0.10fF
+C11 a_n417_n150# a_n225_n150# 0.16fF
+C12 a_n417_n150# a_n129_n150# 0.10fF
+C13 a_n509_n150# a_n225_n150# 0.10fF
+C14 a_n225_n150# a_n33_n150# 0.16fF
+C15 a_n509_n150# a_n129_n150# 0.07fF
+C16 a_n129_n150# a_n33_n150# 0.43fF
+C17 a_255_n150# a_n33_n150# 0.10fF
+C18 a_63_n150# a_n33_n150# 0.43fF
+C19 a_255_n150# a_351_n150# 0.43fF
+C20 a_n417_n150# a_n465_172# 0.10fF
+C21 a_63_n150# a_351_n150# 0.10fF
+C22 a_255_n150# a_447_n150# 0.16fF
+C23 a_447_n150# a_63_n150# 0.07fF
+C24 a_n509_n150# a_n465_172# 0.01fF
+C25 a_n465_172# a_n33_n150# 0.10fF
+C26 a_n225_n150# a_159_n150# 0.07fF
+C27 a_n465_172# a_351_n150# 0.10fF
+C28 a_n129_n150# a_159_n150# 0.10fF
+C29 a_447_n150# a_n465_172# 0.01fF
+C30 a_255_n150# a_159_n150# 0.43fF
+C31 a_n225_n150# a_n321_n150# 0.43fF
+C32 a_63_n150# a_159_n150# 0.43fF
+C33 a_n129_n150# a_n321_n150# 0.16fF
+C34 a_n509_n150# a_n417_n150# 0.43fF
+C35 a_n417_n150# a_n33_n150# 0.07fF
+C36 a_n321_n150# a_63_n150# 0.07fF
+C37 a_n465_172# a_159_n150# 0.10fF
+C38 a_n225_n150# a_n129_n150# 0.43fF
+C39 a_351_n150# a_n33_n150# 0.07fF
+C40 a_n465_172# a_n321_n150# 0.10fF
+C41 a_255_n150# a_n129_n150# 0.07fF
+C42 a_n225_n150# a_63_n150# 0.10fF
+C43 a_n129_n150# a_63_n150# 0.16fF
+C44 a_447_n150# a_351_n150# 0.43fF
+C45 a_447_n150# w_n647_n360# 0.17fF
+C46 a_351_n150# w_n647_n360# 0.10fF
+C47 a_255_n150# w_n647_n360# 0.08fF
+C48 a_159_n150# w_n647_n360# 0.07fF
+C49 a_63_n150# w_n647_n360# 0.04fF
+C50 a_n33_n150# w_n647_n360# 0.04fF
+C51 a_n129_n150# w_n647_n360# 0.04fF
+C52 a_n225_n150# w_n647_n360# 0.07fF
+C53 a_n321_n150# w_n647_n360# 0.08fF
+C54 a_n417_n150# w_n647_n360# 0.10fF
+C55 a_n509_n150# w_n647_n360# 0.17fF
+C56 a_n465_172# w_n647_n360# 1.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_351_n150# a_159_n150# 0.16fF
+C1 a_n465_n247# a_351_n150# 0.08fF
+C2 a_447_n150# w_n647_n369# 0.14fF
+C3 a_n33_n150# a_n225_n150# 0.16fF
+C4 a_63_n150# a_n33_n150# 0.43fF
+C5 a_n225_n150# w_n647_n369# 0.04fF
+C6 a_n321_n150# a_n225_n150# 0.43fF
+C7 a_n509_n150# w_n647_n369# 0.14fF
+C8 a_n321_n150# a_n509_n150# 0.16fF
+C9 a_n33_n150# a_n417_n150# 0.07fF
+C10 a_63_n150# w_n647_n369# 0.02fF
+C11 a_63_n150# a_n321_n150# 0.07fF
+C12 a_n417_n150# w_n647_n369# 0.07fF
+C13 a_n417_n150# a_n321_n150# 0.43fF
+C14 a_255_n150# a_159_n150# 0.43fF
+C15 a_n465_n247# a_255_n150# 0.08fF
+C16 a_n129_n150# a_159_n150# 0.10fF
+C17 a_n465_n247# a_n129_n150# 0.08fF
+C18 a_351_n150# a_255_n150# 0.43fF
+C19 a_n33_n150# w_n647_n369# 0.02fF
+C20 a_n33_n150# a_n321_n150# 0.10fF
+C21 a_n321_n150# w_n647_n369# 0.05fF
+C22 a_447_n150# a_159_n150# 0.10fF
+C23 a_351_n150# a_447_n150# 0.43fF
+C24 a_n225_n150# a_159_n150# 0.07fF
+C25 a_n465_n247# a_n225_n150# 0.08fF
+C26 a_63_n150# a_159_n150# 0.43fF
+C27 a_63_n150# a_n465_n247# 0.08fF
+C28 a_n465_n247# a_n417_n150# 0.08fF
+C29 a_63_n150# a_351_n150# 0.10fF
+C30 a_n129_n150# a_255_n150# 0.07fF
+C31 a_n33_n150# a_159_n150# 0.16fF
+C32 a_447_n150# a_255_n150# 0.16fF
+C33 a_n465_n247# a_n33_n150# 0.08fF
+C34 w_n647_n369# a_159_n150# 0.04fF
+C35 a_n465_n247# w_n647_n369# 0.47fF
+C36 a_n465_n247# a_n321_n150# 0.08fF
+C37 a_n33_n150# a_351_n150# 0.07fF
+C38 a_351_n150# w_n647_n369# 0.07fF
+C39 a_n129_n150# a_n225_n150# 0.43fF
+C40 a_n129_n150# a_n509_n150# 0.07fF
+C41 a_63_n150# a_255_n150# 0.16fF
+C42 a_63_n150# a_n129_n150# 0.16fF
+C43 a_n129_n150# a_n417_n150# 0.10fF
+C44 a_63_n150# a_447_n150# 0.07fF
+C45 a_n33_n150# a_255_n150# 0.10fF
+C46 a_n129_n150# a_n33_n150# 0.43fF
+C47 a_n225_n150# a_n509_n150# 0.10fF
+C48 a_255_n150# w_n647_n369# 0.05fF
+C49 a_63_n150# a_n225_n150# 0.10fF
+C50 a_n129_n150# w_n647_n369# 0.02fF
+C51 a_n129_n150# a_n321_n150# 0.16fF
+C52 a_n417_n150# a_n225_n150# 0.16fF
+C53 a_n417_n150# a_n509_n150# 0.43fF
+C54 a_n465_n247# a_159_n150# 0.08fF
+C55 a_447_n150# VSUBS 0.03fF
+C56 a_351_n150# VSUBS 0.03fF
+C57 a_255_n150# VSUBS 0.03fF
+C58 a_159_n150# VSUBS 0.03fF
+C59 a_63_n150# VSUBS 0.03fF
+C60 a_n33_n150# VSUBS 0.03fF
+C61 a_n129_n150# VSUBS 0.03fF
+C62 a_n225_n150# VSUBS 0.03fF
+C63 a_n321_n150# VSUBS 0.03fF
+C64 a_n417_n150# VSUBS 0.03fF
+C65 a_n509_n150# VSUBS 0.03fF
+C66 a_n465_n247# VSUBS 1.07fF
+C67 w_n647_n369# VSUBS 4.87fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n33_n99# a_n73_n11# 0.02fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 w_n216_n334# a_20_n114# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in out 0.11fF
+C1 in vdd 0.01fF
+C2 out vbulkp 0.08fF
+C3 vdd vbulkp 0.04fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 vdd vbulkn 0.06fF
+C7 in vbulkn 0.54fF
+C8 out vbulkn 0.60fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch vctrl in vbp cap_vco_0/t D0 out vss vdd inverter_csvco_0/vss
++ inverter_csvco_0/vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 cap_vco_0/t out 0.70fF
+C1 in inverter_csvco_0/vdd 0.01fF
+C2 cap_vco_0/t vdd 0.04fF
+C3 in out 0.06fF
+C4 inverter_csvco_0/vss D0 0.02fF
+C5 vbp inverter_csvco_0/vdd 0.75fF
+C6 out inverter_csvco_0/vdd 0.02fF
+C7 in inverter_csvco_0/vss 0.01fF
+C8 vdd inverter_csvco_0/vdd 1.89fF
+C9 vctrl inverter_csvco_0/vss 0.87fF
+C10 vdd vbp 1.21fF
+C11 out inverter_csvco_0/vss 0.03fF
+C12 out D0 0.09fF
+C13 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C14 inverter_csvco_0/vdd vss 0.26fF
+C15 in vss 0.69fF
+C16 out vss 0.93fF
+C17 cap_vco_0/t vss 7.22fF
+C18 D0 vss -0.67fF
+C19 vbp vss 0.13fF
+C20 vdd vss 9.58fF
+C21 inverter_csvco_0/vss vss 1.79fF
+C22 vctrl vss 3.06fF
+.ends
+
+.subckt ring_osc vctrl vss vdd csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss
++ csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/cap_vco_0/t D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp csvco_branch_0/cap_vco_0/t D0 csvco_branch_1/in
++ vss vdd csvco_branch_0/inverter_csvco_0/vss csvco_branch_0/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp csvco_branch_2/cap_vco_0/t
++ D0 out_vco vss vdd csvco_branch_2/inverter_csvco_0/vss csvco_branch_2/inverter_csvco_0/vdd
++ csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp csvco_branch_1/cap_vco_0/t
++ D0 csvco_branch_2/in vss vdd csvco_branch_1/inverter_csvco_0/vss csvco_branch_1/inverter_csvco_0/vdd
++ csvco_branch
+C0 vdd csvco_branch_2/vbp 1.49fF
+C1 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C2 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C3 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C4 out_vco csvco_branch_2/in 0.58fF
+C5 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C6 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C7 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C8 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C9 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
+C10 out_vco csvco_branch_1/in 0.76fF
+C11 csvco_branch_2/inverter_csvco_0/vss D0 0.68fF
+C12 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C13 csvco_branch_2/vbp vctrl 0.06fF
+C14 vctrl D0 4.41fF
+C15 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C16 csvco_branch_2/in vss 1.60fF
+C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
+C18 csvco_branch_1/inverter_csvco_0/vss vss 0.72fF
+C19 csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C20 out_vco vss 0.67fF
+C21 csvco_branch_2/cap_vco_0/t vss 7.10fF
+C22 csvco_branch_2/inverter_csvco_0/vss vss 0.62fF
+C23 csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C24 csvco_branch_1/in vss 1.58fF
+C25 csvco_branch_0/cap_vco_0/t vss 7.10fF
+C26 D0 vss -1.55fF
+C27 vdd vss 31.40fF
+C28 csvco_branch_0/inverter_csvco_0/vss vss 0.66fF
+C29 vctrl vss 11.02fF
+C30 csvco_branch_2/vbp vss 0.77fF
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
+Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+C0 out_div o1 0.11fF
+C1 vdd o1 0.09fF
+C2 out_div out_pad 0.15fF
+C3 out_pad vdd 0.10fF
+C4 out_div vdd 0.17fF
+C5 in_vco vss 0.83fF
+C6 out_div vss 3.00fF
+C7 out_pad vss 0.70fF
+C8 vdd vss 14.54fF
+C9 o1 vss 2.72fF
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
++ a_158_392#
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+C0 VPWR B 0.09fF
+C1 a_194_125# X 0.29fF
+C2 X VPWR 0.07fF
+C3 a_194_125# a_355_368# 0.51fF
+C4 A a_355_368# 0.02fF
+C5 a_194_125# a_158_392# 0.06fF
+C6 VPWR a_355_368# 0.37fF
+C7 X B 0.13fF
+C8 B a_355_368# 0.08fF
+C9 a_194_125# VGND 0.25fF
+C10 A VGND 0.31fF
+C11 VPWR VGND 0.01fF
+C12 X a_355_368# 0.17fF
+C13 B VGND 0.10fF
+C14 A a_194_125# 0.18fF
+C15 a_194_125# VPWR 0.33fF
+C16 A VPWR 0.15fF
+C17 VPB VPWR 0.06fF
+C18 X VGND 0.28fF
+C19 a_194_125# B 0.57fF
+C20 A B 0.28fF
+C21 VGND VNB 0.78fF
+C22 X VNB 0.21fF
+C23 VPWR VNB 0.78fF
+C24 B VNB 0.56fF
+C25 A VNB 0.70fF
+C26 VPB VNB 0.77fF
+C27 a_355_368# VNB 0.08fF
+C28 a_194_125# VNB 0.40fF
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X a_143_136# a_56_136#
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+C0 VPWR B 0.02fF
+C1 A VGND 0.21fF
+C2 a_56_136# B 0.30fF
+C3 X B 0.02fF
+C4 VPB VPWR 0.04fF
+C5 VGND a_56_136# 0.06fF
+C6 VGND X 0.15fF
+C7 A VPWR 0.07fF
+C8 A a_56_136# 0.17fF
+C9 VGND B 0.03fF
+C10 VPWR a_56_136# 0.57fF
+C11 VPWR X 0.20fF
+C12 A B 0.08fF
+C13 a_56_136# X 0.26fF
+C14 VGND VNB 0.50fF
+C15 X VNB 0.23fF
+C16 VPWR VNB 0.50fF
+C17 B VNB 0.24fF
+C18 A VNB 0.36fF
+C19 VPB VNB 0.48fF
+C20 a_56_136# VNB 0.38fF
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X a_152_368# a_63_368#
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+C0 VPWR B 0.01fF
+C1 a_63_368# VPWR 0.29fF
+C2 VPB VPWR 0.04fF
+C3 X VPWR 0.18fF
+C4 A B 0.10fF
+C5 VGND B 0.11fF
+C6 a_63_368# a_152_368# 0.03fF
+C7 a_63_368# A 0.28fF
+C8 a_63_368# VGND 0.27fF
+C9 X A 0.02fF
+C10 X VGND 0.16fF
+C11 a_63_368# B 0.14fF
+C12 A VPWR 0.05fF
+C13 a_63_368# X 0.33fF
+C14 VGND VNB 0.53fF
+C15 X VNB 0.24fF
+C16 A VNB 0.21fF
+C17 B VNB 0.31fF
+C18 VPWR VNB 0.46fF
+C19 VPB VNB 0.48fF
+C20 a_63_368# VNB 0.37fF
+.ends
+
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
++ nCLK DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/latch_diff_1/nD
++ DFlipFlop_2/latch_diff_0/nD DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q0
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q CLK vdd Q1 DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ nQ0 DFlipFlop_1/latch_diff_1/nD vss CLK_5 DFlipFlop_3/latch_diff_0/nD nQ2 DFlipFlop_0/latch_diff_0/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D
++ Q1_shift DFlipFlop_0/latch_diff_0/nD DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_3/latch_diff_1/D DFlipFlop_1/latch_diff_0/nD
++ sky130_fd_sc_hs__and2_1_1/a_143_136# sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in sky130_fd_sc_hs__and2_1_0/a_143_136#
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ nQ2 DFlipFlop_0/Q DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/latch_diff_0/D
++ DFlipFlop_0/latch_diff_1/nD vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ nQ0 Q0 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/latch_diff_0/D
++ DFlipFlop_1/latch_diff_1/nD vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_2/nQ Q1 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/latch_diff_0/D
++ DFlipFlop_2/latch_diff_1/nD vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_3/nQ Q1_shift Q1 DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/latch_diff_0/D
++ DFlipFlop_3/latch_diff_1/nD vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
++ sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
++ sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
++ sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
+C0 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C1 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
+C2 Q1 DFlipFlop_3/latch_diff_0/nD 0.08fF
+C3 nQ2 Q0 0.23fF
+C4 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C5 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C6 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C7 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
+C8 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C9 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C10 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C11 DFlipFlop_2/D Q0 0.25fF
+C12 DFlipFlop_0/D Q1 0.13fF
+C13 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C14 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C15 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C16 nCLK DFlipFlop_3/latch_diff_0/nD 0.08fF
+C17 Q1 nQ0 0.06fF
+C18 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C19 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C20 CLK nQ2 0.17fF
+C21 DFlipFlop_3/nQ CLK 0.01fF
+C22 Q1 vdd 9.49fF
+C23 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
+C24 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C25 Q1 DFlipFlop_1/D 0.03fF
+C26 CLK DFlipFlop_2/D 0.14fF
+C27 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
+C28 CLK_5 vdd 0.15fF
+C29 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C30 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C31 CLK Q0 0.08fF
+C32 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
+C33 nCLK nQ0 0.09fF
+C34 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
+C35 nCLK vdd 0.34fF
+C36 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C37 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
+C38 vdd Q1_shift 0.10fF
+C39 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C40 sky130_fd_sc_hs__or2_1_0/a_63_368# vdd 0.02fF
+C41 nCLK DFlipFlop_1/D 0.14fF
+C42 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
+C43 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C44 Q1 DFlipFlop_2/nQ 0.31fF
+C45 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C46 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C47 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C48 nQ2 nQ0 0.03fF
+C49 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C50 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C51 nQ2 vdd 0.04fF
+C52 DFlipFlop_3/nQ vdd 0.02fF
+C53 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C54 DFlipFlop_0/D Q0 0.39fF
+C55 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C56 DFlipFlop_2/D vdd 0.07fF
+C57 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C58 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
+C59 nCLK DFlipFlop_2/nQ 0.09fF
+C60 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C61 Q0 nQ0 0.33fF
+C62 Q0 vdd 5.33fF
+C63 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C64 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C65 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C66 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C67 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
+C68 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C69 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
+C70 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
+C71 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C72 DFlipFlop_1/D Q0 0.07fF
+C73 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C74 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
+C75 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C76 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
+C77 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C78 Q1 DFlipFlop_0/Q 0.13fF
+C79 CLK nQ0 0.19fF
+C80 CLK vdd 0.41fF
+C81 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C82 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C83 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C84 CLK DFlipFlop_1/D 0.21fF
+C85 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C86 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
+C87 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C88 nCLK Q1 -0.01fF
+C89 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C90 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
+C91 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C92 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C93 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C94 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
+C95 Q1 Q1_shift 0.36fF
+C96 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
+C97 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C98 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C99 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C100 nCLK DFlipFlop_0/Q 0.11fF
+C101 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C102 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C103 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
+C104 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
+C105 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C106 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C107 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C108 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C109 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C110 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C111 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C112 DFlipFlop_0/D vdd 0.19fF
+C113 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C114 Q1 nQ2 0.07fF
+C115 CLK DFlipFlop_2/nQ 0.13fF
+C116 DFlipFlop_3/nQ Q1 0.10fF
+C117 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C118 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
+C119 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C120 nQ2 DFlipFlop_0/Q 0.09fF
+C121 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
+C122 vdd nQ0 0.11fF
+C123 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
+C124 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C125 Q1 DFlipFlop_2/D 0.10fF
+C126 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C127 DFlipFlop_1/D nQ0 0.12fF
+C128 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C129 Q1 Q0 9.65fF
+C130 DFlipFlop_1/D vdd 0.25fF
+C131 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C132 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C133 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
+C134 Q1 DFlipFlop_1/latch_diff_1/D -0.10fF
+C135 nCLK nQ2 0.10fF
+C136 DFlipFlop_3/nQ nCLK 0.02fF
+C137 Q0 DFlipFlop_0/Q 0.21fF
+C138 DFlipFlop_3/nQ Q1_shift 0.04fF
+C139 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
+C140 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C141 nCLK DFlipFlop_2/D 0.41fF
+C142 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C143 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C144 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C145 CLK Q1 -0.10fF
+C146 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C147 nCLK Q0 0.20fF
+C148 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
+C149 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
+C150 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C151 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
+C152 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C153 DFlipFlop_2/nQ vdd 0.02fF
+C154 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C155 CLK DFlipFlop_0/Q 0.08fF
+C156 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C157 CLK_5 vss -0.18fF
+C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
+C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
+C160 sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.38fF
+C161 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.64fF
+C162 Q1_shift vss -0.29fF
+C163 DFlipFlop_3/nQ vss 0.52fF
+C164 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C166 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C171 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C172 Q1 vss 8.55fF
+C173 DFlipFlop_2/nQ vss 0.50fF
+C174 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C176 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C179 DFlipFlop_2/D vss 5.34fF
+C180 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C182 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C183 Q0 vss 0.53fF
+C184 nQ0 vss 3.42fF
+C185 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C187 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C190 DFlipFlop_1/D vss 3.72fF
+C191 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C193 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
+C194 nCLK vss 0.96fF
+C195 DFlipFlop_0/Q vss -0.94fF
+C196 nQ2 vss 2.05fF
+C197 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C198 CLK vss 0.20fF
+C199 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C200 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C203 DFlipFlop_0/D vss 4.04fF
+C204 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C206 vdd vss 146.76fF
+C207 sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C208 sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.42fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n225_n125# a_63_n125# 0.08fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_n317_n125# a_63_n125# 0.06fF
+C3 a_159_n125# a_63_n125# 0.36fF
+C4 a_n33_n125# a_n129_n125# 0.36fF
+C5 a_33_n151# a_n63_n151# 0.02fF
+C6 a_225_n151# a_129_n151# 0.02fF
+C7 a_159_n125# a_255_n125# 0.36fF
+C8 a_255_n125# a_63_n125# 0.13fF
+C9 a_n129_n125# a_n225_n125# 0.36fF
+C10 a_n129_n125# a_n317_n125# 0.13fF
+C11 a_159_n125# a_n129_n125# 0.08fF
+C12 a_n129_n125# a_63_n125# 0.13fF
+C13 a_255_n125# a_n129_n125# 0.06fF
+C14 a_33_n151# a_129_n151# 0.02fF
+C15 a_n33_n125# a_n225_n125# 0.13fF
+C16 a_n33_n125# a_n317_n125# 0.08fF
+C17 a_159_n125# a_n33_n125# 0.13fF
+C18 a_n159_n151# a_n63_n151# 0.02fF
+C19 a_n33_n125# a_63_n125# 0.36fF
+C20 a_n225_n125# a_n317_n125# 0.36fF
+C21 a_159_n125# a_n225_n125# 0.06fF
+C22 a_255_n125# a_n33_n125# 0.08fF
+C23 a_255_n125# w_n455_n335# 0.14fF
+C24 a_159_n125# w_n455_n335# 0.08fF
+C25 a_63_n125# w_n455_n335# 0.07fF
+C26 a_n33_n125# w_n455_n335# 0.08fF
+C27 a_n129_n125# w_n455_n335# 0.07fF
+C28 a_n225_n125# w_n455_n335# 0.08fF
+C29 a_n317_n125# w_n455_n335# 0.14fF
+C30 a_225_n151# w_n455_n335# 0.05fF
+C31 a_129_n151# w_n455_n335# 0.05fF
+C32 a_33_n151# w_n455_n335# 0.05fF
+C33 a_n63_n151# w_n455_n335# 0.05fF
+C34 a_n159_n151# w_n455_n335# 0.05fF
+C35 a_n255_n151# w_n455_n335# 0.05fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_255_n125# a_63_n125# 0.13fF
+C1 a_n225_n125# a_63_n125# 0.08fF
+C2 a_n63_n154# a_n159_n154# 0.02fF
+C3 a_159_n125# a_n129_n125# 0.08fF
+C4 a_n33_n125# a_255_n125# 0.08fF
+C5 a_n63_n154# a_33_n154# 0.02fF
+C6 a_n317_n125# a_n225_n125# 0.36fF
+C7 a_n33_n125# a_n225_n125# 0.13fF
+C8 a_n317_n125# a_63_n125# 0.06fF
+C9 a_n33_n125# a_63_n125# 0.36fF
+C10 a_255_n125# w_n455_n344# 0.11fF
+C11 a_225_n154# a_129_n154# 0.02fF
+C12 a_n225_n125# w_n455_n344# 0.06fF
+C13 a_n33_n125# a_n317_n125# 0.08fF
+C14 w_n455_n344# a_63_n125# 0.04fF
+C15 a_255_n125# a_n129_n125# 0.06fF
+C16 a_n225_n125# a_n129_n125# 0.36fF
+C17 a_n317_n125# w_n455_n344# 0.11fF
+C18 a_n129_n125# a_63_n125# 0.13fF
+C19 a_n33_n125# w_n455_n344# 0.05fF
+C20 a_255_n125# a_159_n125# 0.36fF
+C21 a_n317_n125# a_n129_n125# 0.13fF
+C22 a_n225_n125# a_159_n125# 0.06fF
+C23 a_n33_n125# a_n129_n125# 0.36fF
+C24 a_159_n125# a_63_n125# 0.36fF
+C25 w_n455_n344# a_n129_n125# 0.04fF
+C26 a_n33_n125# a_159_n125# 0.13fF
+C27 a_n255_n154# a_n159_n154# 0.02fF
+C28 a_129_n154# a_33_n154# 0.02fF
+C29 a_159_n125# w_n455_n344# 0.06fF
+C30 a_255_n125# VSUBS 0.03fF
+C31 a_159_n125# VSUBS 0.03fF
+C32 a_63_n125# VSUBS 0.03fF
+C33 a_n33_n125# VSUBS 0.03fF
+C34 a_n129_n125# VSUBS 0.03fF
+C35 a_n225_n125# VSUBS 0.03fF
+C36 a_n317_n125# VSUBS 0.03fF
+C37 a_225_n154# VSUBS 0.05fF
+C38 a_129_n154# VSUBS 0.05fF
+C39 a_33_n154# VSUBS 0.05fF
+C40 a_n63_n154# VSUBS 0.05fF
+C41 a_n159_n154# VSUBS 0.05fF
+C42 a_n255_n154# VSUBS 0.05fF
+C43 w_n455_n344# VSUBS 2.96fF
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+C0 out vdd 0.29fF
+C1 out in 0.85fF
+C2 vdd in 0.04fF
+C3 vdd vss 5.90fF
+C4 out vss 1.30fF
+C5 in vss 1.82fF
+.ends
+
+.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
++ QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.42fF
+C1 nDown vdd 0.80fF
+C2 nUp Up 0.20fF
+C3 inverter_cp_x1_0/out vdd 0.25fF
+C4 nDown inverter_cp_x1_0/out 0.11fF
+C5 QA vdd 0.02fF
+C6 Down vdd 0.09fF
+C7 nUp vdd 0.14fF
+C8 nDown Down 0.23fF
+C9 inverter_cp_x1_2/in Up 0.12fF
+C10 vdd Up 0.60fF
+C11 QB vdd 0.02fF
+C12 Down inverter_cp_x1_0/out 0.12fF
+C13 inverter_cp_x1_2/in vss 2.01fF
+C14 QA vss 1.09fF
+C15 inverter_cp_x1_0/out vss 2.00fF
+C16 QB vss 1.09fF
+C17 vdd vss 28.96fF
+C18 nUp vss 1.32fF
+C19 Up vss 2.53fF
+C20 Down vss 1.26fF
+C21 nDown vss 2.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS a_n129_n90# w_n359_n309# a_n63_n116#
++ a_n159_n207# a_63_n90# a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_159_n90# a_n221_n90# 0.04fF
+C1 a_n33_n90# a_n129_n90# 0.26fF
+C2 a_n63_n116# a_n159_n207# 0.12fF
+C3 a_63_n90# a_n129_n90# 0.09fF
+C4 a_n33_n90# a_63_n90# 0.26fF
+C5 a_n129_n90# w_n359_n309# 0.06fF
+C6 a_n33_n90# w_n359_n309# 0.05fF
+C7 a_63_n90# w_n359_n309# 0.06fF
+C8 a_n129_n90# a_n221_n90# 0.26fF
+C9 a_159_n90# a_n129_n90# 0.06fF
+C10 a_n33_n90# a_n221_n90# 0.09fF
+C11 a_n33_n90# a_159_n90# 0.09fF
+C12 a_63_n90# a_n221_n90# 0.06fF
+C13 a_63_n90# a_159_n90# 0.26fF
+C14 w_n359_n309# a_n221_n90# 0.09fF
+C15 a_159_n90# w_n359_n309# 0.09fF
+C16 a_159_n90# VSUBS 0.03fF
+C17 a_63_n90# VSUBS 0.03fF
+C18 a_n33_n90# VSUBS 0.03fF
+C19 a_n129_n90# VSUBS 0.03fF
+C20 a_n221_n90# VSUBS 0.03fF
+C21 a_n159_n207# VSUBS 0.30fF
+C22 a_n63_n116# VSUBS 0.37fF
+C23 w_n359_n309# VSUBS 2.23fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_63_n45# a_n125_n45# 0.05fF
+C2 a_n125_n45# a_n33_n45# 0.13fF
+C3 a_n129_71# a_33_n71# 0.04fF
+C4 a_63_n45# w_n263_n255# 0.04fF
+C5 a_n33_n45# w_n263_n255# 0.04fF
+C6 a_n125_n45# w_n263_n255# 0.04fF
+C7 a_33_n71# w_n263_n255# 0.11fF
+C8 a_n129_71# w_n263_n255# 0.14fF
+.ends
+
+.subckt nor_pfd vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+C0 vdd A 0.09fF
+C1 B A 0.24fF
+C2 out A 0.06fF
+C3 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
+C5 vdd out 0.11fF
+C6 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C7 out B 0.40fF
+C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C9 out vss 0.45fF
+C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C11 A vss 0.83fF
+C12 B vss 1.09fF
+C13 vdd vss 3.79fF
+.ends
+
+.subckt dff_pfd vss vdd nor_pfd_2/A Q CLK nor_pfd_3/A nor_pfd_2/B Reset
+Xnor_pfd_0 vdd nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/A nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss CLK Q nor_pfd
+Xnor_pfd_1 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# Q nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_3/A nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
++ vss nor_pfd_3/A Reset nor_pfd
+C0 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C1 vdd Q 0.08fF
+C2 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C3 CLK Q 0.04fF
+C4 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C5 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C6 vdd nor_pfd_2/B 0.02fF
+C7 Reset Q 0.14fF
+C8 nor_pfd_2/B Q 2.22fF
+C9 vdd nor_pfd_2/A -0.01fF
+C10 Reset nor_pfd_2/B 0.43fF
+C11 nor_pfd_2/A Q 1.38fF
+C12 vdd nor_pfd_3/A 0.09fF
+C13 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C14 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C15 nor_pfd_3/A Q 0.98fF
+C16 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
+C17 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C18 Reset nor_pfd_3/A 0.12fF
+C19 nor_pfd_2/B nor_pfd_3/A 0.58fF
+C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C21 nor_pfd_2/B vss 1.42fF
+C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 Q vss 2.77fF
+C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 nor_pfd_3/A vss 3.16fF
+C31 vdd vss 16.42fF
+C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C34 CLK vss 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71# a_n129_n45# a_63_n45#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n129_n45# a_159_n45# 0.03fF
+C1 a_n33_n45# a_63_n45# 0.13fF
+C2 a_n129_n45# a_n33_n45# 0.13fF
+C3 a_n221_n45# a_63_n45# 0.03fF
+C4 a_n129_n45# a_n221_n45# 0.13fF
+C5 a_n33_n45# a_159_n45# 0.05fF
+C6 a_n221_n45# a_159_n45# 0.02fF
+C7 a_n129_n45# a_63_n45# 0.05fF
+C8 a_n33_n45# a_n221_n45# 0.05fF
+C9 a_n63_n71# a_n159_n173# 0.10fF
+C10 a_159_n45# a_63_n45# 0.13fF
+C11 a_159_n45# w_n359_n255# 0.04fF
+C12 a_63_n45# w_n359_n255# 0.05fF
+C13 a_n33_n45# w_n359_n255# 0.05fF
+C14 a_n129_n45# w_n359_n255# 0.05fF
+C15 a_n221_n45# w_n359_n255# 0.08fF
+C16 a_n159_n173# w_n359_n255# 0.31fF
+C17 a_n63_n71# w_n359_n255# 0.31fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n125_n90# a_n33_n90# 0.26fF
+C1 a_63_n90# a_n33_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
+C4 a_63_n90# VSUBS 0.03fF
+C5 a_n33_n90# VSUBS 0.03fF
+C6 a_n125_n90# VSUBS 0.03fF
+C7 a_33_n187# VSUBS 0.12fF
+C8 a_n99_n187# VSUBS 0.12fF
+C9 w_n263_n309# VSUBS 1.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+C0 a_n73_n45# a_15_n45# 0.16fF
+C1 a_15_n45# w_n211_n255# 0.08fF
+C2 a_n73_n45# w_n211_n255# 0.06fF
+C3 a_n33_67# w_n211_n255# 0.10fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+C0 a_n73_n90# w_n211_n309# 0.04fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_15_n90# a_n73_n90# 0.31fF
+C3 a_15_n90# VSUBS 0.03fF
+C4 a_n73_n90# VSUBS 0.03fF
+C5 a_n51_n187# VSUBS 0.12fF
+C6 w_n211_n309# VSUBS 1.24fF
+.ends
+
+.subckt and_pfd a_656_410# out vss vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45#
++ sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+C0 a_656_410# A 0.04fF
+C1 a_656_410# out 0.20fF
+C2 a_656_410# vdd 0.20fF
+C3 A B 0.33fF
+C4 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
+C6 A vdd 0.05fF
+C7 out vdd 0.10fF
+C8 a_656_410# B 0.30fF
+C9 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
+C10 vdd vss 4.85fF
+C11 out vss 0.47fF
+C12 a_656_410# vss 1.00fF
+C13 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.13fF
+C14 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.10fF
+C15 A vss 0.85fF
+C16 B vss 0.95fF
+.ends
+
+.subckt PFD vss vdd Reset Down Up A B
+Xdff_pfd_0 vss vdd dff_pfd_0/nor_pfd_2/A Up A dff_pfd_0/nor_pfd_3/A dff_pfd_0/nor_pfd_2/B
++ Reset dff_pfd
+Xdff_pfd_1 vss vdd dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
++ Reset dff_pfd
+Xand_pfd_0 and_pfd_0/a_656_410# Reset vss vdd Up Down and_pfd
+C0 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C1 vdd Up 1.62fF
+C2 Down Up 0.06fF
+C3 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C4 vdd Down 0.08fF
+C5 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C6 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C7 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C8 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C9 vdd Reset 0.02fF
+C10 and_pfd_0/a_656_410# vss 0.99fF
+C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
+C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
+C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C20 Down vss 3.74fF
+C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C23 vdd vss 44.73fF
+C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 B vss 1.07fF
+C27 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C29 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 Reset vss 3.85fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C33 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C34 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C35 Up vss 3.18fF
+C36 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C37 dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C40 A vss 1.07fF
+.ends
+
+.subckt top_pll_v1_pex_c iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
++ pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
++ out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
++ n_out_div_2 div_5_nQ2 out_div_2
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 nswitch pswitch vdd nUp vss Down biasp charge_pump_0/w_2544_775# vco_vctrl
++ iref_cp nDown Up vss charge_pump
+Xdiv_by_2_0 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vdd out_by_2
++ n_out_by_2 out_buffer_div_2 out_div_2 vss n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ out_to_div div_by_2
+Xring_osc_0 vco_vctrl vss vdd ring_osc_0/csvco_branch_2/vbp ring_osc_0/csvco_branch_0/inverter_csvco_0/vss
++ ring_osc_0/csvco_branch_2/inverter_csvco_0/vss ring_osc_0/csvco_branch_2/cap_vco_0/t
++ vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_pad ring_osc_buffer
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
++ n_out_by_2 div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_0/Q
++ out_by_2 vdd div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ vss out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_2/latch_diff_0/D
++ div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
++ div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
++ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5
+Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
++ Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd pfd_reset QB QA in_ref out_div_by_5 PFD
+C0 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C1 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C2 vdd out_div_by_5 0.28fF
+C3 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C4 Down charge_pump_0/w_2544_775# -0.23fF
+C5 vco_vctrl nUp 0.31fF
+C6 Up nUp 2.67fF
+C7 n_out_by_2 div_5_nQ2 0.10fF
+C8 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C9 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C10 iref_cp Down 0.09fF
+C11 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C12 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C13 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C14 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C15 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C16 vdd vco_D0 0.03fF
+C17 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C18 n_out_by_2 div_5_Q1 1.04fF
+C19 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C20 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C21 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C22 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C23 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C24 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C25 n_out_by_2 div_5_nQ0 0.10fF
+C26 nswitch nDown 0.76fF
+C27 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C28 out_to_div out_to_pad 0.11fF
+C29 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C30 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C31 vdd nDown 0.22fF
+C32 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.13fF
+C33 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C34 out_by_2 div_5_nQ2 0.16fF
+C35 vdd vco_vctrl 0.25fF
+C36 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C37 vdd Up 0.30fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C39 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C40 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C41 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C42 n_out_by_2 div_5_Q0 -0.11fF
+C43 n_out_by_2 vdd 1.03fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C45 vdd iref_cp 0.15fF
+C46 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C47 QA vdd -0.04fF
+C48 out_by_2 div_5_Q1 0.42fF
+C49 biasp nDown 0.26fF
+C50 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C51 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C52 pswitch nDown 0.53fF
+C53 out_by_2 div_5_nQ0 0.32fF
+C54 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C55 nswitch Down 0.54fF
+C56 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C58 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C59 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C60 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C61 biasp Up 0.26fF
+C62 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C63 pswitch vco_vctrl 0.59fF
+C64 vdd nUp 0.05fF
+C65 pswitch Up 2.04fF
+C66 charge_pump_0/w_2544_775# nDown 0.05fF
+C67 div_5_Q1_shift out_div_by_5 0.05fF
+C68 div_5_Q1 out_div_by_5 0.01fF
+C69 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C70 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C71 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C72 out_by_2 div_5_Q0 0.09fF
+C73 out_by_2 vdd 0.97fF
+C74 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.47fF
+C75 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C76 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C77 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C78 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C79 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C80 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C81 biasp Down 1.79fF
+C82 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C83 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C84 biasp nUp -0.17fF
+C85 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C86 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C87 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C88 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C89 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C90 Down nDown 2.55fF
+C91 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C92 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C93 pswitch nUp 0.85fF
+C94 nDown nUp -0.09fF
+C95 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C96 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C97 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C98 vdd out_to_div 0.21fF
+C99 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
+C100 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
+C101 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
+C102 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C103 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
+C104 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C105 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C106 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C107 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C108 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C109 QB vss 3.46fF
+C110 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C111 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
+C112 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C113 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 out_div_by_5 vss 0.83fF
+C115 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
+C117 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C118 pfd_reset vss 1.87fF
+C119 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C121 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C122 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C123 QA vss 4.02fF
+C124 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C125 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
+C126 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C127 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C128 in_ref vss 0.72fF
+C129 pfd_cp_interface_0/inverter_cp_x1_2/in vss 1.85fF
+C130 pfd_cp_interface_0/inverter_cp_x1_0/out vss 1.87fF
+C131 nUp vss 5.71fF
+C132 Up vss 5.31fF
+C133 Down vss 1.44fF
+C134 nDown vss 2.10fF
+C135 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.37fF
+C136 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.38fF
+C137 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vss 0.41fF
+C138 div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.57fF
+C139 div_5_Q1_shift vss -1.23fF
+C140 div_by_5_0/DFlipFlop_3/nQ vss 0.48fF
+C141 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C142 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
+C143 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
+C144 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C145 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C146 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C147 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C148 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C149 div_5_Q1 vss 4.34fF
+C150 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C151 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C152 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C153 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C154 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C155 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C156 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C157 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C158 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C159 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C160 div_5_Q0 vss 0.55fF
+C161 div_5_nQ0 vss 1.22fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C164 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C169 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C170 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C171 n_out_by_2 vss 3.25fF
+C172 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
+C173 div_5_nQ2 vss 1.49fF
+C174 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C175 out_by_2 vss 1.54fF
+C176 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C177 div_by_5_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C178 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C179 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C180 div_by_5_0/DFlipFlop_0/D vss 3.96fF
+C181 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C182 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C183 vdd vss 371.65fF
+C184 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
+C185 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
+C186 out_to_div vss 4.82fF
+C187 out_to_pad vss 0.33fF
+C188 out_first_buffer vss 1.45fF
+C189 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
+C190 ring_osc_0/csvco_branch_2/in vss 1.59fF
+C191 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
+C192 ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vss 0.52fF
+C193 ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vss 0.16fF
+C194 vco_out vss 1.61fF
+C195 ring_osc_0/csvco_branch_2/cap_vco_0/t vss 7.09fF
+C196 ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vss 0.50fF
+C197 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vss 0.16fF
+C198 ring_osc_0/csvco_branch_1/in vss 1.58fF
+C199 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
+C200 vco_D0 vss -4.73fF
+C201 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
+C202 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
+C203 n_out_buffer_div_2 vss 2.30fF
+C204 out_buffer_div_2 vss 2.30fF
+C205 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C206 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C207 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C208 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C209 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
+C210 out_div_2 vss -0.79fF
+C211 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C212 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C213 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C214 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C215 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 n_out_div_2 vss 2.63fF
+C217 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C218 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+C219 nswitch vss 4.61fF
+C220 biasp vss 4.91fF
+C221 iref_cp vss 7.56fF
+C222 vco_vctrl vss -128.69fF
+C223 pswitch vss 3.57fF
+C224 lf_vc vss -1365.13fF
+C225 loop_filter_0/m1_166_166# vss 3.82fF
+.ends
+

diff --git a/xschem/simulations/top_pll_v1_pex_no_integration.spice b/xschem/simulations/top_pll_v1_pex_no_integration.spice
new file mode 100644
index 0000000..a4efab9
--- /dev/null
+++ b/xschem/simulations/top_pll_v1_pex_no_integration.spice

@@ -0,0 +1,50 @@
+**.subckt top_pll_v1_pex_no_integration vdd vss in_ref pfd_QA pfd_QB Up nUp Down nDown pfd_reset
+*+ cp_nswitch cp_pswitch cp_biasp iref_cp lf_vc vco_D0 vco_vctrl vco_out out_first_buffer out_to_pad out_to_div
+*+ out_by_2 n_out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2 div_5_Q1 div_5_Q1_shift
+*+ div_5_nQ0 div_5_Q0 div_5_nQ2 out_div_by_5
+*.iopin vdd
+*.iopin vss
+*.ipin in_ref
+*.iopin pfd_QA
+*.iopin pfd_QB
+*.iopin Up
+*.iopin nUp
+*.iopin Down
+*.iopin nDown
+*.iopin pfd_reset
+*.iopin cp_nswitch
+*.iopin cp_pswitch
+*.iopin cp_biasp
+*.ipin iref_cp
+*.iopin lf_vc
+*.iopin vco_D0
+*.iopin vco_vctrl
+*.iopin vco_out
+*.iopin out_first_buffer
+*.opin out_to_pad
+*.iopin out_to_div
+*.iopin out_by_2
+*.iopin n_out_by_2
+*.iopin out_div_2
+*.iopin n_out_div_2
+*.iopin out_buffer_div_2
+*.iopin n_out_buffer_div_2
+*.iopin div_5_Q1
+*.iopin div_5_Q1_shift
+*.iopin div_5_nQ0
+*.iopin div_5_Q0
+*.iopin div_5_nQ2
+*.iopin out_div_by_5
+x1 vss vdd pfd_QA in_ref out_div_by_5 pfd_QB pfd_reset PFD_pex_c
+x2 vdd Up nUp vco_vctrl Down nDown vss iref_cp cp_nswitch cp_pswitch cp_biasp charge_pump_pex_c
+x3 vdd vco_out vco_vctrl vss vco_D0 csvco_pex_c
+x5 vdd out_div_by_5 out_by_2 vss n_out_by_2 div_5_nQ2 div_5_Q1 div_5_nQ0 div_5_Q0 div_5_Q1_shift
++ div_by_5_pex_c
+x6 vss vco_vctrl lf_vc loop_filter_pex_c
+x7 Up vdd pfd_QA nUp Down pfd_QB vss nDown pfd_cp_interface_pex_c
+x8 vdd vco_out out_to_pad out_to_div vss out_first_buffer ring_osc_buffer_pex_c
+x4 n_out_by_2 vss out_to_div vdd out_by_2 out_div_2 n_out_div_2 out_buffer_div_2 n_out_buffer_div_2
++ div_by_2_pex_c
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/simulations/trans_gate.spice b/xschem/simulations/trans_gate.spice
new file mode 100644
index 0000000..33c6be4
--- /dev/null
+++ b/xschem/simulations/trans_gate.spice

@@ -0,0 +1,14 @@
+**.subckt trans_gate vss in out vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out vss in vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 out vdd in vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.25 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=3 m=3 
+**.ends
+** flattened .save nodes
+.end

diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/simulations/user_analog_project_wrapper.spice
similarity index 100%
rename from xschem/user_analog_project_wrapper.spice
rename to xschem/simulations/user_analog_project_wrapper.spice


diff --git a/xschem/simulations/vco.spice b/xschem/simulations/vco.spice
new file mode 100644
index 0000000..3597f3d
--- /dev/null
+++ b/xschem/simulations/vco.spice

@@ -0,0 +1,149 @@
+**.subckt vco vctrl
+*.ipin vctrl
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+C1 out vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+x5 vdd out out4 vss inverter_min_x2
+x4 vdd out4 out3 vss inverter_min_x2
+C2 out_wp vss 10f m=1
+x6 vdd out_wp out4_wp vss inverter_min_x2
+x7 vdd out4_wp out3_wp vss inverter_min_x2
+XM1 net1 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM7 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM8 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 net11 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM3 net12 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM4 net2 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM5 net3 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM6 net4 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM9 net5 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM10 net6 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM11 net7 vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=8 m=8 
+XM12 net8 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM13 net9 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM14 net10 vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+x1 net1 out1 out3 net2 vdd vss inverter_csvco
+x2 net11 out2 out1 net3 vdd vss inverter_csvco
+x3 net12 out3 out2 net4 vdd vss inverter_csvco
+x8 net7 out1_wp out3_wp net8 vdd vss inverter_csvco_pex_c
+x9 net5 out2_wp out1_wp net9 vdd vss inverter_csvco_pex_c
+x10 net6 out3_wp out2_wp net10 vdd vss inverter_csvco_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vctrl = 1.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(out1) = 0.0
+.ic v(out2) = 0.0
+.ic v(out3) = 0.0
+.ic v(out4) = 0.0
+.ic v(out) = 0.0
+.ic v(out1_wp) = 0.0
+.ic v(out2_wp) = 0.0
+.ic v(out3_wp) = 0.0
+.ic v(out4_wp) = 0.0
+.ic v(out_wp) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 50ns
+	meas tran To trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	meas tran To_wp trig v(out_wp) val=0.9 fall=5 targ v(out_wp) val=0.9 fall=15
+	let T = To/10.0
+	let T_wp = To_wp/10.0
+	let f = 1/T
+	let f_wp = 1/T_wp
+	echo .
+	echo --- VCO ----
+	print T f
+	echo --- VCO_wp ----
+	print T_wp f_wp
+	plot v(out) v(out_wp)+2
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2/sch/inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_min_x2/sch/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_csvco/sch/inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sym
+* sch_path: /home/dhernando/sky130-mpw2-fulgor/inverter_csvco/sch/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end

diff --git a/xschem/tb_DFF.sch b/xschem/tb_DFF.sch
new file mode 100644
index 0000000..3a14b17
--- /dev/null
+++ b/xschem/tb_DFF.sch

@@ -0,0 +1,101 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -350 -370 -350 -340 { lab=GND}
+N -200 -370 -200 -340 { lab=vss}
+N 370 -370 370 -340 { lab=vss}
+N -280 -370 -280 -340 { lab=vss}
+N -350 -460 -350 -430 { lab=vss}
+N -200 -460 -200 -430 { lab=B}
+N 370 -460 370 -430 { lab=A}
+N -280 -460 -280 -430 { lab=vdd}
+N -60 -170 -20 -170 { lab=vdd}
+N -50 -140 -20 -140 { lab=A}
+N 30 -80 30 -50 { lab=B}
+N 30 -230 30 -200 { lab=vss}
+N 80 -170 150 -170 { lab=Q}
+N 220 -30 220 0 { lab=vss}
+N 220 -260 220 -230 { lab=vdd}
+N 390 -190 390 -130 { lab=Up}
+N 290 -190 390 -190 { lab=Up}
+N 390 -70 390 -40 { lab=vss}
+C {vsource.sym} -350 -400 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -280 -400 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 370 -400 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {vsource.sym} -200 -400 0 0 {name=Vdiv 
+value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"
+}
+C {gnd.sym} -350 -340 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -350 -460 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -340 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 370 -340 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -200 -340 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -460 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -200 -460 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} 370 -460 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -380 -200 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = 1.8
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/dff_pfd_pex_c.spice
+
+.ic v(net3) = 0.0
+.ic v(net4) = 0.0
+.ic v(Q) = 0.0
+
+* Data to save
+.save all
+
+* Simulation
+.control
+	tran 0.1ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_DFF_nor_tran.raw
+	plot v(A)+2 v(B)+2 v(Q)
+.endc
+
+.end
+"}
+C {lab_pin.sym} -60 -170 0 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -50 -140 2 1 {name=l9 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -50 3 0 {name=l10 sig_type=std_logic lab=B}
+C {lab_pin.sym} 30 -230 1 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 120 -170 0 0 {name=l18 sig_type=std_logic lab=Q}
+C {lab_pin.sym} 220 -260 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 220 0 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {noconn.sym} 290 -70 2 0 {name=l15}
+C {noconn.sym} 290 -110 2 0 {name=l16}
+C {noconn.sym} 290 -150 2 0 {name=l17}
+C {noconn.sym} 150 -90 0 0 {name=l20}
+C {capa.sym} 390 -100 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 390 -40 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 370 -190 0 0 {name=l21 sig_type=std_logic lab=Up}
+C {pfd_cp_interface_pex_c.sym} 220 -130 0 0 {name=x2}
+C {dff_pfd_pex_c.sym} 30 -140 0 0 {name=x1}

diff --git a/xschem/tb_PFD.sch b/xschem/tb_PFD.sch
new file mode 100644
index 0000000..9902432
--- /dev/null
+++ b/xschem/tb_PFD.sch

@@ -0,0 +1,86 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 570 -250 570 -220 { lab=GND}
+N -350 -160 -350 -130 { lab=vss}
+N -350 -360 -350 -330 { lab=vss}
+N 640 -250 640 -220 { lab=vss}
+N 570 -340 570 -310 { lab=vss}
+N -350 -250 -350 -220 { lab=B}
+N -350 -450 -350 -420 { lab=A}
+N 640 -340 640 -310 { lab=vdd}
+N 170 -410 170 -380 { lab=vss}
+N 30 -320 70 -320 { lab=A}
+N 70 -320 80 -320 { lab=A}
+N 30 -240 80 -240 { lab=B}
+N 130 -410 130 -380 { lab=vdd}
+N 220 -320 340 -320 { lab=QA}
+N 220 -240 340 -240 { lab=QB}
+N 410 -180 410 -150 { lab=vss}
+N 410 -410 410 -380 { lab=vdd}
+N 150 -180 150 -140 { lab=Reset}
+C {PFD.sym} 150 -280 0 0 {name=x1}
+C {vsource.sym} 570 -280 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} 640 -280 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -350 -390 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} 570 -220 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} 570 -340 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 -220 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -330 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -130 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 -340 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -350 -250 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} -350 -450 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -320 2 1 {name=l15 sig_type=std_logic lab=A}
+C {lab_pin.sym} 30 -240 2 1 {name=l16 sig_type=std_logic lab=B}
+C {lab_pin.sym} 130 -410 1 0 {name=l17 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 170 -410 1 0 {name=l18 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 750 -330 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 400ns
+	write tb_PFD_tran.raw
+ 	plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+	
+.endc
+
+.end
+"}
+C {vsource.sym} -350 -190 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"}
+C {lab_wire.sym} 290 -320 0 0 {name=l37 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 290 -240 0 0 {name=l38 sig_type=std_logic lab=QB}
+C {lab_pin.sym} 410 -410 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -150 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {noconn.sym} 480 -220 2 0 {name=l9}
+C {noconn.sym} 480 -260 2 0 {name=l10}
+C {noconn.sym} 480 -300 2 0 {name=l12}
+C {noconn.sym} 480 -340 2 0 {name=l13}
+C {pfd_cp_interface_pex_c.sym} 410 -280 0 0 {name=x2}
+C {lab_wire.sym} 150 -170 3 0 {name=l19 sig_type=std_logic lab=Reset}
+C {noconn.sym} 150 -140 3 0 {name=l20}

diff --git a/xschem/tb_PFD_pex.sch b/xschem/tb_PFD_pex.sch
new file mode 100644
index 0000000..31356ab
--- /dev/null
+++ b/xschem/tb_PFD_pex.sch

@@ -0,0 +1,95 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -350 -370 -350 -340 { lab=GND}
+N -350 20 -350 50 { lab=vss}
+N -350 -180 -350 -150 { lab=vss}
+N -280 -370 -280 -340 { lab=vss}
+N -350 -460 -350 -430 { lab=vss}
+N -350 -70 -350 -40 { lab=B}
+N -350 -270 -350 -240 { lab=A}
+N -280 -460 -280 -430 { lab=vdd}
+N 210 -370 210 -340 { lab=vss}
+N 70 -280 110 -280 { lab=A}
+N 110 -280 120 -280 { lab=A}
+N 70 -200 120 -200 { lab=B}
+N 170 -370 170 -340 { lab=vdd}
+N 260 -280 380 -280 { lab=QA}
+N 260 -200 380 -200 { lab=QB}
+N 450 -140 450 -110 { lab=vss}
+N 450 -370 450 -340 { lab=vdd}
+N 190 -140 190 -110 { lab=Reset}
+C {vsource.sym} -350 -400 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -280 -400 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -350 -340 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -350 -460 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -340 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 -150 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -350 50 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 -460 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -350 -70 3 1 {name=l8 sig_type=std_logic lab=B}
+C {lab_pin.sym} -350 -270 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} -170 -450 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 10f
+
+.options TEMP = 100.0
+.option RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+
+* Simulation
+.control
+	tran 0.001ns 400ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_PFD_pex_tran.raw
+ 	plot v(Reset) v(QB)+2 v(QA)+4 v(A)+6 v(B)+6
+.endc
+
+.end
+"}
+C {lab_pin.sym} 70 -280 2 1 {name=l41 sig_type=std_logic lab=A}
+C {lab_pin.sym} 70 -200 2 1 {name=l42 sig_type=std_logic lab=B}
+C {lab_pin.sym} 170 -370 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 210 -370 1 0 {name=l44 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 330 -280 0 0 {name=l63 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 330 -200 0 0 {name=l64 sig_type=std_logic lab=QB}
+C {vsource.sym} -350 -10 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{1.05*Tref/2\} \{1.05*Tref\}) DC \{vin\} AC 0"}
+C {vsource.sym} -350 -210 0 0 {name=Vref1 value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 450 -370 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 450 -110 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {noconn.sym} 520 -180 2 0 {name=l9}
+C {noconn.sym} 520 -220 2 0 {name=l10}
+C {noconn.sym} 520 -260 2 0 {name=l12}
+C {noconn.sym} 520 -300 2 0 {name=l13}
+C {pfd_cp_interface_pex_c.sym} 450 -240 0 0 {name=x2}
+C {PFD_pex_c.sym} 190 -240 0 0 {name=x1}
+C {lab_wire.sym} 190 -130 3 0 {name=l15 sig_type=std_logic lab=Reset}
+C {noconn.sym} 190 -110 3 0 {name=l16}

diff --git a/xschem/tb_charge_pump.sch b/xschem/tb_charge_pump.sch
new file mode 100644
index 0000000..f3f1075
--- /dev/null
+++ b/xschem/tb_charge_pump.sch

@@ -0,0 +1,252 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -640 -210 -610 { lab=GND}
+N 530 -640 530 -610 { lab=vss}
+N 160 -640 160 -610 { lab=vss}
+N -140 -640 -140 -610 { lab=vss}
+N -210 -730 -210 -700 { lab=vss}
+N 530 -730 530 -700 { lab=#net1}
+N 160 -730 160 -700 { lab=#net2}
+N -140 -730 -140 -700 { lab=vdd}
+N 450 -310 540 -310 { lab=nUp}
+N 450 -270 540 -270 { lab=Down}
+N 490 -230 540 -230 { lab=nDown}
+N 490 -350 540 -350 { lab=Up}
+N 640 -420 640 -390 { lab=vdd}
+N 670 -420 670 -390 { lab=vss}
+N 970 -290 970 -220 { lab=vctrl}
+N 880 -290 880 -270 { lab=vctrl}
+N 880 -210 880 -170 { lab=#net3}
+N 880 -110 880 -80 { lab=vss}
+N 970 -160 970 -130 { lab=vss}
+N 880 -290 970 -290 { lab=vctrl}
+N 450 -350 490 -350 { lab=Up}
+N 450 -230 490 -230 { lab=nDown}
+N 580 -430 580 -390 { lab=iref_cp}
+N 270 -330 310 -330 { lab=QA}
+N 270 -250 310 -250 { lab=QB}
+N 380 -420 380 -390 { lab=vdd}
+N 380 -190 380 -160 { lab=vss}
+N 120 -420 120 -390 { lab=vdd}
+N 160 -420 160 -390 { lab=vss}
+N 80 -770 110 -770 { lab=vdd}
+N 210 -770 240 -770 { lab=vss}
+N 160 -890 160 -860 { lab=#net4}
+N 80 -930 110 -930 { lab=vdd}
+N 210 -930 240 -930 { lab=vss}
+N 160 -1060 160 -1020 { lab=QA}
+N 530 -760 530 -730 { lab=#net1}
+N 450 -800 480 -800 { lab=vdd}
+N 580 -800 610 -800 { lab=vss}
+N 530 -920 530 -890 { lab=#net5}
+N 450 -960 480 -960 { lab=vdd}
+N 580 -960 610 -960 { lab=vss}
+N 530 -1090 530 -1050 { lab=QB}
+N 710 -290 750 -290 { lab=cp_out}
+N 750 -290 770 -290 { lab=cp_out}
+N 830 -290 880 -290 { lab=vctrl}
+N 590 -190 590 -140 { lab=nswitch}
+N 620 -190 620 -140 { lab=pswitch}
+N 140 -190 140 -140 { lab=Reset}
+N 650 -190 650 -140 { lab=biasp}
+N -180 -490 -180 -460 { lab=vdd}
+N -200 -100 -200 -70 { lab=vss}
+N -120 -420 -80 -420 { lab=iref_cp}
+N -200 -190 -200 -160 { lab=#net6}
+N -200 -200 -200 -190 { lab=#net6}
+N -160 -200 -160 -170 { lab=vss}
+N -120 -400 -80 -400 { lab=#net7}
+N -120 -380 -80 -380 { lab=#net8}
+N -120 -360 -80 -360 { lab=#net9}
+N -120 -340 -80 -340 { lab=#net10}
+N -120 -320 -80 -320 { lab=#net11}
+N -120 -300 -80 -300 { lab=#net12}
+N -120 -280 -80 -280 { lab=#net13}
+N -120 -260 -80 -260 { lab=#net14}
+N -120 -240 -80 -240 { lab=#net15}
+C {vsource.sym} -210 -670 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -140 -670 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 160 -670 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -210 -610 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -210 -730 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -610 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 160 -610 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 530 -610 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -140 -730 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 530 -1090 3 1 {name=l8 sig_type=std_logic lab=QB}
+C {lab_pin.sym} 160 -1060 3 1 {name=l14 sig_type=std_logic lab=QA}
+C {netlist_not_shown.sym} -30 -720 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param Cn = 0.0001fF
+.param Cp = 0.0001fF
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+*.include ~/caravel_analog_fulgor/xschem/simulations/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(B) = 0.0
+.ic v(vctrl) = 0.0
+
+* Simulation
+.control
+	op
+	echo .
+	echo ---- M1 bias ----
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM1.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M2 bias ----
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM2.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M3 bias ----
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM3.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M4 bias ----
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[id]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vds]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vdsat]
+	print @M.X4.XM4.msky130_fd_pr__pfet_01v8_lvt[vgs]
+	echo ---- M5 bias ----
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[id]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vds]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vdsat]
+	print @M.X4.XM5.msky130_fd_pr__nfet_01v8[vgs]
+	echo ---- M6 bias ----
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[id]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vds]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vdsat]
+	print @M.X4.XM6.msky130_fd_pr__nfet_01v8[vgs]
+	echo ---- M7 bias ----
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[id]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vds]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vdsat]
+	print @M.X4.XM7.msky130_fd_pr__pfet_01v8[vgs]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgs]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgs]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgd]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgd]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgb]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgb]
+	echo --- Cgs ---
+	print @M.X2.XM7.msky130_fd_pr__pfet_01v8[cgg]
+	print @M.X2.XM8.msky130_fd_pr__nfet_01v8[cgg]
+
+	reset
+	
+	
+	tran 0.01ns 400ns
+	write tb_cp_gate_switched_tran.raw
+	plot i(v.x2.vm1) i(v.x2.vm2) 
+	plot v(vctrl) v(nDown)+2 v(Down)+4 v(nUp)+6 v(Up)+8 v(QB)+10 v(QA)+12
+	plot v(pswitch) v(nswitch) xlimit 4ns 44ns
+.endc
+
+.end
+"}
+C {lab_wire.sym} 490 -350 0 0 {name=l20 sig_type=std_logic lab=Up}
+C {lab_wire.sym} 510 -270 0 0 {name=l21 sig_type=std_logic lab=Down}
+C {vsource.sym} 530 -670 0 0 {name=Vdiv value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 640 -420 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -420 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 490 -310 0 0 {name=l29 sig_type=std_logic lab=nUp}
+C {lab_wire.sym} 520 -230 0 0 {name=l30 sig_type=std_logic lab=nDown}
+C {capa.sym} 880 -140 0 0 {name=C1
+m=1
+value=33.5p
+footprint=1206
+device="ceramic capacitor"}
+C {res.sym} 880 -240 0 0 {name=R1
+value=2k
+footprint=1206
+device=resistor
+m=1}
+C {capa.sym} 970 -190 0 0 {name=C2
+m=1
+value=6.7p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 880 -80 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 970 -130 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 960 -290 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {vsource.sym} 800 -290 3 0 {name=vout value=0}
+C {lab_pin.sym} 580 -430 1 0 {name=l25 sig_type=std_logic lab=iref_cp}
+C {PFD.sym} 140 -290 0 0 {name=x1}
+C {lab_pin.sym} 380 -420 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 380 -160 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 120 -420 1 0 {name=l15 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 160 -420 1 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 300 -330 0 0 {name=l31 sig_type=std_logic lab=QA}
+C {lab_wire.sym} 300 -250 0 0 {name=l32 sig_type=std_logic lab=QB}
+C {inverter_cp_x2.sym} 160 -790 3 0 {name=x5}
+C {lab_pin.sym} 80 -770 0 0 {name=l44 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 -770 2 0 {name=l45 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 160 -950 3 0 {name=x6}
+C {lab_pin.sym} 80 -930 0 0 {name=l46 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 -930 2 0 {name=l47 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 530 -820 3 0 {name=x7}
+C {lab_pin.sym} 450 -800 0 0 {name=l48 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -800 2 0 {name=l49 sig_type=std_logic lab=vss}
+C {inverter_cp_x2.sym} 530 -980 3 0 {name=x8}
+C {lab_pin.sym} 450 -960 0 0 {name=l50 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -960 2 0 {name=l51 sig_type=std_logic lab=vss}
+C {pfd_cp_interface_pex_c.sym} 380 -290 0 0 {name=x3}
+C {noconn.sym} 210 -330 2 0 {name=l33}
+C {noconn.sym} 210 -250 2 0 {name=l34}
+C {lab_wire.sym} 760 -290 0 0 {name=l42 sig_type=std_logic lab=cp_out}
+C {noconn.sym} 590 -140 3 0 {name=l38}
+C {noconn.sym} 620 -140 3 0 {name=l39}
+C {lab_wire.sym} 590 -180 3 0 {name=l40 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} 620 -180 3 0 {name=l41 sig_type=std_logic lab=pswitch}
+C {noconn.sym} 70 -250 0 0 {name=l18}
+C {noconn.sym} 70 -330 0 0 {name=l26}
+C {noconn.sym} 140 -140 3 0 {name=l13}
+C {lab_wire.sym} 140 -180 3 0 {name=l16 sig_type=std_logic lab=Reset}
+C {noconn.sym} 650 -140 3 0 {name=l19}
+C {lab_wire.sym} 650 -180 3 0 {name=l23 sig_type=std_logic lab=biasp}
+C {charge_pump_pex_c.sym} 620 -290 0 0 {name=x2}
+C {lab_pin.sym} -180 -490 1 0 {name=l10 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -200 -70 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -80 -420 2 0 {name=l12 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -200 -130 0 0 {name=I0 value=100u}
+C {lab_pin.sym} -160 -170 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {noconn.sym} -80 -400 2 0 {name=l75}
+C {noconn.sym} -80 -380 2 0 {name=l76}
+C {noconn.sym} -80 -360 2 0 {name=l77}
+C {noconn.sym} -80 -340 2 0 {name=l78}
+C {noconn.sym} -80 -320 2 0 {name=l79}
+C {noconn.sym} -80 -300 2 0 {name=l80}
+C {noconn.sym} -80 -280 2 0 {name=l81}
+C {noconn.sym} -80 -260 2 0 {name=l82}
+C {noconn.sym} -80 -240 2 0 {name=l83}
+C {bias_pex_c.sym} -180 -330 0 0 {name=x4}

diff --git a/xschem/tb_csvco.sch b/xschem/tb_csvco.sch
new file mode 100644
index 0000000..9a26ee9
--- /dev/null
+++ b/xschem/tb_csvco.sch

@@ -0,0 +1,182 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo . 
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l11 sig_type=std_logic lab=D0}
+C {csvco.sym} 510 0 0 0 {name=x3}

diff --git a/xschem/tb_csvco_pex_c.sch b/xschem/tb_csvco_pex_c.sch
new file mode 100644
index 0000000..8fadb37
--- /dev/null
+++ b/xschem/tb_csvco_pex_c.sch

@@ -0,0 +1,183 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo . 
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {csvco_pex_c.sym} 510 0 0 0 {name=x3}
+C {lab_pin.sym} 410 40 0 0 {name=l5 sig_type=std_logic lab=D0}

diff --git a/xschem/tb_div_by_2.sch b/xschem/tb_div_by_2.sch
new file mode 100644
index 0000000..2c5d47a
--- /dev/null
+++ b/xschem/tb_div_by_2.sch

@@ -0,0 +1,116 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -230 -230 -230 -200 { lab=vss}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -230 -320 -230 -290 { lab=#net1}
+N -30 -610 -30 -580 { lab=vdd}
+N 450 -320 480 -320 { lab=A}
+N 100 -270 100 -240 { lab=vss}
+N 100 -400 100 -370 { lab=vdd}
+N 620 -340 720 -340 { lab=out}
+N 620 -300 660 -300 { lab=nout}
+N 190 -320 270 -320 { lab=#net2}
+N 310 -270 310 -240 { lab=vss}
+N 310 -400 310 -370 { lab=vdd}
+N -230 -320 60 -320 { lab=#net1}
+N 400 -320 450 -320 { lab=A}
+N 570 -430 570 -400 { lab=vss}
+N 530 -430 530 -400 { lab=vdd}
+N 660 -300 720 -300 { lab=nout}
+N 520 -240 520 -190 { lab=out_div}
+N 540 -240 540 -190 { lab=#net3}
+N 560 -240 560 -190 { lab=#net4}
+N 580 -240 580 -190 { lab=#net5}
+N 720 -300 720 -280 { lab=nout}
+N 800 -340 800 -280 { lab=out}
+N 720 -340 800 -340 { lab=out}
+N 720 -220 720 -190 { lab=vss}
+N 800 -220 800 -190 { lab=vss}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -230 -260 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -230 -200 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 440 -320 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 0.9
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_2_tran.raw
+	plot v(out) v(A) v(nout)+2 v(A)+2
+	plot v(out_div) v(out)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -400 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {div_by_2.sym} 550 -320 0 0 {name=x1}
+C {inverter_min_x2_pex_c.sym} 120 -320 0 0 {name=x2}
+C {inverter_min_x4_pex_c.sym} 330 -320 0 0 {name=x3}
+C {lab_pin.sym} 310 -240 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 310 -400 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -430 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 530 -430 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {noconn.sym} 520 -190 1 1 {name=l20}
+C {noconn.sym} 540 -190 1 1 {name=l21}
+C {noconn.sym} 560 -190 1 1 {name=l22}
+C {noconn.sym} 580 -190 1 1 {name=l23}
+C {lab_pin.sym} 680 -340 3 1 {name=l24 sig_type=std_logic lab=out}
+C {lab_pin.sym} 690 -300 1 1 {name=l25 sig_type=std_logic lab=nout}
+C {lab_pin.sym} 520 -210 2 1 {name=l26 sig_type=std_logic lab=out_div}
+C {capa.sym} 720 -250 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {capa.sym} 800 -250 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 720 -190 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 800 -190 3 0 {name=l8 sig_type=std_logic lab=vss}

diff --git a/xschem/tb_div_by_2_pex_c.sch b/xschem/tb_div_by_2_pex_c.sch
new file mode 100644
index 0000000..975c397
--- /dev/null
+++ b/xschem/tb_div_by_2_pex_c.sch

@@ -0,0 +1,135 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -30 -610 -30 -580 { lab=vdd}
+N 270 -300 300 -300 { lab=A}
+N 390 -410 390 -380 { lab=vss}
+N 350 -410 350 -380 { lab=vdd}
+N 440 -280 480 -280 { lab=nout}
+N 680 -300 730 -300 { lab=#net1}
+N 630 -410 630 -380 { lab=vss}
+N 590 -410 590 -380 { lab=vdd}
+N -440 -210 -440 -180 { lab=vss}
+N -440 -300 -440 -270 { lab=#net2}
+N 240 -300 270 -300 { lab=A}
+N -110 -250 -110 -220 { lab=vss}
+N -110 -380 -110 -350 { lab=vdd}
+N -20 -300 60 -300 { lab=#net3}
+N 100 -250 100 -220 { lab=vss}
+N 100 -380 100 -350 { lab=vdd}
+N -440 -300 -150 -300 { lab=#net2}
+N 190 -300 240 -300 { lab=A}
+N 440 -320 530 -320 { lab=out}
+N 480 -280 530 -280 { lab=nout}
+N 570 -220 570 -170 { lab=#net4}
+N 590 -220 590 -170 { lab=#net5}
+N 610 -220 610 -170 { lab=#net6}
+N 630 -220 630 -170 { lab=#net7}
+N 650 -220 650 -170 { lab=#net8}
+N 340 -220 340 -170 { lab=#net9}
+N 360 -220 360 -170 { lab=#net10}
+N 380 -220 380 -170 { lab=#net11}
+N 400 -220 400 -170 { lab=#net12}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(out) = 0.0
+.ic v(nout) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_2_tran.raw
+	plot v(out) v(A) v(nout)+2 v(A)+2
+.endc
+
+.end
+"}
+C {lab_pin.sym} 390 -410 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -410 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 450 -320 0 1 {name=l15 sig_type=std_logic lab=out}
+C {lab_wire.sym} 450 -280 0 1 {name=l8 sig_type=std_logic lab=nout}
+C {div_by_2_pex_c.sym} 370 -300 0 0 {name=x1}
+C {netlist_not_shown.sym} 290 -590 0 0 {name=STDCELL_MODELS 
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {lab_pin.sym} 630 -410 1 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 590 -410 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {noconn.sym} 730 -300 2 0 {name=l12}
+C {vsource.sym} -440 -240 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} -440 -180 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 230 -300 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} -110 -220 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 -380 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -90 -300 0 0 {name=x3}
+C {inverter_min_x4_pex_c.sym} 120 -300 0 0 {name=x4}
+C {lab_pin.sym} 100 -220 3 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -380 1 0 {name=l18 sig_type=std_logic lab=vdd}
+C {noconn.sym} 570 -170 3 0 {name=l7}
+C {noconn.sym} 590 -170 3 0 {name=l19}
+C {noconn.sym} 610 -170 3 0 {name=l20}
+C {noconn.sym} 630 -170 3 0 {name=l21}
+C {noconn.sym} 650 -170 3 0 {name=l22}
+C {noconn.sym} 340 -170 3 0 {name=l23}
+C {noconn.sym} 360 -170 3 0 {name=l24}
+C {noconn.sym} 380 -170 3 0 {name=l25}
+C {noconn.sym} 400 -170 3 0 {name=l26}
+C {div_by_5_pex_c.sym} 610 -300 0 0 {name=x2}

diff --git a/xschem/tb_div_by_5.sch b/xschem/tb_div_by_5.sch
new file mode 100644
index 0000000..c95644c
--- /dev/null
+++ b/xschem/tb_div_by_5.sch

@@ -0,0 +1,115 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -290 -350 -290 -320 { lab=GND}
+N -260 -120 -260 -90 { lab=vss}
+N -220 -350 -220 -320 { lab=vss}
+N -290 -440 -290 -410 { lab=vss}
+N -260 -210 -260 -180 { lab=CLK}
+N -220 -440 -220 -410 { lab=vdd}
+N 100 -240 130 -240 { lab=CLK}
+N 390 -350 390 -320 { lab=vdd}
+N 520 -170 520 -140 { lab=vss}
+N 180 -350 180 -320 { lab=vdd}
+N 220 -350 220 -320 { lab=vss}
+N 270 -260 330 -260 { lab=clk_2}
+N 520 -240 520 -230 { lab=clk_10}
+N 480 -240 520 -240 { lab=clk_10}
+N 430 -350 430 -320 { lab=vss}
+N 270 -220 330 -220 { lab=nclk_2}
+C {vsource.sym} -290 -380 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -220 -380 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -260 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -290 -320 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -290 -440 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -320 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -260 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -220 -440 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -260 -210 3 1 {name=l14 sig_type=std_logic lab=CLK}
+C {netlist_not_shown.sym} -120 -540 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+
+* Data to save
+.save all
+
+.ic v(CLK) = 0.0
+.ic v(x1.q2) = 0.0
+.ic v(x1.q1) = 0.0
+.ic v(x1.q1_shift) = 0.0
+.ic v(x1.q0) = 0.0
+.ic v(x1.x1.a) = 0.0
+.ic v(x1.x1.D_d) = 0.0
+.ic v(x1.x1.nD_d) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 600ns
+	*meas tran Tosc trig v(out) val=0.9 fall=5 targ v(out) val=0.9 fall=15
+	*meas tran Td1  trig v(out) val=0.9 fall=5 targ v(out1) val=0.9 rise=6 
+	*meas tran Td2  trig v(out1) val=0.9 fall=5 targ v(out2) val=0.9 rise=6
+	*meas tran Td3  trig v(out2) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	*let  T = Tosc/10.0
+	*let  f = 1/T
+	*let Td = 1/(2*3*f)
+	*print T f Td
+	write tb_div_by_5_tran.raw
+	plot v(clk_10) v(clk) v(clk_2) v(clk_2)+3 v(clk)+6
+	plot v(x1.Q2) v(x1.Q1)+2 v(clk_Q0)+4 v(x1.Q1_shift)+6 v(clk_10)+8 
+	
+.endc
+
+.end
+"}
+C {lab_pin.sym} 100 -240 2 1 {name=l7 sig_type=std_logic lab=CLK}
+C {lab_pin.sym} 390 -350 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {capa.sym} 520 -200 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 520 -140 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 520 -240 0 1 {name=l15 sig_type=std_logic lab=clk_10}
+C {lab_pin.sym} 180 -350 1 0 {name=l21 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 220 -350 1 0 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 430 -350 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 280 -260 0 1 {name=l5 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 280 -220 0 1 {name=l12 sig_type=std_logic lab=nclk_2}
+C {launcher.sym} 330 -490 0 0 {name=h2
+descr="sky130_models.tcl"
+tclcommand="eval exec $editor scripts/sky130_models.tcl"
+}
+C {netlist_not_shown.sym} -120 -360 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {div_by_2.sym} 200 -240 0 0 {name=x2}
+C {div_by_5.sym} 410 -240 0 0 {name=x1}
+C {noconn.sym} 370 -160 3 0 {name=l8}
+C {noconn.sym} 390 -160 3 0 {name=l9}
+C {noconn.sym} 410 -160 3 0 {name=l16}
+C {noconn.sym} 430 -160 3 0 {name=l17}
+C {noconn.sym} 450 -160 3 0 {name=l18}
+C {noconn.sym} 170 -160 3 0 {name=l19}
+C {noconn.sym} 190 -160 3 0 {name=l20}
+C {noconn.sym} 210 -160 3 0 {name=l23}
+C {noconn.sym} 230 -160 3 0 {name=l24}

diff --git a/xschem/tb_div_by_5_pex_c.sch b/xschem/tb_div_by_5_pex_c.sch
new file mode 100644
index 0000000..a408506
--- /dev/null
+++ b/xschem/tb_div_by_5_pex_c.sch

@@ -0,0 +1,172 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -100 -520 -100 -490 { lab=GND}
+N -30 -520 -30 -490 { lab=vss}
+N -100 -610 -100 -580 { lab=vss}
+N -30 -610 -30 -580 { lab=vdd}
+N 270 -300 300 -300 { lab=A}
+N 390 -410 390 -380 { lab=vss}
+N 350 -410 350 -380 { lab=vdd}
+N 440 -280 480 -280 { lab=nclk_2}
+N 1130 -420 1130 -390 { lab=vss}
+N 1090 -420 1090 -390 { lab=vdd}
+N -440 -210 -440 -180 { lab=vss}
+N -440 -300 -440 -270 { lab=#net1}
+N 240 -300 270 -300 { lab=A}
+N -110 -250 -110 -220 { lab=vss}
+N -110 -380 -110 -350 { lab=vdd}
+N -20 -300 60 -300 { lab=#net2}
+N 100 -250 100 -220 { lab=vss}
+N 100 -380 100 -350 { lab=vdd}
+N -440 -300 -150 -300 { lab=#net1}
+N 190 -300 240 -300 { lab=A}
+N 440 -320 530 -320 { lab=clk_2}
+N 480 -280 530 -280 { lab=nclk_2}
+N 1070 -230 1070 -180 { lab=#net3}
+N 1090 -230 1090 -180 { lab=#net4}
+N 1110 -230 1110 -180 { lab=#net5}
+N 1130 -230 1130 -180 { lab=#net6}
+N 1150 -230 1150 -180 { lab=#net7}
+N 1190 -310 1230 -310 { lab=clk_5}
+N 1320 -480 1320 -450 { lab=vss}
+N 1280 -480 1280 -450 { lab=vdd}
+N 1300 -250 1300 -200 { lab=#net8}
+N 1370 -310 1420 -310 { lab=#net9}
+N 1370 -390 1420 -390 { lab=#net10}
+N 1180 -390 1230 -390 { lab=#net11}
+N 570 -380 570 -350 { lab=vss}
+N 570 -510 570 -480 { lab=vdd}
+N 660 -430 740 -430 { lab=#net12}
+N 780 -380 780 -350 { lab=vss}
+N 780 -510 780 -480 { lab=vdd}
+N 870 -430 920 -430 { lab=clk_2_buf}
+N 570 -120 570 -90 { lab=vss}
+N 570 -250 570 -220 { lab=vdd}
+N 660 -170 740 -170 { lab=#net13}
+N 780 -120 780 -90 { lab=vss}
+N 780 -250 780 -220 { lab=vdd}
+N 870 -170 920 -170 { lab=nclk_2_buf}
+N 530 -280 530 -170 { lab=nclk_2}
+N 530 -430 530 -320 { lab=clk_2}
+N 930 -330 1030 -330 { lab=clk_2_buf}
+N 930 -430 930 -330 { lab=clk_2_buf}
+N 920 -430 930 -430 { lab=clk_2_buf}
+N 930 -290 1030 -290 { lab=nclk_2_buf}
+N 930 -290 930 -170 { lab=nclk_2_buf}
+N 920 -170 930 -170 { lab=nclk_2_buf}
+N 340 -220 340 -170 { lab=#net14}
+N 360 -220 360 -170 { lab=#net15}
+N 380 -220 380 -170 { lab=#net16}
+N 400 -220 400 -170 { lab=#net17}
+C {vsource.sym} -100 -550 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -30 -550 0 0 {name=VDD value=\{vdd\}}
+C {gnd.sym} -100 -490 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -100 -610 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -490 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -30 -610 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {netlist_not_shown.sym} 80 -600 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 1e9
+.param Tref = 1/fref
+.param C = 1f
+.param iref=100u
+
+.options TEMP = 100.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_min_x4_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+
+* Data to save
+.save all
+
+.ic v(A) = 0.0
+.ic v(x2.q0) = 0.0
+.ic v(x2.nq0) = 0.0
+.ic v(x2.q1) = 0.0
+.ic v(x2.nq1) = 0.0
+.ic v(x2.q1_shift) = 0.0
+.ic v(x2.nq1_shift) = 0.0
+.ic v(x2.q2) = 0.0
+.ic v(x2.nq2) = 0.0
+.ic v(x2.x1.a) = 0.0
+.ic v(x2.x1.na) = 0.0
+.ic v(x2.x1.D_d) = 0.0
+.ic v(x2.x1.nD_d) = 0.0
+.ic v(clk_2) = 0.0
+.ic v(nclk_2) = 0.0
+.ic v(clk_5)
+
+* Simulation
+.control
+	tran 0.01ns 200ns
+	write tb_div_by_5_tran.raw
+	plot v(clk_2) v(A) v(nclk_2)+2 v(A)+2
+	plot v(clk_5) v(clk_2_buf) v(A)
+.endc
+
+.end
+"}
+C {lab_pin.sym} 390 -410 1 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 350 -410 1 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 450 -320 0 1 {name=l15 sig_type=std_logic lab=clk_2}
+C {lab_wire.sym} 450 -280 0 1 {name=l8 sig_type=std_logic lab=nclk_2}
+C {div_by_2_pex_c.sym} 370 -300 0 0 {name=x1}
+C {lab_pin.sym} 1130 -420 1 0 {name=l5 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1090 -420 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {vsource.sym} -440 -240 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} -440 -180 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 230 -300 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} -110 -220 3 0 {name=l13 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -110 -380 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} -90 -300 0 0 {name=x3}
+C {inverter_min_x4_pex_c.sym} 120 -300 0 0 {name=x4}
+C {lab_pin.sym} 100 -220 3 0 {name=l17 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 100 -380 1 0 {name=l18 sig_type=std_logic lab=vdd}
+C {noconn.sym} 1070 -180 3 0 {name=l7}
+C {noconn.sym} 1090 -180 3 0 {name=l19}
+C {noconn.sym} 1110 -180 3 0 {name=l20}
+C {noconn.sym} 1130 -180 3 0 {name=l21}
+C {noconn.sym} 1150 -180 3 0 {name=l22}
+C {PFD_pex_c.sym} 1300 -350 0 0 {name=x5}
+C {lab_pin.sym} 1320 -480 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 1280 -480 1 0 {name=l23 sig_type=std_logic lab=vdd}
+C {noconn.sym} 1300 -200 3 0 {name=l24}
+C {noconn.sym} 1420 -310 2 0 {name=l25}
+C {noconn.sym} 1420 -390 2 0 {name=l26}
+C {noconn.sym} 1180 -390 0 0 {name=l27}
+C {lab_wire.sym} 1200 -310 0 1 {name=l28 sig_type=std_logic lab=clk_5}
+C {div_by_5_pex_c.sym} 1110 -310 0 0 {name=x2}
+C {lab_pin.sym} 570 -350 3 0 {name=l30 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -510 1 0 {name=l31 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} 590 -430 0 0 {name=x6}
+C {inverter_min_x4_pex_c.sym} 800 -430 0 0 {name=x7}
+C {lab_pin.sym} 780 -350 3 0 {name=l32 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 780 -510 1 0 {name=l33 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -90 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 570 -250 1 0 {name=l36 sig_type=std_logic lab=vdd}
+C {inverter_min_x2_pex_c.sym} 590 -170 0 0 {name=x8}
+C {inverter_min_x4_pex_c.sym} 800 -170 0 0 {name=x9}
+C {lab_pin.sym} 780 -90 3 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 780 -250 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 960 -330 0 1 {name=l29 sig_type=std_logic lab=clk_2_buf}
+C {lab_wire.sym} 960 -290 0 1 {name=l34 sig_type=std_logic lab=nclk_2_buf}
+C {noconn.sym} 340 -170 3 0 {name=l39}
+C {noconn.sym} 360 -170 3 0 {name=l40}
+C {noconn.sym} 380 -170 3 0 {name=l41}
+C {noconn.sym} 400 -170 3 0 {name=l42}

diff --git a/xschem/tb_inverter_csvco.sch b/xschem/tb_inverter_csvco.sch
new file mode 100644
index 0000000..6761b76
--- /dev/null
+++ b/xschem/tb_inverter_csvco.sch

@@ -0,0 +1,152 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 150 -450 150 -420 { lab=vss}
+N 150 -580 150 -550 { lab=vdd}
+N 240 -500 320 -500 { lab=out}
+N 50 -500 110 -500 { lab=in}
+N 150 -420 150 -400 { lab=vss}
+N 150 -600 150 -580 { lab=vdd}
+N 320 -790 320 -740 { lab=GND}
+N 500 -790 500 -740 { lab=vss}
+N 410 -790 410 -740 { lab=vss}
+N 320 -900 320 -850 { lab=vss}
+N 500 -900 500 -850 { lab=in}
+N 410 -900 410 -850 { lab=vdd}
+N 320 -500 320 -480 { lab=out}
+N 320 -420 320 -400 { lab=vss}
+N 190 -560 190 -530 { lab=vdd}
+N 190 -580 190 -560 { lab=vdd}
+N 190 -470 190 -440 { lab=vss}
+N 190 -440 190 -420 { lab=vss}
+N 570 -450 570 -420 { lab=vss}
+N 570 -580 570 -550 { lab=vdd}
+N 660 -500 740 -500 { lab=out_pex_c}
+N 470 -500 530 -500 { lab=in}
+N 570 -420 570 -400 { lab=vss}
+N 570 -600 570 -580 { lab=vdd}
+N 740 -500 740 -480 { lab=out_pex_c}
+N 740 -420 740 -400 { lab=vss}
+N 610 -560 610 -530 { lab=vdd}
+N 610 -580 610 -560 { lab=vdd}
+N 610 -470 610 -440 { lab=vss}
+N 610 -440 610 -420 { lab=vss}
+C {lab_pin.sym} 150 -600 1 0 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 -400 3 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 290 -500 0 0 {name=l3 sig_type=std_logic lab=out}
+C {vsource.sym} 320 -820 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} 410 -820 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} 500 -820 0 0 {name=VIN value="PULSE(0 \{vin\} 0 1p 1p \{T/2\} \{T\}) DC \{vin\} AC 0"}
+C {gnd.sym} 320 -740 0 0 {name=l9 lab=GND}
+C {lab_pin.sym} 410 -740 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 500 -740 3 0 {name=l11 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 410 -900 1 0 {name=l12 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 500 -900 1 0 {name=l13 sig_type=std_logic lab=in}
+C {lab_pin.sym} 320 -900 1 0 {name=l14 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 130 -860 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0
+.param vin = vdd
+.param T   = 100n
+
+.options TEMP = 50.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/sky130-mpw2-fulgor/inverter_csvco/sch/simulations/inverter_csvco_pex_c.spice
+
+* Initial Conditions
+.ic v(out) = 0.0
+.ic v(out_wp) = 0.0
+.ic v(out_wp_rc) = 0.0
+.ic v(out_pex_c) = 0.0
+
+* Data to save
+.save all
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[id]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[id]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vds]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vds]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[vdsat]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[vdsat]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgs]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgs]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgd]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgd]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[csb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[csb]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cdb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cdb]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgg]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgg]
++ @M.X1.XM1.msky130_fd_pr__nfet_01v8[cgb]
++ @M.X1.XM2.msky130_fd_pr__pfet_01v8[cgb]
+
+* Simulation
+.control
+	set filetype = ascii
+	op 
+	write tb_inverter_min.raw
+	echo .
+	echo ------ OP Results -----
+	print all
+
+	reset
+	
+	dc vin 0 1.8 0.01
+	setplot dc1
+	plot v(in) v(out) v(out_pex_c)
+	write tb_inverter_min_dc.raw
+
+	reset
+
+	tran 1ns 1us
+	meas tran tpLH trig v(in) val=0.9 fall=5 targ v(out) val=0.9 rise=5
+	meas tran tpHL trig v(in) val=0.9 rise=5 targ v(out) val=0.9 fall=4
+	meas tran tpLHc trig v(in) val=0.9 fall=5 targ v(out_pex_c) val=0.9 rise=5
+	meas tran tpHLc trig v(in) val=0.9 rise=5 targ v(out_pex_c) val=0.9 fall=4
+	let tp = (0.5*(tpLH + tpHL))
+	let tp_c = (0.5*(tpLHc + tpHLc))
+	echo .
+	echo ---- tp Ideal ----
+	print tpLH tpHL tp
+	echo .
+	echo ---- tp PEX C ----
+	print tpLHc tpHLc tp_c
+	write tb_inverter_tran.raw
+	plot v(in) v(out) v(out_pex_c)+2 
+
+.endc
+
+.end
+"}
+C {capa.sym} 320 -450 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 320 -400 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 50 -500 0 0 {name=l5 sig_type=std_logic lab=in}
+C {inverter_csvco.sym} 170 -500 0 0 {name=x1}
+C {lab_pin.sym} 190 -580 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 190 -420 3 0 {name=l28 sig_type=std_logic lab=vss}
+C {inverter_csvco/sch/inverter_csvco_pex_c.sym} 590 -500 0 0 {name=x2}
+C {lab_pin.sym} 570 -600 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 570 -400 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 710 -500 0 0 {name=l8 sig_type=std_logic lab=out_pex_c}
+C {capa.sym} 740 -450 0 0 {name=C2
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 740 -400 3 0 {name=l15 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 470 -500 0 0 {name=l16 sig_type=std_logic lab=in}
+C {lab_pin.sym} 610 -580 1 0 {name=l17 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 610 -420 3 0 {name=l18 sig_type=std_logic lab=vss}

diff --git a/xschem/tb_loop_filter.sch b/xschem/tb_loop_filter.sch
new file mode 100644
index 0000000..db158dc
--- /dev/null
+++ b/xschem/tb_loop_filter.sch

@@ -0,0 +1,76 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -180 -90 -180 -60 { lab=GND}
+N -180 -180 -180 -150 { lab=vss}
+N -90 -90 -90 -60 { lab=vss}
+N -90 -180 -90 -150 { lab=vdd}
+N 130 80 130 110 { lab=vss}
+N 130 -80 130 -60 { lab=A}
+N 20 -110 20 -80 { lab=vss}
+N 20 -200 20 -170 { lab=A}
+N 190 10 240 10 { lab=vc}
+N 390 80 390 110 { lab=vss}
+N 390 -80 390 -60 { lab=A}
+N 450 10 500 10 { lab=vc_pex}
+C {vsource.sym} -180 -120 0 0 {name=VSS value=\{vss\}}
+C {gnd.sym} -180 -60 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -180 -180 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {netlist_not_shown.sym} 390 -220 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 5e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = 0.0
+.param R1 = 1.6k
+.param C1 = 33.5p
+.param C2 = 6.7p
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+
+* Data to save
+
+
+* Simulation
+.control
+
+	tran 0.01ns 200ns
+	meas tran t1 when v(vc)=0.63
+	meas tran t2 when v(vc_pex)=0.63
+	let R = t1/0.5p
+	let Rpex = t2/05.p
+	print R Rpex 
+	plot v(vc) v(vc_pex)
+.endc
+.end
+"}
+C {vsource.sym} -90 -120 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} -90 -180 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -90 -60 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 130 110 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {vsource.sym} 20 -140 0 0 {name=Vref value="PULSE(0 1.0 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {lab_pin.sym} 20 -80 3 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 20 -200 3 1 {name=l14 sig_type=std_logic lab=A}
+C {lab_pin.sym} 130 -80 3 1 {name=l6 sig_type=std_logic lab=A}
+C {loop_filter.sym} 130 10 0 0 {name=x1}
+C {noconn.sym} 240 10 2 0 {name=l83}
+C {lab_pin.sym} 390 110 3 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 390 -80 3 1 {name=l8 sig_type=std_logic lab=A}
+C {noconn.sym} 500 10 2 0 {name=l9}
+C {lab_pin.sym} 220 10 1 0 {name=l11 sig_type=std_logic lab=vc}
+C {lab_pin.sym} 480 10 1 0 {name=l12 sig_type=std_logic lab=vc_pex}
+C {loop_filter_pex_c.sym} 390 10 0 0 {name=x2}

diff --git a/xschem/tb_top_pll_v1.sch b/xschem/tb_top_pll_v1.sch
new file mode 100644
index 0000000..183ca6b
--- /dev/null
+++ b/xschem/tb_top_pll_v1.sch

@@ -0,0 +1,240 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 360 250 400 250 { lab=out_to_pad}
+N 400 250 450 250 { lab=out_to_pad}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f 
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 450 250 2 0 {name=l48}
+C {lab_wire.sym} 370 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {netlist_not_shown.sym} 230 -170 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {top_pll_v1.sym} 10 250 0 0 {name=x1}
+C {bias.sym} -590 210 0 0 {name=x2}

diff --git a/xschem/tb_top_pll_v1_pex_c.sch b/xschem/tb_top_pll_v1_pex_c.sch
new file mode 100644
index 0000000..6b3509f
--- /dev/null
+++ b/xschem/tb_top_pll_v1_pex_c.sch

@@ -0,0 +1,237 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 360 250 400 250 { lab=out_to_pad}
+N 400 250 450 250 { lab=out_to_pad}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 50.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib TT
+.include ~/caravel_analog_fulgor/xschem/simulations/top_pll_v1_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f 
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 450 250 2 0 {name=l48}
+C {lab_wire.sym} 370 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {top_pll_v1_pex_c.sym} 10 250 0 0 {name=x1}
+C {bias_pex_c.sym} -590 210 0 0 {name=x9}

diff --git a/xschem/tb_top_pll_v1_pex_no_integration.sch b/xschem/tb_top_pll_v1_pex_no_integration.sch
new file mode 100644
index 0000000..2048cde
--- /dev/null
+++ b/xschem/tb_top_pll_v1_pex_no_integration.sch

@@ -0,0 +1,250 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -620 -120 -620 -90 { lab=GND}
+N -470 -120 -470 -90 { lab=vss}
+N -550 -120 -550 -90 { lab=vss}
+N -620 -210 -620 -180 { lab=vss}
+N -470 -210 -470 -180 { lab=A}
+N -550 -210 -550 -180 { lab=vdd}
+N -100 -110 -100 -80 { lab=vss}
+N -100 -200 -100 -170 { lab=D0}
+N -590 50 -590 80 { lab=vdd}
+N -610 440 -610 470 { lab=vss}
+N -530 120 -490 120 { lab=iref_cp}
+N -610 350 -610 380 { lab=#net1}
+N -610 340 -610 350 { lab=#net1}
+N -570 340 -570 370 { lab=vss}
+N -530 140 -490 140 { lab=#net2}
+N -530 160 -490 160 { lab=#net3}
+N -530 180 -490 180 { lab=#net4}
+N -530 200 -490 200 { lab=#net5}
+N -530 220 -490 220 { lab=#net6}
+N -530 240 -490 240 { lab=#net7}
+N -530 260 -490 260 { lab=#net8}
+N -530 280 -490 280 { lab=#net9}
+N -530 300 -490 300 { lab=#net10}
+N 180 90 180 120 { lab=vdd}
+N 240 90 240 120 { lab=vss}
+N -280 80 -280 120 { lab=iref_cp}
+N -200 90 -200 120 { lab=D0}
+N -370 250 -340 250 { lab=A}
+N 360 250 400 250 { lab=out_to_pad}
+N 400 250 450 250 { lab=out_to_pad}
+N 280 380 280 430 { lab=div_5_nQ2}
+N 260 380 260 430 { lab=div_5_Q1_shift}
+N 240 380 240 430 { lab=div_5_Q1}
+N 220 380 220 430 { lab=div_5_nQ0}
+N 200 380 200 430 { lab=div_5_Q0}
+N 130 380 130 430 { lab=n_out_buffer_div_2}
+N 110 380 110 430 { lab=out_buffer_div_2}
+N 90 380 90 430 { lab=n_out_div_2}
+N 70 380 70 430 { lab=out_div_2}
+N -120 430 -120 480 { lab=nswitch}
+N -100 430 -100 480 { lab=pswitch}
+N -80 430 -80 480 { lab=biasp}
+N -80 380 -80 430 { lab=biasp}
+N -100 380 -100 430 { lab=pswitch}
+N -120 380 -120 430 { lab=nswitch}
+N -280 430 -280 480 { lab=pfd_reset}
+N -280 380 -280 430 { lab=pfd_reset}
+N -260 430 -260 480 { lab=QA}
+N -260 380 -260 430 { lab=QA}
+N -240 430 -240 480 { lab=QB}
+N -240 380 -240 430 { lab=QB}
+N -210 430 -210 480 { lab=Up}
+N -210 380 -210 430 { lab=Up}
+N -190 430 -190 480 { lab=nUp}
+N -190 380 -190 430 { lab=nUp}
+N -170 430 -170 480 { lab=Down}
+N -170 380 -170 430 { lab=Down}
+N -150 430 -150 480 { lab=nDown}
+N -150 380 -150 430 { lab=nDown}
+N -50 380 -50 430 { lab=lf_vc}
+N -20 430 -20 480 { lab=vctrl}
+N -20 380 -20 430 { lab=vctrl}
+N 0 430 0 480 { lab=vco_out}
+N 0 380 0 430 { lab=vco_out}
+N 20 430 20 480 { lab=vco_buffer_out}
+N 20 380 20 430 { lab=vco_buffer_out}
+N 40 430 40 480 { lab=out_to_div}
+N 40 380 40 430 { lab=out_to_div}
+N 150 430 150 480 { lab=out_by_2}
+N 150 380 150 430 { lab=out_by_2}
+N 170 430 170 480 { lab=n_out_by_2}
+N 170 380 170 430 { lab=n_out_by_2}
+N 300 430 300 480 { lab=out_by_5}
+N 300 380 300 430 { lab=out_by_5}
+C {vsource.sym} -620 -150 0 0 {name=VSS value=\{vss\}}
+C {vsource.sym} -550 -150 0 0 {name=VDD value=\{vdd\}}
+C {vsource.sym} -470 -150 0 0 {name=Vref value="PULSE(0 \{vin\} 0 1p 1p \{Tref/2\} \{Tref\}) DC \{vin\} AC 0"}
+C {gnd.sym} -620 -90 0 0 {name=l1 lab=GND}
+C {lab_pin.sym} -620 -210 1 0 {name=l2 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -90 3 0 {name=l3 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -470 -90 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -550 -210 1 0 {name=l6 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -470 -210 3 1 {name=l14 sig_type=std_logic lab=A}
+C {netlist_not_shown.sym} 60 -170 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param fref = 100e6
+.param Tref = 1/fref
+.param iref = 100u
+.param vd0 = vdd
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/PFD_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/pfd_cp_interface_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/charge_pump_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/loop_filter_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/ring_osc_buffer_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_2_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/div_by_5_pex_c.spice
+.include ~/caravel_analog_fulgor/xschem/simulations/bias_pex_c.spice
+
+
+* Data to save
+
+.ic v(A) = 0.0
+.ic v(QA) = 0.0
+.ic v(QB) = 0.0
+.ic v(Up) = 0.0
+.ic v(nUp) = 0.0
+.ic v(Down) = 0.0
+.ic v(nDown) = 0.0
+.ic v(vctrl) = 0.0
+.ic v(D0) = 0.0
+.ic v(vco_out) = 0.0
+.ic v(vco_buffer_out) = 0.0
+.ic v(out_to_div) = 0.0
+.ic v(out_to_pad) = 0.0
+.ic v(out_div_2) = 0.0
+.ic v(n_out_div_2) = 0.0
+.ic v(out_buffer_div_2) = 0.0
+.ic v(n_out_buffer_div_2) = 0.0
+.ic v(out_by_2) = 0.0
+.ic v(n_out_by_2) = 0.0
+.ic v(div_5_Q0) = 0.0
+.ic v(div_5_nQ0) = 0.0
+.ic v(div_5_Q1) = 0.0
+.ic v(div_5_Q1_shift) = 0.0
+.ic v(div_5_nQ2) = 0.0
+.ic v(out_by_5) = 0.0
+
+* Simulation
+.control
+	tran 0.01ns 1.5us
+	meas tran Tosc trig v(out_to_pad) val=0.9 fall=1005 targ v(out_to_pad) val=0.9 fall=1105
+	let  T = Tosc/100.0
+	let  f = 1/T
+	echo .
+	echo ------ PLL simulation ------
+	print T f 
+	*write tb_PLL_tran.raw
+	plot v(vctrl) v(pfd_reset)+2 v(nDown)+4 v(Down)+6 v(nUp)+8 v(Up)+10 v(QA)+12 v(QB)+12 v(A)+14 v(out_by_5)+16
+ 	plot v(out_to_pad)+9 v(out_to_div)+6 v(out_by_2)+3 v(out_by_5)
+	plot v(out_by_5) v(out_by_2) v(out_to_div)
+	plot v(vctrl)
+	plot v(pswitch) v(nswitch) xlimit 1.4us 1.444us
+.endc
+
+.end
+"}
+C {vsource.sym} -100 -140 0 0 {name=VD0 value=\{vd0\}}
+C {lab_pin.sym} -100 -80 3 0 {name=l52 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -100 -200 1 0 {name=l53 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -590 50 1 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -610 470 3 0 {name=l19 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -490 120 2 0 {name=l23 sig_type=std_logic lab=iref_cp}
+C {isource.sym} -610 410 0 0 {name=I0 value=\{iref\}}
+C {lab_pin.sym} -570 370 3 0 {name=l36 sig_type=std_logic lab=vss}
+C {noconn.sym} -490 140 2 0 {name=l75}
+C {noconn.sym} -490 160 2 0 {name=l76}
+C {noconn.sym} -490 180 2 0 {name=l77}
+C {noconn.sym} -490 200 2 0 {name=l78}
+C {noconn.sym} -490 220 2 0 {name=l79}
+C {noconn.sym} -490 240 2 0 {name=l80}
+C {noconn.sym} -490 260 2 0 {name=l81}
+C {noconn.sym} -490 280 2 0 {name=l82}
+C {noconn.sym} -490 300 2 0 {name=l83}
+C {lab_pin.sym} 180 90 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 240 90 1 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -280 80 1 0 {name=l9 sig_type=std_logic lab=iref_cp}
+C {lab_pin.sym} -200 90 1 0 {name=l10 sig_type=std_logic lab=D0}
+C {lab_pin.sym} -370 250 2 1 {name=l11 sig_type=std_logic lab=A}
+C {noconn.sym} 450 250 2 0 {name=l48}
+C {lab_wire.sym} 370 250 0 1 {name=l61 sig_type=std_logic lab=out_to_pad}
+C {noconn.sym} 280 430 1 1 {name=l66}
+C {noconn.sym} 260 430 1 1 {name=l67}
+C {noconn.sym} 240 430 1 1 {name=l68}
+C {noconn.sym} 220 430 1 1 {name=l69}
+C {noconn.sym} 200 430 1 1 {name=l70}
+C {noconn.sym} 130 430 1 1 {name=l24}
+C {noconn.sym} 110 430 1 1 {name=l42}
+C {noconn.sym} 90 430 1 1 {name=l43}
+C {noconn.sym} 70 430 1 1 {name=l44}
+C {noconn.sym} -120 480 3 0 {name=l33}
+C {noconn.sym} -100 480 3 0 {name=l34}
+C {lab_wire.sym} -120 440 3 0 {name=l50 sig_type=std_logic lab=nswitch}
+C {lab_wire.sym} -100 440 3 0 {name=l51 sig_type=std_logic lab=pswitch}
+C {noconn.sym} -80 480 3 0 {name=l56}
+C {lab_wire.sym} -80 440 3 0 {name=l57 sig_type=std_logic lab=biasp}
+C {noconn.sym} -280 480 3 0 {name=l54}
+C {lab_wire.sym} -280 440 3 0 {name=l55 sig_type=std_logic lab=pfd_reset}
+C {noconn.sym} -260 480 3 0 {name=l12}
+C {lab_wire.sym} -260 440 3 0 {name=l13 sig_type=std_logic lab=QA}
+C {noconn.sym} -240 480 3 0 {name=l15}
+C {lab_wire.sym} -240 440 3 0 {name=l16 sig_type=std_logic lab=QB}
+C {noconn.sym} -210 480 3 0 {name=l17}
+C {lab_wire.sym} -210 440 3 0 {name=l18 sig_type=std_logic lab=Up}
+C {noconn.sym} -190 480 3 0 {name=l20}
+C {lab_wire.sym} -190 440 3 0 {name=l21 sig_type=std_logic lab=nUp}
+C {noconn.sym} -170 480 3 0 {name=l22}
+C {lab_wire.sym} -170 440 3 0 {name=l25 sig_type=std_logic lab=Down}
+C {noconn.sym} -150 480 3 0 {name=l26}
+C {lab_wire.sym} -150 440 3 0 {name=l27 sig_type=std_logic lab=nDown}
+C {noconn.sym} -50 430 1 1 {name=l28}
+C {noconn.sym} -20 480 3 0 {name=l29}
+C {lab_wire.sym} -20 440 3 0 {name=l30 sig_type=std_logic lab=vctrl}
+C {noconn.sym} 0 480 3 0 {name=l31}
+C {lab_wire.sym} 0 440 3 0 {name=l32 sig_type=std_logic lab=vco_out}
+C {noconn.sym} 20 480 3 0 {name=l35}
+C {lab_wire.sym} 20 440 3 0 {name=l37 sig_type=std_logic lab=vco_buffer_out}
+C {noconn.sym} 40 480 3 0 {name=l38}
+C {lab_wire.sym} 40 440 3 0 {name=l39 sig_type=std_logic lab=out_to_div}
+C {noconn.sym} 150 480 3 0 {name=l40}
+C {lab_wire.sym} 150 440 3 0 {name=l41 sig_type=std_logic lab=out_by_2}
+C {noconn.sym} 170 480 3 0 {name=l45}
+C {lab_wire.sym} 170 440 3 0 {name=l46 sig_type=std_logic lab=n_out_by_2}
+C {noconn.sym} 300 480 3 0 {name=l47}
+C {lab_wire.sym} 300 440 3 0 {name=l49 sig_type=std_logic lab=out_by_5}
+C {lab_wire.sym} -50 390 3 0 {name=l58 sig_type=std_logic lab=lf_vc}
+C {lab_wire.sym} 70 420 3 0 {name=l59 sig_type=std_logic lab=out_div_2}
+C {lab_wire.sym} 90 420 3 0 {name=l60 sig_type=std_logic lab=n_out_div_2}
+C {lab_wire.sym} 110 420 3 0 {name=l62 sig_type=std_logic lab=out_buffer_div_2}
+C {lab_wire.sym} 130 420 3 0 {name=l63 sig_type=std_logic lab=n_out_buffer_div_2}
+C {lab_wire.sym} 200 420 3 0 {name=l64 sig_type=std_logic lab=div_5_Q0}
+C {lab_wire.sym} 220 420 3 0 {name=l65 sig_type=std_logic lab=div_5_nQ0}
+C {lab_wire.sym} 240 420 3 0 {name=l71 sig_type=std_logic lab=div_5_Q1}
+C {lab_wire.sym} 260 420 3 0 {name=l72 sig_type=std_logic lab=div_5_Q1_shift}
+C {lab_wire.sym} 280 420 3 0 {name=l73 sig_type=std_logic lab=div_5_nQ2}
+C {netlist_not_shown.sym} 230 -170 0 0 {name=STDCELL_MODELS
+only_toplevel=true
+place=end
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {bias_pex_c.sym} -590 210 0 0 {name=x2}
+C {top_pll_v1_pex_no_integration.sym} 10 250 0 0 {name=x1}

diff --git a/xschem/test.data b/xschem/test.data
deleted file mode 100644
index c9cde37..0000000
--- a/xschem/test.data
+++ /dev/null

@@ -1,101 +0,0 @@
- 7.00000000e-01 -8.93059159e-08  7.00000000e-01  7.00000000e-01 
- 7.01000000e-01 -9.08452852e-08  7.01000000e-01  7.01000000e-01 
- 7.02000000e-01 -9.24385447e-08  7.02000000e-01  7.02000000e-01 
- 7.03000000e-01 -9.40459956e-08  7.03000000e-01  7.03000000e-01 
- 7.04000000e-01 -9.56814959e-08  7.04000000e-01  7.04000000e-01 
- 7.05000000e-01 -9.73455368e-08  7.05000000e-01  7.05000000e-01 
- 7.06000000e-01 -9.90386085e-08  7.06000000e-01  7.06000000e-01 
- 7.07000000e-01 -1.00761227e-07  7.07000000e-01  7.07000000e-01 
- 7.08000000e-01 -1.02513882e-07  7.08000000e-01  7.08000000e-01 
- 7.09000000e-01 -1.04297110e-07  7.09000000e-01  7.09000000e-01 
- 7.10000000e-01 -1.06111443e-07  7.10000000e-01  7.10000000e-01 
- 7.11000000e-01 -1.07957415e-07  7.11000000e-01  7.11000000e-01 
- 7.12000000e-01 -1.09835552e-07  7.12000000e-01  7.12000000e-01 
- 7.13000000e-01 -1.11746436e-07  7.13000000e-01  7.13000000e-01 
- 7.14000000e-01 -1.13690603e-07  7.14000000e-01  7.14000000e-01 
- 7.15000000e-01 -1.15668634e-07  7.15000000e-01  7.15000000e-01 
- 7.16000000e-01 -1.17681129e-07  7.16000000e-01  7.16000000e-01 
- 7.17000000e-01 -1.19728657e-07  7.17000000e-01  7.17000000e-01 
- 7.18000000e-01 -1.21811839e-07  7.18000000e-01  7.18000000e-01 
- 7.19000000e-01 -1.23931259e-07  7.19000000e-01  7.19000000e-01 
- 7.20000000e-01 -1.26087554e-07  7.20000000e-01  7.20000000e-01 
- 7.21000000e-01 -1.28281358e-07  7.21000000e-01  7.21000000e-01 
- 7.22000000e-01 -1.30513286e-07  7.22000000e-01  7.22000000e-01 
- 7.23000000e-01 -1.32784003e-07  7.23000000e-01  7.23000000e-01 
- 7.24000000e-01 -1.35094165e-07  7.24000000e-01  7.24000000e-01 
- 7.25000000e-01 -1.37444453e-07  7.25000000e-01  7.25000000e-01 
- 7.26000000e-01 -1.39835535e-07  7.26000000e-01  7.26000000e-01 
- 7.27000000e-01 -1.42268085e-07  7.27000000e-01  7.27000000e-01 
- 7.28000000e-01 -1.44742842e-07  7.28000000e-01  7.28000000e-01 
- 7.29000000e-01 -1.47260486e-07  7.29000000e-01  7.29000000e-01 
- 7.30000000e-01 -1.49821761e-07  7.30000000e-01  7.30000000e-01 
- 7.31000000e-01 -1.52427364e-07  7.31000000e-01  7.31000000e-01 
- 7.32000000e-01 -1.55078077e-07  7.32000000e-01  7.32000000e-01 
- 7.33000000e-01 -1.57774611e-07  7.33000000e-01  7.33000000e-01 
- 7.34000000e-01 -1.60517775e-07  7.34000000e-01  7.34000000e-01 
- 7.35000000e-01 -1.63308337e-07  7.35000000e-01  7.35000000e-01 
- 7.36000000e-01 -1.66147061e-07  7.36000000e-01  7.36000000e-01 
- 7.37000000e-01 -1.69034765e-07  7.37000000e-01  7.37000000e-01 
- 7.38000000e-01 -1.71972266e-07  7.38000000e-01  7.38000000e-01 
- 7.39000000e-01 -1.74960357e-07  7.39000000e-01  7.39000000e-01 
- 7.40000000e-01 -1.77999888e-07  7.40000000e-01  7.40000000e-01 
- 7.41000000e-01 -1.81091703e-07  7.41000000e-01  7.41000000e-01 
- 7.42000000e-01 -1.84236664e-07  7.42000000e-01  7.42000000e-01 
- 7.43000000e-01 -1.87435634e-07  7.43000000e-01  7.43000000e-01 
- 7.44000000e-01 -1.90689493e-07  7.44000000e-01  7.44000000e-01 
- 7.45000000e-01 -1.93999127e-07  7.45000000e-01  7.45000000e-01 
- 7.46000000e-01 -1.97365464e-07  7.46000000e-01  7.46000000e-01 
- 7.47000000e-01 -2.00789378e-07  7.47000000e-01  7.47000000e-01 
- 7.48000000e-01 -2.04271837e-07  7.48000000e-01  7.48000000e-01 
- 7.49000000e-01 -2.07813739e-07  7.49000000e-01  7.49000000e-01 
- 7.50000000e-01 -2.11416073e-07  7.50000000e-01  7.50000000e-01 
- 7.51000000e-01 -2.15079797e-07  7.51000000e-01  7.51000000e-01 
- 7.52000000e-01 -2.18805863e-07  7.52000000e-01  7.52000000e-01 
- 7.53000000e-01 -2.22595278e-07  7.53000000e-01  7.53000000e-01 
- 7.54000000e-01 -2.26449036e-07  7.54000000e-01  7.54000000e-01 
- 7.55000000e-01 -2.30368144e-07  7.55000000e-01  7.55000000e-01 
- 7.56000000e-01 -2.34353630e-07  7.56000000e-01  7.56000000e-01 
- 7.57000000e-01 -2.38406548e-07  7.57000000e-01  7.57000000e-01 
- 7.58000000e-01 -2.42527913e-07  7.58000000e-01  7.58000000e-01 
- 7.59000000e-01 -2.46718795e-07  7.59000000e-01  7.59000000e-01 
- 7.60000000e-01 -2.50980278e-07  7.60000000e-01  7.60000000e-01 
- 7.61000000e-01 -2.55313430e-07  7.61000000e-01  7.61000000e-01 
- 7.62000000e-01 -2.59719344e-07  7.62000000e-01  7.62000000e-01 
- 7.63000000e-01 -2.64199148e-07  7.63000000e-01  7.63000000e-01 
- 7.64000000e-01 -2.68753946e-07  7.64000000e-01  7.64000000e-01 
- 7.65000000e-01 -2.73384860e-07  7.65000000e-01  7.65000000e-01 
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- 7.67000000e-01 -2.82879650e-07  7.67000000e-01  7.67000000e-01 
- 7.68000000e-01 -2.87745826e-07  7.68000000e-01  7.68000000e-01 
- 7.69000000e-01 -2.92692776e-07  7.69000000e-01  7.69000000e-01 
- 7.70000000e-01 -2.97721660e-07  7.70000000e-01  7.70000000e-01 
- 7.71000000e-01 -3.02833688e-07  7.71000000e-01  7.71000000e-01 
- 7.72000000e-01 -3.08030053e-07  7.72000000e-01  7.72000000e-01 
- 7.73000000e-01 -3.13311974e-07  7.73000000e-01  7.73000000e-01 
- 7.74000000e-01 -3.18680710e-07  7.74000000e-01  7.74000000e-01 
- 7.75000000e-01 -3.24137468e-07  7.75000000e-01  7.75000000e-01 
- 7.76000000e-01 -3.29683509e-07  7.76000000e-01  7.76000000e-01 
- 7.77000000e-01 -3.35320078e-07  7.77000000e-01  7.77000000e-01 
- 7.78000000e-01 -3.41048451e-07  7.78000000e-01  7.78000000e-01 
- 7.79000000e-01 -3.46869908e-07  7.79000000e-01  7.79000000e-01 
- 7.80000000e-01 -3.52785731e-07  7.80000000e-01  7.80000000e-01 
- 7.81000000e-01 -3.58797218e-07  7.81000000e-01  7.81000000e-01 
- 7.82000000e-01 -3.64905663e-07  7.82000000e-01  7.82000000e-01 
- 7.83000000e-01 -3.71112381e-07  7.83000000e-01  7.83000000e-01 
- 7.84000000e-01 -3.77418703e-07  7.84000000e-01  7.84000000e-01 
- 7.85000000e-01 -3.83825919e-07  7.85000000e-01  7.85000000e-01 
- 7.86000000e-01 -3.90335390e-07  7.86000000e-01  7.86000000e-01 
- 7.87000000e-01 -3.96948455e-07  7.87000000e-01  7.87000000e-01 
- 7.88000000e-01 -4.03666461e-07  7.88000000e-01  7.88000000e-01 
- 7.89000000e-01 -4.10490750e-07  7.89000000e-01  7.89000000e-01 
- 7.90000000e-01 -4.17422681e-07  7.90000000e-01  7.90000000e-01 
- 7.91000000e-01 -4.24463629e-07  7.91000000e-01  7.91000000e-01 
- 7.92000000e-01 -4.31614946e-07  7.92000000e-01  7.92000000e-01 
- 7.93000000e-01 -4.38878017e-07  7.93000000e-01  7.93000000e-01 
- 7.94000000e-01 -4.46254218e-07  7.94000000e-01  7.94000000e-01 
- 7.95000000e-01 -4.53744916e-07  7.95000000e-01  7.95000000e-01 
- 7.96000000e-01 -4.61351506e-07  7.96000000e-01  7.96000000e-01 
- 7.97000000e-01 -4.69075369e-07  7.97000000e-01  7.97000000e-01 
- 7.98000000e-01 -4.76917893e-07  7.98000000e-01  7.98000000e-01 
- 7.99000000e-01 -4.84880471e-07  7.99000000e-01  7.99000000e-01 
- 8.00000000e-01 -4.92964482e-07  8.00000000e-01  8.00000000e-01 

diff --git a/xschem/top_pll_v1.sch b/xschem/top_pll_v1.sch
new file mode 100644
index 0000000..80a4648
--- /dev/null
+++ b/xschem/top_pll_v1.sch

@@ -0,0 +1,149 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div_by_5}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div_by_5}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -190 150 -190 180 { lab=vss}
+N -150 150 -150 180 { lab=vdd}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div_by_5}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_pad}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N -470 260 -250 260 { lab=out_div_by_5}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -150 340 -150 380 { lab=div_5_Q1}
+N -170 340 -170 380 { lab=div_5_Q1_shift}
+N -190 340 -190 380 { lab=div_5_nQ0}
+N -210 340 -210 380 { lab=div_5_Q0}
+N -130 340 -130 380 { lab=div_5_nQ2}
+N -390 260 -390 300 { lab=out_div_by_5}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -190 150 3 1 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -150 150 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {iopin.sym} 330 -150 1 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {opin.sym} 740 -250 0 0 {name=p20 lab=out_to_pad}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -150 380 1 0 {name=p28 lab=div_5_Q1}
+C {iopin.sym} -170 380 1 0 {name=p29 lab=div_5_Q1_shift}
+C {iopin.sym} -190 380 1 0 {name=p30 lab=div_5_nQ0}
+C {iopin.sym} -210 380 1 0 {name=p31 lab=div_5_Q0}
+C {iopin.sym} -130 380 1 0 {name=p32 lab=div_5_nQ2}
+C {iopin.sym} -390 300 1 0 {name=p33 lab=out_div_by_5}
+C {PFD.sym} -770 -230 0 0 {name=x1}
+C {charge_pump.sym} -230 -230 0 0 {name=x2}
+C {pfd_cp_interface.sym} -530 -230 0 0 {name=x3}
+C {loop_filter.sym} 60 -140 0 0 {name=x4}
+C {csvco.sym} 410 -230 0 0 {name=x5}
+C {ring_osc_buffer.sym} 640 -230 0 0 {name=x6}
+C {div_by_5.sym} -170 260 0 1 {name=x7}
+C {div_by_2.sym} 160 260 0 1 {name=x8}

diff --git a/xschem/top_pll_v1.sym b/xschem/top_pll_v1.sym
new file mode 100644
index 0000000..ead0800
--- /dev/null
+++ b/xschem/top_pll_v1.sym

@@ -0,0 +1,157 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 330 0 350 0 {}
+L 4 -300 90 -300 110 {}
+L 4 -300 90 -240 90 {}
+L 4 -240 90 -240 110 {}
+L 4 -230 90 -230 110 {}
+L 4 -230 90 -150 90 {}
+L 4 -150 90 -150 110 {}
+L 4 -140 90 -140 110 {}
+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
+L 4 -50 90 -50 110 {}
+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
+L 4 40 90 40 110 {}
+L 4 20 110 50 110 {}
+L 4 50 110 170 110 {}
+L 4 170 90 170 110 {}
+L 4 50 90 170 90 {}
+L 4 50 90 50 110 {}
+L 4 170 110 300 110 {}
+L 4 180 90 180 110 {}
+L 4 180 90 300 90 {}
+L 4 300 90 300 110 {}
+L 4 300 110 330 110 {}
+L 4 -330 110 -300 110 {}
+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
+L 4 -330 -110 330 -110 {}
+L 4 330 -110 330 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 70 -320 110 {}
+L 4 -320 70 320 70 {}
+L 4 320 70 320 110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -210 -130 -210 -110 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
+L 7 290 110 290 130 {}
+L 7 160 110 160 130 {}
+L 7 210 110 210 130 {}
+L 7 250 110 250 130 {}
+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 347.5 -2.5 352.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=vco_D0 dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 327.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}

diff --git a/xschem/top_pll_v1_pex_c.sym b/xschem/top_pll_v1_pex_c.sym
new file mode 100644
index 0000000..6eda278
--- /dev/null
+++ b/xschem/top_pll_v1_pex_c.sym

@@ -0,0 +1,159 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 330 0 350 0 {}
+L 4 -300 90 -300 110 {}
+L 4 -300 90 -240 90 {}
+L 4 -240 90 -240 110 {}
+L 4 -230 90 -230 110 {}
+L 4 -230 90 -150 90 {}
+L 4 -150 90 -150 110 {}
+L 4 -140 90 -140 110 {}
+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
+L 4 -50 90 -50 110 {}
+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
+L 4 40 90 40 110 {}
+L 4 20 110 50 110 {}
+L 4 50 110 170 110 {}
+L 4 170 90 170 110 {}
+L 4 50 90 170 90 {}
+L 4 50 90 50 110 {}
+L 4 170 110 300 110 {}
+L 4 180 90 180 110 {}
+L 4 180 90 300 90 {}
+L 4 300 90 300 110 {}
+L 4 300 110 330 110 {}
+L 4 -330 110 -300 110 {}
+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
+L 4 -330 -110 330 -110 {}
+L 4 330 -110 330 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 80 -320 110 {}
+L 4 -320 70 -320 80 {}
+L 4 -320 70 310 70 {}
+L 4 310 70 320 70 {}
+L 4 320 70 320 110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -210 -130 -210 -110 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
+L 7 290 110 290 130 {}
+L 7 160 110 160 130 {}
+L 7 210 110 210 130 {}
+L 7 250 110 250 130 {}
+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 347.5 -2.5 352.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=vco_D0 dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 327.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}

diff --git a/xschem/top_pll_v1_pex_no_integration.sch b/xschem/top_pll_v1_pex_no_integration.sch
new file mode 100644
index 0000000..a792613
--- /dev/null
+++ b/xschem/top_pll_v1_pex_no_integration.sch

@@ -0,0 +1,149 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -750 -360 -750 -330 { lab=vss}
+N -890 -270 -850 -270 { lab=in_ref}
+N -850 -270 -840 -270 { lab=in_ref}
+N -890 -190 -840 -190 { lab=out_div_by_5}
+N -790 -360 -790 -330 { lab=vdd}
+N -400 -250 -310 -250 { lab=nUp}
+N -400 -210 -310 -210 { lab=Down}
+N -360 -170 -310 -170 { lab=nDown}
+N -360 -290 -310 -290 { lab=Up}
+N 410 -330 410 -300 { lab=vdd}
+N 410 -160 410 -130 { lab=vss}
+N 530 260 570 260 { lab=out_to_div}
+N 330 -190 340 -190 { lab=vco_D0}
+N 230 -230 340 -230 { lab=vco_vctrl}
+N 480 -230 520 -230 { lab=vco_out}
+N -460 -170 -360 -170 { lab=nDown}
+N -460 -210 -400 -210 { lab=Down}
+N -460 -250 -400 -250 { lab=nUp}
+N -460 -290 -360 -290 { lab=Up}
+N -700 -190 -600 -190 { lab=pfd_QB}
+N -530 -360 -530 -330 { lab=vdd}
+N -530 -130 -530 -100 { lab=vss}
+N -890 -190 -890 260 { lab=out_div_by_5}
+N 330 -190 330 -150 { lab=vco_D0}
+N 180 150 180 180 { lab=vdd}
+N -210 -360 -210 -330 { lab=vdd}
+N -180 -360 -180 -330 { lab=vss}
+N -50 -230 -30 -230 { lab=vco_vctrl}
+N -270 -370 -270 -330 { lab=iref_cp}
+N 10 280 90 280 { lab=n_out_by_2}
+N 10 240 90 240 { lab=out_by_2}
+N -60 240 10 240 { lab=out_by_2}
+N -60 280 10 280 { lab=n_out_by_2}
+N -190 150 -190 180 { lab=vss}
+N -150 150 -150 180 { lab=vdd}
+N -90 240 -60 240 { lab=out_by_2}
+N -90 280 -60 280 { lab=n_out_by_2}
+N -890 260 -470 260 { lab=out_div_by_5}
+N 60 -70 60 -40 { lab=vss}
+N 30 -230 90 -230 { lab=vco_vctrl}
+N 90 -230 230 -230 { lab=vco_vctrl}
+N 60 -230 60 -210 { lab=vco_vctrl}
+N 120 -140 160 -140 { lab=lf_vc}
+N 520 -230 580 -230 { lab=vco_out}
+N 620 -330 620 -300 { lab=vdd}
+N 660 -330 660 -300 { lab=vss}
+N 700 -250 740 -250 { lab=out_to_pad}
+N 700 -210 750 -210 { lab=out_to_div}
+N 870 -210 870 260 { lab=out_to_div}
+N 570 260 750 260 { lab=out_to_div}
+N 640 -160 640 -120 { lab=out_first_buffer}
+N 750 -210 870 -210 { lab=out_to_div}
+N 750 260 870 260 { lab=out_to_div}
+N 230 260 530 260 { lab=out_to_div}
+N -470 260 -250 260 { lab=out_div_by_5}
+N 140 150 140 180 { lab=vss}
+N -640 -300 -640 -270 { lab=pfd_QA}
+N -640 -190 -640 -160 { lab=pfd_QB}
+N -450 -310 -440 -310 { lab=Up}
+N -450 -310 -450 -290 { lab=Up}
+N -450 -270 -440 -270 { lab=nUp}
+N -450 -270 -450 -250 { lab=nUp}
+N -450 -230 -440 -230 { lab=Down}
+N -450 -230 -450 -210 { lab=Down}
+N -450 -190 -440 -190 { lab=nDown}
+N -450 -190 -450 -170 { lab=nDown}
+N -770 -130 -770 -100 { lab=pfd_reset}
+N -700 -270 -600 -270 { lab=pfd_QA}
+N -260 -130 -260 -100 { lab=cp_nswitch}
+N -230 -130 -230 -100 { lab=cp_pswitch}
+N -200 -130 -200 -100 { lab=cp_biasp}
+N -140 -230 -50 -230 { lab=vco_vctrl}
+N -30 -230 30 -230 { lab=vco_vctrl}
+N 160 -320 160 -240 { lab=vco_vctrl}
+N 160 -240 160 -230 { lab=vco_vctrl}
+N 520 -320 520 -230 { lab=vco_out}
+N 370 220 370 260 { lab=out_to_div}
+N 0 200 0 240 { lab=out_by_2}
+N 0 280 0 320 { lab=n_out_by_2}
+N 190 340 190 380 { lab=out_div_2}
+N 170 340 170 380 { lab=n_out_div_2}
+N 150 340 150 380 { lab=out_buffer_div_2}
+N 130 340 130 380 { lab=n_out_buffer_div_2}
+N -150 340 -150 380 { lab=div_5_Q1}
+N -170 340 -170 380 { lab=div_5_Q1_shift}
+N -190 340 -190 380 { lab=div_5_nQ0}
+N -210 340 -210 380 { lab=div_5_Q0}
+N -130 340 -130 380 { lab=div_5_nQ2}
+N -390 260 -390 300 { lab=out_div_by_5}
+C {lab_pin.sym} 410 -330 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 -130 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -530 -360 1 0 {name=l7 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -530 -100 3 0 {name=l9 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 180 150 1 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -210 -360 1 0 {name=l27 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -180 -360 1 0 {name=l28 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -190 150 3 1 {name=l22 sig_type=std_logic lab=vss}
+C {lab_pin.sym} -150 150 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 60 -40 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 620 -330 1 0 {name=l16 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 660 -330 1 0 {name=l40 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 150 1 0 {name=l12 sig_type=std_logic lab=vss}
+C {iopin.sym} -790 -360 3 0 {name=p1 lab=vdd}
+C {iopin.sym} -750 -360 3 0 {name=p2 lab=vss}
+C {ipin.sym} -890 -270 0 0 {name=p3 lab=in_ref}
+C {iopin.sym} -640 -300 3 0 {name=p4 lab=pfd_QA}
+C {iopin.sym} -640 -160 1 0 {name=p5 lab=pfd_QB}
+C {iopin.sym} -440 -310 0 0 {name=p6 lab=Up}
+C {iopin.sym} -440 -270 0 0 {name=p7 lab=nUp}
+C {iopin.sym} -440 -230 0 0 {name=p8 lab=Down}
+C {iopin.sym} -440 -190 0 0 {name=p9 lab=nDown}
+C {iopin.sym} -770 -100 1 0 {name=p10 lab=pfd_reset}
+C {iopin.sym} -260 -100 1 0 {name=p11 lab=cp_nswitch}
+C {iopin.sym} -230 -100 1 0 {name=p12 lab=cp_pswitch}
+C {iopin.sym} -200 -100 1 0 {name=p13 lab=cp_biasp}
+C {ipin.sym} -270 -370 1 0 {name=p14 lab=iref_cp}
+C {iopin.sym} 160 -140 0 0 {name=p15 lab=lf_vc}
+C {iopin.sym} 330 -150 1 0 {name=p16 lab=vco_D0}
+C {iopin.sym} 160 -320 3 0 {name=p17 lab=vco_vctrl}
+C {iopin.sym} 520 -320 3 0 {name=p18 lab=vco_out}
+C {iopin.sym} 640 -120 1 0 {name=p19 lab=out_first_buffer}
+C {opin.sym} 740 -250 0 0 {name=p20 lab=out_to_pad}
+C {iopin.sym} 370 220 3 0 {name=p21 lab=out_to_div}
+C {iopin.sym} 0 200 3 0 {name=p22 lab=out_by_2}
+C {iopin.sym} 0 320 1 0 {name=p23 lab=n_out_by_2}
+C {iopin.sym} 190 380 1 0 {name=p24 lab=out_div_2}
+C {iopin.sym} 170 380 1 0 {name=p25 lab=n_out_div_2}
+C {iopin.sym} 150 380 1 0 {name=p26 lab=out_buffer_div_2}
+C {iopin.sym} 130 380 1 0 {name=p27 lab=n_out_buffer_div_2}
+C {iopin.sym} -150 380 1 0 {name=p28 lab=div_5_Q1}
+C {iopin.sym} -170 380 1 0 {name=p29 lab=div_5_Q1_shift}
+C {iopin.sym} -190 380 1 0 {name=p30 lab=div_5_nQ0}
+C {iopin.sym} -210 380 1 0 {name=p31 lab=div_5_Q0}
+C {iopin.sym} -130 380 1 0 {name=p32 lab=div_5_nQ2}
+C {iopin.sym} -390 300 1 0 {name=p33 lab=out_div_by_5}
+C {PFD_pex_c.sym} -770 -230 0 0 {name=x1}
+C {charge_pump_pex_c.sym} -230 -230 0 0 {name=x2}
+C {csvco_pex_c.sym} 410 -230 0 0 {name=x3}
+C {div_by_5_pex_c.sym} -170 260 0 1 {name=x5}
+C {loop_filter_pex_c.sym} 60 -140 0 0 {name=x6}
+C {pfd_cp_interface_pex_c.sym} -530 -230 0 0 {name=x7}
+C {ring_osc_buffer_pex_c.sym} 640 -230 0 0 {name=x8}
+C {div_by_2_pex_c.sym} 160 260 0 1 {name=x4}

diff --git a/xschem/top_pll_v1_pex_no_integration.sym b/xschem/top_pll_v1_pex_no_integration.sym
new file mode 100644
index 0000000..ead0800
--- /dev/null
+++ b/xschem/top_pll_v1_pex_no_integration.sym

@@ -0,0 +1,157 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -240 110 20 110 {}
+L 4 -290 -130 -290 -110 {}
+L 4 -350 0 -330 0 {}
+L 4 330 0 350 0 {}
+L 4 -300 90 -300 110 {}
+L 4 -300 90 -240 90 {}
+L 4 -240 90 -240 110 {}
+L 4 -230 90 -230 110 {}
+L 4 -230 90 -150 90 {}
+L 4 -150 90 -150 110 {}
+L 4 -140 90 -140 110 {}
+L 4 -140 90 -80 90 {}
+L 4 -80 90 -80 110 {}
+L 4 -70 90 -70 110 {}
+L 4 -70 90 -50 90 {}
+L 4 -50 90 -50 110 {}
+L 4 -40 90 -40 110 {}
+L 4 -40 90 40 90 {}
+L 4 40 90 40 110 {}
+L 4 20 110 50 110 {}
+L 4 50 110 170 110 {}
+L 4 170 90 170 110 {}
+L 4 50 90 170 90 {}
+L 4 50 90 50 110 {}
+L 4 170 110 300 110 {}
+L 4 180 90 180 110 {}
+L 4 180 90 300 90 {}
+L 4 300 90 300 110 {}
+L 4 300 110 330 110 {}
+L 4 -330 110 -300 110 {}
+L 4 -300 110 -240 110 {}
+L 4 -330 -0 -330 110 {}
+L 4 -330 -110 -330 0 {}
+L 4 -330 -110 330 -110 {}
+L 4 330 -110 330 110 {}
+L 4 -240 -110 -240 -90 {}
+L 4 -240 -90 -120 -90 {}
+L 4 -120 -110 -120 -90 {}
+L 4 -320 70 -320 110 {}
+L 4 -320 70 320 70 {}
+L 4 320 70 320 110 {}
+L 7 230 -130 230 -110 {}
+L 7 170 -130 170 -110 {}
+L 7 -10 110 -10 130 {}
+L 7 -30 110 -30 130 {}
+L 7 -220 110 -220 130 {}
+L 7 -250 110 -250 130 {}
+L 7 -200 110 -200 130 {}
+L 7 -180 110 -180 130 {}
+L 7 -160 110 -160 130 {}
+L 7 -270 110 -270 130 {}
+L 7 -210 -130 -210 -110 {}
+L 7 -60 110 -60 130 {}
+L 7 10 110 10 130 {}
+L 7 -90 110 -90 130 {}
+L 7 -110 110 -110 130 {}
+L 7 -290 110 -290 130 {}
+L 7 -130 110 -130 130 {}
+L 7 140 110 140 130 {}
+L 7 30 110 30 130 {}
+L 7 290 110 290 130 {}
+L 7 160 110 160 130 {}
+L 7 210 110 210 130 {}
+L 7 250 110 250 130 {}
+L 7 230 110 230 130 {}
+L 7 100 110 100 130 {}
+L 7 120 110 120 130 {}
+L 7 190 110 190 130 {}
+L 7 80 110 80 130 {}
+L 7 270 110 270 130 {}
+L 7 60 110 60 130 {}
+B 5 -292.5 -132.5 -287.5 -127.5 {name=iref_cp dir=in }
+B 5 227.5 -132.5 232.5 -127.5 {name=vss dir=inout }
+B 5 167.5 -132.5 172.5 -127.5 {name=vdd dir=inout }
+B 5 -12.5 127.5 -7.5 132.5 {name=vco_out dir=inout }
+B 5 -32.5 127.5 -27.5 132.5 {name=vco_vctrl dir=inout }
+B 5 -222.5 127.5 -217.5 132.5 {name=Up dir=inout }
+B 5 -252.5 127.5 -247.5 132.5 {name=pfd_QA dir=inout }
+B 5 -202.5 127.5 -197.5 132.5 {name=nUp dir=inout }
+B 5 -352.5 -2.5 -347.5 2.5 {name=in_ref dir=in }
+B 5 347.5 -2.5 352.5 2.5 {name=out_to_pad dir=out }
+B 5 -182.5 127.5 -177.5 132.5 {name=Down dir=inout }
+B 5 -162.5 127.5 -157.5 132.5 {name=nDown dir=inout }
+B 5 -272.5 127.5 -267.5 132.5 {name=pfd_QB dir=inout }
+B 5 -212.5 -132.5 -207.5 -127.5 {name=vco_D0 dir=inout }
+B 5 -62.5 127.5 -57.5 132.5 {name=lf_vc dir=inout }
+B 5 7.5 127.5 12.5 132.5 {name=out_first_buffer dir=inout }
+B 5 -92.5 127.5 -87.5 132.5 {name=cp_biasp dir=inout }
+B 5 -112.5 127.5 -107.5 132.5 {name=cp_pswitch dir=inout }
+B 5 -292.5 127.5 -287.5 132.5 {name=pfd_reset dir=inout }
+B 5 -132.5 127.5 -127.5 132.5 {name=cp_nswitch dir=inout }
+B 5 137.5 127.5 142.5 132.5 {name=out_by_2 dir=inout }
+B 5 27.5 127.5 32.5 132.5 {name=out_to_div dir=inout }
+B 5 287.5 127.5 292.5 132.5 {name=out_div_by_5 dir=inout }
+B 5 157.5 127.5 162.5 132.5 {name=n_out_by_2 dir=inout }
+B 5 207.5 127.5 212.5 132.5 {name=div_5_nQ0 dir=inout }
+B 5 247.5 127.5 252.5 132.5 {name=div_5_Q1_shift dir=inout }
+B 5 227.5 127.5 232.5 132.5 {name=div_5_Q1 dir=inout }
+B 5 97.5 127.5 102.5 132.5 {name=n_out_buffer_div_2 dir=inout }
+B 5 117.5 127.5 122.5 132.5 {name=out_buffer_div_2 dir=inout }
+B 5 187.5 127.5 192.5 132.5 {name=div_5_Q0 dir=inout }
+B 5 77.5 127.5 82.5 132.5 {name=n_out_div_2 dir=inout }
+B 5 267.5 127.5 272.5 132.5 {name=div_5_nQ2 dir=inout }
+B 5 57.5 127.5 62.5 132.5 {name=out_div_2 dir=inout }
+T {@symname} -30 -10 0 0 0.3 0.3 {}
+T {@name} -15 -92 0 0 0.2 0.2 {}
+T {iref_cp} -296 -145 1 0 0.2 0.2 {}
+T {vss} 213.5 -130 3 1 0.2 0.2 {}
+T {vdd} 153.5 -132.5 3 1 0.2 0.2 {}
+T {vco_out} -22.5 112.5 3 1 0.2 0.2 {}
+T {vco_vctrl} -32.5 160 1 1 0.2 0.2 {}
+T {Up} -235 132.5 3 0 0.2 0.2 {}
+T {pfd_QA} -252.5 150 1 1 0.2 0.2 {}
+T {nUp} -215 132.5 3 0 0.2 0.2 {}
+T {in_ref} -325 -12.5 0 0 0.2 0.2 {}
+T {out_to_pad} 327.5 -12.5 0 1 0.2 0.2 {}
+T {Down} -195 140 3 0 0.2 0.2 {}
+T {nDown} -175 147.5 3 0 0.2 0.2 {}
+T {pfd_QB} -272.5 150 1 1 0.2 0.2 {}
+T {vco_D0} -227.5 -150 3 1 0.2 0.2 {}
+T {lf_vc} -62.5 135 1 1 0.2 0.2 {}
+T {out_first_buffer} 7.5 190 1 1 0.2 0.2 {}
+T {cp_biasp} -92.5 157.5 1 1 0.2 0.2 {}
+T {cp_pswitch} -112.5 170 1 1 0.2 0.2 {}
+T {pfd_reset} -292.5 160 1 1 0.2 0.2 {}
+T {cp_nswitch} -132.5 170 1 1 0.2 0.2 {}
+T {out_by_2} 137.5 160 1 1 0.2 0.2 {}
+T {out_to_div} 27.5 165 1 1 0.2 0.2 {}
+T {out_div_by_5} 287.5 180 1 1 0.2 0.2 {}
+T {n_out_by_2} 147.5 112.5 3 1 0.2 0.2 {}
+T {div_5_nQ0} 207.5 167.5 1 1 0.2 0.2 {}
+T {div_5_Q1_shift} 247.5 190 1 1 0.2 0.2 {}
+T {div_5_Q1} 227.5 160 1 1 0.2 0.2 {}
+T {n_out_buffer_div_2} 97.5 210 1 1 0.2 0.2 {}
+T {out_buffer_div_2} 117.5 197.5 1 1 0.2 0.2 {}
+T {div_5_Q0} 187.5 160 1 1 0.2 0.2 {}
+T {n_out_div_2} 77.5 175 1 1 0.2 0.2 {}
+T {div_5_nQ2} 267.5 167.5 1 1 0.2 0.2 {}
+T {out_div_2} 57.5 162.5 1 1 0.2 0.2 {}
+T {PFD} -280 105 2 1 0.2 0.2 {}
+T {Interface} -210 105 2 1 0.2 0.2 {}
+T {CP} -120 105 2 1 0.2 0.2 {}
+T {LF} -65 105 2 1 0.2 0.2 {}
+T {VCO} -10 105 2 1 0.2 0.2 {}
+T {DIV_BY_2} 87.5 105 2 1 0.2 0.2 {}
+T {DIV_BY_5} 212.5 105 2 1 0.2 0.2 {}
+T {Debug} -17.5 85 2 1 0.2 0.2 {}
+T {Config} -197.5 -92.5 2 1 0.2 0.2 {}

diff --git a/xschem/trans_gate.sch b/xschem/trans_gate.sch
new file mode 100644
index 0000000..138ab52
--- /dev/null
+++ b/xschem/trans_gate.sch

@@ -0,0 +1,62 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 380 -100 380 -70 { lab=vss}
+N 380 70 380 100 { lab=vdd}
+N 310 -100 350 -100 { lab=in}
+N 310 -100 310 -40 { lab=in}
+N 280 -40 310 -40 { lab=in}
+N 280 -40 280 0 { lab=in}
+N 310 100 350 100 { lab=in}
+N 310 40 310 100 { lab=in}
+N 280 40 310 40 { lab=in}
+N 280 0 280 40 { lab=in}
+N 410 100 450 100 { lab=out}
+N 450 40 450 100 { lab=out}
+N 450 40 480 40 { lab=out}
+N 480 0 480 40 { lab=out}
+N 410 -100 450 -100 { lab=out}
+N 450 -100 450 -40 { lab=out}
+N 450 -40 480 -40 { lab=out}
+N 480 -40 480 0 { lab=out}
+N 480 -0 540 0 { lab=out}
+N 220 -0 280 0 { lab=in}
+N 380 140 380 170 { lab=vss}
+N 380 -170 380 -140 { lab=vdd}
+C {sky130_fd_pr/pfet_01v8.sym} 380 120 3 0 {name=M2
+L=0.15
+W=1.25
+nf=1
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} 380 170 1 0 {name=p1 lab=vss}
+C {ipin.sym} 220 0 0 0 {name=p2 lab=in}
+C {opin.sym} 540 0 0 0 {name=p3 lab=out}
+C {sky130_fd_pr/nfet_01v8.sym} 380 -120 1 0 {name=M1
+L=0.15
+W=1.25
+nf=1 
+mult=3
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 380 -70 3 0 {name=l1 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 70 1 0 {name=l2 sig_type=std_logic lab=vdd}
+C {iopin.sym} 380 -170 3 0 {name=p4 lab=vdd}

diff --git a/xschem/trans_gate.sym b/xschem/trans_gate.sym
new file mode 100644
index 0000000..54b0866
--- /dev/null
+++ b/xschem/trans_gate.sym

@@ -0,0 +1,49 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 70 0 90 0 {}
+L 4 -90 0 -70 0 {}
+L 4 -20 -50 20 -50 {}
+L 4 -20 -40 20 -40 {}
+L 4 20 -40 20 -20 {}
+L 4 20 -20 40 -20 {}
+L 4 40 -20 40 0 {}
+L 4 40 0 60 0 {}
+L 4 -20 -40 -20 -20 {}
+L 4 -40 -20 -20 -20 {}
+L 4 -40 -20 -40 0 {}
+L 4 -60 0 -40 0 {}
+L 4 -20 50 20 50 {}
+L 4 -20 40 20 40 {}
+L 4 -20 20 -20 40 {}
+L 4 -40 20 -20 20 {}
+L 4 -40 0 -40 20 {}
+L 4 20 20 20 40 {}
+L 4 20 20 40 20 {}
+L 4 40 0 40 20 {}
+L 4 0 -60 -0 -50 {}
+L 4 0 60 0 70 {}
+L 4 -70 80 -0 80 {}
+L 4 -70 -70 -70 80 {}
+L 4 -70 -70 70 -70 {}
+L 4 70 -70 70 80 {}
+L 4 0 80 70 80 {}
+L 7 0 -90 0 -70 {}
+L 7 0 80 0 100 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd dir=inout }
+B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
+B 5 -92.5 -2.5 -87.5 2.5 {name=in dir=in }
+B 5 -2.5 97.5 2.5 102.5 {name=vss dir=inout }
+A 4 0 55.5 5.024937810560445 354.2894068625004 360 {}
+T {@symname} 14 90 0 0 0.3 0.3 {}
+T {@name} -23 -6 0 0 0.2 0.2 {}
+T {vdd} -14 -95 3 1 0.2 0.2 {}
+T {out} 87 -13 0 1 0.2 0.2 {}
+T {in} -86 -14 0 0 0.2 0.2 {}
+T {vss} -2 104 1 1 0.2 0.2 {}

diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index e0da610..0edf5ec 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch

@@ -1,4 +1,4 @@
-v {xschem version=2.9.9 file_version=1.2 }
+v{xschem version=2.9.9 file_version=1.2 }
 G {}
 K {}
 V {}
@@ -24,47 +24,47 @@
 N 4010 -280 4130 -280 { lab=io_out[12]}
 C {example_por.sym} 3860 -310 0 0 {name=x1}
 C {example_por.sym} 3860 20 0 0 {name=x2}
-C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
-C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
-C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
-C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
-C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
-C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
-C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
-C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
-C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
-C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
-C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
-C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
-C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
-C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
-C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
-C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
-C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
-C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
-C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
-C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
-C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
-C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
-C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
-C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
-C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
-C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
-C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
-C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
-C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
-C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
-C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
-C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
-C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
-C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
-C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
-C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
-C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
-C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
-C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
-C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
-C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
-C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}
+C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1}
+C {lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1}
+C {lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1}
+C {lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]}
+C {lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1}
+C {lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]}
+C {lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]}
+C {lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]}
+C {lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]}
+C {lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]}
+C {lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]}

diff --git a/xschem/xschemrc b/xschem/xschemrc
index 98fead5..1401099 100644
--- a/xschem/xschemrc
+++ b/xschem/xschemrc

@@ -14,26 +14,23 @@
 ###########################################################################
 #### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
 ###########################################################################
-#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
-# /home/schippes/.xschem/xschem_library
-# /home/schippes/share/xschem/xschem_library/devices
-# /home/schippes/share/doc/xschem/examples
-# /home/schippes/share/doc/xschem/ngspice
-# /home/schippes/share/doc/xschem/logic
-# /home/schippes/share/doc/xschem/xschem_simulator
-# /home/schippes/share/doc/xschem/binto7seg
-# /home/schippes/share/doc/xschem/pcb
-# /home/schippes/share/doc/xschem/rom8k
-
-#### Flush any previous definition
 set XSCHEM_LIBRARY_PATH {}
-#### include devices/*.sym
-append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
-#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+### GENERAL PURPOSE LIB
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
+### EXAMPLES LIB
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/examples
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/ngspice
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/logic
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/xschem_simulator
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/binto7seg
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/pcb
+append XSCHEM_LIBRARY_PATH :/usr/local/share/doc/xschem/rom8k
+### SKY130 PDK SYMBOLS LIB
+append XSCHEM_LIBRARY_PATH :~/skywater/xschem_sky130
+### USERs CELLS LIB
+append XSCHEM_LIBRARY_PATH :~/caravel_analog_fulgor/xschem
+### CURRENT CELL LIB
 append XSCHEM_LIBRARY_PATH :$env(PWD)
-append XSCHEM_LIBRARY_PATH :/usr/share/pdk/sky130A/libs.tech/xschem
-#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
-append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library 
 
 ###########################################################################
 #### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
@@ -47,6 +44,7 @@
 set dircolor(xschem_sky130$) blue
 set dircolor(xschem_library$) red
 set dircolor(devices$) red
+set dircolor(sky130-mpw2-fulgor) green
 
 ###########################################################################
 #### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
@@ -54,14 +52,14 @@
 #### Start without a design if no filename given on command line:
 #### To avoid absolute paths, use a path that is relative to one of the
 #### XSCHEM_LIBRARY_PATH directories. Default: empty
-set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+# set XSCHEM_START_WINDOW {sky130_tests/top.sch}
 
 ###########################################################################
 #### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
 ###########################################################################
 #### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations) 
 # set netlist_dir $env(HOME)/.xschem/simulations
-set netlist_dir .
+set netlist_dir $env(PWD)/simulations
 
 ###########################################################################
 #### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS 
@@ -237,7 +235,7 @@
 ###########################################################################
 #### set gaw address for socket connection: {host port}
 #### default: set to localhost, port 2020
-# set gaw_tcp_address {localhost 2020}
+ set gaw_tcp_address {localhost 2020}
 
 ###########################################################################
 #### XSCHEM LISTEN TO TCP PORT
@@ -258,7 +256,7 @@
 #### list of tcl files to preload.
 # lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
 lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
-lappend tcl_files /usr/share/pdk/sky130A/libs.tech/xschem/scripts/sky130_models.tcl
+lappend tcl_files ~/skywater/pdk/skywater130/sky130A/libs.tech/xschem/scripts/sky130_models.tcl
 ###########################################################################
 #### XSCHEM TOOLBAR
 ###########################################################################
@@ -269,5 +267,5 @@
 ###########################################################################
 #### SKYWATER PDK SPECIFIC VARIABLES
 ###########################################################################
-set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
-set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+set SKYWATER_MODELS ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+set SKYWATER_STDCELLS ~/skywater/skywater-pdk/libraries/sky130_fd_sc_hs/latest
commit	b038f199accb0941e47d4617a8c08d4ce7db53a2	[log] [tgz]
author	Diego Hernando <djhernando96@gmail.com>	Fri Jun 18 01:26:40 2021 -0300
committer	Diego Hernando <djhernando96@gmail.com>	Fri Jun 18 01:26:40 2021 -0300
tree	b821a1e824328df82f6d4efde5a129fee3e40f25
parent	67640ef400d8df3cfb0a49c79a3b7e14136869b5 [diff]