| v {xschem version=2.9.9 file_version=1.2 } |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| N 4410 160 4410 220 { lab=vdda1} |
| N 4470 160 4470 220 { lab=vssa1} |
| N 3990 530 3990 580 { lab=#net1} |
| N 3990 480 3990 530 { lab=#net1} |
| N 3970 530 3970 580 { lab=#net2} |
| N 3970 480 3970 530 { lab=#net2} |
| N 3950 530 3950 580 { lab=#net3} |
| N 3950 480 3950 530 { lab=#net3} |
| N 4060 530 4060 580 { lab=#net4} |
| N 4060 480 4060 530 { lab=#net4} |
| N 4040 530 4040 580 { lab=#net5} |
| N 4040 480 4040 530 { lab=#net5} |
| N 4020 530 4020 580 { lab=#net6} |
| N 4020 480 4020 530 { lab=#net6} |
| N 4080 530 4080 580 { lab=#net7} |
| N 4080 480 4080 530 { lab=#net7} |
| N 4150 530 4150 580 { lab=#net8} |
| N 4150 480 4150 530 { lab=#net8} |
| N 4130 530 4130 580 { lab=#net9} |
| N 4130 480 4130 530 { lab=#net9} |
| N 4110 530 4110 580 { lab=#net10} |
| N 4110 480 4110 530 { lab=#net10} |
| N 4180 530 4180 580 { lab=#net11} |
| N 4180 480 4180 530 { lab=#net11} |
| N 4210 530 4210 580 { lab=#net12} |
| N 4210 480 4210 530 { lab=#net12} |
| N 4230 530 4230 580 { lab=#net13} |
| N 4230 480 4230 530 { lab=#net13} |
| N 4250 530 4250 580 { lab=#net14} |
| N 4250 480 4250 530 { lab=#net14} |
| N 4270 530 4270 580 { lab=#net15} |
| N 4270 480 4270 530 { lab=#net15} |
| N 4300 530 4300 580 { lab=#net16} |
| N 4300 480 4300 530 { lab=#net16} |
| N 4320 530 4320 580 { lab=#net17} |
| N 4320 480 4320 530 { lab=#net17} |
| N 4340 530 4340 580 { lab=#net18} |
| N 4340 480 4340 530 { lab=#net18} |
| N 4360 530 4360 580 { lab=#net19} |
| N 4360 480 4360 530 { lab=#net19} |
| N 4380 530 4380 580 { lab=#net20} |
| N 4380 480 4380 530 { lab=#net20} |
| N 4400 530 4400 580 { lab=#net21} |
| N 4400 480 4400 530 { lab=#net21} |
| N 4430 530 4430 580 { lab=#net22} |
| N 4430 480 4430 530 { lab=#net22} |
| N 4450 530 4450 580 { lab=#net23} |
| N 4450 480 4450 530 { lab=#net23} |
| N 4470 530 4470 580 { lab=#net24} |
| N 4470 480 4470 530 { lab=#net24} |
| N 4490 530 4490 580 { lab=#net25} |
| N 4490 480 4490 530 { lab=#net25} |
| N 4510 530 4510 580 { lab=#net26} |
| N 4510 480 4510 530 { lab=#net26} |
| N 4530 530 4530 580 { lab=#net27} |
| N 4530 480 4530 530 { lab=#net27} |
| N 4580 530 4580 580 { lab=#net28} |
| N 4580 480 4580 530 { lab=#net28} |
| N 4700 350 4750 350 { lab=io_analog[9]} |
| N 4650 350 4700 350 { lab=io_analog[9]} |
| N 3820 350 3890 350 { lab=io_analog[10]} |
| N 3950 150 3950 220 { lab=iref_cp2} |
| N 4030 150 4030 220 { lab=gpio_noesd[7]} |
| N 3890 -430 3890 -370 { lab=vdda1} |
| N 3950 -290 3990 -290 { lab=iref_cp2} |
| N 3780 350 3820 350 { lab=io_analog[10]} |
| N 3890 -110 3890 -50 { lab=io_analog[5]} |
| N 4000 -270 4050 -270 { lab=#net29} |
| N 3950 -270 4000 -270 { lab=#net29} |
| N 4000 -250 4050 -250 { lab=#net30} |
| N 3950 -250 4000 -250 { lab=#net30} |
| N 4000 -230 4050 -230 { lab=#net31} |
| N 3950 -230 4000 -230 { lab=#net31} |
| N 4000 -210 4050 -210 { lab=#net32} |
| N 3950 -210 4000 -210 { lab=#net32} |
| N 4000 -190 4050 -190 { lab=#net33} |
| N 3950 -190 4000 -190 { lab=#net33} |
| N 4000 -170 4050 -170 { lab=#net34} |
| N 3950 -170 4000 -170 { lab=#net34} |
| N 4000 -150 4050 -150 { lab=#net35} |
| N 3950 -150 4000 -150 { lab=#net35} |
| N 5660 160 5660 220 { lab=vdda1} |
| N 5720 160 5720 220 { lab=vssa1} |
| N 5240 530 5240 580 { lab=#net36} |
| N 5240 480 5240 530 { lab=#net36} |
| N 5220 530 5220 580 { lab=#net37} |
| N 5220 480 5220 530 { lab=#net37} |
| N 5200 530 5200 580 { lab=#net38} |
| N 5200 480 5200 530 { lab=#net38} |
| N 5310 530 5310 580 { lab=#net39} |
| N 5310 480 5310 530 { lab=#net39} |
| N 5290 530 5290 580 { lab=#net40} |
| N 5290 480 5290 530 { lab=#net40} |
| N 5270 530 5270 580 { lab=#net41} |
| N 5270 480 5270 530 { lab=#net41} |
| N 5330 530 5330 580 { lab=#net42} |
| N 5330 480 5330 530 { lab=#net42} |
| N 5400 530 5400 580 { lab=#net43} |
| N 5400 480 5400 530 { lab=#net43} |
| N 5380 530 5380 580 { lab=#net44} |
| N 5380 480 5380 530 { lab=#net44} |
| N 5360 530 5360 580 { lab=#net45} |
| N 5360 480 5360 530 { lab=#net45} |
| N 5430 530 5430 580 { lab=#net46} |
| N 5430 480 5430 530 { lab=#net46} |
| N 5460 530 5460 580 { lab=#net47} |
| N 5460 480 5460 530 { lab=#net47} |
| N 5480 530 5480 580 { lab=#net48} |
| N 5480 480 5480 530 { lab=#net48} |
| N 5500 530 5500 580 { lab=#net49} |
| N 5500 480 5500 530 { lab=#net49} |
| N 5520 530 5520 580 { lab=#net50} |
| N 5520 480 5520 530 { lab=#net50} |
| N 5550 530 5550 580 { lab=#net51} |
| N 5550 480 5550 530 { lab=#net51} |
| N 5570 530 5570 580 { lab=#net52} |
| N 5570 480 5570 530 { lab=#net52} |
| N 5590 530 5590 580 { lab=#net53} |
| N 5590 480 5590 530 { lab=#net53} |
| N 5610 530 5610 580 { lab=#net54} |
| N 5610 480 5610 530 { lab=#net54} |
| N 5630 530 5630 580 { lab=#net55} |
| N 5630 480 5630 530 { lab=#net55} |
| N 5650 530 5650 580 { lab=#net56} |
| N 5650 480 5650 530 { lab=#net56} |
| N 5680 530 5680 580 { lab=#net57} |
| N 5680 480 5680 530 { lab=#net57} |
| N 5700 530 5700 580 { lab=#net58} |
| N 5700 480 5700 530 { lab=#net58} |
| N 5720 530 5720 580 { lab=#net59} |
| N 5720 480 5720 530 { lab=#net59} |
| N 5740 530 5740 580 { lab=#net60} |
| N 5740 480 5740 530 { lab=#net60} |
| N 5760 530 5760 580 { lab=#net61} |
| N 5760 480 5760 530 { lab=#net61} |
| N 5780 530 5780 580 { lab=#net62} |
| N 5780 480 5780 530 { lab=#net62} |
| N 5830 530 5830 580 { lab=#net63} |
| N 5830 480 5830 530 { lab=#net63} |
| N 5950 350 6000 350 { lab=io_analog[8]} |
| N 5900 350 5950 350 { lab=io_analog[8]} |
| N 5070 350 5140 350 { lab=io_analog[10]} |
| N 5200 150 5200 220 { lab=iref_cp1} |
| N 5280 150 5280 220 { lab=gpio_noesd[7]} |
| N 5030 350 5070 350 { lab=io_analog[10]} |
| N 3950 -310 3990 -310 { lab=iref_cp1} |
| N 5340 150 5340 220 { lab=gpio_noesd[8]} |
| N 6880 160 6880 220 { lab=vdda1} |
| N 6940 160 6940 220 { lab=vssa1} |
| N 6460 530 6460 580 { lab=#net64} |
| N 6460 480 6460 530 { lab=#net64} |
| N 6440 530 6440 580 { lab=#net65} |
| N 6440 480 6440 530 { lab=#net65} |
| N 6420 530 6420 580 { lab=#net66} |
| N 6420 480 6420 530 { lab=#net66} |
| N 6530 530 6530 580 { lab=#net67} |
| N 6530 480 6530 530 { lab=#net67} |
| N 6510 530 6510 580 { lab=#net68} |
| N 6510 480 6510 530 { lab=#net68} |
| N 6490 530 6490 580 { lab=#net69} |
| N 6490 480 6490 530 { lab=#net69} |
| N 6550 530 6550 580 { lab=#net70} |
| N 6550 480 6550 530 { lab=#net70} |
| N 6620 530 6620 580 { lab=#net71} |
| N 6620 480 6620 530 { lab=#net71} |
| N 6600 530 6600 580 { lab=#net72} |
| N 6600 480 6600 530 { lab=#net72} |
| N 6580 530 6580 580 { lab=#net73} |
| N 6580 480 6580 530 { lab=#net73} |
| N 6650 530 6650 580 { lab=#net74} |
| N 6650 480 6650 530 { lab=#net74} |
| N 6680 530 6680 580 { lab=#net75} |
| N 6680 480 6680 530 { lab=#net75} |
| N 6700 530 6700 580 { lab=#net76} |
| N 6700 480 6700 530 { lab=#net76} |
| N 6720 530 6720 580 { lab=#net77} |
| N 6720 480 6720 530 { lab=#net77} |
| N 6740 530 6740 580 { lab=#net78} |
| N 6740 480 6740 530 { lab=#net78} |
| N 6770 530 6770 580 { lab=#net79} |
| N 6770 480 6770 530 { lab=#net79} |
| N 6790 530 6790 580 { lab=#net80} |
| N 6790 480 6790 530 { lab=#net80} |
| N 6810 530 6810 580 { lab=#net81} |
| N 6810 480 6810 530 { lab=#net81} |
| N 6830 530 6830 580 { lab=#net82} |
| N 6830 480 6830 530 { lab=#net82} |
| N 6850 530 6850 580 { lab=#net83} |
| N 6850 480 6850 530 { lab=#net83} |
| N 6870 530 6870 580 { lab=#net84} |
| N 6870 480 6870 530 { lab=#net84} |
| N 6900 530 6900 580 { lab=#net85} |
| N 6900 480 6900 530 { lab=#net85} |
| N 6920 530 6920 580 { lab=#net86} |
| N 6920 480 6920 530 { lab=#net86} |
| N 6940 530 6940 580 { lab=#net87} |
| N 6940 480 6940 530 { lab=#net87} |
| N 6960 530 6960 580 { lab=#net88} |
| N 6960 480 6960 530 { lab=#net88} |
| N 6980 530 6980 580 { lab=#net89} |
| N 6980 480 6980 530 { lab=#net89} |
| N 7000 530 7000 580 { lab=#net90} |
| N 7000 480 7000 530 { lab=#net90} |
| N 7050 530 7050 580 { lab=#net91} |
| N 7050 480 7050 530 { lab=#net91} |
| N 7170 350 7220 350 { lab=io_analog[7]} |
| N 7120 350 7170 350 { lab=io_analog[7]} |
| N 6290 350 6360 350 { lab=io_analog[10]} |
| N 6420 150 6420 220 { lab=iref_cp0} |
| N 6500 150 6500 220 { lab=gpio_noesd[7]} |
| N 6250 350 6290 350 { lab=io_analog[10]} |
| N 3950 -330 3990 -330 { lab=iref_cp0} |
| N 4540 -360 4540 -300 { lab=vdda1} |
| N 4540 -240 4540 -180 { lab=vssa1} |
| N 4680 -360 4680 -300 { lab=vdda1} |
| N 4680 -240 4680 -180 { lab=vssa1} |
| N 4820 -360 4820 -300 { lab=vdda1} |
| N 4820 -240 4820 -180 { lab=vssa1} |
| N 5050 -360 5050 -300 { lab=vdda1} |
| N 5050 -240 5050 -180 { lab=vssa1} |
| N 5190 -360 5190 -300 { lab=vdda1} |
| N 5190 -240 5190 -180 { lab=vssa1} |
| N 5330 -360 5330 -300 { lab=vdda1} |
| N 5330 -240 5330 -180 { lab=vssa1} |
| N 5470 -360 5470 -300 { lab=vdda1} |
| N 5470 -240 5470 -180 { lab=vssa1} |
| N 5600 -360 5600 -300 { lab=vdda1} |
| N 5600 -240 5600 -180 { lab=vssa1} |
| N 5750 -360 5750 -300 { lab=vdda1} |
| N 5750 -240 5750 -180 { lab=vssa1} |
| C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1} |
| C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2} |
| C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1} |
| C {iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2} |
| C {iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1} |
| C {iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2} |
| C {iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1} |
| C {iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2} |
| C {ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i} |
| C {ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i} |
| C {ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i} |
| C {ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i} |
| C {ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i} |
| C {ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]} |
| C {ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]} |
| C {ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]} |
| C {opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o} |
| C {opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]} |
| C {ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]} |
| C {opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]} |
| C {ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]} |
| C {ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]} |
| C {ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2} |
| C {opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]} |
| C {opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]} |
| C {iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]} |
| C {iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]} |
| C {iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]} |
| C {iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]} |
| C {iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]} |
| C {opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]} |
| C {ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]} |
| C {top_pll_v1.sym} 4240 350 0 0 {name=x1} |
| C {lab_pin.sym} 4410 160 1 0 {name=l13 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 4470 160 1 0 {name=l14 sig_type=std_logic lab=vssa1} |
| C {noconn.sym} 3990 580 3 0 {name=l15} |
| C {noconn.sym} 3970 580 3 0 {name=l6} |
| C {noconn.sym} 3950 580 3 0 {name=l16} |
| C {noconn.sym} 4060 580 3 0 {name=l17} |
| C {noconn.sym} 4040 580 3 0 {name=l18} |
| C {noconn.sym} 4020 580 3 0 {name=l19} |
| C {noconn.sym} 4080 580 3 0 {name=l20} |
| C {noconn.sym} 4150 580 3 0 {name=l21} |
| C {noconn.sym} 4130 580 3 0 {name=l22} |
| C {noconn.sym} 4110 580 3 0 {name=l23} |
| C {noconn.sym} 4180 580 3 0 {name=l24} |
| C {noconn.sym} 4210 580 3 0 {name=l25} |
| C {noconn.sym} 4230 580 3 0 {name=l26} |
| C {noconn.sym} 4250 580 3 0 {name=l27} |
| C {noconn.sym} 4270 580 3 0 {name=l28} |
| C {noconn.sym} 4300 580 3 0 {name=l29} |
| C {noconn.sym} 4320 580 3 0 {name=l30} |
| C {noconn.sym} 4340 580 3 0 {name=l31} |
| C {noconn.sym} 4360 580 3 0 {name=l32} |
| C {noconn.sym} 4380 580 3 0 {name=l33} |
| C {noconn.sym} 4400 580 3 0 {name=l34} |
| C {noconn.sym} 4430 580 3 0 {name=l35} |
| C {noconn.sym} 4450 580 3 0 {name=l36} |
| C {noconn.sym} 4470 580 3 0 {name=l37} |
| C {noconn.sym} 4490 580 3 0 {name=l38} |
| C {noconn.sym} 4510 580 3 0 {name=l39} |
| C {noconn.sym} 4530 580 3 0 {name=l40} |
| C {noconn.sym} 4580 580 3 0 {name=l41} |
| C {bias.sym} 3890 -240 0 0 {name=x2} |
| C {lab_pin.sym} 3890 -430 1 0 {name=l42 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 3990 -290 2 0 {name=l43 sig_type=std_logic lab=iref_cp2} |
| C {lab_pin.sym} 3950 150 1 0 {name=l44 sig_type=std_logic lab=iref_cp2} |
| C {noconn.sym} 4050 -270 2 0 {name=l48} |
| C {noconn.sym} 4050 -250 2 0 {name=l49} |
| C {noconn.sym} 4050 -230 2 0 {name=l50} |
| C {noconn.sym} 4050 -210 2 0 {name=l51} |
| C {noconn.sym} 4050 -190 2 0 {name=l52} |
| C {noconn.sym} 4050 -170 2 0 {name=l53} |
| C {noconn.sym} 4050 -150 2 0 {name=l54} |
| C {lab_pin.sym} 3780 350 0 0 {name=l45 sig_type=std_logic lab=io_analog[10]} |
| C {lab_pin.sym} 4750 350 2 0 {name=l55 sig_type=std_logic lab=io_analog[9]} |
| C {lab_pin.sym} 4030 150 3 1 {name=l56 sig_type=std_logic lab=gpio_noesd[7]} |
| C {lab_pin.sym} 3890 -50 3 0 {name=l1 sig_type=std_logic lab=io_analog[5]} |
| C {lab_pin.sym} 5660 160 1 0 {name=l2 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5720 160 1 0 {name=l3 sig_type=std_logic lab=vssa1} |
| C {noconn.sym} 5240 580 3 0 {name=l4} |
| C {noconn.sym} 5220 580 3 0 {name=l5} |
| C {noconn.sym} 5200 580 3 0 {name=l7} |
| C {noconn.sym} 5310 580 3 0 {name=l8} |
| C {noconn.sym} 5290 580 3 0 {name=l9} |
| C {noconn.sym} 5270 580 3 0 {name=l10} |
| C {noconn.sym} 5330 580 3 0 {name=l11} |
| C {noconn.sym} 5400 580 3 0 {name=l12} |
| C {noconn.sym} 5380 580 3 0 {name=l57} |
| C {noconn.sym} 5360 580 3 0 {name=l58} |
| C {noconn.sym} 5430 580 3 0 {name=l59} |
| C {noconn.sym} 5460 580 3 0 {name=l60} |
| C {noconn.sym} 5480 580 3 0 {name=l61} |
| C {noconn.sym} 5500 580 3 0 {name=l62} |
| C {noconn.sym} 5520 580 3 0 {name=l63} |
| C {noconn.sym} 5550 580 3 0 {name=l64} |
| C {noconn.sym} 5570 580 3 0 {name=l65} |
| C {noconn.sym} 5590 580 3 0 {name=l66} |
| C {noconn.sym} 5610 580 3 0 {name=l67} |
| C {noconn.sym} 5630 580 3 0 {name=l68} |
| C {noconn.sym} 5650 580 3 0 {name=l69} |
| C {noconn.sym} 5680 580 3 0 {name=l70} |
| C {noconn.sym} 5700 580 3 0 {name=l71} |
| C {noconn.sym} 5720 580 3 0 {name=l72} |
| C {noconn.sym} 5740 580 3 0 {name=l73} |
| C {noconn.sym} 5760 580 3 0 {name=l74} |
| C {noconn.sym} 5780 580 3 0 {name=l75} |
| C {noconn.sym} 5830 580 3 0 {name=l76} |
| C {lab_pin.sym} 5200 150 1 0 {name=l77 sig_type=std_logic lab=iref_cp1} |
| C {lab_pin.sym} 5030 350 0 0 {name=l78 sig_type=std_logic lab=io_analog[10]} |
| C {lab_pin.sym} 6000 350 2 0 {name=l79 sig_type=std_logic lab=io_analog[8]} |
| C {lab_pin.sym} 5280 150 3 1 {name=l80 sig_type=std_logic lab=gpio_noesd[7]} |
| C {lab_pin.sym} 3990 -310 2 0 {name=l81 sig_type=std_logic lab=iref_cp1} |
| C {top_pll_v2.sym} 5490 350 0 0 {name=x3} |
| C {lab_pin.sym} 5340 150 3 1 {name=l47 sig_type=std_logic lab=gpio_noesd[8]} |
| C {top_pll_v1.sym} 6710 350 0 0 {name=x4} |
| C {lab_pin.sym} 6880 160 1 0 {name=l82 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 6940 160 1 0 {name=l83 sig_type=std_logic lab=vssa1} |
| C {noconn.sym} 6460 580 3 0 {name=l84} |
| C {noconn.sym} 6440 580 3 0 {name=l85} |
| C {noconn.sym} 6420 580 3 0 {name=l86} |
| C {noconn.sym} 6530 580 3 0 {name=l87} |
| C {noconn.sym} 6510 580 3 0 {name=l88} |
| C {noconn.sym} 6490 580 3 0 {name=l89} |
| C {noconn.sym} 6550 580 3 0 {name=l90} |
| C {noconn.sym} 6620 580 3 0 {name=l91} |
| C {noconn.sym} 6600 580 3 0 {name=l92} |
| C {noconn.sym} 6580 580 3 0 {name=l93} |
| C {noconn.sym} 6650 580 3 0 {name=l94} |
| C {noconn.sym} 6680 580 3 0 {name=l95} |
| C {noconn.sym} 6700 580 3 0 {name=l96} |
| C {noconn.sym} 6720 580 3 0 {name=l97} |
| C {noconn.sym} 6740 580 3 0 {name=l98} |
| C {noconn.sym} 6770 580 3 0 {name=l99} |
| C {noconn.sym} 6790 580 3 0 {name=l100} |
| C {noconn.sym} 6810 580 3 0 {name=l101} |
| C {noconn.sym} 6830 580 3 0 {name=l102} |
| C {noconn.sym} 6850 580 3 0 {name=l103} |
| C {noconn.sym} 6870 580 3 0 {name=l104} |
| C {noconn.sym} 6900 580 3 0 {name=l105} |
| C {noconn.sym} 6920 580 3 0 {name=l106} |
| C {noconn.sym} 6940 580 3 0 {name=l107} |
| C {noconn.sym} 6960 580 3 0 {name=l108} |
| C {noconn.sym} 6980 580 3 0 {name=l109} |
| C {noconn.sym} 7000 580 3 0 {name=l110} |
| C {noconn.sym} 7050 580 3 0 {name=l111} |
| C {lab_pin.sym} 6420 150 1 0 {name=l112 sig_type=std_logic lab=iref_cp0} |
| C {lab_pin.sym} 6250 350 0 0 {name=l113 sig_type=std_logic lab=io_analog[10]} |
| C {lab_pin.sym} 7220 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]} |
| C {lab_pin.sym} 6500 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]} |
| C {lab_pin.sym} 3990 -330 2 0 {name=l46 sig_type=std_logic lab=iref_cp0} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 4540 -270 0 0 {name=C1 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X} |
| C {lab_pin.sym} 4540 -360 1 0 {name=l116 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 4540 -180 3 0 {name=l117 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 4680 -270 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X} |
| C {lab_pin.sym} 4680 -360 1 0 {name=l118 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 4680 -180 3 0 {name=l119 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X} |
| C {lab_pin.sym} 4820 -360 1 0 {name=l120 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 4820 -180 3 0 {name=l121 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5050 -270 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5050 -360 1 0 {name=l122 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5050 -180 3 0 {name=l123 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5190 -270 0 0 {name=C5 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5190 -360 1 0 {name=l124 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5190 -180 3 0 {name=l125 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5330 -270 0 0 {name=C6 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5330 -360 1 0 {name=l126 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5330 -180 3 0 {name=l127 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5470 -270 0 0 {name=C7 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5470 -360 1 0 {name=l128 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5470 -180 3 0 {name=l129 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5600 -270 0 0 {name=C8 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5600 -360 1 0 {name=l130 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5600 -180 3 0 {name=l131 sig_type=std_logic lab=vssa1} |
| C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X} |
| C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1} |
| C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1} |
