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G {}
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B 5 -342.5 -132.5 -337.5 -127.5 {name=iref_cp dir=in }
B 5 357.5 -132.5 362.5 -127.5 {name=vss dir=inout }
B 5 317.5 -132.5 322.5 -127.5 {name=vdd dir=inout }
B 5 -42.5 127.5 -37.5 132.5 {name=vco_out dir=inout }
B 5 -62.5 127.5 -57.5 132.5 {name=vco_vctrl dir=inout }
B 5 -282.5 127.5 -277.5 132.5 {name=Up dir=inout }
B 5 -342.5 127.5 -337.5 132.5 {name=pfd_QA dir=inout }
B 5 437.5 127.5 442.5 132.5 {name=out_to_buffer dir=inout }
B 5 -412.5 -2.5 -407.5 2.5 {name=in_ref dir=in }
B 5 -262.5 127.5 -257.5 132.5 {name=nUp dir=inout }
B 5 487.5 -2.5 492.5 2.5 {name=out_to_pad dir=out }
B 5 -242.5 127.5 -237.5 132.5 {name=Down dir=inout }
B 5 -222.5 127.5 -217.5 132.5 {name=nDown dir=inout }
B 5 -322.5 127.5 -317.5 132.5 {name=pfd_QB dir=inout }
B 5 -282.5 -132.5 -277.5 -127.5 {name=lf_D0 dir=in }
B 5 -102.5 127.5 -97.5 132.5 {name=lf_vc dir=inout }
B 5 -22.5 127.5 -17.5 132.5 {name=out_first_buffer dir=inout }
B 5 -142.5 127.5 -137.5 132.5 {name=cp_biasp dir=inout }
B 5 -162.5 127.5 -157.5 132.5 {name=cp_pswitch dir=inout }
B 5 -182.5 127.5 -177.5 132.5 {name=cp_nswitch dir=inout }
B 5 -362.5 127.5 -357.5 132.5 {name=pfd_reset dir=inout }
B 5 -162.5 -132.5 -157.5 -127.5 {name=s_0 sig_type=std_logic dir=in}
B 5 -132.5 -132.5 -127.5 -127.5 {name=MC sig_type=std_logic dir=in}
B 5 -192.5 -132.5 -187.5 -127.5 {name=s_1 sig_type=std_logic dir=in}
B 5 117.5 127.5 122.5 132.5 {name=out_by_2 dir=inout }
B 5 -2.5 127.5 2.5 132.5 {name=out_to_div dir=inout }
B 5 397.5 127.5 402.5 132.5 {name=out_div dir=inout }
B 5 137.5 127.5 142.5 132.5 {name=n_out_by_2 dir=inout }
B 5 57.5 127.5 62.5 132.5 {name=n_out_div_2 dir=inout }
B 5 37.5 127.5 42.5 132.5 {name=out_div_2 dir=inout }
B 5 77.5 127.5 82.5 132.5 {name=n_out_buffer_div_2 dir=inout }
B 5 97.5 127.5 102.5 132.5 {name=out_buffer_div_2 dir=inout }
B 5 197.5 127.5 202.5 132.5 {name=n_clk_0 sig_type=std_logic dir=inout }
B 5 377.5 127.5 382.5 132.5 {name=s1n sig_type=std_logic dir=inout }
B 5 357.5 127.5 362.5 132.5 {name=s0n sig_type=std_logic dir=inout }
B 5 337.5 127.5 342.5 132.5 {name=clk_2_f sig_type=std_logic dir=inout }
B 5 317.5 127.5 322.5 132.5 {name=clk_d sig_type=std_logic dir=inout }
B 5 297.5 127.5 302.5 132.5 {name=clk_out_mux21 sig_type=std_logic dir=inout }
B 5 277.5 127.5 282.5 132.5 {name=clk_5 sig_type=std_logic dir=inout }
B 5 257.5 127.5 262.5 132.5 {name=clk_pre sig_type=std_logic dir=inout }
B 5 237.5 127.5 242.5 132.5 {name=n_clk_1 sig_type=std_logic dir=inout }
B 5 217.5 127.5 222.5 132.5 {name=clk_1 sig_type=std_logic dir=inout }
B 5 177.5 127.5 182.5 132.5 {name=clk_0 sig_type=std_logic dir=inout }
B 5 -242.5 -132.5 -237.5 -127.5 {name=lf_D0 dir=in}
T {@symname} -33 -6 0 0 0.3 0.3 {}
T {@name} -15 -102 0 0 0.2 0.2 {}
T {iref_cp} -336 -105 1 0 0.2 0.2 {}
T {vss} 364 -105 1 0 0.2 0.2 {}
T {vdd} 324 -105 1 0 0.2 0.2 {}
T {vco_out} -41 190 1 1 0.2 0.2 {}
T {vco_vctrl} -61 190 1 1 0.2 0.2 {}
T {Up} -294 165 3 0 0.2 0.2 {}
T {pfd_QA} -354 165 3 0 0.2 0.2 {}
T {out_to_buffer} 439 190 1 1 0.2 0.2 {}
T {in_ref} -375 -4 0 0 0.2 0.2 {}
T {nUp} -274 165 3 0 0.2 0.2 {}
T {out_to_pad} 465 -4 0 1 0.2 0.2 {}
T {Down} -254 165 3 0 0.2 0.2 {}
T {nDown} -234 165 3 0 0.2 0.2 {}
T {pfd_QB} -334 165 3 0 0.2 0.2 {}
T {vco_D0} -294 -155 3 1 0.2 0.2 {}
T {lf_vc} -101 160 1 1 0.2 0.2 {}
T {out_first_buffer} -21 190 1 1 0.2 0.2 {}
T {cp_biasp} -141 180 1 1 0.2 0.2 {}
T {cp_pswitch} -161 180 1 1 0.2 0.2 {}
T {cp_nswitch} -181 180 1 1 0.2 0.2 {}
T {pfd_reset} -374 165 3 0 0.2 0.2 {}
T {s_0} -174 -135 3 1 0.2 0.2 {}
T {MC} -144 -135 3 1 0.2 0.2 {}
T {s_1} -204 -135 3 1 0.2 0.2 {}
T {out_by_2} 106 210 3 0 0.2 0.2 {}
T {out_to_div} -1 190 1 1 0.2 0.2 {}
T {out_div} 399 190 1 1 0.2 0.2 {}
T {n_out_by_2} 126 210 3 0 0.2 0.2 {}
T {n_out_div_2} 46 210 3 0 0.2 0.2 {}
T {out_div_2} 26 210 3 0 0.2 0.2 {}
T {n_out_buffer_div_2} 66 210 3 0 0.2 0.2 {}
T {out_buffer_div_2} 86 210 3 0 0.2 0.2 {}
T {n_clk_0} 199 190 1 1 0.2 0.2 {}
T {s1n} 379 190 1 1 0.2 0.2 {}
T {s0n} 359 190 1 1 0.2 0.2 {}
T {clk_2_f} 339 190 1 1 0.2 0.2 {}
T {clk_d} 319 190 1 1 0.2 0.2 {}
T {clk_out_mux21} 299 190 1 1 0.2 0.2 {}
T {clk_5} 279 190 1 1 0.2 0.2 {}
T {clk_pre} 259 190 1 1 0.2 0.2 {}
T {n_clk_1} 239 190 1 1 0.2 0.2 {}
T {clk_1} 219 190 1 1 0.2 0.2 {}
T {clk_0} 179 190 1 1 0.2 0.2 {}
T {lf_D0} -254 -155 3 1 0.2 0.2 {}
T {PFD} -350 93.5 0 0 0.2 0.2 {}
T {Interface} -273.75 94.75 0 0 0.2 0.2 {}
T {CP} -166.25 93.5 0 0 0.2 0.2 {}
T {LF} -106.25 93.5 0 0 0.2 0.2 {}
T {VCO} -42.5 93.5 0 0 0.2 0.2 {}
T {DIV_BY_2} 65 93.5 0 0 0.2 0.2 {}
T {FREQ_DIV} 261.25 93.5 0 0 0.2 0.2 {}
T {OUT} 430 93.5 0 0 0.2 0.2 {}
T {DEBUG} 3.75 73.5 0 0 0.2 0.2 {}
T {CONFIG} -236.25 -86.5 0 0 0.2 0.2 {}
T {FREQ_DIV} -186.25 -105.25 0 0 0.2 0.2 {}
T {VCO} -290 -105.25 0 0 0.2 0.2 {}
T {LF} -245 -105.25 0 0 0.2 0.2 {}