| v {xschem version=2.9.9 file_version=1.2 } |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| N 2550 -430 2600 -430 { lab=clk} |
| N 2730 -510 2730 -480 { lab=avdd1p8} |
| N 2680 -510 2730 -510 { lab=avdd1p8} |
| N 2730 -380 2730 -360 { lab=avss1p8} |
| N 2680 -360 2730 -360 { lab=avss1p8} |
| N 2770 -390 2770 -320 { lab=delay_reg0} |
| N 2780 -390 2780 -320 { lab=delay_reg1} |
| N 2830 -430 2920 -430 { lab=clk_out} |
| N 2790 -390 2790 -320 { lab=delay_reg2} |
| N 3020 -780 3090 -780 { lab=clk_out} |
| N 3020 -800 3090 -800 { lab=inn} |
| N 3020 -820 3090 -820 { lab=inp} |
| N 3200 -800 3270 -800 { lab=outp} |
| N 3200 -820 3270 -820 { lab=outn} |
| N 3140 -910 3140 -860 { lab=avdd1p8} |
| N 3140 -760 3140 -710 { lab=avss1p8} |
| N 3670 -670 3670 -650 { lab=outn_cap} |
| N 3710 -700 3730 -700 { lab=clk_out_b} |
| N 3730 -700 3730 -650 { lab=clk_out_b} |
| N 3640 -650 3640 -610 { lab=outn_cap} |
| N 3860 -630 3860 -580 { lab=outn_cap} |
| N 3860 -520 3860 -470 { lab=avss1p8} |
| N 3810 -550 3860 -550 { lab=avss1p8} |
| N 3190 -820 3200 -820 { lab=outn} |
| N 3190 -800 3200 -800 { lab=outp} |
| N 3020 -840 3090 -840 { lab=vctrl} |
| N 3610 -760 3610 -730 { lab=outn} |
| N 3640 -770 3640 -760 { lab=outn} |
| N 3270 -820 3590 -820 { lab=outn} |
| N 3610 -670 3610 -650 { lab=outn_cap} |
| N 3610 -650 3670 -650 { lab=outn_cap} |
| N 3550 -700 3570 -700 { lab=clk_out} |
| N 3550 -700 3550 -660 { lab=clk_out} |
| N 3670 -760 3670 -730 { lab=outn} |
| N 3610 -760 3670 -760 { lab=outn} |
| N 3660 -700 3670 -700 { lab=avss1p8} |
| N 3610 -700 3620 -700 { lab=avdd1p8} |
| N 3660 -730 3660 -700 { lab=avss1p8} |
| N 3620 -700 3620 -670 { lab=avdd1p8} |
| N 3400 -680 3400 -660 { lab=outp_cap} |
| N 3440 -710 3460 -710 { lab=clk_out_b} |
| N 3460 -710 3460 -660 { lab=clk_out_b} |
| N 3340 -770 3340 -740 { lab=outp} |
| N 3370 -780 3370 -770 { lab=outp} |
| N 3340 -680 3340 -660 { lab=outp_cap} |
| N 3340 -660 3400 -660 { lab=outp_cap} |
| N 3280 -710 3300 -710 { lab=clk_out} |
| N 3280 -710 3280 -670 { lab=clk_out} |
| N 3400 -770 3400 -740 { lab=outp} |
| N 3340 -770 3400 -770 { lab=outp} |
| N 3390 -710 3400 -710 { lab=avss1p8} |
| N 3340 -710 3350 -710 { lab=avdd1p8} |
| N 3390 -740 3390 -710 { lab=avss1p8} |
| N 3350 -710 3350 -680 { lab=avdd1p8} |
| N 3370 -660 3370 -620 { lab=outp_cap} |
| N 2920 -430 2970 -430 { lab=clk_out} |
| N 3010 -510 3010 -480 { lab=avdd1p8} |
| N 2960 -510 3010 -510 { lab=avdd1p8} |
| N 3010 -380 3010 -360 { lab=avss1p8} |
| N 2960 -360 3010 -360 { lab=avss1p8} |
| N 3100 -430 3170 -430 { lab=clk_out_b} |
| N 3900 -550 3960 -550 { lab=rst} |
| N 2600 -430 2650 -430 { lab=clk} |
| N 2650 -430 2690 -430 { lab=clk} |
| N 4060 -630 4060 -580 { lab=outp_cap} |
| N 4060 -520 4060 -470 { lab=avss1p8} |
| N 4060 -550 4110 -550 { lab=avss1p8} |
| N 3960 -550 4020 -550 { lab=rst} |
| N 2740 -950 2740 -900 { lab=avdd1p8} |
| N 2710 -780 2710 -730 { lab=avss1p8} |
| N 2810 -840 3020 -840 { lab=vctrl} |
| N 2550 -870 2670 -870 { lab=iref} |
| N 2740 -780 2740 -730 { lab=iref_reg0} |
| N 2750 -780 2750 -730 { lab=iref_reg1} |
| N 2760 -780 2760 -730 { lab=iref_reg2} |
| N 3640 -790 3640 -770 { lab=outn} |
| N 3640 -820 3640 -790 { lab=outn} |
| N 3590 -820 3640 -820 { lab=outn} |
| N 3270 -800 3370 -800 { lab=outp} |
| N 3370 -800 3370 -780 { lab=outp} |
| N 3370 -620 3370 -590 { lab=outp_cap} |
| N 3640 -610 3640 -580 { lab=outn_cap} |
| N 3730 -850 3780 -850 { lab=outn} |
| N 3730 -830 3780 -830 { lab=outp} |
| N 3730 -810 3780 -810 { lab=outn_cap} |
| N 3730 -790 3780 -790 { lab=outp_cap} |
| N 3970 -550 3970 -500 { lab=rst} |
| C {ipin.sym} 2550 -430 0 0 {name=p4 lab=clk} |
| C {opin.sym} 3780 -830 0 0 {name=p7 lab=outp} |
| C {opin.sym} 3780 -850 0 0 {name=p8 lab=outn} |
| C {iopin.sym} 3140 -910 0 0 {name=p15 lab=avdd1p8} |
| C {iopin.sym} 3140 -710 2 0 {name=p16 lab=avss1p8} |
| C {delay_cell_buff.sym} 2780 -260 0 0 {name=x3} |
| C {lab_wire.sym} 2710 -510 0 0 {name=l4 sig_type=std_logic lab=avdd1p8} |
| C {lab_wire.sym} 2710 -360 0 0 {name=l9 sig_type=std_logic lab=avss1p8} |
| C {lab_wire.sym} 2900 -430 2 0 {name=l14 sig_type=std_logic lab=clk_out} |
| C {lab_wire.sym} 3020 -780 2 0 {name=l27 sig_type=std_logic lab=clk_out} |
| C {lab_wire.sym} 3370 -800 2 0 {name=l28 sig_type=std_logic lab=outp} |
| C {lab_wire.sym} 3430 -820 2 0 {name=l29 sig_type=std_logic lab=outn} |
| C {ngspice_probe.sym} 3320 -800 0 0 {name=r2} |
| C {ngspice_probe.sym} 3230 -800 0 0 {name=r3} |
| C {ngspice_probe.sym} 3040 -780 0 0 {name=r5} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 3880 -550 0 1 {name=M3 |
| L=0.15 |
| W=1 |
| nf=1 |
| mult=3 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 3860 -600 3 1 {name=l34 sig_type=std_logic lab=outn_cap} |
| C {lab_wire.sym} 3860 -500 1 1 {name=l35 sig_type=std_logic lab=avss1p8} |
| C {lab_wire.sym} 3820 -550 1 1 {name=l37 sig_type=std_logic lab=avss1p8} |
| C {ngspice_probe.sym} 3040 -840 0 0 {name=r10} |
| C {res_amp_lin.sym} 3180 -640 0 0 {name=x4} |
| C {lab_wire.sym} 2950 -840 0 0 {name=l36 sig_type=std_logic lab=vctrl} |
| C {lab_wire.sym} 3620 -680 1 0 {name=l39 sig_type=std_logic lab=avdd1p8} |
| C {lab_wire.sym} 3660 -720 3 0 {name=l47 sig_type=std_logic lab=avss1p8} |
| C {lab_wire.sym} 3370 -630 2 0 {name=l48 sig_type=std_logic lab=outp_cap} |
| C {lab_wire.sym} 3350 -690 1 0 {name=l50 sig_type=std_logic lab=avdd1p8} |
| C {lab_wire.sym} 3390 -730 3 0 {name=l51 sig_type=std_logic lab=avss1p8} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 3420 -710 0 1 {name=M1 |
| L=0.15 |
| W=1 |
| nf=1 |
| mult=5 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 3690 -700 0 1 {name=M2 |
| L=0.15 |
| W=1 |
| nf=1 |
| mult=5 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/pfet_01v8_lvt.sym} 3320 -710 0 0 {name=M5 |
| L=0.35 |
| W=1 |
| nf=1 |
| mult=10 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=pfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/pfet_01v8_lvt.sym} 3590 -700 0 0 {name=M6 |
| L=0.35 |
| W=1 |
| nf=1 |
| mult=10 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=pfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 3640 -620 2 0 {name=l42 sig_type=std_logic lab=outn_cap} |
| C {inverter_min_x4.sym} 3030 -430 0 0 {name=x5} |
| C {lab_wire.sym} 2990 -510 0 0 {name=l15 sig_type=std_logic lab=avdd1p8} |
| C {lab_wire.sym} 2990 -360 0 0 {name=l32 sig_type=std_logic lab=avss1p8} |
| C {lab_wire.sym} 3140 -430 2 0 {name=l33 sig_type=std_logic lab=clk_out_b} |
| C {lab_wire.sym} 3280 -680 0 0 {name=l38 sig_type=std_logic lab=clk_out} |
| C {lab_wire.sym} 3460 -680 2 0 {name=l40 sig_type=std_logic lab=clk_out_b} |
| C {lab_wire.sym} 3550 -690 0 0 {name=l44 sig_type=std_logic lab=clk_out} |
| C {lab_wire.sym} 3730 -680 2 0 {name=l45 sig_type=std_logic lab=clk_out_b} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 4040 -550 0 0 {name=M4 |
| L=0.15 |
| W=1 |
| nf=1 |
| mult=3 |
| ad="'int((nf+1)/2) * W/nf * 0.29'" |
| pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" |
| as="'int((nf+2)/2) * W/nf * 0.29'" |
| ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 4060 -600 1 0 {name=l61 sig_type=std_logic lab=outp_cap} |
| C {lab_wire.sym} 4060 -500 3 0 {name=l62 sig_type=std_logic lab=avss1p8} |
| C {lab_wire.sym} 4100 -550 3 0 {name=l63 sig_type=std_logic lab=avss1p8} |
| C {iref_ctrl_res_amp.sym} 2760 -670 0 0 {name=x7} |
| C {lab_wire.sym} 2740 -930 0 0 {name=l1 sig_type=std_logic lab=avdd1p8} |
| C {lab_wire.sym} 2710 -740 0 0 {name=l2 sig_type=std_logic lab=avss1p8} |
| C {ipin.sym} 2550 -870 0 0 {name=p1 lab=iref} |
| C {ipin.sym} 3020 -820 0 0 {name=p5 lab=inp} |
| C {ipin.sym} 3020 -800 0 0 {name=p6 lab=inn} |
| C {ipin.sym} 2740 -730 3 0 {name=p2 lab=iref_reg0} |
| C {ipin.sym} 2750 -730 3 0 {name=p3 lab=iref_reg1} |
| C {ipin.sym} 2760 -730 3 0 {name=p9 lab=iref_reg2} |
| C {opin.sym} 3780 -790 0 0 {name=p10 lab=outp_cap} |
| C {opin.sym} 3780 -810 0 0 {name=p11 lab=outn_cap} |
| C {ipin.sym} 2770 -320 3 0 {name=p12 lab=delay_reg0} |
| C {ipin.sym} 2780 -320 3 0 {name=p13 lab=delay_reg1} |
| C {ipin.sym} 2790 -320 3 0 {name=p14 lab=delay_reg2} |
| C {ipin.sym} 3970 -500 3 0 {name=p17 lab=rst} |
