diff --git a/mag/csvco_branch_v2.mag b/mag/csvco_branch_v2.mag
new file mode 100644
index 0000000..61b2c26
--- /dev/null
+++ b/mag/csvco_branch_v2.mag
@@ -0,0 +1,219 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624064496
+<< nwell >>
+rect -363 387 931 1955
+<< pwell >>
+rect -363 -680 931 387
+rect -363 -771 162 -680
+rect 184 -771 931 -680
+rect -363 -1002 931 -771
+<< psubdiff >>
+rect 608 -174 632 -140
+rect 790 -174 814 -140
+rect -255 -966 -231 -932
+rect 799 -966 823 -932
+<< nsubdiff >>
+rect -247 1871 -223 1905
+rect 807 1871 831 1905
+<< psubdiffcont >>
+rect 632 -174 790 -140
+rect -231 -966 799 -932
+<< nsubdiffcont >>
+rect -223 1871 807 1905
+<< locali >>
+rect -239 1871 -223 1905
+rect 807 1871 823 1905
+<< viali >>
+rect -223 1871 807 1905
+rect 104 1742 454 1776
+rect 104 1214 138 1742
+rect 420 1214 454 1742
+rect 104 1180 454 1214
+rect 536 -85 886 -51
+rect 536 -174 632 -140
+rect 632 -174 790 -140
+rect 790 -174 886 -140
+rect 106 -285 456 -251
+rect 106 -796 140 -285
+rect 422 -796 456 -285
+rect 106 -837 459 -796
+rect -327 -966 -231 -932
+rect -231 -966 799 -932
+rect 799 -966 895 -932
+<< metal1 >>
+rect -363 1905 931 1911
+rect -363 1871 -223 1905
+rect 807 1871 931 1905
+rect -363 1776 931 1871
+rect -363 1736 104 1776
+rect 68 1180 104 1736
+rect 138 1736 420 1742
+rect 138 1220 144 1736
+rect 185 1641 195 1699
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+rect 138 1214 420 1220
+rect 454 1736 931 1776
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+rect 209 27 261 37
+rect 619 8 629 60
+rect 733 8 743 60
+rect 61 -174 81 -45
+rect 500 -51 931 -45
+rect 500 -85 536 -51
+rect 886 -85 931 -51
+rect 500 -140 931 -85
+rect 500 -174 536 -140
+rect 886 -174 931 -140
+rect 61 -220 931 -174
+rect 61 -251 932 -220
+rect 61 -790 106 -251
+rect 456 -256 932 -251
+rect 456 -257 737 -256
+rect -363 -837 106 -790
+rect 140 -291 422 -285
+rect 140 -790 146 -291
+rect 416 -364 422 -291
+rect 191 -651 201 -374
+rect 258 -651 268 -374
+rect 249 -701 313 -692
+rect 178 -704 313 -701
+rect 178 -756 184 -704
+rect 308 -756 318 -704
+rect 347 -790 422 -364
+rect 140 -796 422 -790
+rect 456 -291 468 -257
+rect 456 -790 462 -291
+rect 456 -796 931 -790
+rect 459 -837 931 -796
+rect -363 -932 931 -837
+rect -363 -966 -327 -932
+rect 895 -966 931 -932
+rect -363 -972 931 -966
+<< via1 >>
+rect 195 1641 307 1699
+rect 184 1278 252 1569
+rect 209 617 261 897
+rect 78 361 286 413
+rect 366 361 490 413
+rect 641 361 693 413
+rect 209 37 261 167
+rect 770 89 831 234
+rect 629 8 733 60
+rect 201 -651 258 -374
+rect 184 -756 308 -704
+<< metal2 >>
+rect 195 1699 307 1709
+rect 80 1641 195 1682
+rect 307 1641 312 1682
+rect 80 1629 312 1641
+rect 184 1574 252 1579
+rect 184 1569 261 1574
+rect 252 1278 261 1569
+rect 184 1268 261 1278
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+rect 209 607 261 617
+rect 78 413 286 423
+rect 68 361 78 413
+rect 78 351 286 361
+rect 366 413 490 423
+rect 641 413 693 423
+rect 490 361 641 413
+rect 693 361 931 413
+rect 366 351 490 361
+rect 641 351 693 361
+rect 813 244 874 245
+rect 770 235 874 244
+rect 770 234 813 235
+rect 209 167 261 177
+rect 831 89 874 90
+rect 770 80 874 89
+rect 770 79 831 80
+rect 209 -364 261 37
+rect 629 62 733 72
+rect 629 -4 733 6
+rect 201 -374 261 -364
+rect 258 -463 261 -374
+rect 201 -661 258 -651
+rect 184 -703 308 -694
+rect 699 -703 886 -702
+rect 73 -704 321 -703
+rect 73 -756 184 -704
+rect 308 -756 321 -704
+rect 699 -713 900 -703
+rect 699 -748 797 -713
+rect 73 -758 321 -756
+rect 184 -766 308 -758
+rect 797 -781 900 -771
+<< via2 >>
+rect 813 234 874 235
+rect 813 90 831 234
+rect 831 90 874 234
+rect 629 60 733 62
+rect 629 8 733 60
+rect 629 6 733 8
+rect 797 -771 900 -713
+<< metal3 >>
+rect 803 239 884 240
+rect 803 235 886 239
+rect 803 90 813 235
+rect 874 90 886 235
+rect 803 85 886 90
+rect 619 62 743 67
+rect 619 6 629 62
+rect 733 6 743 62
+rect 619 1 743 6
+rect 650 -194 710 1
+rect 819 -708 886 85
+rect 787 -713 910 -708
+rect 787 -771 797 -713
+rect 900 -771 910 -713
+rect 787 -776 910 -771
+use cap_vco  cap_vco_0
+timestamp 1624049879
+transform 1 0 -37 0 1 -744
+box 554 -6 926 514
+use sky130_fd_pr__nfet_01v8_EDT3AT  sky130_fd_pr__nfet_01v8_EDT3AT_0
+timestamp 1624049879
+transform 1 0 711 0 1 100
+box -211 -221 211 221
+use sky130_fd_pr__nfet_01v8_CBSTVW  sky130_fd_pr__nfet_01v8_CBSTVW_0
+timestamp 1624058804
+transform 1 0 281 0 1 -544
+box -211 -329 211 329
+use inverter_csvco  inverter_csvco_0
+timestamp 1624049879
+transform 1 0 68 0 1 387
+box 0 -597 432 757
+use sky130_fd_pr__pfet_01v8_MJP3BN  sky130_fd_pr__pfet_01v8_MJP3BN_0
+timestamp 1624058804
+transform 1 0 279 0 1 1478
+box -211 -334 211 334
+<< labels >>
+rlabel metal2 68 361 78 413 1 in
+rlabel metal3 650 -194 710 6 1 D0
+rlabel metal2 693 361 931 413 1 out
+rlabel metal2 73 -758 177 -703 1 vctrl
+rlabel metal1 -363 1776 931 1871 1 vdd
+rlabel metal1 -363 -932 931 -837 1 vss
+<< end >>
diff --git a/mag/extractions/csvco_branch_v2_lvs.spice b/mag/extractions/csvco_branch_v2_lvs.spice
new file mode 100644
index 0000000..b104bdf
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_lvs.spice
@@ -0,0 +1,43 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.end
+
diff --git a/mag/extractions/csvco_branch_v2_pex_c.spice b/mag/extractions/csvco_branch_v2_pex_c.spice
new file mode 100644
index 0000000..a271b47
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_pex_c.spice
@@ -0,0 +1,104 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_n73_n119# a_15_n119# 0.51fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n186# a_15_n186# 0.51fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 w_n211_n334# a_15_n186# 0.21fF
+C3 w_n211_n334# a_n33_145# 0.05fF
+C4 w_n211_n334# a_n73_n186# 0.21fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n33_n99# a_n73_n11# 0.02fF
+C2 a_n33_n99# a_15_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# a_20_n114# 0.42fF
+C1 w_n216_n334# a_20_n114# 0.20fF
+C2 w_n216_n334# a_n78_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd vbulkp 0.04fF
+C1 out in 0.11fF
+C2 out vbulkp 0.08fF
+C3 in vdd 0.01fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C1 vdd cap_vco_0/t 0.06fF
+C2 inverter_csvco_0/vss vctrl 0.23fF
+C3 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C4 inverter_csvco_0/vss in 0.01fF
+C5 inverter_csvco_0/vdd vdd 0.97fF
+C6 inverter_csvco_0/vss out 0.03fF
+C7 out cap_vco_0/t 0.70fF
+C8 D0 out 0.09fF
+C9 out vdd 0.03fF
+C10 inverter_csvco_0/vdd in 0.01fF
+C11 inverter_csvco_0/vdd out 0.02fF
+C12 out in 0.06fF
+C13 m1_185_1641# vdd 0.48fF
+C14 inverter_csvco_0/vss D0 0.01fF
+C15 vdd vss 3.61fF
+C16 out vss 0.94fF
+C17 inverter_csvco_0/vdd vss 0.23fF
+C18 in vss 0.70fF
+C19 inverter_csvco_0/vss vss 0.61fF
+C20 D0 vss -0.68fF
+C21 m1_185_1641# vss -0.03fF
+C22 cap_vco_0/t vss 7.22fF
+C23 vctrl vss 0.44fF
+.end
+
diff --git a/mag/extractions/csvco_branch_v2_pex_rc.spice b/mag/extractions/csvco_branch_v2_pex_rc.spice
new file mode 100644
index 0000000..c83b08d
--- /dev/null
+++ b/mag/extractions/csvco_branch_v2_pex_rc.spice
@@ -0,0 +1,104 @@
+* NGSPICE file created from csvco_branch_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_n207# a_n73_n119# 0.02fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_15_n119# a_n73_n119# 0.51fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n334# a_n33_145# 0.05fF
+C1 w_n211_n334# a_15_n186# 0.21fF
+C2 w_n211_n334# a_n73_n186# 0.21fF
+C3 a_15_n186# a_n33_145# 0.01fF
+C4 a_n73_n186# a_n33_145# 0.01fF
+C5 a_n73_n186# a_15_n186# 0.51fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n99# a_n73_n11# 0.02fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_15_n11# a_n73_n11# 0.15fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_20_n114# 0.20fF
+C1 w_n216_n334# a_n78_n114# 0.20fF
+C2 a_n78_n114# a_20_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vdd in 0.01fF
+C1 in vss 0.01fF
+C2 vbulkp out 0.08fF
+C3 vbulkp vdd 0.04fF
+C4 out in 0.11fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+
+* Top level circuit csvco_branch_v2
+
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 m1_185_1641# vdd 0.48fF
+C1 out D0 0.09fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C4 in inverter_csvco_0/vss 0.01fF
+C5 out vdd 0.03fF
+C6 out inverter_csvco_0/vdd 0.02fF
+C7 out cap_vco_0/t 0.70fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 inverter_csvco_0/vdd vdd 0.97fF
+C10 out in 0.06fF
+C11 cap_vco_0/t vdd 0.06fF
+C12 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C13 vctrl inverter_csvco_0/vss 0.23fF
+C14 in inverter_csvco_0/vdd 0.01fF
+C15 vdd vss 3.61fF
+C16 out vss 0.94fF
+C17 inverter_csvco_0/vdd vss 0.23fF
+C18 in vss 0.70fF
+C19 inverter_csvco_0/vss vss 0.61fF
+C20 D0 vss -0.68fF
+C21 m1_185_1641# vss -0.03fF
+C22 cap_vco_0/t vss 7.22fF
+C23 vctrl vss 0.44fF
+.end
+
diff --git a/mag/extractions/lvs b/mag/extractions/lvs
new file mode 100644
index 0000000..7a5e6d8
--- /dev/null
+++ b/mag/extractions/lvs
@@ -0,0 +1,78 @@
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_AQR2CW in circuit inverter_csvco (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_HRYSXS in circuit inverter_csvco (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_CBSTVW in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_MJP3BN in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_EDT3AT in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell cap_vco in circuit csvco_branch_v2 (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_CBAU6Y in circuit mag/extractions/ring_osc_v2_lvs.spice (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_4757AC in circuit mag/extractions/ring_osc_v2_lvs.spice (0)(1 instance)
+Equate elements:  no current cell.
+Equate elements:  no current cell.
+
+Subcircuit summary:
+Circuit 1: inverter_csvco                  |Circuit 2: inverter_csvco                  
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+sky130_fd_pr__pfet_01v8 (1)                |sky130_fd_pr__pfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 6                          |Number of nets: 6                          
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: inverter_csvco                  |Circuit 2: inverter_csvco                  
+-------------------------------------------|-------------------------------------------
+vss                                        |vss                                        
+vbulkn                                     |vbulkn                                     
+vdd                                        |vdd                                        
+vbulkp                                     |vbulkp                                     
+out                                        |out                                        
+in                                         |in                                         
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes inverter_csvco and inverter_csvco are equivalent.
+
+Subcircuit summary:
+Circuit 1: csvco_branch_v2                 |Circuit 2: csvco_branch_v2                 
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (2)                |sky130_fd_pr__nfet_01v8 (2)                
+sky130_fd_pr__pfet_01v8 (1)                |sky130_fd_pr__pfet_01v8 (1)                
+inverter_csvco (1)                         |inverter_csvco (1)                         
+c (1)                                      |c (1)                                      
+Number of devices: 5                       |Number of devices: 5                       
+Number of nets: 10                         |Number of nets: 10                         
+---------------------------------------------------------------------------------------
+Circuits match uniquely.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: csvco_branch_v2                 |Circuit 2: csvco_branch_v2                 
+-------------------------------------------|-------------------------------------------
+vdd                                        |vdd                                        
+vss                                        |vss                                        
+m1_185_1641#                               |vbp **Mismatch**                           
+vctrl                                      |vctrl                                      
+D0                                         |D0                                         
+in                                         |in                                         
+out                                        |out                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes csvco_branch_v2 and csvco_branch_v2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: mag/extractions/ring_osc_v2_lvs |Circuit 2: xschem/simulations/csvco_v2.spi 
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+csvco_branch_v2 (3)                        |csvco_branch_v2 (3)                        
+sky130_fd_pr__pfet_01v8 (1)                |sky130_fd_pr__pfet_01v8 (1)                
+Number of devices: 5                       |Number of devices: 5                       
+Number of nets: 8                          |Number of nets: 8                          
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match with 2 symmetries.
+Circuits match correctly.
+Cells have no pins;  pin matching not needed.
+Device classes mag/extractions/ring_osc_v2_lvs.spice and xschem/simulations/csvco_v2.spice are equivalent.
+Circuits match uniquely.
diff --git a/mag/extractions/ring_osc_v2_lvs.spice b/mag/extractions/ring_osc_v2_lvs.spice
new file mode 100644
index 0000000..43179a3
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_lvs.spice
@@ -0,0 +1,62 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch_v2 vctrl in D0 out m1_185_1641# vss vdd
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in D0 csvco_branch_v2_2/in vbp vss vdd
++ csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco D0 csvco_branch_v2_1/in vbp vss vdd csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in D0 out_vco vbp vss vdd csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+.end
+
diff --git a/mag/extractions/ring_osc_v2_lvs_port.spice b/mag/extractions/ring_osc_v2_lvs_port.spice
new file mode 100644
index 0000000..7ae1803
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_lvs_port.spice
@@ -0,0 +1,52 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt csvco_branch_v2 vctrl in D0 out m1_185_1641# vss vdd
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt ring_osc_v2 vss vdd out_vco D0 vctrl vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in D0 csvco_branch_v2_2/in vbp vss vdd
++ csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco D0 csvco_branch_v2_1/in vbp vss vdd csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in D0 out_vco vbp vss vdd csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+.ends
+
diff --git a/mag/extractions/ring_osc_v2_pex_c.spice b/mag/extractions/ring_osc_v2_pex_c.spice
new file mode 100644
index 0000000..a29f6f9
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_c.spice
@@ -0,0 +1,169 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_n33_n238# a_15_n150# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_15_n119# 0.51fF
+C1 a_n33_n207# a_15_n119# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# a_n73_n186# 0.01fF
+C1 w_n211_n334# a_n73_n186# 0.21fF
+C2 w_n211_n334# a_n33_145# 0.05fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 a_n33_145# a_15_n186# 0.01fF
+C5 w_n211_n334# a_15_n186# 0.21fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_15_n11# 0.15fF
+C1 a_n33_n99# a_15_n11# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_n78_n106# a_20_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 a_20_n114# a_n78_n114# 0.42fF
+C2 w_n216_n334# a_20_n114# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 vss in 0.01fF
+C1 in vdd 0.01fF
+C2 in out 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 vbulkp out 0.08fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 cap_vco_0/t vctrl 0.03fF
+C1 inverter_csvco_0/vss in 0.01fF
+C2 inverter_csvco_0/vss vctrl 0.23fF
+C3 vdd out 0.03fF
+C4 in inverter_csvco_0/vdd 0.01fF
+C5 out D0 0.09fF
+C6 cap_vco_0/t out 0.11fF
+C7 inverter_csvco_0/vss out 0.03fF
+C8 in out 0.06fF
+C9 inverter_csvco_0/vdd out 0.02fF
+C10 vdd m1_185_1641# 0.48fF
+C11 vdd inverter_csvco_0/vdd 0.97fF
+C12 cap_vco_0/t D0 0.18fF
+C13 m1_185_1641# inverter_csvco_0/vdd 0.13fF
+C14 inverter_csvco_0/vss D0 0.01fF
+C15 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n33_181# 0.05fF
+C1 a_n33_181# a_n73_n150# 0.01fF
+C2 w_n211_n369# a_n73_n150# 0.20fF
+C3 a_n33_181# a_15_n150# 0.01fF
+C4 w_n211_n369# a_15_n150# 0.20fF
+C5 a_15_n150# a_n73_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_2/inverter_csvco_0/vss D0 0.04fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/cap_vco_0/t vctrl 0.24fF
+C3 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C4 out_vco csvco_branch_v2_2/in 0.59fF
+C5 csvco_branch_v2_1/cap_vco_0/t D0 0.12fF
+C6 vbp vctrl 0.06fF
+C7 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C8 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C9 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C10 vbp vdd 3.04fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 vdd csvco_branch_v2_2/in 0.01fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.46fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.end
+
diff --git a/mag/extractions/ring_osc_v2_pex_c_port.spice b/mag/extractions/ring_osc_v2_pex_c_port.spice
new file mode 100644
index 0000000..e943714
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_c_port.spice
@@ -0,0 +1,174 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n73_n150# 0.51fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n119# a_n73_n119# 0.51fF
+C1 a_15_n119# a_n33_n207# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n186# w_n211_n334# 0.21fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_n73_n186# w_n211_n334# 0.21fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 w_n211_n334# a_n33_145# 0.05fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# w_n216_n334# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out vbulkp 0.08fF
+C1 out in 0.11fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd out 0.03fF
+C1 out inverter_csvco_0/vdd 0.02fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 D0 cap_vco_0/t 0.18fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss vctrl 0.23fF
+C6 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C7 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 in inverter_csvco_0/vss 0.01fF
+C10 in inverter_csvco_0/vdd 0.01fF
+C11 out cap_vco_0/t 0.11fF
+C12 D0 out 0.09fF
+C13 out in 0.06fF
+C14 vdd inverter_csvco_0/vdd 0.97fF
+C15 out inverter_csvco_0/vss 0.03fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_15_n150# a_n33_181# 0.01fF
+C2 w_n211_n369# a_15_n150# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 w_n211_n369# a_n73_n150# 0.20fF
+C5 w_n211_n369# a_n33_181# 0.05fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt csvco_v2_pex_c vdd out_vco D0 vctrl vss vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/inverter_csvco_0/vss D0 0.04fF
+C3 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 vbp vdd 3.04fF
+C6 vctrl vbp 0.06fF
+C7 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C8 csvco_branch_v2_2/in out_vco 0.59fF
+C9 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/mag/extractions/ring_osc_v2_pex_rc.spice b/mag/extractions/ring_osc_v2_pex_rc.spice
new file mode 100644
index 0000000..ef45b0a
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_rc.spice
@@ -0,0 +1,169 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_15_n119# a_n73_n119# 0.51fF
+C2 a_15_n119# a_n33_n207# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# w_n211_n334# 0.05fF
+C1 a_15_n186# a_n73_n186# 0.51fF
+C2 a_n73_n186# a_n33_145# 0.01fF
+C3 a_15_n186# a_n33_145# 0.01fF
+C4 a_n73_n186# w_n211_n334# 0.21fF
+C5 a_15_n186# w_n211_n334# 0.21fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# a_n78_n114# 0.42fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# w_n216_n334# 0.20fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 in vdd 0.01fF
+C1 out vbulkp 0.08fF
+C2 in out 0.11fF
+C3 vdd vbulkp 0.04fF
+C4 in vss 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 out in 0.06fF
+C1 out inverter_csvco_0/vss 0.03fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 vdd inverter_csvco_0/vdd 0.97fF
+C4 out inverter_csvco_0/vdd 0.02fF
+C5 out D0 0.09fF
+C6 vdd out 0.03fF
+C7 vctrl inverter_csvco_0/vss 0.23fF
+C8 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C9 vdd m1_185_1641# 0.48fF
+C10 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C11 in inverter_csvco_0/vss 0.01fF
+C12 D0 cap_vco_0/t 0.18fF
+C13 out cap_vco_0/t 0.11fF
+C14 inverter_csvco_0/vdd in 0.01fF
+C15 D0 inverter_csvco_0/vss 0.01fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_181# w_n211_n369# 0.05fF
+C1 a_n73_n150# w_n211_n369# 0.20fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 a_n33_181# a_15_n150# 0.01fF
+C5 a_n73_n150# a_15_n150# 0.51fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+
+* Top level circuit ring_osc_v2
+
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_1/in vdd 0.01fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 vctrl csvco_branch_v2_0/cap_vco_0/t 0.24fF
+C3 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 csvco_branch_v2_2/in out_vco 0.59fF
+C6 D0 csvco_branch_v2_0/cap_vco_0/t 0.12fF
+C7 vdd vbp 3.04fF
+C8 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C9 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C10 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C11 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C12 vctrl vbp 0.06fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.46fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.end
+
diff --git a/mag/extractions/ring_osc_v2_pex_rc_port.spice b/mag/extractions/ring_osc_v2_pex_rc_port.spice
new file mode 100644
index 0000000..2af6754
--- /dev/null
+++ b/mag/extractions/ring_osc_v2_pex_rc_port.spice
@@ -0,0 +1,167 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_n33_n238# 0.02fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 a_15_n150# a_n33_n238# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n119# a_n33_n207# 0.02fF
+C1 a_15_n119# a_n73_n119# 0.51fF
+C2 a_15_n119# a_n33_n207# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n33_145# w_n211_n334# 0.05fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_15_n186# a_n33_145# 0.01fF
+C3 a_n73_n186# w_n211_n334# 0.21fF
+C4 a_15_n186# w_n211_n334# 0.21fF
+C5 a_15_n186# a_n73_n186# 0.51fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n11# a_n33_n99# 0.02fF
+C1 a_15_n11# a_n73_n11# 0.15fF
+C2 a_15_n11# a_n33_n99# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_n78_n114# w_n216_n334# 0.20fF
+C1 a_20_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out in 0.11fF
+C1 vbulkp out 0.08fF
+C2 vdd in 0.01fF
+C3 vss in 0.01fF
+C4 vbulkp vdd 0.04fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+C0 out in 0.06fF
+C1 vctrl cap_vco_0/t 0.03fF
+C2 out inverter_csvco_0/vss 0.03fF
+C3 out inverter_csvco_0/vdd 0.02fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C6 vdd inverter_csvco_0/vdd 0.97fF
+C7 D0 inverter_csvco_0/vss 0.01fF
+C8 out cap_vco_0/t 0.11fF
+C9 vdd out 0.03fF
+C10 out D0 0.09fF
+C11 inverter_csvco_0/vss vctrl 0.23fF
+C12 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C13 in inverter_csvco_0/vss 0.01fF
+C14 inverter_csvco_0/vdd in 0.01fF
+C15 D0 cap_vco_0/t 0.18fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 w_n211_n369# a_n73_n150# 0.20fF
+C1 w_n211_n369# a_n33_181# 0.05fF
+C2 a_n73_n150# a_n33_181# 0.01fF
+C3 w_n211_n369# a_15_n150# 0.20fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n33_181# a_15_n150# 0.01fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt ring_osc_v2 vss vdd out_vco D0 vctrl vbp
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 vctrl vbp 0.06fF
+C1 csvco_branch_v2_1/in vdd 0.01fF
+C2 csvco_branch_v2_1/in out_vco 0.76fF
+C3 vctrl csvco_branch_v2_0/cap_vco_0/t 0.24fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 csvco_branch_v2_1/cap_vco_0/t vctrl 0.24fF
+C6 csvco_branch_v2_2/in out_vco 0.59fF
+C7 D0 csvco_branch_v2_0/cap_vco_0/t 0.12fF
+C8 vdd vbp 3.04fF
+C9 csvco_branch_v2_1/cap_vco_0/t D0 0.12fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C12 D0 csvco_branch_v2_1/inverter_csvco_0/vss 0.04fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/mag/extractions/user_analog_prject_wrapper_lvs.spice b/mag/extractions/user_analog_prject_wrapper_lvs.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_lvs.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_prject_wrapper_pex_c.spice b/mag/extractions/user_analog_prject_wrapper_pex_c.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_pex_c.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/extractions/user_analog_prject_wrapper_pex_rc.spice b/mag/extractions/user_analog_prject_wrapper_pex_rc.spice
new file mode 100644
index 0000000..43c04f2
--- /dev/null
+++ b/mag/extractions/user_analog_prject_wrapper_pex_rc.spice
@@ -0,0 +1,7 @@
+* NGSPICE file created from user_analog_prject_wrapper.ext - technology: sky130A
+
+
+* Top level circuit user_analog_prject_wrapper
+
+.end
+
diff --git a/mag/mimcap_decoup_1x5.mag b/mag/mimcap_decoup_1x5.mag
new file mode 100644
index 0000000..6709076
--- /dev/null
+++ b/mag/mimcap_decoup_1x5.mag
@@ -0,0 +1,32 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624376995
+<< metal5 >>
+rect 42 43 278 6161
+rect 664 142 6584 6062
+rect 6986 43 7222 6161
+rect 7608 142 13528 6062
+rect 13930 43 14166 6161
+rect 14552 142 20472 6062
+rect 20874 43 21110 6161
+rect 21496 142 27416 6062
+rect 27818 43 28054 6161
+rect 28440 142 34360 6062
+use sky130_fd_pr__cap_mim_m3_2_2Y8F6P  decap
+array 0 4 -6944 0 0 -991
+timestamp 1624129585
+transform -1 0 3373 0 -1 3102
+box -3351 -3261 3373 3261
+<< labels >>
+rlabel metal5 27818 43 28054 6161 1 b
+rlabel metal5 20874 43 21110 6161 1 b
+rlabel metal5 13930 43 14166 6161 1 b
+rlabel metal5 6986 43 7222 6161 1 b
+rlabel metal5 42 43 278 6161 1 b
+rlabel metal5 664 142 6584 6062 1 t
+rlabel metal5 7608 142 13528 6062 1 t
+rlabel metal5 14552 142 20472 6062 1 t
+rlabel metal5 21496 142 27416 6062 1 t
+rlabel metal5 28440 142 34360 6062 1 t
+<< end >>
diff --git a/mag/ring_osc_v2.mag b/mag/ring_osc_v2.mag
new file mode 100644
index 0000000..c130acd
--- /dev/null
+++ b/mag/ring_osc_v2.mag
@@ -0,0 +1,178 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624065706
+<< nwell >>
+rect -422 2867 0 2956
+<< pwell >>
+rect 1294 809 1725 1389
+rect 2588 809 3019 1389
+rect -422 165 -411 166
+rect -422 0 0 165
+<< psubdiff >>
+rect -314 36 -290 70
+rect -132 36 -108 70
+<< nsubdiff >>
+rect -314 2886 -290 2920
+rect -132 2886 -108 2920
+<< psubdiffcont >>
+rect -290 36 -132 70
+<< nsubdiffcont >>
+rect -290 2886 -132 2920
+<< viali >>
+rect -386 2886 -290 2920
+rect -290 2886 -132 2920
+rect -132 2886 -36 2920
+rect -386 2797 -36 2831
+rect -386 125 -36 159
+rect -386 36 -290 70
+rect -290 36 -132 70
+rect -132 36 -36 70
+<< metal1 >>
+rect -422 2920 3882 2926
+rect -422 2886 -386 2920
+rect -36 2898 3882 2920
+rect -36 2886 0 2898
+rect -422 2831 0 2886
+rect -422 2797 -386 2831
+rect -36 2797 0 2831
+rect -422 2791 0 2797
+rect -324 2348 -278 2791
+rect -243 2695 -233 2747
+rect -129 2695 -119 2747
+rect 1264 2738 1323 2781
+rect 2559 2738 2625 2801
+rect 3873 2738 3882 2778
+rect -243 2686 -144 2695
+rect -190 2646 -144 2686
+rect -190 2199 -144 2353
+rect -236 739 -98 2199
+rect 1294 783 1725 957
+rect 2588 783 3019 957
+rect 1294 779 1727 783
+rect 2588 779 3021 783
+rect 1295 746 1727 779
+rect 2589 746 3021 779
+rect -324 165 -278 599
+rect -190 597 -144 739
+rect -243 261 -119 270
+rect -243 209 -233 261
+rect -129 209 -119 261
+rect -422 159 0 165
+rect -422 125 -386 159
+rect -36 125 0 159
+rect -422 70 0 125
+rect 686 70 3266 165
+rect -422 36 -386 70
+rect -36 36 0 70
+rect -422 30 0 36
+<< via1 >>
+rect -233 2695 -129 2747
+rect -233 209 -129 261
+<< metal2 >>
+rect -233 2747 3266 2757
+rect -129 2695 3266 2747
+rect -233 2685 3266 2695
+rect 443 2631 678 2685
+rect 1736 2631 1971 2685
+rect 3031 2638 3266 2685
+rect 440 1417 608 1427
+rect 3316 1417 3440 1427
+rect 1255 1363 1757 1415
+rect 2557 1363 3030 1415
+rect 440 1351 608 1361
+rect 3651 1363 3882 1415
+rect 3316 1351 3440 1361
+rect 436 299 678 300
+rect 436 278 684 299
+rect -230 271 684 278
+rect -233 261 684 271
+rect -129 209 684 261
+rect -233 199 684 209
+rect -230 184 684 199
+rect 564 162 684 184
+rect 1730 162 1971 295
+rect 3023 162 3214 294
+rect 564 68 3215 162
+<< via2 >>
+rect 440 1361 608 1417
+rect 3316 1361 3440 1417
+<< metal3 >>
+rect 430 1421 618 1422
+rect 430 1417 441 1421
+rect 607 1417 618 1421
+rect 430 1361 440 1417
+rect 608 1361 618 1417
+rect 430 1357 441 1361
+rect 607 1357 618 1361
+rect 430 1356 618 1357
+rect 3306 1421 3450 1425
+rect 3306 1417 3317 1421
+rect 3306 1361 3316 1417
+rect 3306 1357 3317 1361
+rect 3440 1357 3450 1421
+rect 3306 1353 3450 1357
+rect 3601 868 3661 1007
+rect 983 797 993 868
+rect 1100 797 1110 868
+rect 2289 799 2299 867
+rect 2377 799 2387 867
+rect 3584 799 3594 866
+rect 3672 799 3682 866
+rect 3601 88 3661 799
+<< via3 >>
+rect 441 1417 607 1421
+rect 441 1361 607 1417
+rect 441 1357 607 1361
+rect 3317 1417 3440 1421
+rect 3317 1361 3440 1417
+rect 3317 1357 3440 1361
+rect 993 797 1100 868
+rect 2299 799 2377 867
+rect 3594 799 3672 866
+<< metal4 >>
+rect 440 1421 608 1422
+rect 3316 1421 3441 1422
+rect 440 1357 441 1421
+rect 607 1357 3317 1421
+rect 3440 1357 3441 1421
+rect 440 1356 608 1357
+rect 3316 1356 3441 1357
+rect 992 868 3680 869
+rect 992 797 993 868
+rect 1100 867 3680 868
+rect 1100 799 2299 867
+rect 2377 866 3680 867
+rect 2377 799 3594 866
+rect 3672 799 3680 866
+rect 1100 798 3680 799
+rect 1100 797 1101 798
+rect 992 796 1101 797
+use csvco_branch_v2  csvco_branch_v2_1
+timestamp 1624064496
+transform 1 0 1657 0 1 1002
+box -363 -1002 932 1955
+use csvco_branch_v2  csvco_branch_v2_2
+timestamp 1624064496
+transform 1 0 2951 0 1 1002
+box -363 -1002 932 1955
+use sky130_fd_pr__pfet_01v8_4757AC  sky130_fd_pr__pfet_01v8_4757AC_0
+timestamp 1624049879
+transform 1 0 -211 0 1 2498
+box -211 -369 211 369
+use sky130_fd_pr__nfet_01v8_CBAU6Y  sky130_fd_pr__nfet_01v8_CBAU6Y_0
+timestamp 1624049879
+transform 1 0 -211 0 1 449
+box -211 -360 211 360
+use csvco_branch_v2  csvco_branch_v2_0
+timestamp 1624064496
+transform 1 0 363 0 1 1002
+box -363 -1002 932 1955
+<< labels >>
+rlabel metal1 -422 70 0 125 1 vss
+rlabel metal1 -422 2831 0 2886 1 vdd
+rlabel metal2 3651 1363 3882 1415 1 out_vco
+rlabel metal3 3601 88 3661 148 1 D0
+rlabel metal2 -105 212 -39 260 1 vctrl
+rlabel metal2 41 2699 69 2726 1 vbp
+<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag b/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag
new file mode 100644
index 0000000..84b5fbd
--- /dev/null
+++ b/mag/sky130_fd_pr__cap_mim_m3_2_2Y8F6P.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624129585
+<< metal4 >>
+rect -3351 3059 3351 3100
+rect -3351 -3059 3095 3059
+rect 3331 -3059 3351 3059
+rect -3351 -3100 3351 -3059
+<< via4 >>
+rect 3095 -3059 3331 3059
+<< mimcap2 >>
+rect -3251 2960 2749 3000
+rect -3251 -2960 -3211 2960
+rect 2709 -2960 2749 2960
+rect -3251 -3000 2749 -2960
+<< mimcap2contact >>
+rect -3211 -2960 2709 2960
+<< metal5 >>
+rect 3053 3059 3373 3261
+rect -3235 2960 2733 2984
+rect -3235 -2960 -3211 2960
+rect 2709 -2960 2733 2960
+rect -3235 -2984 2733 -2960
+rect 3053 -3059 3095 3059
+rect 3331 -3059 3373 3059
+rect 3053 -3261 3373 -3059
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_2
+string FIXED_BBOX -3351 -3100 2849 3100
+string parameters w 30 l 30 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag b/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag
new file mode 100644
index 0000000..f567c55
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_CBSTVW.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624058804
+<< error_p >>
+rect -29 -157 29 -151
+rect -29 -191 -17 -157
+rect -29 -197 29 -191
+<< pwell >>
+rect -211 -329 211 329
+<< nmos >>
+rect -15 -119 15 181
+<< ndiff >>
+rect -73 169 -15 181
+rect -73 -107 -61 169
+rect -27 -107 -15 169
+rect -73 -119 -15 -107
+rect 15 169 73 181
+rect 15 -107 27 169
+rect 61 -107 73 169
+rect 15 -119 73 -107
+<< ndiffc >>
+rect -61 -107 -27 169
+rect 27 -107 61 169
+<< psubdiff >>
+rect -175 259 -79 293
+rect 79 259 175 293
+rect -175 197 -141 259
+rect 141 197 175 259
+rect -175 -259 -141 -197
+rect 141 -259 175 -197
+rect -175 -293 -79 -259
+rect 79 -293 175 -259
+<< psubdiffcont >>
+rect -79 259 79 293
+rect -175 -197 -141 197
+rect 141 -197 175 197
+rect -79 -293 79 -259
+<< poly >>
+rect -15 181 15 207
+rect -15 -141 15 -119
+rect -33 -157 33 -141
+rect -33 -191 -17 -157
+rect 17 -191 33 -157
+rect -33 -207 33 -191
+<< polycont >>
+rect -17 -191 17 -157
+<< locali >>
+rect -175 259 -79 293
+rect 79 259 175 293
+rect -175 197 -141 259
+rect 141 197 175 259
+rect -61 169 -27 185
+rect -61 -123 -27 -107
+rect 27 169 61 185
+rect 27 -123 61 -107
+rect -33 -191 -17 -157
+rect 17 -191 33 -157
+rect -175 -259 -141 -197
+rect 141 -259 175 -197
+rect -175 -293 -79 -259
+rect 79 -293 175 -259
+<< viali >>
+rect -61 -107 -27 169
+rect 27 -107 61 169
+rect -17 -191 17 -157
+<< metal1 >>
+rect -67 169 -21 181
+rect -67 -107 -61 169
+rect -27 -107 -21 169
+rect -67 -119 -21 -107
+rect 21 169 67 181
+rect 21 -107 27 169
+rect 61 -107 67 169
+rect 21 -119 67 -107
+rect -29 -157 29 -151
+rect -29 -191 -17 -157
+rect 17 -191 29 -157
+rect -29 -197 29 -191
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string FIXED_BBOX -158 -276 158 276
+string parameters w 1.5 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt  sky130_fd_bs_flash__special_sonosfet_star  sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt  sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag b/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag
new file mode 100644
index 0000000..8177698
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_MJP3BN.mag
@@ -0,0 +1,85 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624058804
+<< error_p >>
+rect -29 195 29 201
+rect -29 161 -17 195
+rect -29 155 29 161
+<< nwell >>
+rect -211 -334 211 334
+<< pmos >>
+rect -15 -186 15 114
+<< pdiff >>
+rect -73 102 -15 114
+rect -73 -174 -61 102
+rect -27 -174 -15 102
+rect -73 -186 -15 -174
+rect 15 102 73 114
+rect 15 -174 27 102
+rect 61 -174 73 102
+rect 15 -186 73 -174
+<< pdiffc >>
+rect -61 -174 -27 102
+rect 27 -174 61 102
+<< nsubdiff >>
+rect -175 264 -79 298
+rect 79 264 175 298
+rect -175 201 -141 264
+rect 141 201 175 264
+rect -175 -264 -141 -201
+rect 141 -264 175 -201
+rect -175 -298 -79 -264
+rect 79 -298 175 -264
+<< nsubdiffcont >>
+rect -79 264 79 298
+rect -175 -201 -141 201
+rect 141 -201 175 201
+rect -79 -298 79 -264
+<< poly >>
+rect -33 195 33 211
+rect -33 161 -17 195
+rect 17 161 33 195
+rect -33 145 33 161
+rect -15 114 15 145
+rect -15 -212 15 -186
+<< polycont >>
+rect -17 161 17 195
+<< locali >>
+rect -175 264 -79 298
+rect 79 264 175 298
+rect -175 201 -141 264
+rect 141 201 175 264
+rect -33 161 -17 195
+rect 17 161 33 195
+rect -61 102 -27 118
+rect -61 -190 -27 -174
+rect 27 102 61 118
+rect 27 -190 61 -174
+rect -175 -264 -141 -201
+rect 141 -264 175 -201
+rect -175 -298 -79 -264
+rect 79 -298 175 -264
+<< viali >>
+rect -17 161 17 195
+rect -61 -174 -27 102
+rect 27 -174 61 102
+<< metal1 >>
+rect -29 195 29 201
+rect -29 161 -17 195
+rect 17 161 29 195
+rect -29 155 29 161
+rect -67 102 -21 114
+rect -67 -174 -61 102
+rect -27 -174 -21 102
+rect -67 -186 -21 -174
+rect 21 102 67 114
+rect 21 -174 27 102
+rect 61 -174 67 102
+rect 21 -186 67 -174
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string FIXED_BBOX -158 -281 158 281
+string parameters w 1.5 l 0.15 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8  sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt  sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+string library sky130
+<< end >>
diff --git a/xschem/csvco_branch_v2.sch b/xschem/csvco_branch_v2.sch
new file mode 100644
index 0000000..5cd32b9
--- /dev/null
+++ b/xschem/csvco_branch_v2.sch
@@ -0,0 +1,92 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 540 -300 540 -270 { lab=vdd_inv}
+N 540 -70 580 -70 { lab=vss}
+N 440 -220 500 -220 { lab=in}
+N 630 -220 700 -220 { lab=out}
+N 540 -350 540 -300 { lab=vdd_inv}
+N 540 -440 540 -410 { lab=vdd}
+N 540 -380 570 -380 { lab=vdd}
+N 540 -170 540 -100 { lab=vss_inv}
+N 540 -40 540 0 { lab=vss}
+N 460 -70 500 -70 { lab=vctrl}
+N 580 -190 580 -150 { lab=vss}
+N 580 -280 580 -250 { lab=vdd}
+N 700 -220 760 -220 { lab=out}
+N 900 -220 1440 -220 { lab=out}
+N 760 -220 900 -220 { lab=out}
+N 460 -380 500 -380 { lab=vbp}
+N 1440 -220 1490 -220 { lab=out}
+N 1070 -220 1070 -180 { lab=out}
+N 1000 -150 1030 -150 { lab=D0}
+N 1070 -150 1110 -150 { lab=vss}
+N 1070 -120 1070 -80 { lab=#net1}
+N 1070 -20 1070 20 { lab=vss}
+C {lab_pin.sym} 580 -70 2 0 {name=l3 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} 520 -380 0 0 {name=M1
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_pin.sym} 570 -380 2 0 {name=l2 sig_type=std_logic lab=vdd}
+C {ipin.sym} 460 -70 0 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 580 -150 3 0 {name=l127 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 580 -280 1 0 {name=l139 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 640 -220 0 1 {name=l106 sig_type=std_logic lab=out}
+C {ipin.sym} 460 -380 0 0 {name=p1 sig_type=std_logic lab=vbp}
+C {iopin.sym} 540 -440 3 0 {name=p6 sig_type=std_logic lab=vdd}
+C {iopin.sym} 540 0 1 0 {name=p7 sig_type=std_logic lab=vss}
+C {ipin.sym} 440 -220 0 0 {name=p8 sig_type=std_logic lab=in}
+C {opin.sym} 1490 -220 0 0 {name=p9 sig_type=std_logic lab=out}
+C {lab_wire.sym} 540 -340 3 0 {name=l1 sig_type=std_logic lab=vdd_inv}
+C {lab_wire.sym} 540 -160 3 0 {name=l4 sig_type=std_logic lab=vss_inv}
+C {sky130_fd_pr/nfet_01v8.sym} 520 -70 0 0 {name=M2
+L=0.15
+W=1.5
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1050 -150 0 0 {name=M4
+L=0.15
+W=0.42
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {ipin.sym} 1000 -150 0 0 {name=p3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 1110 -150 2 0 {name=l8 sig_type=std_logic lab=vss}
+C {capa.sym} 1070 -50 0 0 {name=C1
+m=1
+value=5.78f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1070 20 3 0 {name=l5 sig_type=std_logic lab=vss}
+C {inverter_csvco.sym} 560 -220 0 0 {name=x1}
diff --git a/xschem/csvco_branch_v2.sym b/xschem/csvco_branch_v2.sym
new file mode 100644
index 0000000..0289106
--- /dev/null
+++ b/xschem/csvco_branch_v2.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -70 -40 -50 -40 {}
+L 4 -70 0 -50 0 {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 -70 -50 70 {}
+L 4 -50 70 50 70 {}
+L 4 50 -70 50 70 {}
+L 4 -50 -70 50 -70 {}
+L 4 40 70 40 90 {}
+L 7 0 -90 0 -70 {}
+L 7 0 70 0 90 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd sig_type=std_logic dir=inout }
+B 5 -72.5 -42.5 -67.5 -37.5 {name=vbp sig_type=std_logic dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=in sig_type=std_logic dir=in }
+B 5 67.5 -2.5 72.5 2.5 {name=out sig_type=std_logic dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=vctrl sig_type=std_logic dir=in }
+B 5 -2.5 87.5 2.5 92.5 {name=vss sig_type=std_logic dir=inout }
+B 5 37.5 87.5 42.5 92.5 {name=D0 sig_type=std_logic dir=in }
+T {@symname} 58 54 0 0 0.3 0.3 {}
+T {@name} -15 -2 0 0 0.2 0.2 {}
+T {vdd} -4 -65 3 1 0.2 0.2 {}
+T {vbp} -45 -44 0 0 0.2 0.2 {}
+T {in} -45 -4 0 0 0.2 0.2 {}
+T {out} 45 -4 0 1 0.2 0.2 {}
+T {vctrl} -45 36 0 0 0.2 0.2 {}
+T {vss} 4 65 1 1 0.2 0.2 {}
+T {D0} 36 65 3 0 0.2 0.2 {}
diff --git a/xschem/csvco_v2.sch b/xschem/csvco_v2.sch
new file mode 100644
index 0000000..c7f8414
--- /dev/null
+++ b/xschem/csvco_v2.sch
@@ -0,0 +1,93 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N -210 -150 -210 -120 { lab=vdd}
+N -320 10 -280 10 { lab=vctrl}
+N -510 10 -470 10 { lab=vss}
+N -470 40 -470 80 { lab=vss}
+N -430 10 -390 10 { lab=vctrl}
+N -470 -130 -470 -100 { lab=vdd}
+N -500 -70 -470 -70 { lab=vdd}
+N -210 60 -210 100 { lab=vss}
+N -170 60 -170 70 { lab=D0}
+N -430 -70 -280 -70 { lab=vbp}
+N -470 -30 -420 -30 { lab=vbp}
+N -420 -30 -410 -30 { lab=vbp}
+N -410 -70 -410 -30 { lab=vbp}
+N -470 -30 -470 -20 { lab=vbp}
+N -470 -40 -470 -30 { lab=vbp}
+N -390 10 -320 10 { lab=vctrl}
+N -350 10 -350 70 { lab=vctrl}
+N -340 -30 -280 -30 { lab=out}
+N -140 -30 -70 -30 { lab=out1}
+N -70 -30 30 -30 { lab=out1}
+N -10 -70 30 -70 { lab=vbp}
+N -10 10 30 10 { lab=vctrl}
+N 100 -150 100 -120 { lab=vdd}
+N 100 60 100 100 { lab=vss}
+N 140 60 140 70 { lab=D0}
+N 170 -30 240 -30 { lab=out2}
+N 240 -30 340 -30 { lab=out2}
+N 300 -70 340 -70 { lab=vbp}
+N 300 10 340 10 { lab=vctrl}
+N 410 -150 410 -120 { lab=vdd}
+N 410 60 410 100 { lab=vss}
+N 450 60 450 70 { lab=D0}
+N 480 -30 540 -30 { lab=out}
+C {lab_pin.sym} -210 -150 1 0 {name=l5 sig_type=std_logic lab=vdd}
+C {ipin.sym} -350 70 3 0 {name=p83 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} -510 10 2 1 {name=l83 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} -450 10 0 1 {name=M1
+L=0.15
+W=1.5
+nf=1 
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 80 3 1 {name=p84 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/pfet_01v8.sym} -450 -70 0 1 {name=M2
+L=0.15
+W=1.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'" 
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'" 
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {iopin.sym} -470 -130 1 1 {name=p86 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} -500 -70 2 1 {name=l87 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} -350 -70 0 1 {name=l88 sig_type=std_logic lab=vbp}
+C {opin.sym} 540 -30 2 1 {name=p1 sig_type=std_logic lab=out}
+C {lab_pin.sym} -210 100 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {ipin.sym} -170 70 3 0 {name=p6 sig_type=std_logic lab=D0}
+C {lab_wire.sym} -340 -30 0 1 {name=l8 sig_type=std_logic lab=out}
+C {lab_wire.sym} -70 -30 0 1 {name=l12 sig_type=std_logic lab=out1}
+C {lab_pin.sym} -10 -70 0 0 {name=l32 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} -10 10 0 0 {name=l33 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 100 -150 1 0 {name=l34 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 100 100 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 140 70 3 0 {name=l46 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 300 -70 0 0 {name=l36 sig_type=std_logic lab=vbp}
+C {lab_pin.sym} 300 10 0 0 {name=l37 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 410 -150 1 0 {name=l38 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 100 3 0 {name=l39 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 450 70 3 0 {name=l47 sig_type=std_logic lab=D0}
+C {lab_wire.sym} 240 -30 0 1 {name=l48 sig_type=std_logic lab=out2}
+C {csvco_branch_v2.sym} -210 -30 0 0 {name=x2}
+C {csvco_branch_v2.sym} 100 -30 0 0 {name=x3}
+C {csvco_branch_v2.sym} 410 -30 0 0 {name=x4}
diff --git a/xschem/csvco_v2.sym b/xschem/csvco_v2.sym
new file mode 100644
index 0000000..52a2546
--- /dev/null
+++ b/xschem/csvco_v2.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -70 0 -50 0 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {D0} -66.5 27.5 0 0 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
diff --git a/xschem/csvco_v2_pex_c.sym b/xschem/csvco_v2_pex_c.sym
new file mode 100644
index 0000000..b24a424
--- /dev/null
+++ b/xschem/csvco_v2_pex_c.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=primitive
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 50 0 70 0 {}
+L 4 -70 0 -50 0 {}
+L 4 -70 40 -50 40 {}
+L 4 -50 40 -40 30 {}
+L 7 0 -70 0 -50 {}
+L 7 0 50 0 70 {}
+B 5 -2.5 -72.5 2.5 -67.5 {name=vdd dir=inout }
+B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
+B 5 -72.5 -2.5 -67.5 2.5 {name=vctrl dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+B 5 -72.5 37.5 -67.5 42.5 {name=D0 dir=in }
+A 4 -0.1779661016949153 0 50.00031671833042 89.79606673072159 360 {}
+A 4 -14 12.5 18.76832437912346 41.76029970389787 96.47940059220427 {}
+A 4 14 -12.5 18.76832437912346 221.7602997038979 96.47940059220427 {}
+T {@symname} 7.5 52 0 0 0.3 0.3 {}
+T {@name} -15.5 -42.5 0 0 0.2 0.2 {}
+T {vdd} -14.5 -71.5 3 1 0.2 0.2 {}
+T {out} 73.5 -13.5 0 1 0.2 0.2 {}
+T {vctrl} -73.5 -14 0 0 0.2 0.2 {}
+T {vss} -1.5 68.5 1 1 0.2 0.2 {}
+T {D0} -73.5 26 0 0 0.2 0.2 {}
diff --git a/xschem/simulations/csvco_branch_v2.spice b/xschem/simulations/csvco_branch_v2.spice
new file mode 100644
index 0000000..4812219
--- /dev/null
+++ b/xschem/simulations/csvco_branch_v2.spice
@@ -0,0 +1,41 @@
+**.subckt csvco_branch_v2 vctrl vbp vdd vss in out D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+C1 net1 vss 5.78f m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+**.ends
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_v2.spice b/xschem/simulations/csvco_v2.spice
new file mode 100644
index 0000000..325c09e
--- /dev/null
+++ b/xschem/simulations/csvco_v2.spice
@@ -0,0 +1,62 @@
+**.subckt csvco_v2 vctrl vss vdd out D0
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x2 vdd vbp out out1 vctrl vss D0 csvco_branch_v2
+x3 vdd vbp out1 out2 vctrl vss D0 csvco_branch_v2
+x4 vdd vbp out2 out vctrl vss D0 csvco_branch_v2
+**.ends
+
+* expanding   symbol:  csvco_branch_v2.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sch
+.subckt csvco_branch_v2  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco
+C1 net1 vss 5.78f m=1
+.ends
+
+
+* expanding   symbol:  inverter_csvco.sym # of pins=6
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+.subckt inverter_csvco  vdd out in vss vbulkp vbulkn
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+*.iopin vbulkn
+*.iopin vbulkp
+XM1 out in vss vbulkn sky130_fd_pr__nfet_01v8 L=0.2 W=0.75 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out in vdd vbulkp sky130_fd_pr__pfet_01v8 L=0.2 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/csvco_v2_pex_c.spice b/xschem/simulations/csvco_v2_pex_c.spice
new file mode 100644
index 0000000..1507fd5
--- /dev/null
+++ b/xschem/simulations/csvco_v2_pex_c.spice
@@ -0,0 +1,174 @@
+* NGSPICE file created from ring_osc_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n150# a_n73_n150# 0.51fF
+C1 a_15_n150# a_n33_n238# 0.02fF
+C2 a_n33_n238# a_n73_n150# 0.02fF
+C3 a_15_n150# w_n211_n360# 0.23fF
+C4 a_n73_n150# w_n211_n360# 0.23fF
+C5 a_n33_n238# w_n211_n360# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBSTVW a_n73_n119# a_n33_n207# w_n211_n329# a_15_n119#
+X0 a_15_n119# a_n33_n207# a_n73_n119# w_n211_n329# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n119# a_n73_n119# 0.51fF
+C1 a_15_n119# a_n33_n207# 0.02fF
+C2 a_n33_n207# a_n73_n119# 0.02fF
+C3 a_15_n119# w_n211_n329# 0.24fF
+C4 a_n73_n119# w_n211_n329# 0.24fF
+C5 a_n33_n207# w_n211_n329# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJP3BN VSUBS a_15_n186# w_n211_n334# a_n33_145# a_n73_n186#
+X0 a_15_n186# a_n33_145# a_n73_n186# w_n211_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_15_n186# w_n211_n334# 0.21fF
+C1 a_n73_n186# a_n33_145# 0.01fF
+C2 a_n73_n186# w_n211_n334# 0.21fF
+C3 a_15_n186# a_n73_n186# 0.51fF
+C4 w_n211_n334# a_n33_145# 0.05fF
+C5 a_15_n186# a_n33_145# 0.01fF
+C6 a_15_n186# VSUBS 0.03fF
+C7 a_n73_n186# VSUBS 0.03fF
+C8 a_n33_145# VSUBS 0.12fF
+C9 w_n211_n334# VSUBS 1.81fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_15_n11# a_n73_n11# 0.15fF
+C1 a_15_n11# a_n33_n99# 0.02fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
+C3 a_15_n11# w_n211_n221# 0.09fF
+C4 a_n73_n11# w_n211_n221# 0.09fF
+C5 a_n33_n99# w_n211_n221# 0.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+C0 a_20_n106# a_n78_n106# 0.21fF
+C1 a_20_n106# w_n216_n254# 0.14fF
+C2 a_n78_n106# w_n216_n254# 0.14fF
+C3 a_n33_66# w_n216_n254# 0.12fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+C0 a_20_n114# w_n216_n334# 0.20fF
+C1 a_n78_n114# w_n216_n334# 0.20fF
+C2 a_20_n114# a_n78_n114# 0.42fF
+C3 a_20_n114# VSUBS 0.03fF
+C4 a_n78_n114# VSUBS 0.03fF
+C5 a_n33_n211# VSUBS 0.12fF
+C6 w_n216_n334# VSUBS 1.66fF
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+C0 out vbulkp 0.08fF
+C1 out in 0.11fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in vdd 0.01fF
+C5 vbulkp vbulkn 2.49fF
+C6 out vbulkn 0.60fF
+C7 vdd vbulkn 0.06fF
+C8 in vbulkn 0.54fF
+C9 vss vbulkn 0.17fF
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+C1 t VSUBS 0.42fF
+C2 b VSUBS 0.09fF
+.ends
+
+.subckt csvco_branch_v2 vctrl in cap_vco_0/t D0 out m1_185_1641# vss vdd inverter_csvco_0/vss
+Xsky130_fd_pr__nfet_01v8_CBSTVW_0 inverter_csvco_0/vss vctrl vss vss sky130_fd_pr__nfet_01v8_CBSTVW
+Xsky130_fd_pr__pfet_01v8_MJP3BN_0 vss vdd vdd m1_185_1641# inverter_csvco_0/vdd sky130_fd_pr__pfet_01v8_MJP3BN
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+C0 vdd out 0.03fF
+C1 out inverter_csvco_0/vdd 0.02fF
+C2 vctrl cap_vco_0/t 0.03fF
+C3 D0 cap_vco_0/t 0.18fF
+C4 vdd m1_185_1641# 0.48fF
+C5 inverter_csvco_0/vss vctrl 0.23fF
+C6 inverter_csvco_0/vdd m1_185_1641# 0.13fF
+C7 inverter_csvco_0/vss cap_vco_0/t 0.12fF
+C8 D0 inverter_csvco_0/vss 0.01fF
+C9 in inverter_csvco_0/vss 0.01fF
+C10 in inverter_csvco_0/vdd 0.01fF
+C11 out cap_vco_0/t 0.11fF
+C12 D0 out 0.09fF
+C13 out in 0.06fF
+C14 vdd inverter_csvco_0/vdd 0.97fF
+C15 out inverter_csvco_0/vss 0.03fF
+C16 vdd vss 3.58fF
+C17 out vss 0.87fF
+C18 inverter_csvco_0/vdd vss 0.14fF
+C19 in vss 0.70fF
+C20 inverter_csvco_0/vss vss 0.72fF
+C21 D0 vss -0.49fF
+C22 m1_185_1641# vss -0.03fF
+C23 cap_vco_0/t vss 8.30fF
+C24 vctrl vss 0.44fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+C0 a_n73_n150# a_15_n150# 0.51fF
+C1 a_15_n150# a_n33_181# 0.01fF
+C2 w_n211_n369# a_15_n150# 0.20fF
+C3 a_n73_n150# a_n33_181# 0.01fF
+C4 w_n211_n369# a_n73_n150# 0.20fF
+C5 w_n211_n369# a_n33_181# 0.05fF
+C6 a_15_n150# VSUBS 0.03fF
+C7 a_n73_n150# VSUBS 0.03fF
+C8 a_n33_181# VSUBS 0.13fF
+C9 w_n211_n369# VSUBS 1.98fF
+.ends
+
+.subckt csvco_v2_pex_c vdd out_vco D0 vctrl vss
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xcsvco_branch_v2_1 vctrl csvco_branch_v2_1/in csvco_branch_v2_1/cap_vco_0/t D0 csvco_branch_v2_2/in
++ vbp vss vdd csvco_branch_v2_1/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_0 vctrl out_vco csvco_branch_v2_0/cap_vco_0/t D0 csvco_branch_v2_1/in
++ vbp vss vdd csvco_branch_v2_0/inverter_csvco_0/vss csvco_branch_v2
+Xcsvco_branch_v2_2 vctrl csvco_branch_v2_2/in csvco_branch_v2_2/cap_vco_0/t D0 out_vco
++ vbp vss vdd csvco_branch_v2_2/inverter_csvco_0/vss csvco_branch_v2
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd vbp vdd vbp sky130_fd_pr__pfet_01v8_4757AC
+C0 csvco_branch_v2_0/cap_vco_0/t vctrl 0.24fF
+C1 csvco_branch_v2_1/in out_vco 0.76fF
+C2 csvco_branch_v2_1/inverter_csvco_0/vss D0 0.04fF
+C3 csvco_branch_v2_0/cap_vco_0/t D0 0.12fF
+C4 csvco_branch_v2_2/in vdd 0.01fF
+C5 vbp vdd 3.04fF
+C6 vctrl vbp 0.06fF
+C7 vctrl csvco_branch_v2_1/cap_vco_0/t 0.24fF
+C8 csvco_branch_v2_2/in out_vco 0.59fF
+C9 D0 csvco_branch_v2_2/inverter_csvco_0/vss 0.04fF
+C10 D0 csvco_branch_v2_2/cap_vco_0/t 1.03fF
+C11 csvco_branch_v2_1/in vdd 0.01fF
+C12 D0 csvco_branch_v2_1/cap_vco_0/t 0.12fF
+C13 vdd vss 14.19fF
+C14 csvco_branch_v2_2/inverter_csvco_0/vdd vss 0.14fF
+C15 csvco_branch_v2_2/inverter_csvco_0/vss vss 0.44fF
+C16 csvco_branch_v2_2/cap_vco_0/t vss 7.06fF
+C17 csvco_branch_v2_1/in vss 1.66fF
+C18 csvco_branch_v2_0/inverter_csvco_0/vdd vss 0.14fF
+C19 out_vco vss 0.49fF
+C20 csvco_branch_v2_0/inverter_csvco_0/vss vss 0.44fF
+C21 D0 vss -1.24fF
+C22 vbp vss -0.38fF
+C23 csvco_branch_v2_0/cap_vco_0/t vss 7.07fF
+C24 vctrl vss 5.55fF
+C25 csvco_branch_v2_2/in vss 1.67fF
+C26 csvco_branch_v2_1/inverter_csvco_0/vdd vss 0.14fF
+C27 csvco_branch_v2_1/inverter_csvco_0/vss vss 0.44fF
+C28 csvco_branch_v2_1/cap_vco_0/t vss 7.07fF
+.ends
+
diff --git a/xschem/simulations/tb_csvco_v2.spice b/xschem/simulations/tb_csvco_v2.spice
new file mode 100644
index 0000000..37d8c8b
--- /dev/null
+++ b/xschem/simulations/tb_csvco_v2.spice
@@ -0,0 +1,219 @@
+**.subckt tb_csvco_v2
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+VD0 D0 vss DC {vd0} 
+x3 vdd out_ro D0 vctrl vss csvco_v2
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  csvco_v2.sym # of pins=5
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_v2.sch
+.subckt csvco_v2  vdd out D0 vctrl vss
+*.ipin vctrl
+*.iopin vss
+*.iopin vdd
+*.opin out
+*.ipin D0
+XM1 vbp vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vbp vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+x2 vdd vbp out out1 vctrl vss D0 csvco_branch_v2
+x3 vdd vbp out1 out2 vctrl vss D0 csvco_branch_v2
+x4 vdd vbp out2 out vctrl vss D0 csvco_branch_v2
+.ends
+
+
+* expanding   symbol:  csvco_branch_v2.sym # of pins=7
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch_v2.sch
+.subckt csvco_branch_v2  vdd vbp in out vctrl vss D0
+*.ipin vctrl
+*.ipin vbp
+*.iopin vdd
+*.iopin vss
+*.ipin in
+*.opin out
+*.ipin D0
+XM1 vdd_inv vbp vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 vss_inv vctrl vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=1.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM4 out D0 net1 vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+C1 net1 vss 5.78f m=1
+x1 vdd_inv out in vss_inv vdd vss inverter_csvco_pex_c
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/tb_csvco_v2_pex_c.spice b/xschem/simulations/tb_csvco_v2_pex_c.spice
new file mode 100644
index 0000000..69cf631
--- /dev/null
+++ b/xschem/simulations/tb_csvco_v2_pex_c.spice
@@ -0,0 +1,173 @@
+**.subckt tb_csvco_v2_pex_c
+vss vss GND {vss} 
+vdd vdd vss {vdd} 
+x1 vdd out_ro_n out_ro vss inverter_min_x2
+x2 vdd out_ro_buf out_ro_n vss inverter_min_x4
+C1 out_ro_buf vss 10f m=1
+Vctrl vctrl vss DC {vctrl} 
+VD0 D0 vss DC {vd0} 
+x3 vdd out_ro vctrl vss D0 csvco_v2_pex_c
+**** begin user architecture code
+
+
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_v2_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 200ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo .
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  inverter_min_x2.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+.subckt inverter_min_x2  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+.GLOBAL GND
+** flattened .save nodes
+.end
diff --git a/xschem/tb_csvco_v2.sch b/xschem/tb_csvco_v2.sch
new file mode 100644
index 0000000..325ca90
--- /dev/null
+++ b/xschem/tb_csvco_v2.sch
@@ -0,0 +1,184 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+
+.options TEMP = 100.0
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib SS
+.include ~/caravel_analog_fulgor/xschem/simulations/inverter_csvco_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 50ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo . 
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l11 sig_type=std_logic lab=D0}
+C {csvco_v2.sym} 510 0 0 0 {name=x3}
diff --git a/xschem/tb_csvco_v2_pex_c.sch b/xschem/tb_csvco_v2_pex_c.sch
new file mode 100644
index 0000000..3611bd2
--- /dev/null
+++ b/xschem/tb_csvco_v2_pex_c.sch
@@ -0,0 +1,184 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 30 70 70 { lab=GND}
+N 70 -60 70 -30 { lab=vss}
+N 150 -60 150 -30 { lab=vdd}
+N 150 30 150 70 { lab=vss}
+N 760 0 850 0 { lab=out_ro_n}
+N 670 50 670 80 { lab=vss}
+N 670 80 890 80 { lab=vss}
+N 890 50 890 80 { lab=vss}
+N 1050 0 1050 50 { lab=out_ro_buf}
+N 980 0 1050 0 { lab=out_ro_buf}
+N 1050 110 1050 150 { lab=vss}
+N 240 -60 240 -30 { lab=vctrl}
+N 240 30 240 70 { lab=vss}
+N 510 80 670 80 { lab=vss}
+N 380 0 410 0 { lab=vctrl}
+N 280 -370 280 -340 { lab=D0}
+N 280 -280 280 -240 { lab=vss}
+N 580 -0 630 -0 { lab=out_ro}
+N 510 70 510 80 { lab=vss}
+N 410 -0 440 -0 { lab=vctrl}
+N 510 -100 510 -70 { lab=vdd}
+N 670 -80 670 -50 { lab=vdd}
+N 890 -80 890 -50 { lab=vdd}
+N 410 40 440 40 { lab=D0}
+C {netlist_not_shown.sym} 80 -320 0 0 {name=simulation only_toplevel=false 
+value="
+
+* Parameters
+.param kp = 1.0
+.param vdd = kp*1.8
+.param vss = 0.0
+.param vin = vdd
+.param vctrl = 0.0
+.param vd0 = 0.0
+
+.options TEMP = 0.0
+.options RSHUNT = 1e20
+
+* Models
+.lib ~/skywater/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/sky130.lib FF
+.include ~/caravel_analog_fulgor/xschem/simulations/csvco_v2_pex_c.spice
+
+
+* Data to save
+.save all
+
+.ic v(out_ro) = 0.0
+.ic v(x3.out1) = 0.0
+.ic v(x3.out2) = 0.0
+.ic v(x3.out) = 0.0
+
+* Simulation
+.control
+let i = 0.0
+while i <= 1.9
+      tran 0.01ns 200ns
+      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+      let T = Tosc/10.0
+      let Tbuf = Toscbuf/10.0
+      let f = 1/T
+      let fbuf = 1/Tbuf
+      let Td = 1/(2*3*f)
+      print T Tbuf f fbuf Td
+      let i = i + 0.1
+      alterparam vctrl = $&i
+      reset
+end
+echo . 
+echo ----- Vctrl = 0.0 -----
+print tran1.f
+echo ----- Vctrl = 0.1 -----
+print tran2.f
+echo ----- Vctrl = 0.2 -----
+print tran3.f
+echo ----- Vctrl = 0.3 -----
+print tran4.f
+echo ----- Vctrl = 0.4 -----
+print tran5.f
+echo ----- Vctrl = 0.5 -----
+print tran6.f
+echo ----- Vctrl = 0.6 -----
+print tran7.f
+echo ----- Vctrl = 0.7 -----
+print tran8.f
+echo ----- Vctrl = 0.8 -----
+print tran9.f
+echo ----- Vctrl = 0.9 -----
+print tran10.f
+echo ----- Vctrl = 1.0 -----
+print tran11.f
+echo ----- Vctrl = 1.1 -----
+print tran12.f
+echo ----- Vctrl = 1.2 -----
+print tran13.f
+echo ----- Vctrl = 1.3 -----
+print tran14.f
+echo ----- Vctrl = 1.4 -----
+print tran15.f
+echo ----- Vctrl = 1.5 -----
+print tran16.f
+echo ----- Vctrl = 1.6 -----
+print tran17.f
+echo ----- Vctrl = 1.7 -----
+print tran18.f
+echo ----- Vctrl = 1.8 -----
+print tran19.f
+
+*plot tran1.f tran2.f
+
+*  let i = 0
+*  let j = 0
+*  while j < 2
+*    while i < 2
+*      tran 0.1ns 100us
+*      meas tran Tosc trig v(out_ro) val=0.9 fall=5 targ v(out_ro) val=0.9 fall=15
+*      meas tran Toscbuf trig v(out_ro_buf) val=0.9 fall=5 targ v(out_ro_buf) val=0.9 fall=15
+*      let T = Tosc/10.0
+*      let Tbuf = Toscbuf/10.0
+*      let f = 1/T
+*      let fbuf = 1/Tbuf
+*      let Td = 1/(2*3*f)
+*      print T Tbuf f fbuf Td
+*      let i = i + 1
+*      alterparam vctrl = 1.8
+*      reset
+*    end
+*    alterparam vctrl = 0.7
+*    alterparam vd0 = 0.0
+*    alterparam vd1 = 1.8
+*    alterparam vd2 = 1.8
+*    alterpatam vd3 = 0.0
+*    let i = 0
+*    let j = j + 1
+*    reset
+*  end
+*  plot v(tran1.out_ro) v(tran1.out_ro_buf)+2
+*  plot v(tran2.out_ro) v(tran2.out_ro_buf)+2
+*  plot v(tran3.out_ro) v(tran3.out_ro_buf)+2
+*  plot v(tran4.out_ro) v(tran4.out_ro_buf)+2
+*  print tran1.f tran2.f tran3.f tran4.f
+*  let frange_vtun_0 = tran2.f - tran1.f
+*  let frange_vtun_1 = tran4.f - tran3.f
+*  print frange_vtun_0 frange_vtun_1
+.endc
+
+.end
+"}
+C {vsource.sym} 70 0 0 0 {name=vss value=\{vss\}}
+C {gnd.sym} 70 70 0 0 {name=l7 lab=GND}
+C {vsource.sym} 150 0 0 0 {name=vdd value=\{vdd\}}
+C {lab_pin.sym} 70 -60 1 0 {name=l8 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 150 -60 1 0 {name=l9 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 150 70 3 0 {name=l12 sig_type=std_logic lab=vss}
+C {inverter_min_x2.sym} 690 0 0 0 {name=x1}
+C {inverter_min_x4.sym} 910 0 0 0 {name=x2}
+C {capa.sym} 1050 80 0 0 {name=C1
+m=1
+value=10f
+footprint=1206
+device="ceramic capacitor"}
+C {lab_pin.sym} 1050 150 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 830 0 0 0 {name=l24 sig_type=std_logic lab=out_ro_n}
+C {lab_wire.sym} 1040 0 0 0 {name=l25 sig_type=std_logic lab=out_ro_buf}
+C {lab_wire.sym} 820 80 0 0 {name=l27 sig_type=std_logic lab=vss}
+C {vsource.sym} 240 0 0 0 {name=Vctrl value="DC \{vctrl\}" }
+C {lab_pin.sym} 240 -60 1 0 {name=l49 sig_type=std_logic lab=vctrl}
+C {lab_pin.sym} 240 70 3 0 {name=l50 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 380 0 0 0 {name=l1 sig_type=std_logic lab=vctrl}
+C {lab_wire.sym} 620 0 0 0 {name=l2 sig_type=std_logic lab=out_ro}
+C {vsource.sym} 280 -310 0 0 {name=VD0 value="DC \{vd0\}" }
+C {lab_pin.sym} 280 -370 1 0 {name=l3 sig_type=std_logic lab=D0}
+C {lab_pin.sym} 280 -240 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 510 -100 1 0 {name=l30 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 670 -80 1 0 {name=l26 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 890 -80 1 0 {name=l43 sig_type=std_logic lab=vdd}
+C {lab_pin.sym} 410 40 0 0 {name=l5 sig_type=std_logic lab=D0}
+C {csvco_v2_pex_c.sym} 510 0 0 0 {name=x3}