diff --git a/mag/afernandez_residue_amplifier/res_amp_top.mag b/mag/afernandez_residue_amplifier/res_amp_top.mag
index 85be0c2..cf22c7f 100644
--- a/mag/afernandez_residue_amplifier/res_amp_top.mag
+++ b/mag/afernandez_residue_amplifier/res_amp_top.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1624402156
+timestamp 1624471326
 << nwell >>
 rect 18234 4138 21604 4172
 << pwell >>
@@ -469,6 +469,7 @@
 rect 7936 7205 8696 7471
 rect 11259 6504 11353 6610
 rect 19819 8489 20467 8935
+rect 18358 6216 18645 7205
 rect 28373 6957 29021 7403
 rect 21744 6516 21940 6620
 rect -4945 1523 -4297 1969
@@ -483,6 +484,7 @@
 rect 9277 2391 9430 2471
 rect -107 500 77 579
 rect -3006 -27 -2358 419
+rect 18362 1138 18649 2127
 rect 21745 1699 21941 1803
 rect 12813 895 13201 1085
 rect 15257 783 15796 949
@@ -526,26 +528,31 @@
 rect 19809 8484 20477 8489
 rect 7797 7205 7936 7471
 rect 8696 7205 8854 7471
-rect 7797 4525 8854 7205
 rect 28363 7403 29031 7408
+rect 7797 4525 8854 7205
+rect 18348 7205 18655 7210
+rect 18348 7194 18358 7205
 rect 10855 6954 10865 7060
 rect 10959 6954 10969 7060
 rect 11459 6958 11469 7064
 rect 11563 6958 11573 7064
 rect 12458 6951 12468 7057
 rect 12562 6951 12572 7057
-rect 28363 6957 28373 7403
-rect 29021 6957 29031 7403
-rect 28363 6952 29031 6957
-rect 21734 6620 21950 6625
 rect 11249 6610 11363 6615
 rect 11249 6504 11259 6610
 rect 11353 6504 11363 6610
 rect 11249 6499 11363 6504
 rect 14157 6163 15942 6545
+rect 17483 6216 18358 7194
+rect 18645 6216 18655 7205
+rect 28363 6957 28373 7403
+rect 29021 6957 29031 7403
+rect 28363 6952 29031 6957
+rect 21734 6620 21950 6625
 rect 21734 6516 21744 6620
 rect 21940 6516 21950 6620
 rect 21734 6511 21950 6516
+rect 18348 6211 18655 6216
 rect 15131 5204 15351 5209
 rect 15131 4691 15141 5204
 rect 15341 4691 15351 5204
@@ -593,20 +600,25 @@
 rect 27116 2914 27336 2919
 rect 17802 2552 17812 2700
 rect 18033 2552 18043 2700
+rect 18352 2127 18659 2132
 rect -4955 1969 -4287 1974
 rect -4955 1523 -4945 1969
 rect -4297 1523 -4287 1969
 rect 14152 1733 15942 2115
-rect 21735 1803 21951 1808
 rect -4955 1518 -4287 1523
 rect 12803 1085 13211 1090
 rect 12803 895 12813 1085
 rect 13201 895 13211 1085
 rect 15316 954 15765 1733
+rect 17444 1138 18362 2127
+rect 18649 1138 18659 2127
+rect 21735 1803 21951 1808
 rect 21735 1699 21745 1803
 rect 21941 1699 21951 1803
 rect 21735 1694 21951 1699
+rect 17444 1133 18659 1138
 rect 28395 1367 29063 1372
+rect 17444 1118 18362 1133
 rect 12803 890 13211 895
 rect 15247 949 15806 954
 rect 15247 783 15257 949
@@ -641,8 +653,8 @@
 rect 10865 6954 10959 7060
 rect 11469 6958 11563 7064
 rect 12468 6951 12562 7057
-rect 28373 6957 29021 7403
 rect 11259 6504 11353 6610
+rect 28373 6957 29021 7403
 rect 15141 4691 15341 5204
 rect -3014 4004 -2366 4450
 rect 8505 4266 8631 4334
@@ -720,6 +732,7 @@
 rect 28372 6956 29022 6957
 rect 12467 6950 12563 6951
 rect 17640 5768 18034 5769
+rect 16535 5205 16887 5720
 rect 17640 5620 17812 5768
 rect 18033 5620 18034 5768
 rect 17640 5619 18034 5620
@@ -750,6 +763,7 @@
 rect 15341 3307 15342 3621
 rect 15341 3108 17841 3307
 rect 15140 3107 17841 3108
+rect 16535 2596 16887 3107
 rect 17641 2701 17841 3107
 rect 27125 3126 27327 3127
 rect 27125 2919 27126 3126
@@ -892,12 +906,20 @@
 rect 20467 -611 20491 -605
 rect 19795 -635 20491 -611
 rect -4958 -972 -4262 -948
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF  sky130_fd_pr__cap_mim_m3_1_U5ZKVF_0
+timestamp 1624471326
+transform 1 0 16786 0 1 6344
+box -700 -850 699 850
+use sky130_fd_pr__cap_mim_m3_1_U5ZKVF  sky130_fd_pr__cap_mim_m3_1_U5ZKVF_1
+timestamp 1624471326
+transform 1 0 16786 0 1 1968
+box -700 -850 699 850
 use res_amp_lin_prog  res_amp_lin_prog_0
-timestamp 1624402156
+timestamp 1624397222
 transform 1 0 -5726 0 1 -7077
 box 5835 7077 21302 14799
 use res_amp_sync_v2  res_amp_sync_v2_0
-timestamp 1624402156
+timestamp 1624397222
 transform 1 0 -899 0 1 4870
 box -92 -2189 8342 7015
 use source_follower_buff_diff  source_follower_buff_diff_0
diff --git a/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag b/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag
new file mode 100644
index 0000000..51c0b09
--- /dev/null
+++ b/mag/afernandez_residue_amplifier/sky130_fd_pr__cap_mim_m3_1_U5ZKVF.mag
@@ -0,0 +1,33 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1624471326
+<< metal3 >>
+rect -700 822 699 850
+rect -700 -822 615 822
+rect 679 -822 699 822
+rect -700 -850 699 -822
+<< via3 >>
+rect 615 -822 679 822
+<< mimcap >>
+rect -600 710 500 750
+rect -600 -710 -560 710
+rect 460 -710 500 710
+rect -600 -750 500 -710
+<< mimcapcontact >>
+rect -560 -710 460 710
+<< metal4 >>
+rect 599 822 695 838
+rect -561 710 461 711
+rect -561 -710 -560 710
+rect 460 -710 461 710
+rect -561 -711 461 -710
+rect 599 -822 615 822
+rect 679 -822 695 822
+rect 599 -838 695 -822
+<< properties >>
+string gencell sky130_fd_pr__cap_mim_m3_1
+string FIXED_BBOX -700 -850 600 850
+string parameters w 5.5 l 7.5 val 87.44 carea 2.00 cperi 0.19 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 ccov 100
+string library sky130
+<< end >>
diff --git a/mag/extractions/user_analog_project_wrapper_lvs.spice b/mag/extractions/user_analog_project_wrapper_lvs.spice
index a508333..2c675c4 100644
--- a/mag/extractions/user_analog_project_wrapper_lvs.spice
+++ b/mag/extractions/user_analog_project_wrapper_lvs.spice
@@ -1,5 +1,822 @@
 * NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
 
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q D vdd CLK nCLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+.ends
+
+.subckt res_amp_sync_v2 vss avdd1p8 clk_amp clkn clkp rst
+XDFlipFlop_0 vss DFlipFlop_0/nQ DFlipFlop_0/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_1 vss DFlipFlop_1/nQ DFlipFlop_2/D DFlipFlop_1/D avdd1p8 DFlipFlop_3/D
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ DFlipFlop_2/Q DFlipFlop_2/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ DFlipFlop_3/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 vss DFlipFlop_4/nQ DFlipFlop_4/Q DFlipFlop_4/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+.ends
+
+.subckt delay_cell_buff clk clk_out avss1p8 avdd1p8 reg0 reg2 reg1 mux_2to1_logic_5/w_947_n633#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_9/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 mux_2to1_logic_3/DinB
++ buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/w_947_n633# avss1p8 mux_2to1_logic_0/out
++ clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/w_947_n633# avss1p8 mux_2to1_logic_1/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/w_947_n633# avss1p8 mux_2to1_logic_2/out
++ mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/w_947_n633# avss1p8 mux_2to1_logic_3/out
++ mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/w_947_n633# avss1p8 mux_2to1_logic_4/out
++ mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/w_947_n633# avss1p8 mux_2to1_logic_5/out
++ mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/w_947_n633# avss1p8 nand_logic_0/in1
++ mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_11/in
++ buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 mux_2to1_logic_4/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_13/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 mux_2to1_logic_4/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_1/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_3/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 mux_2to1_logic_0/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 mux_2to1_logic_1/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_5/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 mux_2to1_logic_1/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_7/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 mux_2to1_logic_3/DinA
++ buffer_no_inv_x05
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt iref_ctrl_res_amp vctrl avdd1p8 reg0 reg1 reg2 iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+.ends
+
+.subckt res_amp_lin_prog avdd1p8 delay_reg2 clk avss1p8 outp_cap iref_reg0 iref_reg1
++ iref_reg2 iref delay_reg0 inn outn_cap inp delay_reg1 rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 clk res_amp_lin_0/clk avss1p8 avdd1p8 delay_reg0 delay_reg2 delay_reg1
++ avss1p8 delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 inn outn outp
++ inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 res_amp_lin_0/vctrl avdd1p8 iref_reg0 iref_reg1 iref_reg2 iref
++ avss1p8 iref_ctrl_res_amp
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_pmos in avdd1p8 out iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_nmos in avdd1p8 avss1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+.ends
+
+.subckt source_follower_buff_diff VSUBS avdd1p8 iref1 iref2 iref3 iref4 inn outn inp
++ outp
+Xsource_follower_buff_pmos_0 inn avdd1p8 source_follower_buff_nmos_0/in iref3 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 inp avdd1p8 source_follower_buff_nmos_1/in iref1 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/in avdd1p8 VSUBS outn iref4
++ source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/in avdd1p8 VSUBS outp iref2
++ source_follower_buff_nmos
+.ends
+
+.subckt res_amp_top iref0 iref1 avss1p8 iref2 iref3 iref4 avdd1p8 res_amp_sync_v2_0/clkp
++ iref_reg0 iref_reg1 iref_reg2 delay_reg0 delay_reg1 inn outn delay_reg2 outp inp
++ clkn
+Xres_amp_sync_v2_0 avss1p8 avdd1p8 res_amp_lin_prog_0/clk clkn res_amp_sync_v2_0/clkp
++ res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 avdd1p8 delay_reg2 res_amp_lin_prog_0/clk avss1p8 res_amp_lin_prog_0/outp_cap
++ iref_reg0 iref_reg1 iref_reg2 iref0 delay_reg0 inn res_amp_lin_prog_0/outn_cap inp
++ delay_reg1 res_amp_sync_v2_0/rst res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 avss1p8 avdd1p8 iref1 iref2 iref3 iref4 res_amp_lin_prog_0/outn_cap
++ outn res_amp_lin_prog_0/outp_cap outp source_follower_buff_diff
+.ends
+
 .subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
 + m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
 + m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
@@ -242,107 +1059,6 @@
 + biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
 .ends
 
-.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
-X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
-+ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-.ends
-
-.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
-Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
-+ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
-Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
-+ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n81_n125#
-X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
-+ a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-.ends
-
-.subckt inverter_cp_x1 in vss out vdd
-Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
-Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
-.ends
-
-.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
-Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
-Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
-Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
-Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
-+ a_n63_n192#
-X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
-+ a_n173_n125# a_n81_n125#
-X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
-X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-.ends
-
-.subckt latch_diff nQ Q vss CLK vdd nD D
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
-Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
-Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
-.ends
-
-.subckt DFlipFlop vss nQ Q vdd CLK nCLK D
-Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
-Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
-+ latch_diff
-Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
-+ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
-X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
-+ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
-X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-.ends
-
-.subckt inverter_min_x4 in vss out vdd
-Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
-Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
-.ends
-
 .subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
 + a_n125_n42# a_63_n42#
 X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
@@ -361,10 +1077,10 @@
 .ends
 
 .subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
-XDFlipFlop_0 vss nout_div out_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK nout_div DFlipFlop
+XDFlipFlop_0 vss nout_div out_div nout_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
 Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
-Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
-Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
 Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
 Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
 .ends
@@ -619,8 +1335,8 @@
 .ends
 
 .subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
-Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
-Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
 Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
 .ends
 
@@ -655,12 +1371,12 @@
 X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
 .ends
 
-.subckt div_by_5 nCLK vdd Q0 CLK nQ0 CLK_5 nQ2 vss Q1 Q1_shift
+.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
 Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q vdd CLK nCLK DFlipFlop_0/D DFlipFlop
-XDFlipFlop_1 vss nQ0 Q0 vdd CLK nCLK DFlipFlop_1/D DFlipFlop
-XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 vdd CLK nCLK DFlipFlop_2/D DFlipFlop
-XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift vdd nCLK CLK Q1 DFlipFlop
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q DFlipFlop_0/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 DFlipFlop_2/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 DFlipFlop_1/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift Q1 vdd nCLK CLK DFlipFlop
 Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
@@ -700,8 +1416,8 @@
 Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
 Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
 Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
-Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
 Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
 .ends
 
 .subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
@@ -773,7 +1489,7 @@
 Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
 Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
 + div_5_Q1 div_5_Q1_shift div_by_5
 Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
@@ -837,7 +1553,7 @@
 X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
 .ends
 
-.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
 + vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
@@ -904,7 +1620,7 @@
 Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
 Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 n_out_by_2 vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2 vss
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
 + div_5_Q1 div_5_Q1_shift div_by_5
 Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
@@ -917,8 +1633,8 @@
 *+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
 *+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
 *+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-*+ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[7] io_analog[8] io_analog[9]
-*+ io_analog[4] io_analog[6] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
+*+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
+*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
 *+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
 *+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
 *+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
@@ -1015,6 +1731,9 @@
 *+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
 *+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
 *+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 bias_0/iref_9 bias_0/iref_8 vssa1 bias_0/iref_6 bias_0/iref_7 bias_0/iref_5
++ vdda1 io_analog[6] gpio_noesd[4] gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[2]
++ io_analog[2] io_analog[0] gpio_noesd[1] io_analog[1] io_analog[3] io_analog[4] res_amp_top
 Xtop_pll_v1_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_2 io_analog[9]
 + top_pll_v1
 Xtop_pll_v1_1 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_0 io_analog[7]
@@ -1028,7 +1747,8 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 io_analog[5] bias
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
@@ -1051,8 +1771,6 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
@@ -1065,7 +1783,9 @@
 Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xtop_pll_v2_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 gpio_noesd[8]
 + io_analog[8] top_pll_v2
-.ends
+.end
 
diff --git a/mag/extractions/user_analog_project_wrapper_lvs_backup.spice b/mag/extractions/user_analog_project_wrapper_lvs_backup.spice
new file mode 100644
index 0000000..cf6e276
--- /dev/null
+++ b/mag/extractions/user_analog_project_wrapper_lvs_backup.spice
@@ -0,0 +1,1785 @@
+* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x1 in vss out vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+.ends
+
+.subckt clock_inverter vss CLK vdd CLK_d nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 CLK vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss CLK_d vdd inverter_cp_x1
+Xinverter_cp_x1_1 CLK vss inverter_cp_x1_2/in vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+.ends
+
+.subckt latch_diff nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+.ends
+
+.subckt DFlipFlop vss nQ Q D vdd CLK nCLK
+Xclock_inverter_0 vss D vdd latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_1/nD latch_diff_1/D vss CLK vdd latch_diff_0/nD latch_diff_0/D
++ latch_diff
+Xlatch_diff_1 nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D latch_diff
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+.ends
+
+.subckt res_amp_sync_v2 vss avdd1p8 clk_amp clkn clkp rst
+XDFlipFlop_0 vss DFlipFlop_0/nQ DFlipFlop_0/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_1 vss DFlipFlop_1/nQ DFlipFlop_2/D DFlipFlop_1/D avdd1p8 DFlipFlop_3/D
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ DFlipFlop_2/Q DFlipFlop_2/D avdd1p8 clkp clkn DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ DFlipFlop_3/Q DFlipFlop_3/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 vss DFlipFlop_4/nQ DFlipFlop_4/Q DFlipFlop_4/D avdd1p8 clkp clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+.ends
+
+.subckt delay_cell_buff clk clk_out avss1p8 avdd1p8 reg0 reg2 reg1 mux_2to1_logic_5/w_947_n633#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_9/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 mux_2to1_logic_3/DinB
++ buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/w_947_n633# avss1p8 mux_2to1_logic_0/out
++ clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/w_947_n633# avss1p8 mux_2to1_logic_1/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/w_947_n633# avss1p8 mux_2to1_logic_2/out
++ mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/w_947_n633# avss1p8 mux_2to1_logic_3/out
++ mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/w_947_n633# avss1p8 mux_2to1_logic_4/out
++ mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/w_947_n633# avss1p8 mux_2to1_logic_5/out
++ mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/w_947_n633# avss1p8 nand_logic_0/in1
++ mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_11/in
++ buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 mux_2to1_logic_4/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_13/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 mux_2to1_logic_4/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_1/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_3/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 mux_2to1_logic_0/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 mux_2to1_logic_1/DinA
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_5/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 mux_2to1_logic_1/DinB
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_7/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 mux_2to1_logic_3/DinA
++ buffer_no_inv_x05
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt iref_ctrl_res_amp vctrl avdd1p8 reg0 reg1 reg2 iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+.ends
+
+.subckt res_amp_lin_prog avdd1p8 delay_reg2 clk avss1p8 outp_cap iref_reg0 iref_reg1
++ iref_reg2 iref delay_reg0 inn outn_cap inp delay_reg1 rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 clk res_amp_lin_0/clk avss1p8 avdd1p8 delay_reg0 delay_reg2 delay_reg1
++ avss1p8 delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 inn outn outp
++ inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 res_amp_lin_0/vctrl avdd1p8 iref_reg0 iref_reg1 iref_reg2 iref
++ avss1p8 iref_ctrl_res_amp
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_pmos in avdd1p8 out iref avss1p8
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt source_follower_buff_nmos in avdd1p8 avss1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+.ends
+
+.subckt source_follower_buff_diff VSUBS avdd1p8 iref1 iref2 iref3 iref4 inn outn inp
++ outp
+Xsource_follower_buff_pmos_0 inn avdd1p8 source_follower_buff_nmos_0/in iref3 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 inp avdd1p8 source_follower_buff_nmos_1/in iref1 VSUBS
++ source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/in avdd1p8 VSUBS outn iref4
++ source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/in avdd1p8 VSUBS outp iref2
++ source_follower_buff_nmos
+.ends
+
+.subckt res_amp_top iref0 iref1 avss1p8 iref2 iref3 iref4 avdd1p8 res_amp_sync_v2_0/clkp
++ iref_reg0 iref_reg1 iref_reg2 delay_reg0 delay_reg1 inn outn delay_reg2 outp inp
++ clkn
+Xres_amp_sync_v2_0 avss1p8 avdd1p8 res_amp_lin_prog_0/clk clkn res_amp_sync_v2_0/clkp
++ res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 avdd1p8 delay_reg2 res_amp_lin_prog_0/clk avss1p8 res_amp_lin_prog_0/outp_cap
++ iref_reg0 iref_reg1 iref_reg2 iref0 delay_reg0 inn res_amp_lin_prog_0/outn_cap inp
++ delay_reg1 res_amp_sync_v2_0/rst res_amp_lin_prog
+Xsource_follower_buff_diff_0 avss1p8 avdd1p8 iref1 iref2 iref3 iref4 res_amp_lin_prog_0/outn_cap
++ outn res_amp_lin_prog_0/outp_cap outp source_follower_buff_diff
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
++ m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
++ m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
++ m3_n13288_2700# m3_n7969_n7900# m3_n13288_n7900# m3_2669_n2600# m3_n7969_2700# m3_7988_n13200#
++ c1_n13188_n13100# m3_7988_n2600# m3_n2650_n2600# m3_n2650_8000# m3_2669_8000#
+X0 c1_n13188_n13100# m3_2669_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X1 c1_n13188_n13100# m3_n2650_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X2 c1_n13188_n13100# m3_2669_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X3 c1_n13188_n13100# m3_n13288_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X4 c1_n13188_n13100# m3_n7969_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X5 c1_n13188_n13100# m3_n13288_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X6 c1_n13188_n13100# m3_2669_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X7 c1_n13188_n13100# m3_7988_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X8 c1_n13188_n13100# m3_2669_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X9 c1_n13188_n13100# m3_7988_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X10 c1_n13188_n13100# m3_n7969_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X11 c1_n13188_n13100# m3_7988_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X12 c1_n13188_n13100# m3_n7969_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X13 c1_n13188_n13100# m3_7988_8000# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X14 c1_n13188_n13100# m3_n13288_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X15 c1_n13188_n13100# m3_n7969_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X16 c1_n13188_n13100# m3_n2650_n7900# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X17 c1_n13188_n13100# m3_n2650_n13200# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X18 c1_n13188_n13100# m3_n2650_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X19 c1_n13188_n13100# m3_7988_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X20 c1_n13188_n13100# m3_n13288_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X21 c1_n13188_n13100# m3_n13288_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
+.ends
+
+.subckt cap1_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_MACBVW_0 VSUBS out out out out out out out out out out
++ out out out out out out out out out out out in out out out out sky130_fd_pr__cap_mim_m3_1_MACBVW
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_W3JTNJ VSUBS m3_n6469_n2100# c1_n6369_n6300# m3_2169_n6400#
++ m3_n2150_n6400# c1_2269_n6300# m3_n6469_2200# m3_n2150_n2100# c1_n2050_n6300# m3_n2150_2200#
++ m3_n6469_n6400#
+X0 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n2050_n6300# m3_n2150_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_n6369_n6300# m3_n6469_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X4 c1_2269_n6300# m3_2169_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X5 c1_n6369_n6300# m3_n6469_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap2_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_W3JTNJ_0 VSUBS out in out out in out out in out out sky130_fd_pr__cap_mim_m3_1_W3JTNJ
+.ends
+
+.subckt sky130_fd_pr__res_high_po_5p73_X44RQA a_n573_2292# w_n739_n2890# a_n573_n2724#
+X0 a_n573_n2724# a_n573_2292# w_n739_n2890# sky130_fd_pr__res_high_po_5p73 l=2.292e+07u
+.ends
+
+.subckt res_loop_filter vss out in
+Xsky130_fd_pr__res_high_po_5p73_X44RQA_0 in vss out sky130_fd_pr__res_high_po_5p73_X44RQA
+.ends
+
+.subckt loop_filter vc_pex in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4ML9WA VSUBS a_429_n486# w_n2457_n634# a_887_n486#
++ a_n29_n486# a_1345_n486# a_n2261_n512# a_1803_n486# a_n487_n486# a_n945_n486# a_n2319_n486#
++ a_n1403_n486# a_2261_n486# a_n1861_n486#
+X0 a_2261_n486# a_n2261_n512# a_1803_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X1 a_n945_n486# a_n2261_n512# a_n1403_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X2 a_429_n486# a_n2261_n512# a_n29_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X3 a_1803_n486# a_n2261_n512# a_1345_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X4 a_887_n486# a_n2261_n512# a_429_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X5 a_n487_n486# a_n2261_n512# a_n945_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X6 a_n1403_n486# a_n2261_n512# a_n1861_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_YCGG98 a_n1041_n75# a_n561_n75# a_1167_n75# a_303_n75#
++ a_687_n75# a_n849_n75# a_n369_n75# a_975_n75# a_111_n75# a_495_n75# a_n1137_n75#
++ a_n657_n75# a_n177_n75# a_783_n75# a_n945_n75# a_n465_n75# a_207_n75# a_1071_n75#
++ a_591_n75# a_15_n75# a_n753_n75# w_n1367_n285# a_n273_n75# a_879_n75# a_399_n75#
++ a_n1229_n75# a_n81_n75# a_n1167_n101#
+X0 a_207_n75# a_n1167_n101# a_111_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_303_n75# a_n1167_n101# a_207_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_399_n75# a_n1167_n101# a_303_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_495_n75# a_n1167_n101# a_399_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_591_n75# a_n1167_n101# a_495_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_783_n75# a_n1167_n101# a_687_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_687_n75# a_n1167_n101# a_591_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_879_n75# a_n1167_n101# a_783_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_975_n75# a_n1167_n101# a_879_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_n1041_n75# a_n1167_n101# a_n1137_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_n1137_n75# a_n1167_n101# a_n1229_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n561_n75# a_n1167_n101# a_n657_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_1071_n75# a_n1167_n101# a_975_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n945_n75# a_n1167_n101# a_n1041_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n753_n75# a_n1167_n101# a_n849_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n657_n75# a_n1167_n101# a_n753_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n465_n75# a_n1167_n101# a_n561_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n369_n75# a_n1167_n101# a_n465_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_1167_n75# a_n1167_n101# a_1071_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n849_n75# a_n1167_n101# a_n945_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X20 a_15_n75# a_n1167_n101# a_n81_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X21 a_n81_n75# a_n1167_n101# a_n177_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_MUHGM9 a_33_n101# a_n129_n75# a_735_n75# a_255_n75#
++ a_n417_n75# a_n989_n75# a_63_n75# a_543_n75# a_n705_n75# a_n225_n75# a_n33_n75#
++ a_831_n75# a_351_n75# a_n927_n101# a_n513_n75# a_n897_n75# w_n1127_n285# a_639_n75#
++ a_159_n75# a_n801_n75# a_n321_n75# a_927_n75# a_447_n75# a_n609_n75#
+X0 a_63_n75# a_33_n101# a_n33_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X1 a_927_n75# a_33_n101# a_831_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X2 a_n33_n75# a_n927_n101# a_n129_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X3 a_159_n75# a_33_n101# a_63_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X4 a_255_n75# a_33_n101# a_159_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X5 a_351_n75# a_33_n101# a_255_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X6 a_447_n75# a_33_n101# a_351_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X7 a_543_n75# a_33_n101# a_447_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X8 a_735_n75# a_33_n101# a_639_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X9 a_831_n75# a_33_n101# a_735_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X10 a_639_n75# a_33_n101# a_543_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X11 a_n321_n75# a_n927_n101# a_n417_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X12 a_n801_n75# a_n927_n101# a_n897_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X13 a_n705_n75# a_n927_n101# a_n801_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X14 a_n513_n75# a_n927_n101# a_n609_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X15 a_n417_n75# a_n927_n101# a_n513_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X16 a_n225_n75# a_n927_n101# a_n321_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X17 a_n129_n75# a_n927_n101# a_n225_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X18 a_n897_n75# a_n927_n101# a_n989_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+X19 a_n609_n75# a_n927_n101# a_n705_n75# w_n1127_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_NKZXKB VSUBS a_33_n247# a_n801_n150# a_n417_n150#
++ a_351_n150# a_255_n150# a_n705_n150# a_n609_n150# a_159_n150# a_543_n150# a_447_n150#
++ a_831_n150# a_n897_n150# a_n33_n150# a_735_n150# a_n927_n247# a_639_n150# a_n321_n150#
++ a_927_n150# a_n225_n150# a_63_n150# a_n989_n150# a_n513_n150# a_n129_n150# w_n1127_n369#
+X0 a_n513_n150# a_n927_n247# a_n609_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_63_n150# a_33_n247# a_n33_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_735_n150# a_33_n247# a_639_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n801_n150# a_n927_n247# a_n897_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n927_n247# a_n225_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n927_n247# a_n513_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_639_n150# a_33_n247# a_543_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n705_n150# a_n927_n247# a_n801_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n33_n150# a_n927_n247# a_n129_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_351_n150# a_33_n247# a_255_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_n609_n150# a_n927_n247# a_n705_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n897_n150# a_n927_n247# a_n989_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_927_n150# a_33_n247# a_831_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_255_n150# a_33_n247# a_159_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n321_n150# a_n927_n247# a_n417_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_543_n150# a_33_n247# a_447_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_831_n150# a_33_n247# a_735_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_159_n150# a_33_n247# a_63_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_n225_n150# a_n927_n247# a_n321_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_447_n150# a_33_n247# a_351_n150# w_n1127_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8GRULZ a_n1761_n132# a_1045_n44# a_n1461_n44# a_n1103_n44#
++ a_n29_n44# a_n387_n44# a_1761_n44# a_n1819_n44# a_1403_n44# a_687_n44# w_n1957_n254#
++ a_329_n44# a_n745_n44#
+X0 a_329_n44# a_n1761_n132# a_n29_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X1 a_1761_n44# a_n1761_n132# a_1403_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X2 a_n745_n44# a_n1761_n132# a_n1103_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X3 a_1045_n44# a_n1761_n132# a_687_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X4 a_n29_n44# a_n1761_n132# a_n387_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X5 a_n1103_n44# a_n1761_n132# a_n1461_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X6 a_n387_n44# a_n1761_n132# a_n745_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ND88ZC VSUBS a_303_n150# a_n753_n150# a_n369_n150#
++ w_n1367_n369# a_207_n150# a_n657_n150# a_591_n150# a_n1229_n150# a_n945_n150# a_495_n150#
++ a_n1041_n150# a_n849_n150# a_n81_n150# a_399_n150# a_783_n150# a_1071_n150# a_687_n150#
++ a_975_n150# a_n1137_n150# a_n273_n150# a_111_n150# a_879_n150# a_n177_n150# a_n561_n150#
++ a_15_n150# a_1167_n150# a_n1167_n247# a_n465_n150#
+X0 a_n1137_n150# a_n1167_n247# a_n1229_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_495_n150# a_n1167_n247# a_399_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n561_n150# a_n1167_n247# a_n657_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_111_n150# a_n1167_n247# a_15_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_783_n150# a_n1167_n247# a_687_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_1071_n150# a_n1167_n247# a_975_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_399_n150# a_n1167_n247# a_303_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_n465_n150# a_n1167_n247# a_n561_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_687_n150# a_n1167_n247# a_591_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n753_n150# a_n1167_n247# a_n849_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X10 a_975_n150# a_n1167_n247# a_879_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X11 a_n81_n150# a_n1167_n247# a_n177_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X12 a_15_n150# a_n1167_n247# a_n81_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X13 a_n1041_n150# a_n1167_n247# a_n1137_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X14 a_n369_n150# a_n1167_n247# a_n465_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X15 a_n657_n150# a_n1167_n247# a_n753_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X16 a_879_n150# a_n1167_n247# a_783_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X17 a_n945_n150# a_n1167_n247# a_n1041_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X18 a_1167_n150# a_n1167_n247# a_1071_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X19 a_303_n150# a_n1167_n247# a_207_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X20 a_n273_n150# a_n1167_n247# a_n369_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X21 a_591_n150# a_n1167_n247# a_495_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt charge_pump Down out iref pswitch nDown biasp Up nswitch vss vdd nUp
+Xsky130_fd_pr__pfet_01v8_4ML9WA_0 vss pswitch vdd pswitch pswitch pswitch nUp pswitch
++ pswitch pswitch pswitch pswitch pswitch pswitch sky130_fd_pr__pfet_01v8_4ML9WA
+Xsky130_fd_pr__nfet_01v8_YCGG98_0 vss out out vss vss vss out out vss vss out vss
++ out out out vss out vss out out out vss vss vss out vss vss nswitch sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_1 iref vss vss iref iref iref vss vss iref iref vss
++ iref vss vss vss iref vss iref vss vss vss vss iref iref vss iref iref iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_YCGG98_2 biasp vss vss biasp biasp biasp vss vss biasp biasp
++ vss biasp vss vss vss biasp vss biasp vss vss vss vss biasp biasp vss biasp biasp
++ iref sky130_fd_pr__nfet_01v8_YCGG98
+Xsky130_fd_pr__nfet_01v8_MUHGM9_0 nDown iref nswitch vss nswitch nswitch vss nswitch
++ iref nswitch nswitch vss nswitch Down iref iref vss vss nswitch nswitch iref nswitch
++ vss nswitch sky130_fd_pr__nfet_01v8_MUHGM9
+Xsky130_fd_pr__pfet_01v8_NKZXKB_0 vss Up pswitch pswitch pswitch vdd biasp pswitch
++ pswitch pswitch vdd vdd biasp pswitch pswitch nUp vdd biasp pswitch pswitch vdd
++ pswitch biasp biasp vdd sky130_fd_pr__pfet_01v8_NKZXKB
+Xsky130_fd_pr__nfet_01v8_8GRULZ_0 Down nswitch nswitch nswitch nswitch nswitch nswitch
++ nswitch nswitch nswitch vss nswitch nswitch sky130_fd_pr__nfet_01v8_8GRULZ
+Xsky130_fd_pr__pfet_01v8_ND88ZC_0 vss vdd out out vdd out vdd out vdd out vdd vdd
++ vdd vdd out out vdd vdd out out vdd vdd vdd out out out out pswitch vdd sky130_fd_pr__pfet_01v8_ND88ZC
+Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
++ biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
++ biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
++ a_n125_n42# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZPB9BB VSUBS a_n63_n110# a_33_n110# a_n125_n84# a_63_n84#
++ w_n263_n303# a_n33_n84#
+X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+.ends
+
+.subckt inverter_min_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
+Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
+.ends
+
+.subckt div_by_2 vss vdd CLK_2 nCLK_2 o1 CLK out_div o2 nout_div
+XDFlipFlop_0 vss nout_div out_div nout_div vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
+Xclock_inverter_0 vss CLK vdd DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
+Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
+Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_58ZKDE VSUBS a_n257_n777# a_n129_n600# a_n221_n600#
++ w_n257_n702#
+X0 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_T69Y3A a_n129_n300# a_n221_n300# w_n257_n327# a_n257_n404#
+X0 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
+.ends
+
+.subckt buffer_salida in out vss vdd
+Xsky130_fd_pr__pfet_01v8_58ZKDE_1 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_2 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_3 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_0 a_678_n100# vss vss in sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_1 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_4 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_5 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_2 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_3 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_6 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_70 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_4 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_7 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_8 vss a_678_n100# a_3996_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_71 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_60 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_5 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_72 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_61 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_50 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_6 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_9 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_62 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_51 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_7 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_40 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_8 a_3996_n100# vss vss a_678_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_63 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_52 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_30 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_41 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_64 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_53 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_9 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_20 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_31 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_42 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_65 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_54 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_10 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_21 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_32 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_43 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_66 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_55 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_11 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_22 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_33 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_44 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_67 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_56 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_12 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_23 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_34 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_45 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_68 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_57 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_13 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_24 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_35 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_46 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_69 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_58 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_14 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_25 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_36 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_47 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_59 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_48 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_15 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_26 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_37 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_49 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_16 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_27 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_38 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_70 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_17 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_28 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_39 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_71 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_60 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_18 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__nfet_01v8_T69Y3A_29 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_72 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_61 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_50 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_62 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_51 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__nfet_01v8_T69Y3A_19 out vss vss a_3996_n100# sky130_fd_pr__nfet_01v8_T69Y3A
+Xsky130_fd_pr__pfet_01v8_58ZKDE_40 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_63 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_52 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_30 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_41 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_64 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_53 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_20 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_31 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_42 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_65 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_54 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_10 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_21 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_32 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_43 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_66 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_55 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_11 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_22 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_33 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_44 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_67 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_56 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_12 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_23 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_34 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_45 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_68 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_57 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_46 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_13 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_24 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_35 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_69 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_58 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_14 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_25 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_36 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_47 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_59 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_15 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_26 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_37 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_48 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_49 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_16 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_27 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_38 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_17 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_28 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_39 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_18 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
+X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
+X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7H8F5S a_n465_172# a_n417_n150# a_351_n150# a_255_n150#
++ w_n647_n360# a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150#
+X0 a_159_n150# a_n465_172# a_63_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n225_n150# a_n465_172# a_n321_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_447_n150# a_n465_172# a_351_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_63_n150# a_n465_172# a_n33_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_n129_n150# a_n465_172# a_n225_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_n417_n150# a_n465_172# a_n509_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n33_n150# a_n465_172# a_n129_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_8DL6ZL VSUBS a_n417_n150# a_351_n150# a_255_n150#
++ a_159_n150# a_447_n150# a_n509_n150# a_n33_n150# a_n465_n247# a_n321_n150# a_n225_n150#
++ a_63_n150# a_n129_n150# w_n647_n369#
+X0 a_63_n150# a_n465_n247# a_n33_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X1 a_n129_n150# a_n465_n247# a_n225_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X2 a_n417_n150# a_n465_n247# a_n509_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X3 a_n33_n150# a_n465_n247# a_n129_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X4 a_351_n150# a_n465_n247# a_255_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X5 a_255_n150# a_n465_n247# a_159_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X6 a_n321_n150# a_n465_n247# a_n417_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
+X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AQR2CW a_n33_66# a_n78_n106# w_n216_n254# a_20_n106#
+X0 a_20_n106# a_n33_66# a_n78_n106# w_n216_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=200000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
++ a_20_n114#
+X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
+.ends
+
+.subckt inverter_csvco in vbulkn out vbulkp vdd vss
+Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
+Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
+.ends
+
+.subckt cap_vco t b VSUBS
+C0 t b 5.78fF
+*C1 t VSUBS 0.42fF
+*C2 b VSUBS 0.09fF
+.ends
+
+
+.subckt csvco_branch vctrl in vbp D0 out vss vdd
+Xsky130_fd_pr__nfet_01v8_7H8F5S_0 vctrl inverter_csvco_0/vss inverter_csvco_0/vss
++ vss vss inverter_csvco_0/vss vss vss inverter_csvco_0/vss vss inverter_csvco_0/vss
++ vss vss sky130_fd_pr__nfet_01v8_7H8F5S
+Xsky130_fd_pr__pfet_01v8_8DL6ZL_0 vss inverter_csvco_0/vdd inverter_csvco_0/vdd vdd
++ inverter_csvco_0/vdd vdd vdd inverter_csvco_0/vdd vbp vdd inverter_csvco_0/vdd vdd
++ vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
+Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
+Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
+Xcap_vco_0 cap_vco_0/t vss vss cap_vco
+.ends
+
+.subckt ring_osc vctrl vdd vss D0 out_vco
+Xsky130_fd_pr__nfet_01v8_CBAU6Y_0 vss vctrl vss csvco_branch_2/vbp sky130_fd_pr__nfet_01v8_CBAU6Y
+Xsky130_fd_pr__pfet_01v8_4757AC_0 vss vdd csvco_branch_2/vbp vdd csvco_branch_2/vbp
++ sky130_fd_pr__pfet_01v8_4757AC
+Xcsvco_branch_0 vctrl out_vco csvco_branch_2/vbp D0 csvco_branch_1/in vss vdd csvco_branch
+Xcsvco_branch_2 vctrl csvco_branch_2/in csvco_branch_2/vbp D0 out_vco vss vdd csvco_branch
+Xcsvco_branch_1 vctrl csvco_branch_1/in csvco_branch_2/vbp D0 csvco_branch_2/in vss
++ vdd csvco_branch
+.ends
+
+.subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
+Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
+.ends
+
+.subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X
+X0 X B a_455_87# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X1 X a_194_125# a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X2 a_194_125# B a_158_392# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_158_392# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 VPWR A a_355_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X5 a_355_368# B VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X6 a_194_125# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__and2_1 A B VGND VNB VPB VPWR X
+X0 VGND B a_143_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X1 X a_56_136# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X2 VPWR B a_56_136# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
+X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+.ends
+
+.subckt sky130_fd_sc_hs__or2_1 A B VGND VNB VPB VPWR X
+X0 VPWR A a_152_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_152_368# B a_63_368# VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 X a_63_368# VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
+X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
+X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
+.ends
+
+.subckt div_by_5 nCLK vss vdd Q0 CLK nQ0 CLK_5 nQ2 Q1 Q1_shift
+Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1
+XDFlipFlop_0 vss nQ2 DFlipFlop_0/Q DFlipFlop_0/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_2 vss DFlipFlop_2/nQ Q1 DFlipFlop_2/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_1 vss nQ0 Q0 DFlipFlop_1/D vdd CLK nCLK DFlipFlop
+XDFlipFlop_3 vss DFlipFlop_3/nQ Q1_shift Q1 vdd nCLK CLK DFlipFlop
+Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1
+Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_AZESM8 a_n63_n151# a_n33_n125# a_n255_n151# a_33_n151#
++ a_n225_n125# a_63_n125# a_n129_n125# a_n159_n151# w_n455_n335# a_225_n151# a_255_n125#
++ a_129_n151# a_159_n125# a_n317_n125#
+X0 a_159_n125# a_129_n151# a_63_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n225_n125# a_n255_n151# a_n317_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_63_n125# a_33_n151# a_n33_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XJXT7S VSUBS a_n33_n125# a_n255_n154# a_33_n154# a_n225_n125#
++ a_n159_n154# a_63_n125# a_n129_n125# a_225_n154# a_129_n154# a_255_n125# a_159_n125#
++ a_n317_n125# w_n455_n344# a_n63_n154#
+X0 a_n129_n125# a_n159_n154# a_n225_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n33_n125# a_n63_n154# a_n129_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_255_n125# a_225_n154# a_159_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+.ends
+
+.subckt inverter_cp_x2 in out vss vdd
+Xsky130_fd_pr__nfet_01v8_AZESM8_0 in vss in in vss out out in vss in out in vss out
++ sky130_fd_pr__nfet_01v8_AZESM8
+Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
++ in sky130_fd_pr__pfet_01v8_XJXT7S
+.ends
+
+.subckt pfd_cp_interface vss vdd Down QA QB nDown Up nUp
+Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
+Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
+Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 QB vss inverter_cp_x1_0/out vdd inverter_cp_x1
+Xinverter_cp_x1_1 QA vss inverter_cp_x1_2/in vdd inverter_cp_x1
+Xinverter_cp_x1_2 inverter_cp_x1_2/in vss Up vdd inverter_cp_x1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F35BC VSUBS w_n359_n309# a_n63_n116# a_n159_n207#
++ a_n33_n90# a_n221_n90# a_159_n90#
+X0 a_159_n90# a_n63_n116# a_63_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_C3YG4M a_n33_n45# a_33_n71# a_n129_71# w_n263_n255#
++ a_n125_n45# a_63_n45#
+X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt nor_pfd out vss vdd A B
+Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss vdd B A out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
+Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
+.ends
+
+.subckt dff_pfd vdd vss Q CLK Reset
+Xnor_pfd_0 nor_pfd_2/A vss vdd CLK Q nor_pfd
+Xnor_pfd_1 Q vss vdd nor_pfd_2/A nor_pfd_3/A nor_pfd
+Xnor_pfd_2 nor_pfd_3/A vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
+Xnor_pfd_3 nor_pfd_2/B vss vdd nor_pfd_3/A Reset nor_pfd
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZCYAJJ w_n359_n255# a_n33_n45# a_n159_n173# a_n221_n45#
++ a_159_n45# a_n63_n71#
+X0 a_63_n45# a_n159_n173# a_n33_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7T83YG VSUBS a_n125_n90# a_63_n90# a_33_n187# a_n99_n187#
++ a_n33_n90# w_n263_n309#
+X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
+X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
+X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
+.ends
+
+.subckt and_pfd vss out vdd A B
+Xsky130_fd_pr__nfet_01v8_ZCYAJJ_0 vss a_656_410# A vss vss B sky130_fd_pr__nfet_01v8_ZCYAJJ
+Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
+Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
+Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
+.ends
+
+.subckt PFD vss vdd Down Up A B Reset
+Xdff_pfd_0 vdd vss Up A Reset dff_pfd
+Xdff_pfd_1 vdd vss Down B Reset dff_pfd
+Xand_pfd_0 vss Reset vdd Up Down and_pfd
+.ends
+
+.subckt top_pll_v1 vdd in_ref w_13905_n238# vss vco_D0 iref_cp out_to_pad
+Xloop_filter_0 lf_vc vco_vctrl vss loop_filter
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss vco_D0 vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
+X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_8P223X VSUBS a_n2017_n1317# a_n1731_n1219# a_n1879_n1219#
++ a_n2017_n61# w_n2018_n202#
+X0 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X1 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X2 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X3 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X4 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X5 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X6 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X7 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X8 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X9 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X10 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X11 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X12 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X13 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X14 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X15 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X16 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X17 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X18 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X19 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X20 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X21 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X22 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X23 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X24 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X25 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X26 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X27 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X28 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X29 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X30 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X31 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X32 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X33 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X34 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X35 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X36 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X37 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X38 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X39 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X40 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X41 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X42 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X43 a_n1879_n1219# a_n2017_n1317# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X44 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X45 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X46 a_n1731_n1219# a_n2017_n61# w_n2018_n202# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
+.ends
+
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
++ vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
++ iref_5 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_7 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219#
++ iref_6 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_9 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219#
++ iref_8 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_8 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219#
++ iref_7 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_10 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219#
++ iref_9 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_0 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219#
++ iref_0 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_1 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219#
++ iref_1 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_2 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219#
++ iref_2 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_3 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219#
++ iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
++ iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
+.ends
+
+.subckt mimcap_decoup_1x5 VSUBS t b
+Xdecap[0] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[1] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[2] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[3] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xdecap[4] VSUBS t b sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_WHJTNJ VSUBS m3_n4309_50# m3_n4309_n4250# c1_n4209_n4150#
++ c1_110_n4150# m3_10_n4250#
+X0 c1_n4209_n4150# m3_n4309_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
+.ends
+
+.subckt cap3_loop_filter VSUBS in out
+Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
+X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
+.ends
+
+.subckt loop_filter_v2 vc_pex D0_cap in vss
+Xcap1_loop_filter_0 vss vc_pex vss cap1_loop_filter
+Xcap3_loop_filter_0 vss cap3_loop_filter_0/in vss cap3_loop_filter
+Xcap2_loop_filter_0 vss in vss cap2_loop_filter
+Xsky130_fd_pr__nfet_01v8_U2JGXT_0 vss D0_cap in cap3_loop_filter_0/in sky130_fd_pr__nfet_01v8_U2JGXT
+Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
+Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
+Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
+.ends
+
+.subckt top_pll_v2 vdd in_ref w_13905_n238# vss D0_vco iref_cp DO_cap out_to_pad
+Xcharge_pump_0 Down vco_vctrl iref_cp pswitch nDown biasp Up nswitch vss vdd nUp charge_pump
+Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
+Xdiv_by_2_0 vss vdd out_by_2 n_out_by_2 out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2
++ n_out_div_2 div_by_2
+Xbuffer_salida_0 out_to_buffer out_to_pad vss vdd buffer_salida
+Xring_osc_0 vco_vctrl vdd vss D0_vco vco_out ring_osc
+Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
+Xdiv_by_5_0 n_out_by_2 vss vdd div_5_Q0 out_by_2 div_5_nQ0 out_div_by_5 div_5_nQ2
++ div_5_Q1 div_5_Q1_shift div_by_5
+Xpfd_cp_interface_0 vss vdd Down QA QB nDown Up nUp pfd_cp_interface
+XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
+.ends
+
+*.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
+*+ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
+*+ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
+*+ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
+*+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
+*+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
+*+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
+*+ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
+*+ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
+*+ io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
+*+ io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
+*+ io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
+*+ io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14]
+*+ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1]
+*+ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25]
+*+ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7]
+*+ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
+*+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
+*+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3]
+*+ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10]
+*+ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18]
+*+ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25]
+*+ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8]
+*+ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103]
+*+ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108]
+*+ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113]
+*+ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118]
+*+ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123]
+*+ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13]
+*+ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19]
+*+ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24]
+*+ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2]
+*+ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35]
+*+ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40]
+*+ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46]
+*+ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51]
+*+ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57]
+*+ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62]
+*+ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68]
+*+ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73]
+*+ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79]
+*+ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84]
+*+ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8]
+*+ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95]
+*+ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0]
+*+ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104]
+*+ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109]
+*+ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113]
+*+ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118]
+*+ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122]
+*+ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127]
+*+ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16]
+*+ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21]
+*+ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26]
+*+ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31]
+*+ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36]
+*+ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41]
+*+ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46]
+*+ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51]
+*+ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56]
+*+ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61]
+*+ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66]
+*+ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71]
+*+ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76]
+*+ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81]
+*+ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86]
+*+ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91]
+*+ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96]
+*+ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100]
+*+ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107]
+*+ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113]
+*+ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11]
+*+ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126]
+*+ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17]
+*+ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23]
+*+ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2]
+*+ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36]
+*+ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42]
+*+ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49]
+*+ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55]
+*+ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61]
+*+ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68]
+*+ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74]
+*+ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80]
+*+ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87]
+*+ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93]
+*+ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9]
+*+ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2
+*+ vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11]
+*+ wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17]
+*+ wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22]
+*+ wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28]
+*+ wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4]
+*+ wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0]
+*+ wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15]
+*+ wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20]
+*+ wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26]
+*+ wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31]
+*+ wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9]
+*+ wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14]
+*+ wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1]
+*+ wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25]
+*+ wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
+*+ wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
+*+ wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 bias_0/iref_9 bias_0/iref_8 vssa1 bias_0/iref_6 bias_0/iref_7 bias_0/iref_5
++ vdda1 io_analog[6] gpio_noesd[4] gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[2]
++ io_analog[2] io_analog[0] gpio_noesd[1] io_analog[1] io_analog[3] io_analog[4] res_amp_top
+Xtop_pll_v1_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_2 io_analog[9]
++ top_pll_v1
+Xtop_pll_v1_1 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_0 io_analog[7]
++ top_pll_v1
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_0[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_0[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_1[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[3] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
+Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_3[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_4[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xtop_pll_v2_0 vdda1 io_analog[10] vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 gpio_noesd[8]
++ io_analog[8] top_pll_v2
+.end
+
diff --git a/mag/extractions/user_analog_project_wrapper_pex_c.spice b/mag/extractions/user_analog_project_wrapper_pex_c.spice
index 8dd104e..03ec8de 100644
--- a/mag/extractions/user_analog_project_wrapper_pex_c.spice
+++ b/mag/extractions/user_analog_project_wrapper_pex_c.spice
@@ -1,5 +1,4080 @@
 * NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
 
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n111_n156# a_n15_n156# 0.02fF
+C1 a_n81_n125# a_15_n125# 0.36fF
+C2 a_n81_n125# a_111_n125# 0.13fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 w_n311_n344# a_15_n125# 0.09fF
+C6 w_n311_n344# a_111_n125# 0.14fF
+C7 a_n173_n125# a_n81_n125# 0.36fF
+C8 a_n173_n125# a_15_n125# 0.13fF
+C9 a_n173_n125# a_111_n125# 0.08fF
+C10 a_n15_n156# a_81_n156# 0.02fF
+C11 w_n311_n344# a_n173_n125# 0.14fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_111_n125# a_n173_n125# 0.08fF
+C1 a_111_n125# a_n81_n125# 0.13fF
+C2 a_15_n125# a_n173_n125# 0.13fF
+C3 a_15_n125# a_n81_n125# 0.36fF
+C4 a_n173_n125# a_n81_n125# 0.36fF
+C5 a_111_n125# a_15_n125# 0.36fF
+C6 a_81_n151# a_n15_n151# 0.02fF
+C7 a_n111_n151# a_n15_n151# 0.02fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 vdd m1_187_n605# 0.55fF
+C1 vdd m1_45_n513# 0.69fF
+C2 m1_45_n513# m1_187_n605# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_15_n125# w_n311_n344# 0.09fF
+C2 a_15_n125# a_111_n125# 0.36fF
+C3 w_n311_n344# a_n81_n125# 0.09fF
+C4 a_n173_n125# a_15_n125# 0.13fF
+C5 a_111_n125# a_n81_n125# 0.13fF
+C6 a_n173_n125# a_n81_n125# 0.36fF
+C7 a_15_n125# a_n81_n125# 0.36fF
+C8 w_n311_n344# a_111_n125# 0.14fF
+C9 a_n173_n125# w_n311_n344# 0.14fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_n81_n125# 0.36fF
+C1 a_n173_n125# a_15_n125# 0.13fF
+C2 a_111_n125# a_n81_n125# 0.13fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 a_15_n125# a_n81_n125# 0.36fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in CLK 0.31fF
+C1 inverter_cp_x1_2/in CLK_d 0.12fF
+C2 inverter_cp_x1_2/in vdd 0.21fF
+C3 CLK inverter_cp_x1_0/out 0.31fF
+C4 nCLK_d inverter_cp_x1_0/out 0.11fF
+C5 vdd CLK 0.36fF
+C6 vdd nCLK_d 0.03fF
+C7 vdd CLK_d 0.03fF
+C8 vdd inverter_cp_x1_0/out 0.28fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_63_n95# w_n263_n314# 0.11fF
+C1 w_n263_n314# a_n125_n95# 0.11fF
+C2 a_n33_n95# a_63_n95# 0.28fF
+C3 a_n33_n95# a_n125_n95# 0.28fF
+C4 a_63_n95# a_n125_n95# 0.10fF
+C5 a_n33_n95# w_n263_n314# 0.08fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_15_n125# a_n173_n125# 0.13fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_n129_n213# a_n173_n125# 0.02fF
+C4 a_15_n125# a_111_n125# 0.36fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_15_n125# a_n81_n125# 0.36fF
+C7 a_n129_n213# a_111_n125# 0.01fF
+C8 a_15_n125# a_n129_n213# 0.10fF
+C9 a_n81_n125# a_n129_n213# 0.10fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n81_n183# a_n33_n95# 0.10fF
+C1 a_n33_n95# a_n125_n95# 0.88fF
+C2 a_n81_n183# a_n125_n95# 0.16fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 m1_657_280# CLK 0.24fF
+C1 nQ nD 0.05fF
+C2 D Q 0.05fF
+C3 vdd Q 0.16fF
+C4 D nQ 0.05fF
+C5 nQ Q 0.93fF
+C6 nQ vdd 0.16fF
+C7 m1_657_280# Q 0.94fF
+C8 nD Q 0.05fF
+C9 m1_657_280# nQ 1.41fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
++ clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C1 latch_diff_1/D latch_diff_0/nD 0.41fF
+C2 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C4 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C5 nQ latch_diff_1/D 0.11fF
+C6 latch_diff_1/D latch_diff_1/nD 0.33fF
+C7 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C8 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C9 latch_diff_1/D latch_diff_0/D 0.11fF
+C10 latch_diff_1/D vdd 0.03fF
+C11 latch_diff_0/nD vdd 0.14fF
+C12 latch_diff_1/nD Q 0.01fF
+C13 nQ latch_diff_1/nD 0.08fF
+C14 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C15 latch_diff_1/nD latch_diff_0/D 0.04fF
+C16 latch_diff_1/nD vdd 0.02fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C18 latch_diff_0/D vdd 0.09fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n129_n84# a_n221_n84# 0.24fF
+C1 a_n221_n84# w_n359_n303# 0.08fF
+C2 a_n129_n84# w_n359_n303# 0.06fF
+C3 a_n33_n84# a_63_n84# 0.24fF
+C4 a_n63_n110# a_33_n110# 0.02fF
+C5 a_63_n84# a_n221_n84# 0.05fF
+C6 a_n129_n84# a_63_n84# 0.09fF
+C7 a_n63_n110# a_n159_n110# 0.02fF
+C8 a_63_n84# w_n359_n303# 0.06fF
+C9 a_n33_n84# a_159_n84# 0.09fF
+C10 a_n221_n84# a_159_n84# 0.04fF
+C11 a_n129_n84# a_159_n84# 0.05fF
+C12 w_n359_n303# a_159_n84# 0.08fF
+C13 a_33_n110# a_129_n110# 0.02fF
+C14 a_63_n84# a_159_n84# 0.24fF
+C15 a_n33_n84# a_n221_n84# 0.09fF
+C16 a_n33_n84# a_n129_n84# 0.24fF
+C17 a_n33_n84# w_n359_n303# 0.05fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_63_n42# 0.12fF
+C1 a_n33_n42# a_n221_n42# 0.05fF
+C2 a_n221_n42# a_63_n42# 0.03fF
+C3 a_n33_n42# a_n129_n42# 0.12fF
+C4 a_n129_n42# a_63_n42# 0.05fF
+C5 a_n63_n68# a_33_n68# 0.02fF
+C6 a_n129_n42# a_n221_n42# 0.12fF
+C7 a_129_n68# a_33_n68# 0.02fF
+C8 a_n63_n68# a_n159_n68# 0.02fF
+C9 a_n33_n42# a_159_n42# 0.05fF
+C10 a_159_n42# a_63_n42# 0.12fF
+C11 a_159_n42# a_n221_n42# 0.02fF
+C12 a_159_n42# a_n129_n42# 0.03fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 out vdd 0.62fF
+C1 in vdd 0.33fF
+C2 in out 0.67fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_255_n84# a_351_n84# 0.24fF
+C1 a_n417_n84# a_n705_n84# 0.05fF
+C2 a_639_n84# w_n935_n303# 0.04fF
+C3 a_351_n84# a_159_n84# 0.09fF
+C4 a_n321_n84# a_n705_n84# 0.04fF
+C5 a_n225_n84# a_n513_n84# 0.05fF
+C6 a_n33_n84# a_63_n84# 0.24fF
+C7 a_735_n84# a_543_n84# 0.09fF
+C8 a_n609_n84# a_n705_n84# 0.24fF
+C9 a_543_n84# a_447_n84# 0.24fF
+C10 a_n417_n84# a_n225_n84# 0.09fF
+C11 a_543_n84# a_255_n84# 0.05fF
+C12 a_735_n84# a_447_n84# 0.05fF
+C13 a_n225_n84# a_n129_n84# 0.24fF
+C14 a_n417_n84# a_n513_n84# 0.24fF
+C15 a_159_n84# a_n225_n84# 0.04fF
+C16 a_351_n84# a_63_n84# 0.05fF
+C17 a_n321_n84# a_n225_n84# 0.24fF
+C18 a_255_n84# a_447_n84# 0.09fF
+C19 a_543_n84# a_159_n84# 0.04fF
+C20 w_n935_n303# a_n705_n84# 0.04fF
+C21 a_n129_n84# a_n513_n84# 0.04fF
+C22 a_n225_n84# a_n609_n84# 0.04fF
+C23 a_n321_n84# a_n513_n84# 0.09fF
+C24 a_159_n84# a_447_n84# 0.05fF
+C25 a_255_n84# a_n129_n84# 0.04fF
+C26 a_n417_n84# a_n129_n84# 0.05fF
+C27 a_255_n84# a_159_n84# 0.24fF
+C28 a_n417_n84# a_n321_n84# 0.24fF
+C29 a_n797_n84# a_n705_n84# 0.24fF
+C30 a_n513_n84# a_n609_n84# 0.24fF
+C31 a_351_n84# a_639_n84# 0.05fF
+C32 a_63_n84# a_n225_n84# 0.05fF
+C33 a_159_n84# a_n129_n84# 0.05fF
+C34 a_n417_n84# a_n609_n84# 0.09fF
+C35 a_n321_n84# a_n129_n84# 0.09fF
+C36 a_543_n84# w_n935_n303# 0.03fF
+C37 a_63_n84# a_447_n84# 0.04fF
+C38 a_n321_n84# a_n609_n84# 0.05fF
+C39 a_255_n84# a_63_n84# 0.09fF
+C40 a_735_n84# w_n935_n303# 0.08fF
+C41 a_n513_n84# w_n935_n303# 0.02fF
+C42 a_447_n84# w_n935_n303# 0.02fF
+C43 a_n33_n84# a_351_n84# 0.04fF
+C44 a_63_n84# a_n129_n84# 0.09fF
+C45 a_543_n84# a_639_n84# 0.24fF
+C46 a_n797_n84# a_n513_n84# 0.05fF
+C47 a_159_n84# a_63_n84# 0.24fF
+C48 a_n321_n84# a_63_n84# 0.04fF
+C49 a_n417_n84# a_n797_n84# 0.04fF
+C50 a_735_n84# a_639_n84# 0.24fF
+C51 a_447_n84# a_639_n84# 0.09fF
+C52 a_255_n84# a_639_n84# 0.04fF
+C53 w_n935_n303# a_n609_n84# 0.03fF
+C54 a_n33_n84# a_n225_n84# 0.09fF
+C55 a_n797_n84# a_n609_n84# 0.09fF
+C56 a_n33_n84# a_255_n84# 0.05fF
+C57 a_n417_n84# a_n33_n84# 0.04fF
+C58 a_543_n84# a_351_n84# 0.09fF
+C59 a_n797_n84# w_n935_n303# 0.08fF
+C60 a_n33_n84# a_n129_n84# 0.24fF
+C61 a_735_n84# a_351_n84# 0.04fF
+C62 a_n33_n84# a_159_n84# 0.09fF
+C63 a_n513_n84# a_n705_n84# 0.09fF
+C64 a_n33_n84# a_n321_n84# 0.05fF
+C65 a_351_n84# a_447_n84# 0.24fF
+C66 a_735_n84# VSUBS 0.03fF
+C67 a_639_n84# VSUBS 0.03fF
+C68 a_543_n84# VSUBS 0.03fF
+C69 a_447_n84# VSUBS 0.03fF
+C70 a_351_n84# VSUBS 0.03fF
+C71 a_255_n84# VSUBS 0.03fF
+C72 a_159_n84# VSUBS 0.03fF
+C73 a_63_n84# VSUBS 0.03fF
+C74 a_n33_n84# VSUBS 0.03fF
+C75 a_n129_n84# VSUBS 0.03fF
+C76 a_n225_n84# VSUBS 0.03fF
+C77 a_n321_n84# VSUBS 0.03fF
+C78 a_n417_n84# VSUBS 0.03fF
+C79 a_n513_n84# VSUBS 0.03fF
+C80 a_n609_n84# VSUBS 0.03fF
+C81 a_n705_n84# VSUBS 0.03fF
+C82 a_n797_n84# VSUBS 0.03fF
+C83 a_n753_n181# VSUBS 2.56fF
+C84 w_n935_n303# VSUBS 4.96fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_351_n42# a_159_n42# 0.05fF
+C1 a_n797_n42# a_n609_n42# 0.05fF
+C2 a_n417_n42# a_n225_n42# 0.05fF
+C3 a_n129_n42# a_255_n42# 0.02fF
+C4 a_n33_n42# a_351_n42# 0.02fF
+C5 a_159_n42# a_255_n42# 0.12fF
+C6 a_n513_n42# a_n417_n42# 0.12fF
+C7 a_n417_n42# a_n705_n42# 0.03fF
+C8 a_351_n42# a_543_n42# 0.05fF
+C9 a_543_n42# a_639_n42# 0.12fF
+C10 a_n129_n42# a_n225_n42# 0.12fF
+C11 a_n33_n42# a_255_n42# 0.03fF
+C12 a_351_n42# a_639_n42# 0.03fF
+C13 a_n225_n42# a_159_n42# 0.02fF
+C14 a_543_n42# a_255_n42# 0.03fF
+C15 a_n129_n42# a_n513_n42# 0.02fF
+C16 a_n129_n42# a_63_n42# 0.05fF
+C17 a_351_n42# a_255_n42# 0.12fF
+C18 a_n417_n42# a_n321_n42# 0.12fF
+C19 a_639_n42# a_255_n42# 0.02fF
+C20 a_n33_n42# a_n225_n42# 0.05fF
+C21 a_n513_n42# a_n797_n42# 0.03fF
+C22 a_n797_n42# a_n705_n42# 0.12fF
+C23 a_159_n42# a_63_n42# 0.12fF
+C24 a_n609_n42# a_n225_n42# 0.02fF
+C25 a_n129_n42# a_n321_n42# 0.05fF
+C26 a_735_n42# a_447_n42# 0.03fF
+C27 a_n33_n42# a_63_n42# 0.12fF
+C28 a_n513_n42# a_n609_n42# 0.12fF
+C29 a_n609_n42# a_n705_n42# 0.12fF
+C30 a_159_n42# a_447_n42# 0.03fF
+C31 a_351_n42# a_63_n42# 0.03fF
+C32 a_n33_n42# a_n321_n42# 0.03fF
+C33 a_543_n42# a_447_n42# 0.12fF
+C34 a_255_n42# a_63_n42# 0.05fF
+C35 a_n129_n42# a_n417_n42# 0.03fF
+C36 a_n609_n42# a_n321_n42# 0.03fF
+C37 a_351_n42# a_447_n42# 0.12fF
+C38 a_639_n42# a_447_n42# 0.05fF
+C39 a_n513_n42# a_n225_n42# 0.03fF
+C40 a_n417_n42# a_n797_n42# 0.02fF
+C41 a_n225_n42# a_63_n42# 0.03fF
+C42 a_n513_n42# a_n705_n42# 0.05fF
+C43 a_447_n42# a_255_n42# 0.05fF
+C44 a_n33_n42# a_n417_n42# 0.02fF
+C45 a_n129_n42# a_159_n42# 0.03fF
+C46 a_n225_n42# a_n321_n42# 0.12fF
+C47 a_n417_n42# a_n609_n42# 0.05fF
+C48 a_n129_n42# a_n33_n42# 0.12fF
+C49 a_543_n42# a_735_n42# 0.05fF
+C50 a_n513_n42# a_n321_n42# 0.05fF
+C51 a_n705_n42# a_n321_n42# 0.02fF
+C52 a_n33_n42# a_159_n42# 0.05fF
+C53 a_n321_n42# a_63_n42# 0.02fF
+C54 a_351_n42# a_735_n42# 0.02fF
+C55 a_735_n42# a_639_n42# 0.12fF
+C56 a_447_n42# a_63_n42# 0.02fF
+C57 a_543_n42# a_159_n42# 0.02fF
+C58 a_735_n42# w_n935_n252# 0.07fF
+C59 a_639_n42# w_n935_n252# 0.05fF
+C60 a_543_n42# w_n935_n252# 0.05fF
+C61 a_447_n42# w_n935_n252# 0.04fF
+C62 a_351_n42# w_n935_n252# 0.04fF
+C63 a_255_n42# w_n935_n252# 0.04fF
+C64 a_159_n42# w_n935_n252# 0.04fF
+C65 a_63_n42# w_n935_n252# 0.04fF
+C66 a_n33_n42# w_n935_n252# 0.04fF
+C67 a_n129_n42# w_n935_n252# 0.04fF
+C68 a_n225_n42# w_n935_n252# 0.04fF
+C69 a_n321_n42# w_n935_n252# 0.04fF
+C70 a_n417_n42# w_n935_n252# 0.04fF
+C71 a_n513_n42# w_n935_n252# 0.04fF
+C72 a_n609_n42# w_n935_n252# 0.05fF
+C73 a_n705_n42# w_n935_n252# 0.05fF
+C74 a_n797_n42# w_n935_n252# 0.07fF
+C75 a_n757_64# w_n935_n252# 2.44fF
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+C0 vdd in 1.15fF
+C1 vdd out 1.63fF
+C2 in out 1.40fF
+C3 out vss 0.98fF
+C4 in vss 7.30fF
+C5 vdd vss 10.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n129_n102# w_n359_n321# 0.07fF
+C1 a_n33_n102# a_n129_n102# 0.30fF
+C2 a_159_n102# w_n359_n321# 0.10fF
+C3 a_159_n102# a_n33_n102# 0.11fF
+C4 a_63_n102# w_n359_n321# 0.07fF
+C5 a_63_n102# a_n33_n102# 0.30fF
+C6 a_159_n102# a_n129_n102# 0.07fF
+C7 a_63_n102# a_n129_n102# 0.11fF
+C8 a_n177_n199# a_25_n199# 0.07fF
+C9 a_63_n102# a_159_n102# 0.30fF
+C10 a_n221_n102# w_n359_n321# 0.10fF
+C11 a_n221_n102# a_n33_n102# 0.11fF
+C12 a_n221_n102# a_n129_n102# 0.30fF
+C13 a_n33_n102# w_n359_n321# 0.06fF
+C14 a_159_n102# a_n221_n102# 0.05fF
+C15 a_63_n102# a_n221_n102# 0.07fF
+C16 a_159_n102# VSUBS 0.03fF
+C17 a_63_n102# VSUBS 0.03fF
+C18 a_n33_n102# VSUBS 0.03fF
+C19 a_n129_n102# VSUBS 0.03fF
+C20 a_n221_n102# VSUBS 0.03fF
+C21 a_25_n199# VSUBS 0.22fF
+C22 a_n177_n199# VSUBS 0.22fF
+C23 w_n359_n321# VSUBS 2.35fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n125_n102# a_63_n102# 0.11fF
+C1 a_n125_n102# a_n33_n102# 0.30fF
+C2 a_n33_n102# a_63_n102# 0.30fF
+C3 a_63_n102# w_n263_n312# 0.06fF
+C4 a_n33_n102# w_n263_n312# 0.08fF
+C5 a_n125_n102# w_n263_n312# 0.12fF
+C6 a_n81_124# w_n263_n312# 0.21fF
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out m1_21_n341#
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+C0 out m1_21_n341# 0.13fF
+C1 out avdd1p8 0.20fF
+C2 avdd1p8 in2 0.02fF
+C3 out in1 0.10fF
+C4 m1_21_n341# avdd1p8 0.01fF
+C5 in1 in2 0.07fF
+C6 m1_21_n341# in1 0.25fF
+C7 out in2 0.37fF
+C8 m1_21_n341# avss1p8 0.92fF
+C9 out avss1p8 0.47fF
+C10 in2 avss1p8 0.91fF
+C11 in1 avss1p8 0.93fF
+C12 avdd1p8 avss1p8 2.37fF
+.ends
+
+.subckt res_amp_sync_v2 avdd1p8 DFlipFlop_4/Q vss clkn DFlipFlop_4/latch_diff_1/m1_657_280#
++ DFlipFlop_4/nQ DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_3/Q
++ DFlipFlop_3/D DFlipFlop_4/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_1/D DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
++ rst
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
++ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic_0/m1_21_n341#
++ nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
++ nand_logic
+C0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C1 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
+C2 clkp avdd1p8 0.53fF
+C3 DFlipFlop_1/latch_diff_0/D DFlipFlop_0/Q 0.74fF
+C4 DFlipFlop_3/Q clkn 0.12fF
+C5 DFlipFlop_2/D DFlipFlop_2/nQ 0.03fF
+C6 nand_logic_1/m1_21_n341# nand_logic_1/out 0.01fF
+C7 DFlipFlop_4/Q avdd1p8 4.03fF
+C8 clkn DFlipFlop_4/latch_diff_1/D 0.08fF
+C9 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C10 DFlipFlop_0/Q avdd1p8 0.66fF
+C11 clkp DFlipFlop_4/nQ 0.02fF
+C12 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_3/D 0.43fF
+C13 clkp DFlipFlop_2/Q 0.11fF
+C14 clkp DFlipFlop_3/D 0.35fF
+C15 clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C16 DFlipFlop_0/latch_diff_0/D DFlipFlop_3/D 0.31fF
+C17 nand_logic_1/out avdd1p8 0.04fF
+C18 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
+C19 DFlipFlop_3/nQ avdd1p8 0.03fF
+C20 DFlipFlop_2/D avdd1p8 4.16fF
+C21 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C22 clk_amp inverter_min_x4_4/out 0.12fF
+C23 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
+C24 DFlipFlop_3/Q nand_logic_0/out 0.01fF
+C25 DFlipFlop_4/Q DFlipFlop_4/nQ 0.06fF
+C26 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
+C27 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
+C28 clkp DFlipFlop_2/latch_diff_0/nD 0.08fF
+C29 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
+C30 clkp DFlipFlop_3/Q 0.17fF
+C31 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C32 DFlipFlop_1/nQ DFlipFlop_3/D 0.05fF
+C33 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C34 DFlipFlop_3/Q nand_logic_0/m1_21_n341# 0.07fF
+C35 DFlipFlop_4/D avdd1p8 0.52fF
+C36 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
+C37 clkp DFlipFlop_4/latch_diff_1/D 0.15fF
+C38 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
+C39 clkp clkn 0.22fF
+C40 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
+C41 clkp DFlipFlop_2/latch_diff_0/m1_657_280# 0.30fF
+C42 DFlipFlop_4/Q DFlipFlop_3/Q 0.11fF
+C43 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
+C44 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
+C45 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C46 clkp inverter_min_x4_4/out 0.43fF
+C47 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/D 0.54fF
+C48 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
+C49 clkp clk_amp 0.52fF
+C50 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
+C51 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
+C52 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C53 DFlipFlop_4/latch_diff_1/nD clkp 0.10fF
+C54 DFlipFlop_1/nQ DFlipFlop_1/D 0.02fF
+C55 DFlipFlop_2/latch_diff_0/D clkn 0.12fF
+C56 DFlipFlop_4/Q inverter_min_x4_4/out 0.01fF
+C57 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
+C58 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
+C59 DFlipFlop_3/nQ clkn 0.10fF
+C60 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C61 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
+C62 rst nand_logic_1/out 0.04fF
+C63 DFlipFlop_2/D clkn 0.15fF
+C64 DFlipFlop_2/D DFlipFlop_1/D 0.02fF
+C65 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
+C66 DFlipFlop_0/nQ DFlipFlop_3/D 0.08fF
+C67 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C68 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C69 clkp DFlipFlop_3/latch_diff_0/nD 0.08fF
+C70 DFlipFlop_0/latch_diff_1/D DFlipFlop_3/D 0.08fF
+C71 clkp DFlipFlop_4/latch_diff_0/m1_657_280# 0.30fF
+C72 DFlipFlop_4/D clkn 0.15fF
+C73 DFlipFlop_4/Q clkp 0.20fF
+C74 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C75 DFlipFlop_0/latch_diff_1/nD clkn 0.17fF
+C76 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
+C77 DFlipFlop_3/Q DFlipFlop_2/latch_diff_1/m1_657_280# 0.04fF
+C78 DFlipFlop_3/Q DFlipFlop_2/nQ 0.02fF
+C79 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
+C80 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
+C81 avdd1p8 DFlipFlop_2/Q 0.05fF
+C82 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C83 DFlipFlop_3/D avdd1p8 4.16fF
+C84 clkp nand_logic_1/out 0.03fF
+C85 DFlipFlop_0/nQ clkn 0.02fF
+C86 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C87 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C88 clkp DFlipFlop_3/nQ 0.13fF
+C89 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
+C90 clkn DFlipFlop_2/nQ 0.02fF
+C91 clkp DFlipFlop_2/D 0.15fF
+C92 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
+C93 clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
+C94 DFlipFlop_1/nQ DFlipFlop_0/Q 0.01fF
+C95 DFlipFlop_4/D nand_logic_0/out 0.04fF
+C96 DFlipFlop_3/Q avdd1p8 0.76fF
+C97 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
+C98 nand_logic_1/m1_21_n341# rst 0.02fF
+C99 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
+C100 clkp DFlipFlop_4/D 0.24fF
+C101 clkn DFlipFlop_2/latch_diff_1/nD 0.17fF
+C102 DFlipFlop_2/latch_diff_1/D DFlipFlop_2/D 0.03fF
+C103 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
+C104 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C105 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
+C106 DFlipFlop_4/D nand_logic_0/m1_21_n341# 0.02fF
+C107 DFlipFlop_3/latch_diff_0/D clkn 0.12fF
+C108 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
+C109 avdd1p8 clkn -1.00fF
+C110 DFlipFlop_1/D avdd1p8 2.55fF
+C111 rst avdd1p8 0.02fF
+C112 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
+C113 avdd1p8 inverter_min_x4_4/out 0.09fF
+C114 DFlipFlop_4/Q DFlipFlop_4/D 0.27fF
+C115 clkp DFlipFlop_0/nQ 0.02fF
+C116 clk_amp avdd1p8 0.10fF
+C117 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C118 clkp DFlipFlop_2/nQ 0.13fF
+C119 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C120 clkp DFlipFlop_0/latch_diff_1/D 0.15fF
+C121 DFlipFlop_3/Q DFlipFlop_2/Q 0.09fF
+C122 clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C123 nand_logic_1/m1_21_n341# clkp 0.09fF
+C124 DFlipFlop_4/D nand_logic_1/out 0.01fF
+C125 clkp DFlipFlop_3/latch_diff_1/D 0.15fF
+C126 DFlipFlop_4/nQ clkn 0.02fF
+C127 clkp DFlipFlop_2/latch_diff_1/nD 0.20fF
+C128 DFlipFlop_3/D clkn 0.35fF
+C129 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
+C130 DFlipFlop_0/Q DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.55fF
+C131 avdd1p8 nand_logic_0/out 0.03fF
+C132 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C133 DFlipFlop_4/D DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out 0.42fF
+C134 DFlipFlop_4/latch_diff_1/m1_657_280# clkn 0.30fF
+C135 nand_logic_1/m1_21_n341# vss 0.86fF
+C136 nand_logic_0/m1_21_n341# vss 0.90fF
+C137 clk_amp vss 0.43fF
+C138 inverter_min_x4_4/out vss 5.90fF
+C139 nand_logic_1/out vss 1.76fF
+C140 rst vss 0.71fF
+C141 DFlipFlop_4/nQ vss 0.48fF
+C142 DFlipFlop_4/Q vss -2.08fF
+C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
+C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
+C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C150 DFlipFlop_4/D vss 4.59fF
+C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
+C152 nand_logic_0/out vss 1.26fF
+C153 DFlipFlop_0/Q vss -3.86fF
+C154 DFlipFlop_3/nQ vss 0.50fF
+C155 DFlipFlop_3/Q vss -2.01fF
+C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C157 clkn vss -2.25fF
+C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C161 clkp vss -22.80fF
+C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C165 DFlipFlop_3/D vss 1.64fF
+C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C167 avdd1p8 vss 196.01fF
+C168 DFlipFlop_2/nQ vss 0.48fF
+C169 DFlipFlop_2/Q vss -1.05fF
+C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 DFlipFlop_2/D vss -0.35fF
+C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 DFlipFlop_1/nQ vss 0.48fF
+C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
+C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C187 DFlipFlop_1/D vss -1.00fF
+C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C189 DFlipFlop_0/nQ vss 0.48fF
+C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_n221_n200# a_35_n200# 0.15fF
+C1 w_n487_n419# a_291_n200# 0.18fF
+C2 a_n93_n200# a_n291_n238# 0.08fF
+C3 a_291_n200# a_163_n200# 0.36fF
+C4 w_n487_n419# a_163_n200# 0.08fF
+C5 a_35_n200# a_n291_n238# 0.08fF
+C6 a_n221_n200# w_n487_n419# 0.08fF
+C7 a_n221_n200# a_163_n200# 0.09fF
+C8 a_n291_n238# w_n487_n419# 0.30fF
+C9 a_n291_n238# a_163_n200# 0.08fF
+C10 a_n93_n200# a_n349_n200# 0.15fF
+C11 a_n221_n200# a_n291_n238# 0.08fF
+C12 a_35_n200# a_n349_n200# 0.09fF
+C13 w_n487_n419# a_n349_n200# 0.18fF
+C14 a_n221_n200# a_n349_n200# 0.36fF
+C15 a_n93_n200# a_35_n200# 0.36fF
+C16 a_n93_n200# a_291_n200# 0.09fF
+C17 a_n93_n200# w_n487_n419# 0.06fF
+C18 a_n93_n200# a_163_n200# 0.15fF
+C19 a_35_n200# a_291_n200# 0.15fF
+C20 a_35_n200# w_n487_n419# 0.06fF
+C21 a_n93_n200# a_n221_n200# 0.36fF
+C22 a_35_n200# a_163_n200# 0.36fF
+C23 a_291_n200# VSUBS 0.03fF
+C24 a_163_n200# VSUBS 0.03fF
+C25 a_35_n200# VSUBS 0.03fF
+C26 a_n93_n200# VSUBS 0.03fF
+C27 a_n221_n200# VSUBS 0.03fF
+C28 a_n349_n200# VSUBS 0.03fF
+C29 a_n291_n238# VSUBS 0.72fF
+C30 w_n487_n419# VSUBS 4.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n73# a_n33_33# 0.02fF
+C1 a_n33_33# a_15_n73# 0.02fF
+C2 a_n73_n73# a_15_n73# 0.15fF
+C3 a_15_n73# w_n211_n221# 0.11fF
+C4 a_n73_n73# w_n211_n221# 0.11fF
+C5 a_n33_33# w_n211_n221# 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_n48# a_15_n48# 0.29fF
+C1 a_n33_n145# a_n73_n48# 0.01fF
+C2 a_n73_n48# w_n211_n268# 0.13fF
+C3 a_n33_n145# a_15_n48# 0.01fF
+C4 a_15_n48# w_n211_n268# 0.13fF
+C5 a_n33_n145# w_n211_n268# 0.06fF
+C6 a_15_n48# VSUBS 0.03fF
+C7 a_n73_n48# VSUBS 0.03fF
+C8 a_n33_n145# VSUBS 0.12fF
+C9 w_n211_n268# VSUBS 1.50fF
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+C0 vdd out 0.20fF
+C1 vdd in 0.13fF
+C2 out in 0.67fF
+C3 out vss 0.52fF
+C4 in vss 0.72fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+C0 out inverter_min_1/in 0.12fF
+C1 inverter_min_1/in avdd1p8 0.09fF
+C2 out avdd1p8 0.02fF
+C3 in inverter_min_1/in 0.07fF
+C4 in VSUBS 0.63fF
+C5 avdd1p8 VSUBS 4.78fF
+C6 out VSUBS 0.45fF
+C7 inverter_min_1/in VSUBS 1.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_21_142# a_63_n111# 0.02fF
+C1 a_21_142# w_n263_n330# 0.05fF
+C2 w_n263_n330# a_n87_142# 0.05fF
+C3 a_n125_n111# a_n87_142# 0.02fF
+C4 a_63_n111# w_n263_n330# 0.14fF
+C5 a_n33_n111# a_63_n111# 0.32fF
+C6 a_63_n111# a_n125_n111# 0.12fF
+C7 a_n33_n111# w_n263_n330# 0.10fF
+C8 w_n263_n330# a_n125_n111# 0.14fF
+C9 a_n33_n111# a_n125_n111# 0.32fF
+C10 a_21_142# a_n87_142# 0.14fF
+C11 a_63_n111# VSUBS 0.03fF
+C12 a_n33_n111# VSUBS 0.03fF
+C13 a_n125_n111# VSUBS 0.03fF
+C14 a_21_142# VSUBS 0.16fF
+C15 a_n87_142# VSUBS 0.16fF
+C16 w_n263_n330# VSUBS 2.11fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n73_n142# a_n33_102# 0.03fF
+C1 a_15_n142# a_n73_n142# 0.38fF
+C2 a_15_n142# a_n33_102# 0.03fF
+C3 a_15_n142# w_n211_n290# 0.19fF
+C4 a_n73_n142# w_n211_n290# 0.19fF
+C5 a_n33_102# w_n211_n290# 0.21fF
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 sel_b w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+C0 DinA DinB 0.07fF
+C1 sel_b DinA 0.56fF
+C2 out DinA 0.30fF
+C3 sel_b DinB 0.27fF
+C4 sel DinA 0.07fF
+C5 out DinB 0.37fF
+C6 out sel_b 0.58fF
+C7 sel DinB 0.02fF
+C8 sel_b sel 0.32fF
+C9 out sel 0.53fF
+C10 avdd1p8 DinA 0.26fF
+C11 avdd1p8 DinB 0.16fF
+C12 sel_b avdd1p8 0.74fF
+C13 out avdd1p8 0.23fF
+C14 avdd1p8 sel 0.72fF
+C15 DinA avss1p8 0.63fF
+C16 sel_b avss1p8 2.16fF
+C17 out avss1p8 1.11fF
+C18 DinB avss1p8 -0.09fF
+C19 sel avss1p8 2.55fF
+C20 avdd1p8 avss1p8 8.26fF
+.ends
+
+.subckt delay_cell_buff buffer_no_inv_x05_2/inverter_min_1/in reg2 avss1p8 mux_2to1_logic_4/DinA
++ avdd1p8 buffer_no_inv_x05_13/in clk mux_2to1_logic_3/DinA clk_out mux_2to1_logic_3/DinB
++ reg0 buffer_no_inv_x05_10/inverter_min_1/in reg1 buffer_no_inv_x05_7/inverter_min_1/in
++ nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b mux_2to1_logic_4/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/sel_b buffer_no_inv_x05_3/in mux_2to1_logic_5/out
++ mux_2to1_logic_0/out mux_2to1_logic_4/DinB mux_2to1_logic_3/out buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_1/out mux_2to1_logic_5/w_947_n633# buffer_no_inv_x05_12/inverter_min_1/in
++ nand_logic_0/m1_21_n341#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in
++ buffer_no_inv_x05_9/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in
++ mux_2to1_logic_3/DinB buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/sel_b mux_2to1_logic_0/w_947_n633#
++ avss1p8 mux_2to1_logic_0/out clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/sel_b mux_2to1_logic_1/w_947_n633#
++ avss1p8 mux_2to1_logic_1/out mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/sel_b mux_2to1_logic_2/w_947_n633#
++ avss1p8 mux_2to1_logic_2/out mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/sel_b mux_2to1_logic_3/w_947_n633#
++ avss1p8 mux_2to1_logic_3/out mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/sel_b mux_2to1_logic_4/w_947_n633#
++ avss1p8 mux_2to1_logic_4/out mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/sel_b mux_2to1_logic_5/w_947_n633#
++ avss1p8 mux_2to1_logic_5/out mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/sel_b mux_2to1_logic_6/w_947_n633#
++ avss1p8 nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in
++ buffer_no_inv_x05_11/in buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic_0/m1_21_n341#
++ nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in
++ mux_2to1_logic_4/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in
++ buffer_no_inv_x05_13/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_4/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in
++ buffer_no_inv_x05_3/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in
++ mux_2to1_logic_0/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in
++ mux_2to1_logic_1/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in
++ buffer_no_inv_x05_5/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in
++ mux_2to1_logic_1/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in
++ buffer_no_inv_x05_7/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
++ mux_2to1_logic_3/DinA buffer_no_inv_x05
+C0 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
+C1 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
+C2 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
+C3 reg2 mux_2to1_logic_4/DinB 0.05fF
+C4 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_4/sel_b 0.01fF
+C5 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
+C6 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
+C7 mux_2to1_logic_0/out reg1 0.63fF
+C8 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C9 clk mux_2to1_logic_0/out 0.05fF
+C10 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
+C11 reg2 mux_2to1_logic_1/DinA 0.18fF
+C12 mux_2to1_logic_4/DinA mux_2to1_logic_4/out 0.27fF
+C13 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinA 0.07fF
+C14 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
+C15 reg1 mux_2to1_logic_4/out 0.37fF
+C16 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinA 0.23fF
+C17 reg0 mux_2to1_logic_4/DinB -0.24fF
+C18 clk mux_2to1_logic_4/DinA 0.01fF
+C19 clk mux_2to1_logic_3/DinA 0.01fF
+C20 mux_2to1_logic_5/sel_b mux_2to1_logic_4/out 0.20fF
+C21 avdd1p8 mux_2to1_logic_1/DinA 0.55fF
+C22 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C23 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
+C24 mux_2to1_logic_5/sel_b reg1 0.06fF
+C25 clk mux_2to1_logic_0/DinB 0.01fF
+C26 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C27 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
+C28 reg1 mux_2to1_logic_1/out 0.36fF
+C29 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
+C30 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
+C31 avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in 0.03fF
+C32 mux_2to1_logic_3/DinB buffer_no_inv_x05_9/inverter_min_1/in 0.18fF
+C33 avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in 0.03fF
+C34 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C35 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
+C36 reg2 mux_2to1_logic_2/out 0.85fF
+C37 reg2 mux_2to1_logic_3/out 0.36fF
+C38 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/inverter_min_1/in 0.23fF
+C39 mux_2to1_logic_3/DinB mux_2to1_logic_4/DinB 0.29fF
+C40 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
+C41 reg2 mux_2to1_logic_0/sel_b 0.14fF
+C42 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C43 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
+C44 avdd1p8 mux_2to1_logic_2/out 0.41fF
+C45 avdd1p8 mux_2to1_logic_3/out 0.39fF
+C46 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
+C47 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C48 mux_2to1_logic_3/sel_b mux_2to1_logic_1/out 0.04fF
+C49 avdd1p8 mux_2to1_logic_0/sel_b 0.05fF
+C50 buffer_no_inv_x05_13/inverter_min_1/in mux_2to1_logic_4/DinB 0.11fF
+C51 mux_2to1_logic_1/DinB buffer_no_inv_x05_4/inverter_min_1/in 0.15fF
+C52 mux_2to1_logic_2/out reg0 0.44fF
+C53 buffer_no_inv_x05_9/in buffer_no_inv_x05_9/inverter_min_1/in 0.12fF
+C54 buffer_no_inv_x05_3/inverter_min_1/in buffer_no_inv_x05_3/in 0.12fF
+C55 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
+C56 mux_2to1_logic_3/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.02fF
+C57 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
+C58 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
+C59 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
+C60 buffer_no_inv_x05_5/inverter_min_1/in buffer_no_inv_x05_5/in 0.12fF
+C61 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
+C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
+C63 buffer_no_inv_x05_13/in buffer_no_inv_x05_12/inverter_min_1/in 0.07fF
+C64 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
+C65 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C66 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
+C67 reg1 mux_2to1_logic_4/DinB 0.40fF
+C68 buffer_no_inv_x05_5/in buffer_no_inv_x05_4/inverter_min_1/in 0.07fF
+C69 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
+C70 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C71 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
+C72 clk mux_2to1_logic_4/DinB 0.12fF
+C73 buffer_no_inv_x05_8/inverter_min_1/in mux_2to1_logic_3/DinA 0.12fF
+C74 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
+C75 mux_2to1_logic_5/sel_b mux_2to1_logic_4/DinB 0.31fF
+C76 mux_2to1_logic_3/DinB buffer_no_inv_x05_7/in 0.10fF
+C77 clk mux_2to1_logic_1/DinA 0.01fF
+C78 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
+C79 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinA 0.04fF
+C80 reg2 mux_2to1_logic_1/DinB 0.07fF
+C81 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
+C82 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C83 avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in 0.01fF
+C84 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
+C85 mux_2to1_logic_1/DinB buffer_no_inv_x05_5/in 0.15fF
+C86 mux_2to1_logic_4/DinA buffer_no_inv_x05_11/inverter_min_1/in 0.08fF
+C87 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
+C88 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C89 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
+C90 avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in 0.03fF
+C91 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
+C92 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
+C93 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
+C94 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
+C95 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
+C96 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
+C97 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
+C98 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
+C99 reg1 mux_2to1_logic_2/out 1.41fF
+C100 mux_2to1_logic_3/out reg1 0.47fF
+C101 mux_2to1_logic_5/sel_b mux_2to1_logic_2/out 0.20fF
+C102 mux_2to1_logic_5/sel_b mux_2to1_logic_3/out 0.37fF
+C103 mux_2to1_logic_3/sel_b buffer_no_inv_x05_6/inverter_min_1/in 0.01fF
+C104 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
+C105 mux_2to1_logic_2/out mux_2to1_logic_1/out 0.35fF
+C106 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C107 reg2 mux_2to1_logic_4/sel_b 0.06fF
+C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
+C109 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C110 reg2 avdd1p8 0.14fF
+C111 mux_2to1_logic_3/sel_b mux_2to1_logic_2/out 0.33fF
+C112 clk_out nand_logic_0/m1_21_n341# 0.02fF
+C113 buffer_no_inv_x05_3/inverter_min_1/in avdd1p8 0.03fF
+C114 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
+C115 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
+C116 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
+C117 mux_2to1_logic_5/out mux_2to1_logic_3/out 0.07fF
+C118 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
+C119 avdd1p8 reg0 0.05fF
+C120 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C121 mux_2to1_logic_6/sel_b mux_2to1_logic_4/DinB 0.28fF
+C122 reg2 mux_2to1_logic_2/sel_b 0.07fF
+C123 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
+C124 mux_2to1_logic_2/sel_b buffer_no_inv_x05_5/in 0.01fF
+C125 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
+C126 buffer_no_inv_x05_10/inverter_min_1/in buffer_no_inv_x05_11/in 0.07fF
+C127 mux_2to1_logic_3/DinB mux_2to1_logic_4/sel_b 0.04fF
+C128 avdd1p8 clk_out 0.04fF
+C129 reg2 mux_2to1_logic_3/DinB 0.08fF
+C130 buffer_no_inv_x05_1/in buffer_no_inv_x05_0/inverter_min_1/in 0.07fF
+C131 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
+C132 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
+C133 mux_2to1_logic_1/DinB mux_2to1_logic_3/DinA 0.07fF
+C134 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
+C135 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinA 0.21fF
+C136 mux_2to1_logic_4/DinA buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C137 clk mux_2to1_logic_1/DinB 0.01fF
+C138 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C139 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
+C140 mux_2to1_logic_1/DinA buffer_no_inv_x05_2/inverter_min_1/in 0.10fF
+C141 clk buffer_no_inv_x05_13/in 0.07fF
+C142 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C143 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C144 mux_2to1_logic_1/DinB mux_2to1_logic_1/out 0.23fF
+C145 reg2 buffer_no_inv_x05_1/in 0.01fF
+C146 mux_2to1_logic_1/DinB mux_2to1_logic_1/sel_b -0.06fF
+C147 mux_2to1_logic_0/out reg2 0.45fF
+C148 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C149 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
+C150 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinA 0.16fF
+C151 reg2 mux_2to1_logic_3/DinA 0.33fF
+C152 reg2 mux_2to1_logic_4/DinA 0.31fF
+C153 mux_2to1_logic_0/out avdd1p8 0.43fF
+C154 reg2 reg1 2.15fF
+C155 clk reg2 0.12fF
+C156 avdd1p8 mux_2to1_logic_4/out 0.76fF
+C157 reg2 mux_2to1_logic_0/DinB 0.06fF
+C158 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
+C159 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
+C160 avdd1p8 reg1 0.08fF
+C161 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
+C162 buffer_no_inv_x05_6/inverter_min_1/in buffer_no_inv_x05_7/in 0.07fF
+C163 clk avdd1p8 1.01fF
+C164 mux_2to1_logic_5/sel_b avdd1p8 0.09fF
+C165 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
+C166 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
+C167 reg1 reg0 0.01fF
+C168 buffer_no_inv_x05_3/in buffer_no_inv_x05_2/inverter_min_1/in 0.07fF
+C169 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
+C170 avdd1p8 mux_2to1_logic_1/out 0.84fF
+C171 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
+C172 reg2 mux_2to1_logic_1/sel_b 0.13fF
+C173 reg2 mux_2to1_logic_3/sel_b 0.13fF
+C174 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C175 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
+C176 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
+C177 mux_2to1_logic_2/sel_b reg1 0.06fF
+C178 clk clk_out 0.33fF
+C179 mux_2to1_logic_5/out avdd1p8 0.64fF
+C180 mux_2to1_logic_3/DinB mux_2to1_logic_3/DinA 1.18fF
+C181 mux_2to1_logic_2/sel_b mux_2to1_logic_1/out 0.19fF
+C182 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
+C183 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
+C184 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
+C185 clk mux_2to1_logic_3/DinB 0.01fF
+C186 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
+C187 mux_2to1_logic_5/sel_b mux_2to1_logic_3/DinB 0.01fF
+C188 mux_2to1_logic_5/out reg0 0.23fF
+C189 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
+C190 mux_2to1_logic_1/DinB mux_2to1_logic_1/DinA 0.66fF
+C191 mux_2to1_logic_1/DinB buffer_no_inv_x05_6/inverter_min_1/in 0.12fF
+C192 mux_2to1_logic_3/sel_b mux_2to1_logic_3/DinB 0.21fF
+C193 buffer_no_inv_x05_1/inverter_min_1/in buffer_no_inv_x05_1/in 0.12fF
+C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
+C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C205 clk avss1p8 2.54fF
+C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C214 clk_out avss1p8 0.27fF
+C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
+C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C217 nand_logic_0/in1 avss1p8 1.63fF
+C218 reg0 avss1p8 3.16fF
+C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C220 mux_2to1_logic_5/out avss1p8 -1.59fF
+C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
+C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C223 mux_2to1_logic_4/out avss1p8 -2.14fF
+C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C226 mux_2to1_logic_3/out avss1p8 -2.13fF
+C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
+C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C230 reg1 avss1p8 4.95fF
+C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
+C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
+C233 mux_2to1_logic_1/out avss1p8 -2.38fF
+C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C235 reg2 avss1p8 13.29fF
+C236 avdd1p8 avss1p8 125.49fF
+C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C238 mux_2to1_logic_0/out avss1p8 0.32fF
+C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
+C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
+C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n173_n100# 0.29fF
+C1 a_111_n100# a_15_n100# 0.29fF
+C2 a_n81_n100# a_15_n100# 0.29fF
+C3 a_n128_122# a_15_n100# 0.10fF
+C4 a_n173_n100# a_15_n100# 0.11fF
+C5 a_n81_n100# a_111_n100# 0.11fF
+C6 a_111_n100# a_n173_n100# 0.06fF
+C7 a_n81_n100# a_n128_122# 0.10fF
+C8 a_111_n100# w_n311_n310# 0.15fF
+C9 a_15_n100# w_n311_n310# 0.11fF
+C10 a_n81_n100# w_n311_n310# 0.11fF
+C11 a_n173_n100# w_n311_n310# 0.15fF
+C12 a_n128_122# w_n311_n310# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_15_n100# 0.29fF
+C1 a_n81_n100# a_n173_n100# 0.29fF
+C2 a_n81_n100# w_n311_n319# 0.08fF
+C3 a_n81_n100# a_n129_131# 0.08fF
+C4 a_15_n100# a_n173_n100# 0.11fF
+C5 a_15_n100# w_n311_n319# 0.08fF
+C6 a_15_n100# a_n129_131# 0.08fF
+C7 w_n311_n319# a_n173_n100# 0.12fF
+C8 w_n311_n319# a_n129_131# 0.16fF
+C9 a_n81_n100# a_111_n100# 0.11fF
+C10 a_15_n100# a_111_n100# 0.29fF
+C11 a_111_n100# a_n173_n100# 0.06fF
+C12 w_n311_n319# a_111_n100# 0.12fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_131# VSUBS 0.32fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_111_n100# 0.05fF
+C1 a_111_n100# a_207_n100# 0.29fF
+C2 a_15_n100# a_111_n100# 0.29fF
+C3 a_n225_131# a_n177_n100# 0.08fF
+C4 a_n81_n100# w_n407_n319# 0.06fF
+C5 a_n269_n100# a_15_n100# 0.06fF
+C6 a_n81_n100# a_111_n100# 0.11fF
+C7 a_15_n100# a_207_n100# 0.11fF
+C8 a_n225_131# w_n407_n319# 0.25fF
+C9 a_n177_n100# w_n407_n319# 0.05fF
+C10 a_n225_131# a_111_n100# 0.08fF
+C11 a_n269_n100# a_n81_n100# 0.11fF
+C12 a_n81_n100# a_207_n100# 0.06fF
+C13 a_15_n100# a_n81_n100# 0.29fF
+C14 a_111_n100# a_n177_n100# 0.06fF
+C15 a_15_n100# a_n225_131# 0.08fF
+C16 a_111_n100# w_n407_n319# 0.05fF
+C17 a_n269_n100# a_n177_n100# 0.29fF
+C18 a_207_n100# a_n177_n100# 0.05fF
+C19 a_15_n100# a_n177_n100# 0.11fF
+C20 a_n225_131# a_n81_n100# 0.08fF
+C21 a_n269_n100# w_n407_n319# 0.10fF
+C22 a_207_n100# w_n407_n319# 0.10fF
+C23 a_15_n100# w_n407_n319# 0.06fF
+C24 a_n81_n100# a_n177_n100# 0.29fF
+C25 a_207_n100# VSUBS 0.03fF
+C26 a_111_n100# VSUBS 0.03fF
+C27 a_15_n100# VSUBS 0.03fF
+C28 a_n81_n100# VSUBS 0.03fF
+C29 a_n177_n100# VSUBS 0.03fF
+C30 a_n269_n100# VSUBS 0.03fF
+C31 a_n225_131# VSUBS 0.54fF
+C32 w_n407_n319# VSUBS 2.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+C0 a_15_n81# a_n73_n81# 0.17fF
+C1 a_n73_n81# a_n33_41# 0.02fF
+C2 a_15_n81# a_n33_41# 0.02fF
+C3 a_15_n81# w_n211_n229# 0.12fF
+C4 a_n73_n81# w_n211_n229# 0.12fF
+C5 a_n33_41# w_n211_n229# 0.18fF
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 a_3747_261# vp inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+C0 avdd1p8 inn 1.05fF
+C1 vctrl clk 0.02fF
+C2 clk avdd1p8 2.36fF
+C3 vctrl a_3747_261# 0.76fF
+C4 outn avdd1p8 1.33fF
+C5 a_3747_261# avdd1p8 1.24fF
+C6 vp avdd1p8 6.92fF
+C7 avdd1p8 inp 1.02fF
+C8 avdd1p8 outp 1.56fF
+C9 outn inn 1.15fF
+C10 vp inn 0.84fF
+C11 inp inn 2.67fF
+C12 clk outn 0.71fF
+C13 clk a_3747_261# 0.44fF
+C14 vp clk 0.79fF
+C15 clk inp 0.06fF
+C16 vp a_3747_261# 1.08fF
+C17 vp outn 4.23fF
+C18 outn inp 5.59fF
+C19 outp inn 5.76fF
+C20 vp inp 0.78fF
+C21 vctrl avdd1p8 1.19fF
+C22 clk outp 0.56fF
+C23 outn outp 4.18fF
+C24 vp outp 4.81fF
+C25 inp outp 1.28fF
+C26 outn avss1p8 0.69fF
+C27 inp avss1p8 -0.11fF
+C28 outp avss1p8 -0.62fF
+C29 vp avss1p8 -4.89fF
+C30 inn avss1p8 0.23fF
+C31 avdd1p8 avss1p8 31.50fF
+C32 clk avss1p8 1.49fF
+C33 a_3747_261# avss1p8 -0.95fF
+C34 vctrl avss1p8 -0.82fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n177_n100# 0.29fF
+C1 a_n177_n100# a_n269_n100# 0.29fF
+C2 a_15_n100# a_n81_n100# 0.29fF
+C3 a_15_n100# a_n269_n100# 0.06fF
+C4 a_n225_n188# a_n81_n100# 0.10fF
+C5 a_111_n100# a_n81_n100# 0.11fF
+C6 a_15_n100# a_n177_n100# 0.11fF
+C7 a_111_n100# a_n269_n100# 0.05fF
+C8 a_n225_n188# a_n177_n100# 0.10fF
+C9 a_15_n100# a_n225_n188# 0.10fF
+C10 a_111_n100# a_n177_n100# 0.06fF
+C11 a_15_n100# a_111_n100# 0.29fF
+C12 a_n81_n100# a_207_n100# 0.06fF
+C13 a_n225_n188# a_111_n100# 0.10fF
+C14 a_n177_n100# a_207_n100# 0.05fF
+C15 a_15_n100# a_207_n100# 0.11fF
+C16 a_n81_n100# a_n269_n100# 0.11fF
+C17 a_111_n100# a_207_n100# 0.29fF
+C18 a_207_n100# w_n407_n310# 0.13fF
+C19 a_111_n100# w_n407_n310# 0.08fF
+C20 a_15_n100# w_n407_n310# 0.09fF
+C21 a_n81_n100# w_n407_n310# 0.09fF
+C22 a_n177_n100# w_n407_n310# 0.08fF
+C23 a_n269_n100# w_n407_n310# 0.13fF
+C24 a_n225_n188# w_n407_n310# 0.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_255_n100# 0.05fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_255_n100# a_159_n100# 0.29fF
+C3 a_n33_n100# a_159_n100# 0.11fF
+C4 a_n225_n100# a_n33_n100# 0.11fF
+C5 a_255_n100# a_63_n100# 0.11fF
+C6 a_n33_n100# a_63_n100# 0.29fF
+C7 a_n129_n100# a_159_n100# 0.06fF
+C8 a_n225_n100# a_n129_n100# 0.29fF
+C9 a_n225_n100# a_159_n100# 0.05fF
+C10 a_n129_n100# a_63_n100# 0.11fF
+C11 a_63_n100# a_159_n100# 0.29fF
+C12 a_n225_n100# a_63_n100# 0.06fF
+C13 a_n33_n100# a_n271_122# 0.10fF
+C14 a_n129_n100# a_n271_122# 0.10fF
+C15 a_n271_122# a_159_n100# 0.10fF
+C16 a_n225_n100# a_n271_122# 0.10fF
+C17 a_n33_n100# a_n317_n100# 0.06fF
+C18 a_n271_122# a_63_n100# 0.10fF
+C19 a_n129_n100# a_n317_n100# 0.11fF
+C20 a_n33_n100# a_255_n100# 0.06fF
+C21 a_n225_n100# a_n317_n100# 0.29fF
+C22 a_63_n100# a_n317_n100# 0.05fF
+C23 a_255_n100# w_n455_n310# 0.13fF
+C24 a_159_n100# w_n455_n310# 0.08fF
+C25 a_63_n100# w_n455_n310# 0.07fF
+C26 a_n33_n100# w_n455_n310# 0.08fF
+C27 a_n129_n100# w_n455_n310# 0.07fF
+C28 a_n225_n100# w_n455_n310# 0.08fF
+C29 a_n317_n100# w_n455_n310# 0.13fF
+C30 a_n271_122# w_n455_n310# 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n125_n100# a_n33_n100# 0.29fF
+C1 a_n33_n100# a_n79_122# 0.11fF
+C2 a_n33_n100# a_63_n100# 0.29fF
+C3 a_n125_n100# a_n79_122# 0.02fF
+C4 a_n125_n100# a_63_n100# 0.11fF
+C5 a_n79_122# a_63_n100# 0.02fF
+C6 a_63_n100# w_n263_n310# 0.16fF
+C7 a_n33_n100# w_n263_n310# 0.12fF
+C8 a_n125_n100# w_n263_n310# 0.16fF
+C9 a_n79_122# w_n263_n310# 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n225_n100# a_63_n100# 0.06fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_n33_n100# a_255_n100# 0.06fF
+C3 a_n321_n100# a_n129_n100# 0.11fF
+C4 a_351_n100# a_159_n100# 0.11fF
+C5 a_n129_n100# a_n413_n100# 0.06fF
+C6 a_n368_122# a_n33_n100# 0.10fF
+C7 a_n368_122# a_n321_n100# 0.10fF
+C8 a_351_n100# a_63_n100# 0.06fF
+C9 a_n129_n100# a_255_n100# 0.05fF
+C10 a_n33_n100# a_159_n100# 0.11fF
+C11 a_n368_122# a_n129_n100# 0.10fF
+C12 a_n368_122# a_255_n100# 0.10fF
+C13 a_n33_n100# a_n225_n100# 0.11fF
+C14 a_n321_n100# a_n225_n100# 0.29fF
+C15 a_n33_n100# a_63_n100# 0.29fF
+C16 a_n413_n100# a_n225_n100# 0.11fF
+C17 a_n321_n100# a_63_n100# 0.05fF
+C18 a_n129_n100# a_159_n100# 0.06fF
+C19 a_159_n100# a_255_n100# 0.29fF
+C20 a_n129_n100# a_n225_n100# 0.29fF
+C21 a_n33_n100# a_351_n100# 0.05fF
+C22 a_n368_122# a_159_n100# 0.10fF
+C23 a_n129_n100# a_63_n100# 0.11fF
+C24 a_255_n100# a_63_n100# 0.11fF
+C25 a_n368_122# a_n225_n100# 0.10fF
+C26 a_n368_122# a_63_n100# 0.10fF
+C27 a_351_n100# a_255_n100# 0.29fF
+C28 a_n321_n100# a_n33_n100# 0.06fF
+C29 a_n225_n100# a_159_n100# 0.05fF
+C30 a_n413_n100# a_n33_n100# 0.05fF
+C31 a_159_n100# a_63_n100# 0.29fF
+C32 a_n321_n100# a_n413_n100# 0.29fF
+C33 a_351_n100# w_n551_n310# 0.13fF
+C34 a_255_n100# w_n551_n310# 0.08fF
+C35 a_159_n100# w_n551_n310# 0.07fF
+C36 a_63_n100# w_n551_n310# 0.06fF
+C37 a_n33_n100# w_n551_n310# 0.04fF
+C38 a_n129_n100# w_n551_n310# 0.06fF
+C39 a_n225_n100# w_n551_n310# 0.07fF
+C40 a_n321_n100# w_n551_n310# 0.08fF
+C41 a_n413_n100# w_n551_n310# 0.13fF
+C42 a_n368_122# w_n551_n310# 1.26fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_111_n100# a_n81_n100# 0.11fF
+C1 a_15_n100# a_n81_n100# 0.29fF
+C2 a_111_n100# a_15_n100# 0.29fF
+C3 a_n129_n197# a_n81_n100# 0.08fF
+C4 a_n129_n197# a_15_n100# 0.08fF
+C5 w_n311_n319# a_n81_n100# 0.08fF
+C6 a_111_n100# w_n311_n319# 0.12fF
+C7 a_n173_n100# a_n81_n100# 0.29fF
+C8 a_111_n100# a_n173_n100# 0.06fF
+C9 w_n311_n319# a_15_n100# 0.08fF
+C10 a_n129_n197# w_n311_n319# 0.17fF
+C11 a_n173_n100# a_15_n100# 0.11fF
+C12 a_n173_n100# w_n311_n319# 0.12fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_n197# VSUBS 0.34fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_n33_n100# 0.29fF
+C1 a_n129_n100# a_159_n100# 0.06fF
+C2 a_n129_n100# a_n221_n100# 0.29fF
+C3 a_159_n100# a_n33_n100# 0.11fF
+C4 a_n129_n100# a_63_n100# 0.11fF
+C5 a_n33_n100# a_n221_n100# 0.11fF
+C6 a_n129_n100# a_n176_122# 0.10fF
+C7 a_159_n100# a_n221_n100# 0.05fF
+C8 a_63_n100# a_n33_n100# 0.29fF
+C9 a_159_n100# a_63_n100# 0.29fF
+C10 a_n176_122# a_n33_n100# 0.10fF
+C11 a_63_n100# a_n221_n100# 0.06fF
+C12 a_63_n100# a_n176_122# 0.10fF
+C13 a_159_n100# w_n359_n310# 0.13fF
+C14 a_63_n100# w_n359_n310# 0.10fF
+C15 a_n33_n100# w_n359_n310# 0.10fF
+C16 a_n129_n100# w_n359_n310# 0.10fF
+C17 a_n221_n100# w_n359_n310# 0.13fF
+C18 a_n176_122# w_n359_n310# 0.64fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# w_n263_n319# 0.09fF
+C1 a_n81_n197# w_n263_n319# 0.11fF
+C2 a_63_n100# a_n125_n100# 0.11fF
+C3 a_n33_n100# a_n125_n100# 0.29fF
+C4 a_n33_n100# a_63_n100# 0.29fF
+C5 a_n33_n100# a_n81_n197# 0.08fF
+C6 w_n263_n319# a_n125_n100# 0.13fF
+C7 w_n263_n319# a_63_n100# 0.13fF
+C8 a_63_n100# VSUBS 0.03fF
+C9 a_n33_n100# VSUBS 0.03fF
+C10 a_n125_n100# VSUBS 0.03fF
+C11 a_n81_n197# VSUBS 0.23fF
+C12 w_n263_n319# VSUBS 2.05fF
+.ends
+
+.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
++ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+C0 m1_448_n363# m1_964_n363# 0.24fF
+C1 m1_1996_n363# m1_1384_n363# 0.18fF
+C2 m1_964_n363# reg0 0.47fF
+C3 iref reg2 0.03fF
+C4 m1_448_n363# vctrl 1.16fF
+C5 reg1 m1_1384_n363# 0.85fF
+C6 vctrl reg0 0.04fF
+C7 m1_448_n363# m1_n356_n363# 0.17fF
+C8 m1_448_n363# avdd1p8 0.77fF
+C9 m1_511_801# vctrl 1.08fF
+C10 avdd1p8 reg0 0.03fF
+C11 iref m1_1384_n363# 0.22fF
+C12 m1_511_801# avdd1p8 1.05fF
+C13 vctrl m1_964_n363# 0.52fF
+C14 reg1 reg0 0.04fF
+C15 vctrl m1_n356_n363# 0.08fF
+C16 vctrl avdd1p8 0.52fF
+C17 iref m1_448_n363# 0.29fF
+C18 avdd1p8 m1_n356_n363# 1.41fF
+C19 iref reg0 0.02fF
+C20 vctrl m1_1996_n363# 1.72fF
+C21 iref m1_511_801# 0.05fF
+C22 iref m1_964_n363# 0.11fF
+C23 vctrl reg1 0.06fF
+C24 m1_1384_n363# reg0 0.06fF
+C25 m1_1996_n363# reg1 0.06fF
+C26 iref vctrl 2.27fF
+C27 vctrl reg2 0.07fF
+C28 iref m1_n356_n363# 1.89fF
+C29 iref avdd1p8 0.32fF
+C30 m1_1384_n363# m1_964_n363# 0.18fF
+C31 iref m1_1996_n363# 0.41fF
+C32 m1_1996_n363# reg2 1.30fF
+C33 vctrl m1_1384_n363# 0.95fF
+C34 iref reg1 0.03fF
+C35 reg1 reg2 0.04fF
+C36 m1_511_801# avss1p8 -1.62fF
+C37 m1_1384_n363# avss1p8 1.30fF
+C38 reg1 avss1p8 1.36fF
+C39 m1_448_n363# avss1p8 -0.27fF
+C40 vctrl avss1p8 2.17fF
+C41 m1_1996_n363# avss1p8 -0.61fF
+C42 reg2 avss1p8 1.98fF
+C43 reg0 avss1p8 0.44fF
+C44 m1_964_n363# avss1p8 -0.38fF
+C45 avdd1p8 avss1p8 6.02fF
+C46 m1_n356_n363# avss1p8 1.89fF
+C47 iref avss1p8 2.30fF
+.ends
+
+.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
++ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
++ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
++ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
++ iref_ctrl_res_amp_0/m1_1384_n363# delay_cell_buff_0/buffer_no_inv_x05_3/in res_amp_lin_0/vp
++ delay_cell_buff_0/nand_logic_0/m1_21_n341# delay_cell_buff_0/mux_2to1_logic_1/out
++ delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ iref delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_0/a_3747_261# delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_13/in inn
++ delay_cell_buff_0/mux_2to1_logic_4/out iref_ctrl_res_amp_0/m1_1996_n363# delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ inverter_min_x4_0/out delay_cell_buff_0/mux_2to1_logic_4/sel_b rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_reg2
++ avss1p8 delay_cell_buff_0/mux_2to1_logic_4/DinA avdd1p8 delay_cell_buff_0/buffer_no_inv_x05_13/in
++ clk delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/clk delay_cell_buff_0/mux_2to1_logic_3/DinB
++ delay_reg0 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_cell_buff_0/nand_logic_0/in1 delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ delay_cell_buff_0/mux_2to1_logic_4/out delay_cell_buff_0/mux_2to1_logic_1/DinA delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_cell_buff_0/buffer_no_inv_x05_3/in delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/mux_2to1_logic_0/out delay_cell_buff_0/mux_2to1_logic_4/DinB delay_cell_buff_0/mux_2to1_logic_3/out
++ delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_1/out
++ avss1p8 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 res_amp_lin_0/a_3747_261#
++ res_amp_lin_0/vp inn outn outp inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
++ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 outn_cap outn 1.90fF
+C1 inverter_min_x4_0/out rst 0.01fF
+C2 res_amp_lin_0/clk avdd1p8 1.99fF
+C3 outn_cap inverter_min_x4_0/out 0.57fF
+C4 outn_cap avdd1p8 0.26fF
+C5 res_amp_lin_0/vctrl avdd1p8 1.42fF
+C6 outp outp_cap 1.90fF
+C7 res_amp_lin_0/vctrl iref 0.10fF
+C8 res_amp_lin_0/clk outn_cap 1.04fF
+C9 inverter_min_x4_0/out outp_cap 0.57fF
+C10 outn_cap rst 0.34fF
+C11 outn inverter_min_x4_0/out 0.32fF
+C12 inverter_min_x4_0/out outp 0.32fF
+C13 avdd1p8 outp_cap 0.25fF
+C14 outn avdd1p8 0.36fF
+C15 res_amp_lin_0/clk outp_cap 1.04fF
+C16 outp avdd1p8 0.34fF
+C17 res_amp_lin_0/clk outn 0.09fF
+C18 res_amp_lin_0/clk outp 0.09fF
+C19 rst outp_cap 0.34fF
+C20 res_amp_lin_0/clk inverter_min_x4_0/out 0.14fF
+C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C23 iref_reg1 avss1p8 0.47fF
+C24 iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C25 res_amp_lin_0/vctrl avss1p8 -1.88fF
+C26 iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.23fF
+C27 iref_reg2 avss1p8 -0.15fF
+C28 iref_reg0 avss1p8 -0.42fF
+C29 iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C30 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.51fF
+C31 iref avss1p8 0.07fF
+C32 outn avss1p8 1.87fF
+C33 inp avss1p8 -0.35fF
+C34 outp avss1p8 -4.58fF
+C35 res_amp_lin_0/vp avss1p8 -4.89fF
+C36 inn avss1p8 0.17fF
+C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C38 outn_cap avss1p8 -1.33fF
+C39 rst avss1p8 0.58fF
+C40 res_amp_lin_0/clk avss1p8 5.34fF
+C41 inverter_min_x4_0/out avss1p8 7.53fF
+C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C53 clk avss1p8 -4.09fF
+C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C65 delay_reg0 avss1p8 2.77fF
+C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C77 delay_reg1 avss1p8 3.80fF
+C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C82 delay_reg2 avss1p8 11.07fF
+C83 avdd1p8 avss1p8 177.60fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C90 outp_cap avss1p8 -6.93fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+C0 m3_n700_n850# c1_n600_n750# 5.48fF
+C1 m3_n700_n850# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_611_n236# a_355_n236# 0.15fF
+C1 a_n413_n236# a_n157_n236# 0.15fF
+C2 a_n29_n236# a_n157_n236# 0.36fF
+C3 a_n541_n236# a_n157_n236# 0.09fF
+C4 a_99_n236# w_n807_n384# 0.02fF
+C5 a_483_n236# a_611_n236# 0.36fF
+C6 a_n285_n236# a_n157_n236# 0.36fF
+C7 a_355_n236# w_n807_n384# 0.06fF
+C8 a_n611_n262# w_n807_n384# 0.60fF
+C9 a_355_n236# a_99_n236# 0.15fF
+C10 a_n611_n262# a_99_n236# 0.08fF
+C11 a_483_n236# w_n807_n384# 0.09fF
+C12 a_483_n236# a_99_n236# 0.09fF
+C13 a_n611_n262# a_355_n236# 0.08fF
+C14 a_227_n236# a_n157_n236# 0.09fF
+C15 a_n413_n236# w_n807_n384# 0.06fF
+C16 a_n29_n236# w_n807_n384# 0.02fF
+C17 a_n541_n236# w_n807_n384# 0.09fF
+C18 a_n29_n236# a_99_n236# 0.36fF
+C19 a_483_n236# a_355_n236# 0.36fF
+C20 a_n285_n236# w_n807_n384# 0.02fF
+C21 a_483_n236# a_n611_n262# 0.08fF
+C22 a_n285_n236# a_99_n236# 0.09fF
+C23 a_227_n236# a_611_n236# 0.09fF
+C24 a_n29_n236# a_355_n236# 0.09fF
+C25 a_n611_n262# a_n413_n236# 0.08fF
+C26 a_n29_n236# a_n611_n262# 0.08fF
+C27 a_n669_n236# w_n807_n384# 0.19fF
+C28 a_n611_n262# a_n541_n236# 0.08fF
+C29 a_n611_n262# a_n285_n236# 0.08fF
+C30 a_227_n236# w_n807_n384# 0.02fF
+C31 a_n29_n236# a_n413_n236# 0.09fF
+C32 a_227_n236# a_99_n236# 0.36fF
+C33 a_n413_n236# a_n541_n236# 0.36fF
+C34 a_n157_n236# w_n807_n384# 0.02fF
+C35 a_n413_n236# a_n285_n236# 0.36fF
+C36 a_n29_n236# a_n285_n236# 0.15fF
+C37 a_n285_n236# a_n541_n236# 0.15fF
+C38 a_99_n236# a_n157_n236# 0.15fF
+C39 a_227_n236# a_355_n236# 0.36fF
+C40 a_227_n236# a_n611_n262# 0.08fF
+C41 a_n413_n236# a_n669_n236# 0.15fF
+C42 a_611_n236# w_n807_n384# 0.19fF
+C43 a_n541_n236# a_n669_n236# 0.36fF
+C44 a_227_n236# a_483_n236# 0.15fF
+C45 a_n611_n262# a_n157_n236# 0.08fF
+C46 a_n285_n236# a_n669_n236# 0.09fF
+C47 a_n29_n236# a_227_n236# 0.15fF
+C48 a_611_n236# VSUBS 0.03fF
+C49 a_483_n236# VSUBS 0.03fF
+C50 a_355_n236# VSUBS 0.03fF
+C51 a_227_n236# VSUBS 0.03fF
+C52 a_99_n236# VSUBS 0.03fF
+C53 a_n29_n236# VSUBS 0.03fF
+C54 a_n157_n236# VSUBS 0.03fF
+C55 a_n285_n236# VSUBS 0.03fF
+C56 a_n413_n236# VSUBS 0.03fF
+C57 a_n541_n236# VSUBS 0.03fF
+C58 a_n669_n236# VSUBS 0.03fF
+C59 a_n611_n262# VSUBS 1.37fF
+C60 w_n807_n384# VSUBS 6.11fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_495_n100# a_399_n100# 0.29fF
+C1 a_495_n100# a_591_n100# 0.29fF
+C2 a_303_n100# a_n705_n197# 0.08fF
+C3 a_303_n100# a_n81_n100# 0.05fF
+C4 a_15_n100# w_n887_n319# 0.02fF
+C5 a_n273_n100# a_15_n100# 0.06fF
+C6 w_n887_n319# a_111_n100# 0.02fF
+C7 a_n273_n100# a_111_n100# 0.05fF
+C8 a_303_n100# a_399_n100# 0.29fF
+C9 a_303_n100# a_591_n100# 0.06fF
+C10 a_111_n100# a_495_n100# 0.05fF
+C11 a_n369_n100# a_n749_n100# 0.05fF
+C12 w_n887_n319# a_n465_n100# 0.03fF
+C13 a_n273_n100# w_n887_n319# 0.02fF
+C14 a_n273_n100# a_n465_n100# 0.11fF
+C15 a_303_n100# a_15_n100# 0.06fF
+C16 w_n887_n319# a_495_n100# 0.04fF
+C17 a_303_n100# a_111_n100# 0.11fF
+C18 a_n369_n100# a_n177_n100# 0.11fF
+C19 a_n369_n100# a_n561_n100# 0.11fF
+C20 w_n887_n319# a_n657_n100# 0.05fF
+C21 a_n369_n100# a_n705_n197# 0.08fF
+C22 a_n465_n100# a_n657_n100# 0.11fF
+C23 a_n273_n100# a_n657_n100# 0.05fF
+C24 a_n177_n100# a_207_n100# 0.05fF
+C25 a_n369_n100# a_n81_n100# 0.06fF
+C26 a_n749_n100# a_n561_n100# 0.11fF
+C27 a_207_n100# a_n705_n197# 0.08fF
+C28 a_207_n100# a_n81_n100# 0.06fF
+C29 a_303_n100# w_n887_n319# 0.02fF
+C30 a_303_n100# a_495_n100# 0.11fF
+C31 a_207_n100# a_399_n100# 0.11fF
+C32 a_207_n100# a_591_n100# 0.05fF
+C33 a_687_n100# a_399_n100# 0.06fF
+C34 a_n177_n100# a_n561_n100# 0.05fF
+C35 a_687_n100# a_591_n100# 0.29fF
+C36 a_n177_n100# a_n705_n197# 0.08fF
+C37 a_n705_n197# a_n561_n100# 0.08fF
+C38 a_15_n100# a_n369_n100# 0.05fF
+C39 a_n177_n100# a_n81_n100# 0.29fF
+C40 a_n81_n100# a_n705_n197# 0.08fF
+C41 a_15_n100# a_207_n100# 0.11fF
+C42 a_111_n100# a_207_n100# 0.29fF
+C43 a_n705_n197# a_399_n100# 0.08fF
+C44 a_591_n100# a_n705_n197# 0.08fF
+C45 w_n887_n319# a_n369_n100# 0.02fF
+C46 a_n369_n100# a_n465_n100# 0.29fF
+C47 a_n273_n100# a_n369_n100# 0.29fF
+C48 a_591_n100# a_399_n100# 0.11fF
+C49 w_n887_n319# a_207_n100# 0.02fF
+C50 w_n887_n319# a_n749_n100# 0.10fF
+C51 a_15_n100# a_n177_n100# 0.11fF
+C52 a_n465_n100# a_n749_n100# 0.06fF
+C53 a_15_n100# a_n705_n197# 0.08fF
+C54 a_207_n100# a_495_n100# 0.06fF
+C55 a_n177_n100# a_111_n100# 0.06fF
+C56 a_15_n100# a_n81_n100# 0.29fF
+C57 w_n887_n319# a_687_n100# 0.10fF
+C58 a_111_n100# a_n705_n197# 0.08fF
+C59 a_n369_n100# a_n657_n100# 0.06fF
+C60 a_111_n100# a_n81_n100# 0.11fF
+C61 a_687_n100# a_495_n100# 0.11fF
+C62 a_15_n100# a_399_n100# 0.05fF
+C63 a_n749_n100# a_n657_n100# 0.29fF
+C64 a_111_n100# a_399_n100# 0.06fF
+C65 w_n887_n319# a_n177_n100# 0.02fF
+C66 a_n177_n100# a_n465_n100# 0.06fF
+C67 a_n273_n100# a_n177_n100# 0.29fF
+C68 w_n887_n319# a_n561_n100# 0.04fF
+C69 a_n465_n100# a_n561_n100# 0.29fF
+C70 a_303_n100# a_207_n100# 0.29fF
+C71 a_n273_n100# a_n561_n100# 0.06fF
+C72 w_n887_n319# a_n705_n197# 0.82fF
+C73 a_n465_n100# a_n705_n197# 0.08fF
+C74 a_n273_n100# a_n705_n197# 0.08fF
+C75 w_n887_n319# a_n81_n100# 0.02fF
+C76 a_n465_n100# a_n81_n100# 0.05fF
+C77 a_n273_n100# a_n81_n100# 0.11fF
+C78 a_495_n100# a_n705_n197# 0.08fF
+C79 a_303_n100# a_687_n100# 0.05fF
+C80 w_n887_n319# a_399_n100# 0.03fF
+C81 w_n887_n319# a_591_n100# 0.05fF
+C82 a_15_n100# a_111_n100# 0.29fF
+C83 a_n657_n100# a_n561_n100# 0.29fF
+C84 a_n657_n100# a_n705_n197# 0.08fF
+C85 a_687_n100# VSUBS 0.03fF
+C86 a_591_n100# VSUBS 0.03fF
+C87 a_495_n100# VSUBS 0.03fF
+C88 a_399_n100# VSUBS 0.03fF
+C89 a_303_n100# VSUBS 0.03fF
+C90 a_207_n100# VSUBS 0.03fF
+C91 a_111_n100# VSUBS 0.03fF
+C92 a_15_n100# VSUBS 0.03fF
+C93 a_n81_n100# VSUBS 0.03fF
+C94 a_n177_n100# VSUBS 0.03fF
+C95 a_n273_n100# VSUBS 0.03fF
+C96 a_n369_n100# VSUBS 0.03fF
+C97 a_n465_n100# VSUBS 0.03fF
+C98 a_n561_n100# VSUBS 0.03fF
+C99 a_n657_n100# VSUBS 0.03fF
+C100 a_n749_n100# VSUBS 0.03fF
+C101 a_n705_n197# VSUBS 1.60fF
+C102 w_n887_n319# VSUBS 5.82fF
+.ends
+
+.subckt source_follower_buff_pmos m1_957_828# in avss1p8 avdd1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+C0 m1_957_828# iref 0.88fF
+C1 m1_957_828# in 0.52fF
+C2 avdd1p8 iref 0.29fF
+C3 avdd1p8 m1_957_828# 1.12fF
+C4 m1_957_828# out 1.52fF
+C5 avdd1p8 in 0.32fF
+C6 out in 1.16fF
+C7 avdd1p8 out 3.96fF
+C8 out avss1p8 -1.64fF
+C9 in avss1p8 1.94fF
+C10 avdd1p8 avss1p8 15.90fF
+C11 m1_957_828# avss1p8 -34.25fF
+C12 iref avss1p8 4.22fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_1599_109# a_1215_109# 0.05fF
+C1 a_n801_n309# a_n705_n309# 0.29fF
+C2 a_n801_109# a_n897_109# 0.29fF
+C3 a_n1089_n309# a_n705_n309# 0.05fF
+C4 a_1599_109# a_1791_109# 0.11fF
+C5 a_n801_n309# a_n897_n309# 0.29fF
+C6 a_n1089_n309# a_n897_n309# 0.11fF
+C7 a_n321_109# a_n609_109# 0.06fF
+C8 a_543_109# a_831_109# 0.06fF
+C9 a_255_109# a_n129_109# 0.05fF
+C10 a_735_109# a_1023_109# 0.06fF
+C11 a_831_109# a_1215_109# 0.05fF
+C12 a_n609_109# a_n897_109# 0.06fF
+C13 a_63_109# a_447_109# 0.05fF
+C14 a_1887_109# a_1887_n309# 0.01fF
+C15 a_n801_109# a_n801_n309# 0.01fF
+C16 a_1311_n309# a_1599_n309# 0.06fF
+C17 a_639_109# a_351_109# 0.06fF
+C18 a_n1089_n309# a_n1473_n309# 0.05fF
+C19 a_1407_109# a_1407_n309# 0.01fF
+C20 a_n225_109# a_n609_109# 0.05fF
+C21 a_n1665_109# a_n1377_109# 0.06fF
+C22 a_1119_109# a_1407_109# 0.06fF
+C23 a_n1569_n309# a_n1761_n309# 0.11fF
+C24 a_927_109# a_927_n309# 0.01fF
+C25 a_n1857_n309# a_n1761_n309# 0.29fF
+C26 a_1023_n309# a_831_n309# 0.11fF
+C27 a_1695_n309# a_1599_n309# 0.29fF
+C28 a_n993_109# a_n993_n309# 0.01fF
+C29 a_n609_n309# a_n225_n309# 0.05fF
+C30 a_n321_n309# a_n321_109# 0.01fF
+C31 a_1695_n309# a_1887_n309# 0.11fF
+C32 a_255_109# a_159_109# 0.29fF
+C33 a_n1473_n309# a_n1761_n309# 0.06fF
+C34 a_n33_n309# a_n321_n309# 0.06fF
+C35 a_927_109# a_1311_109# 0.05fF
+C36 a_n321_109# a_n513_109# 0.11fF
+C37 a_n801_109# a_n1185_109# 0.05fF
+C38 a_639_109# a_1023_109# 0.05fF
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+C365 a_351_n309# w_n2087_n519# 0.04fF
+C366 a_255_n309# w_n2087_n519# 0.04fF
+C367 a_159_n309# w_n2087_n519# 0.04fF
+C368 a_63_n309# w_n2087_n519# 0.04fF
+C369 a_n33_n309# w_n2087_n519# 0.04fF
+C370 a_n129_n309# w_n2087_n519# 0.04fF
+C371 a_n225_n309# w_n2087_n519# 0.04fF
+C372 a_n321_n309# w_n2087_n519# 0.04fF
+C373 a_n417_n309# w_n2087_n519# 0.04fF
+C374 a_n513_n309# w_n2087_n519# 0.04fF
+C375 a_n609_n309# w_n2087_n519# 0.04fF
+C376 a_n705_n309# w_n2087_n519# 0.04fF
+C377 a_n801_n309# w_n2087_n519# 0.04fF
+C378 a_n897_n309# w_n2087_n519# 0.04fF
+C379 a_n993_n309# w_n2087_n519# 0.04fF
+C380 a_n1089_n309# w_n2087_n519# 0.04fF
+C381 a_n1185_n309# w_n2087_n519# 0.04fF
+C382 a_n1281_n309# w_n2087_n519# 0.04fF
+C383 a_n1377_n309# w_n2087_n519# 0.04fF
+C384 a_n1473_n309# w_n2087_n519# 0.04fF
+C385 a_n1569_n309# w_n2087_n519# 0.04fF
+C386 a_n1665_n309# w_n2087_n519# 0.04fF
+C387 a_n1761_n309# w_n2087_n519# 0.04fF
+C388 a_n1857_n309# w_n2087_n519# 0.04fF
+C389 a_n1949_n309# w_n2087_n519# 0.04fF
+C390 a_1887_109# w_n2087_n519# 0.12fF
+C391 a_1791_109# w_n2087_n519# 0.08fF
+C392 a_1695_109# w_n2087_n519# 0.06fF
+C393 a_1599_109# w_n2087_n519# 0.06fF
+C394 a_1503_109# w_n2087_n519# 0.04fF
+C395 a_1407_109# w_n2087_n519# 0.04fF
+C396 a_1311_109# w_n2087_n519# 0.04fF
+C397 a_1215_109# w_n2087_n519# 0.04fF
+C398 a_1119_109# w_n2087_n519# 0.04fF
+C399 a_1023_109# w_n2087_n519# 0.04fF
+C400 a_927_109# w_n2087_n519# 0.04fF
+C401 a_831_109# w_n2087_n519# 0.04fF
+C402 a_735_109# w_n2087_n519# 0.04fF
+C403 a_639_109# w_n2087_n519# 0.04fF
+C404 a_543_109# w_n2087_n519# 0.04fF
+C405 a_447_109# w_n2087_n519# 0.04fF
+C406 a_351_109# w_n2087_n519# 0.04fF
+C407 a_255_109# w_n2087_n519# 0.04fF
+C408 a_159_109# w_n2087_n519# 0.04fF
+C409 a_63_109# w_n2087_n519# 0.04fF
+C410 a_n33_109# w_n2087_n519# 0.04fF
+C411 a_n129_109# w_n2087_n519# 0.04fF
+C412 a_n225_109# w_n2087_n519# 0.04fF
+C413 a_n321_109# w_n2087_n519# 0.04fF
+C414 a_n417_109# w_n2087_n519# 0.04fF
+C415 a_n513_109# w_n2087_n519# 0.04fF
+C416 a_n609_109# w_n2087_n519# 0.04fF
+C417 a_n705_109# w_n2087_n519# 0.04fF
+C418 a_n801_109# w_n2087_n519# 0.04fF
+C419 a_n897_109# w_n2087_n519# 0.04fF
+C420 a_n993_109# w_n2087_n519# 0.04fF
+C421 a_n1089_109# w_n2087_n519# 0.04fF
+C422 a_n1185_109# w_n2087_n519# 0.04fF
+C423 a_n1281_109# w_n2087_n519# 0.04fF
+C424 a_n1377_109# w_n2087_n519# 0.04fF
+C425 a_n1473_109# w_n2087_n519# 0.04fF
+C426 a_n1569_109# w_n2087_n519# 0.04fF
+C427 a_n1665_109# w_n2087_n519# 0.04fF
+C428 a_n1761_109# w_n2087_n519# 0.04fF
+C429 a_n1857_109# w_n2087_n519# 0.04fF
+C430 a_n1949_109# w_n2087_n519# 0.04fF
+C431 a_n1905_n87# w_n2087_n519# 6.17fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
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+C902 a_n1949_527# w_n2087_n937# 0.04fF
+C903 a_n1905_n505# w_n2087_n937# 14.96fF
+.ends
+
+.subckt source_follower_buff_nmos w_2250_n1147# out avdd1p8 avss1p8 in m1_460_n1129#
++ iref w_2049_850# w_2250_1287# w_2250_355#
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+C0 iref out 22.08fF
+C1 in out 10.03fF
+C2 in iref 0.11fF
+C3 out avdd1p8 9.98fF
+C4 in avdd1p8 2.17fF
+C5 iref m1_460_n1129# 2.64fF
+C6 iref avss1p8 18.70fF
+C7 in avss1p8 -31.17fF
+C8 out avss1p8 -28.37fF
+C9 m1_460_n1129# avss1p8 2.61fF
+C10 avdd1p8 avss1p8 2.63fF
+.ends
+
+.subckt source_follower_buff_diff outn VSUBS avdd1p8 inp source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_nmos_1/m1_460_n1129# source_follower_buff_pmos_1/m1_957_828#
++ source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_nmos_1/in
++ source_follower_buff_nmos_0/w_2250_355# inn
+Xsource_follower_buff_pmos_0 source_follower_buff_pmos_0/m1_957_828# inn VSUBS avdd1p8
++ source_follower_buff_nmos_0/in iref3 source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 source_follower_buff_pmos_1/m1_957_828# inp VSUBS avdd1p8
++ source_follower_buff_nmos_1/in iref1 source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/w_2250_n1147# outn avdd1p8
++ VSUBS source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# iref4
++ source_follower_buff_nmos_0/w_2049_850# source_follower_buff_nmos_0/w_2250_1287#
++ source_follower_buff_nmos_0/w_2250_355# source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/w_2250_n1147# outp avdd1p8
++ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
++ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
++ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
+C0 avdd1p8 source_follower_buff_nmos_0/in 0.63fF
+C1 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C2 iref3 inn 0.01fF
+C3 source_follower_buff_nmos_0/in outn 0.11fF
+C4 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
+C5 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
+C6 source_follower_buff_nmos_0/in inn -0.25fF
+C7 inp iref1 0.01fF
+C8 avdd1p8 outn 0.18fF
+C9 avdd1p8 inn 0.07fF
+C10 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
+C11 avdd1p8 source_follower_buff_nmos_0/w_2250_1287# 0.18fF
+C12 source_follower_buff_nmos_1/in outp 0.11fF
+C13 inp source_follower_buff_nmos_1/in -0.25fF
+C14 avdd1p8 inp 0.07fF
+C15 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C16 iref2 VSUBS 11.84fF
+C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
+C18 outp VSUBS 0.56fF
+C19 source_follower_buff_nmos_1/m1_460_n1129# VSUBS 1.47fF
+C20 iref4 VSUBS 12.04fF
+C21 source_follower_buff_nmos_0/in VSUBS -32.98fF
+C22 outn VSUBS 2.12fF
+C23 source_follower_buff_nmos_0/m1_460_n1129# VSUBS 1.50fF
+C24 avdd1p8 VSUBS 35.96fF
+C25 inp VSUBS 2.70fF
+C26 source_follower_buff_pmos_1/m1_957_828# VSUBS -35.44fF
+C27 iref1 VSUBS 3.02fF
+C28 inn VSUBS 4.09fF
+C29 source_follower_buff_pmos_0/m1_957_828# VSUBS -35.44fF
+C30 iref3 VSUBS 3.13fF
+.ends
+
+.subckt res_amp_top avss1p8 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ avdd1p8 iref0 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# iref1 res_amp_lin_prog_0/res_amp_lin_0/vp
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out iref2 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_lin_prog_0/outn iref3 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ delay_reg0 iref4 res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ inn source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# inp res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/outp_cap iref_reg0 res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_sync_v2_0/clkp iref_reg1 source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_reg1 outn source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ outp clkn res_amp_sync_v2_0/rst
+Xres_amp_sync_v2_0 avdd1p8 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 clkn res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280#
++ res_amp_sync_v2_0/DFlipFlop_4/nQ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_sync_v2_0/DFlipFlop_3/D res_amp_sync_v2_0/DFlipFlop_4/D
++ res_amp_sync_v2_0/DFlipFlop_1/D res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD
++ res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ
++ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
++ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ res_amp_lin_prog_0/outn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA
++ res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ iref_reg1 iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in iref0
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# delay_reg1 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ inn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/inverter_min_x4_0/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_sync_v2_0/rst
++ res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 outn avss1p8 avdd1p8 res_amp_lin_prog_0/outp_cap source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
++ source_follower_buff_diff
+C0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avdd1p8 1.10fF
+C1 inn inp 1.68fF
+C2 res_amp_sync_v2_0/rst inn 0.09fF
+C3 iref0 res_amp_lin_prog_0/res_amp_lin_0/vctrl -0.03fF
+C4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# iref4 0.13fF
+C5 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
+C6 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/Q 0.44fF
+C7 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avdd1p8 0.39fF
+C8 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C9 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/D 0.08fF
+C10 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D 0.20fF
+C11 res_amp_lin_prog_0/clk avdd1p8 9.77fF
+C12 res_amp_sync_v2_0/DFlipFlop_1/D avdd1p8 0.29fF
+C13 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C14 outn avdd1p8 0.30fF
+C15 delay_reg1 delay_reg2 0.23fF
+C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
+C17 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D 0.47fF
+C18 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# outn 0.15fF
+C19 delay_reg2 avdd1p8 0.08fF
+C20 iref0 avdd1p8 -0.63fF
+C21 iref_reg2 avdd1p8 -0.57fF
+C22 res_amp_sync_v2_0/clkp clkn 0.06fF
+C23 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# iref1 0.10fF
+C24 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/Q 0.25fF
+C25 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/D 0.07fF
+C26 inp avdd1p8 0.46fF
+C27 res_amp_sync_v2_0/rst avdd1p8 0.80fF
+C28 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D 0.47fF
+C29 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
+C30 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C31 outp avdd1p8 0.31fF
+C32 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
+C33 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# 0.06fF
+C34 inn avdd1p8 0.46fF
+C35 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD 0.28fF
+C36 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C37 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D 0.23fF
+C38 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
+C39 res_amp_lin_prog_0/res_amp_lin_0/vctrl avdd1p8 0.03fF
+C40 clkn avdd1p8 0.74fF
+C41 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
+C42 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
+C43 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
+C44 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avdd1p8 0.02fF
+C45 iref_reg1 avdd1p8 0.05fF
+C46 delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.03fF
+C47 delay_reg1 avdd1p8 0.04fF
+C48 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C49 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in 0.48fF
+C50 res_amp_sync_v2_0/rst inp 0.09fF
+C51 res_amp_lin_prog_0/clk clkn 0.07fF
+C52 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avdd1p8 0.40fF
+C53 iref2 avss1p8 12.17fF
+C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
+C55 outp avss1p8 -1.74fF
+C56 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# avss1p8 1.82fF
+C57 iref4 avss1p8 12.36fF
+C58 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avss1p8 -32.87fF
+C59 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# avss1p8 0.08fF
+C60 outn avss1p8 -1.13fF
+C61 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# avss1p8 1.84fF
+C62 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avss1p8 -35.44fF
+C63 iref1 avss1p8 3.33fF
+C64 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avss1p8 -35.44fF
+C65 iref3 avss1p8 3.02fF
+C66 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C67 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C68 iref_reg1 avss1p8 0.41fF
+C69 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C70 res_amp_lin_prog_0/res_amp_lin_0/vctrl avss1p8 -1.99fF
+C71 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.18fF
+C72 iref_reg2 avss1p8 0.06fF
+C73 iref_reg0 avss1p8 -0.21fF
+C74 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C75 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.55fF
+C76 iref0 avss1p8 0.37fF
+C77 res_amp_lin_prog_0/outn avss1p8 1.55fF
+C78 inp avss1p8 0.21fF
+C79 res_amp_lin_prog_0/outp avss1p8 -4.89fF
+C80 res_amp_lin_prog_0/res_amp_lin_0/vp avss1p8 -4.89fF
+C81 inn avss1p8 -6.68fF
+C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
+C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
+C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C108 delay_reg0 avss1p8 2.90fF
+C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C120 delay_reg1 avss1p8 3.97fF
+C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C125 delay_reg2 avss1p8 11.33fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C132 res_amp_lin_prog_0/outp_cap avss1p8 -6.67fF
+C133 res_amp_sync_v2_0/nand_logic_1/m1_21_n341# avss1p8 0.72fF
+C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
+C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
+C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
+C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
+C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
+C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
+C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C155 clkn avss1p8 -7.50fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
+C165 avdd1p8 avss1p8 415.30fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
+C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
+.ends
+
 .subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
 + m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
 + m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
@@ -30,71 +4105,71 @@
 X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
 X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
 X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 m3_7988_n7900# m3_2669_n7900# 2.73fF
-C1 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
-C2 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
-C3 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C4 c1_n13188_n13100# m3_7988_8000# 60.75fF
-C5 m3_2669_n13200# m3_2669_n7900# 3.28fF
-C6 m3_n13288_8000# m3_n7969_8000# 2.73fF
-C7 m3_n7969_2700# m3_n2650_2700# 2.73fF
-C8 c1_n13188_n13100# m3_n7969_2700# 58.86fF
-C9 m3_7988_n13200# c1_n13188_n13100# 60.75fF
-C10 m3_n2650_2700# m3_2669_2700# 2.73fF
-C11 c1_n13188_n13100# m3_2669_2700# 58.86fF
-C12 c1_n13188_n13100# m3_n7969_8000# 58.61fF
-C13 m3_7988_n7900# m3_7988_n13200# 3.39fF
-C14 c1_n13188_n13100# m3_7988_2700# 61.01fF
-C15 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
-C16 c1_n13188_n13100# m3_2669_8000# 58.61fF
-C17 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
-C18 m3_n7969_8000# m3_n2650_8000# 2.73fF
-C19 c1_n13188_n13100# m3_n7969_n2600# 58.86fF
-C20 m3_7988_2700# m3_7988_n2600# 3.39fF
-C21 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
-C22 m3_2669_n13200# m3_7988_n13200# 2.73fF
-C23 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
-C24 c1_n13188_n13100# m3_2669_n2600# 58.86fF
-C25 m3_n2650_8000# m3_2669_8000# 2.73fF
-C26 m3_n13288_n2600# m3_n13288_n7900# 3.28fF
-C27 m3_n13288_n2600# m3_n7969_n2600# 2.73fF
-C28 m3_n13288_n7900# m3_n7969_n7900# 2.73fF
-C29 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
-C30 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
-C31 m3_2669_n2600# m3_7988_n2600# 2.73fF
-C32 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C33 m3_n13288_8000# m3_n13288_2700# 3.28fF
-C34 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
-C35 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
-C36 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
-C37 m3_n2650_n2600# m3_2669_n2600# 2.73fF
-C38 c1_n13188_n13100# m3_n13288_8000# 58.36fF
-C39 m3_n2650_n7900# m3_2669_n7900# 2.73fF
-C40 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C0 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C1 m3_2669_n13200# m3_7988_n13200# 2.73fF
+C2 m3_n2650_n7900# m3_n2650_n2600# 3.28fF
+C3 m3_n7969_n7900# m3_n7969_n2600# 3.28fF
+C4 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C5 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
+C6 m3_7988_2700# c1_n13188_n13100# 61.01fF
+C7 m3_7988_8000# c1_n13188_n13100# 60.75fF
+C8 m3_2669_2700# m3_n2650_2700# 2.73fF
+C9 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C10 m3_7988_2700# m3_7988_8000# 3.39fF
+C11 m3_n2650_8000# m3_2669_8000# 2.73fF
+C12 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C13 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C14 m3_n13288_8000# c1_n13188_n13100# 58.36fF
+C15 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C16 m3_n7969_8000# m3_n7969_2700# 3.28fF
+C17 m3_7988_n13200# c1_n13188_n13100# 60.75fF
+C18 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C19 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
+C20 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C21 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C22 m3_n7969_n13200# m3_n7969_n7900# 3.28fF
+C23 m3_2669_2700# c1_n13188_n13100# 58.86fF
+C24 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C25 m3_2669_n13200# m3_n2650_n13200# 2.73fF
+C26 m3_n2650_2700# m3_n2650_8000# 3.28fF
+C27 m3_2669_2700# m3_7988_2700# 2.73fF
+C28 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C29 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C30 m3_7988_n2600# m3_2669_n2600# 2.73fF
+C31 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C32 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C33 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C34 m3_2669_n7900# m3_2669_n2600# 3.28fF
+C35 m3_n2650_8000# c1_n13188_n13100# 58.61fF
+C36 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C37 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
+C38 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C39 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C40 c1_n13188_n13100# m3_2669_n2600# 58.86fF
 C41 c1_n13188_n13100# m3_n13288_2700# 58.61fF
-C42 m3_2669_n2600# m3_2669_n7900# 3.28fF
-C43 m3_7988_2700# m3_7988_8000# 3.39fF
-C44 c1_n13188_n13100# m3_n2650_2700# 58.86fF
-C45 m3_n7969_8000# m3_n7969_2700# 3.28fF
-C46 m3_2669_8000# m3_7988_8000# 2.73fF
-C47 m3_n13288_n2600# m3_n13288_2700# 3.28fF
-C48 c1_n13188_n13100# m3_7988_n2600# 61.01fF
-C49 m3_n2650_8000# m3_n2650_2700# 3.28fF
-C50 c1_n13188_n13100# m3_n2650_8000# 58.61fF
-C51 m3_7988_n7900# c1_n13188_n13100# 61.01fF
-C52 m3_7988_2700# m3_2669_2700# 2.73fF
-C53 m3_n7969_n2600# m3_n7969_2700# 3.28fF
-C54 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
-C55 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
-C56 m3_2669_8000# m3_2669_2700# 3.28fF
-C57 m3_n7969_n13200# c1_n13188_n13100# 58.61fF
-C58 m3_7988_n7900# m3_7988_n2600# 3.39fF
-C59 m3_n2650_n2600# m3_n2650_2700# 3.28fF
-C60 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
-C61 c1_n13188_n13100# m3_2669_n7900# 58.86fF
-C62 m3_2669_n13200# c1_n13188_n13100# 58.61fF
-C63 m3_2669_n2600# m3_2669_2700# 3.28fF
-C64 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
+C42 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C43 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C44 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C45 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C46 m3_2669_n13200# m3_2669_n7900# 3.28fF
+C47 m3_n13288_8000# m3_n13288_2700# 3.28fF
+C48 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C49 m3_n2650_2700# m3_n2650_n2600# 3.28fF
+C50 m3_2669_2700# m3_2669_n2600# 3.28fF
+C51 m3_2669_8000# c1_n13188_n13100# 58.61fF
+C52 m3_n7969_8000# c1_n13188_n13100# 58.61fF
+C53 m3_7988_8000# m3_2669_8000# 2.73fF
+C54 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C55 m3_7988_n2600# c1_n13188_n13100# 61.01fF
+C56 c1_n13188_n13100# m3_n2650_n2600# 58.86fF
+C57 m3_7988_n2600# m3_7988_2700# 3.39fF
+C58 m3_2669_n13200# c1_n13188_n13100# 58.61fF
+C59 m3_2669_n7900# c1_n13188_n13100# 58.86fF
+C60 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C61 m3_n2650_2700# c1_n13188_n13100# 58.86fF
+C62 m3_n7969_8000# m3_n13288_8000# 2.73fF
+C63 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C64 m3_2669_2700# m3_2669_8000# 3.28fF
 C65 c1_n13188_n13100# VSUBS 2.51fF
 C66 m3_7988_n13200# VSUBS 12.57fF
 C67 m3_2669_n13200# VSUBS 12.37fF
@@ -143,25 +4218,25 @@
 X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
-C1 c1_n2050_n6300# m3_n2150_2200# 38.10fF
-C2 c1_n6369_n6300# m3_n6469_n2100# 38.10fF
-C3 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
-C4 m3_n2150_2200# m3_n6469_2200# 1.75fF
-C5 c1_2269_n6300# m3_2169_n6400# 121.67fF
-C6 c1_n6369_n6300# m3_n6469_2200# 38.10fF
-C7 m3_2169_n6400# m3_n2150_n2100# 1.75fF
-C8 c1_2269_n6300# c1_n2050_n6300# 1.99fF
-C9 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
-C10 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
-C11 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
-C12 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
-C13 m3_n6469_n2100# m3_n6469_2200# 2.63fF
-C14 m3_n2150_n6400# m3_2169_n6400# 1.75fF
-C15 m3_2169_n6400# m3_n2150_2200# 1.75fF
-C16 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
-C17 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
-C18 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C0 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C1 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C2 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C3 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C4 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C5 c1_n2050_n6300# c1_2269_n6300# 1.99fF
+C6 m3_2169_n6400# m3_n2150_n2100# 1.75fF
+C7 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C8 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C9 m3_2169_n6400# m3_n2150_n6400# 1.75fF
+C10 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C11 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
+C12 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C13 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C14 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
+C15 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C16 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C17 m3_n6469_n2100# m3_n6469_2200# 2.63fF
+C18 c1_n2050_n6300# m3_n2150_n6400# 38.10fF
 C19 c1_2269_n6300# VSUBS 0.16fF
 C20 c1_n2050_n6300# VSUBS 0.16fF
 C21 c1_n6369_n6300# VSUBS 0.16fF
@@ -218,17 +4293,17 @@
 X7 a_n1861_n486# a_n2261_n512# a_n2319_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
 X8 a_n29_n486# a_n2261_n512# a_n487_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
 X9 a_1345_n486# a_n2261_n512# a_887_n486# w_n2457_n634# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=2e+06u
-C0 a_n1861_n486# w_n2457_n634# 0.02fF
-C1 a_887_n486# w_n2457_n634# 0.02fF
+C0 w_n2457_n634# a_1345_n486# 0.02fF
+C1 w_n2457_n634# a_n1861_n486# 0.02fF
 C2 a_n29_n486# w_n2457_n634# 0.02fF
-C3 a_n945_n486# w_n2457_n634# 0.02fF
-C4 a_n1403_n486# w_n2457_n634# 0.02fF
-C5 a_n2319_n486# w_n2457_n634# 0.02fF
-C6 a_1345_n486# w_n2457_n634# 0.02fF
-C7 a_2261_n486# w_n2457_n634# 0.02fF
-C8 a_429_n486# w_n2457_n634# 0.02fF
-C9 a_1803_n486# w_n2457_n634# 0.02fF
-C10 a_n487_n486# w_n2457_n634# 0.02fF
+C3 a_2261_n486# w_n2457_n634# 0.02fF
+C4 w_n2457_n634# a_n945_n486# 0.02fF
+C5 a_887_n486# w_n2457_n634# 0.02fF
+C6 w_n2457_n634# a_n1403_n486# 0.02fF
+C7 w_n2457_n634# a_1803_n486# 0.02fF
+C8 a_n2319_n486# w_n2457_n634# 0.02fF
+C9 a_n487_n486# w_n2457_n634# 0.02fF
+C10 w_n2457_n634# a_429_n486# 0.02fF
 C11 a_2261_n486# VSUBS 0.03fF
 C12 a_1803_n486# VSUBS 0.03fF
 C13 a_1345_n486# VSUBS 0.03fF
@@ -274,100 +4349,100 @@
 X22 a_111_n75# a_n1167_n101# a_15_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
 X23 a_n273_n75# a_n1167_n101# a_n369_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
 X24 a_n177_n75# a_n1167_n101# a_n273_n75# w_n1367_n285# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=150000u
-C0 a_n657_n75# a_n849_n75# 0.08fF
-C1 a_783_n75# a_1071_n75# 0.05fF
-C2 a_n1137_n75# a_n1229_n75# 0.22fF
-C3 a_n1041_n75# a_n753_n75# 0.05fF
-C4 a_n369_n75# a_n465_n75# 0.22fF
-C5 a_591_n75# a_975_n75# 0.03fF
-C6 a_n561_n75# a_n369_n75# 0.08fF
-C7 a_687_n75# a_495_n75# 0.08fF
-C8 a_783_n75# a_1167_n75# 0.03fF
-C9 a_n273_n75# a_n81_n75# 0.08fF
-C10 a_879_n75# a_1071_n75# 0.08fF
-C11 a_687_n75# a_783_n75# 0.22fF
-C12 a_111_n75# a_n273_n75# 0.03fF
-C13 a_591_n75# a_495_n75# 0.22fF
-C14 a_n945_n75# a_n1229_n75# 0.05fF
-C15 a_687_n75# a_399_n75# 0.05fF
-C16 a_879_n75# a_1167_n75# 0.05fF
-C17 a_687_n75# a_879_n75# 0.08fF
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-C19 a_n849_n75# a_n1137_n75# 0.05fF
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+C66 a_n705_n150# a_n513_n150# 0.16fF
+C67 a_255_n150# a_447_n150# 0.16fF
+C68 a_639_n150# a_447_n150# 0.16fF
+C69 a_n129_n150# a_n33_n150# 0.43fF
+C70 a_159_n150# a_63_n150# 0.43fF
+C71 a_n609_n150# a_n705_n150# 0.43fF
+C72 a_n705_n150# a_n989_n150# 0.10fF
+C73 a_159_n150# a_543_n150# 0.07fF
+C74 a_639_n150# a_831_n150# 0.16fF
 C75 a_927_n150# VSUBS 0.03fF
 C76 a_831_n150# VSUBS 0.03fF
 C77 a_735_n150# VSUBS 0.03fF
@@ -659,16 +4734,16 @@
 X7 a_687_n44# a_n1761_n132# a_329_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
 X8 a_1403_n44# a_n1761_n132# a_1045_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
 X9 a_n1461_n44# a_n1761_n132# a_n1819_n44# w_n1957_n254# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=750000u l=1.5e+06u
-C0 a_n29_n44# a_329_n44# 0.04fF
-C1 a_n29_n44# a_n387_n44# 0.04fF
-C2 a_687_n44# a_329_n44# 0.04fF
-C3 a_1045_n44# a_687_n44# 0.04fF
-C4 a_n387_n44# a_n745_n44# 0.04fF
-C5 a_n1103_n44# a_n745_n44# 0.04fF
-C6 a_1045_n44# a_1403_n44# 0.04fF
-C7 a_n1103_n44# a_n1461_n44# 0.04fF
-C8 a_n1819_n44# a_n1461_n44# 0.04fF
-C9 a_1761_n44# a_1403_n44# 0.04fF
+C0 a_1403_n44# a_1045_n44# 0.04fF
+C1 a_n1819_n44# a_n1461_n44# 0.04fF
+C2 a_1045_n44# a_687_n44# 0.04fF
+C3 a_n745_n44# a_n1103_n44# 0.04fF
+C4 a_1403_n44# a_1761_n44# 0.04fF
+C5 a_687_n44# a_329_n44# 0.04fF
+C6 a_n387_n44# a_n29_n44# 0.04fF
+C7 a_n387_n44# a_n745_n44# 0.04fF
+C8 a_n29_n44# a_329_n44# 0.04fF
+C9 a_n1103_n44# a_n1461_n44# 0.04fF
 C10 a_1761_n44# w_n1957_n254# 0.04fF
 C11 a_1403_n44# w_n1957_n254# 0.04fF
 C12 a_1045_n44# w_n1957_n254# 0.04fF
@@ -713,104 +4788,104 @@
 X22 a_n849_n150# a_n1167_n247# a_n945_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X23 a_207_n150# a_n1167_n247# a_111_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X24 a_n177_n150# a_n1167_n247# a_n273_n150# w_n1367_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n177_n150# a_n465_n150# 0.10fF
-C1 a_207_n150# a_n81_n150# 0.10fF
-C2 a_n369_n150# a_n465_n150# 0.43fF
-C3 a_n177_n150# a_207_n150# 0.07fF
-C4 a_1071_n150# a_687_n150# 0.07fF
-C5 a_783_n150# a_1071_n150# 0.10fF
-C6 a_399_n150# a_111_n150# 0.10fF
-C7 a_303_n150# a_n81_n150# 0.07fF
-C8 a_975_n150# a_591_n150# 0.07fF
-C9 a_111_n150# a_207_n150# 0.43fF
-C10 a_n657_n150# a_n369_n150# 0.10fF
-C11 a_n465_n150# a_n273_n150# 0.16fF
-C12 a_399_n150# a_15_n150# 0.07fF
-C13 a_111_n150# a_303_n150# 0.16fF
-C14 a_15_n150# a_207_n150# 0.16fF
-C15 a_n657_n150# a_n273_n150# 0.07fF
-C16 a_n465_n150# a_n561_n150# 0.43fF
-C17 a_783_n150# a_1167_n150# 0.07fF
-C18 a_n753_n150# a_n465_n150# 0.10fF
-C19 a_879_n150# a_1071_n150# 0.16fF
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-C21 a_n1137_n150# a_n945_n150# 0.16fF
-C22 a_783_n150# a_975_n150# 0.16fF
-C23 a_15_n150# a_303_n150# 0.10fF
-C24 a_n657_n150# a_n561_n150# 0.43fF
-C25 a_n753_n150# a_n657_n150# 0.43fF
-C26 a_n753_n150# a_n1041_n150# 0.10fF
-C27 a_n849_n150# a_n561_n150# 0.10fF
-C28 a_n753_n150# a_n849_n150# 0.43fF
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-C30 a_591_n150# a_495_n150# 0.43fF
-C31 a_399_n150# a_495_n150# 0.43fF
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-C33 a_975_n150# a_879_n150# 0.43fF
-C34 a_n1229_n150# a_n1041_n150# 0.16fF
-C35 a_n849_n150# a_n1229_n150# 0.07fF
-C36 a_1071_n150# a_1167_n150# 0.43fF
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-C42 a_495_n150# a_687_n150# 0.16fF
-C43 a_783_n150# a_495_n150# 0.10fF
-C44 a_n177_n150# a_n369_n150# 0.16fF
-C45 w_n1367_n369# a_1071_n150# 0.07fF
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-C47 a_399_n150# a_591_n150# 0.16fF
-C48 a_111_n150# a_n81_n150# 0.16fF
-C49 a_207_n150# a_591_n150# 0.07fF
-C50 a_399_n150# a_207_n150# 0.16fF
-C51 a_111_n150# a_n177_n150# 0.10fF
-C52 a_n657_n150# a_n465_n150# 0.16fF
-C53 a_n945_n150# a_n561_n150# 0.07fF
-C54 a_n849_n150# a_n465_n150# 0.07fF
-C55 a_n753_n150# a_n945_n150# 0.16fF
-C56 a_n81_n150# a_n273_n150# 0.16fF
-C57 a_15_n150# a_n81_n150# 0.43fF
-C58 a_n177_n150# a_n273_n150# 0.43fF
-C59 a_975_n150# a_1167_n150# 0.16fF
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-C63 a_n369_n150# a_n273_n150# 0.43fF
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-C66 a_n657_n150# a_n1041_n150# 0.07fF
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-C78 a_n177_n150# a_n561_n150# 0.07fF
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+C63 a_n1137_n150# a_n1229_n150# 0.43fF
+C64 a_n177_n150# a_207_n150# 0.07fF
+C65 a_n273_n150# a_15_n150# 0.10fF
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+C67 a_n177_n150# a_15_n150# 0.16fF
+C68 a_n1041_n150# a_n849_n150# 0.16fF
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+C70 a_n945_n150# a_n753_n150# 0.16fF
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+C72 a_n561_n150# a_n849_n150# 0.10fF
+C73 a_n1229_n150# a_n945_n150# 0.10fF
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+C77 a_n81_n150# a_n465_n150# 0.07fF
+C78 a_687_n150# a_303_n150# 0.07fF
 C79 a_975_n150# w_n1367_n369# 0.05fF
-C80 a_n369_n150# a_n561_n150# 0.16fF
-C81 a_n753_n150# a_n369_n150# 0.07fF
-C82 a_n945_n150# a_n1229_n150# 0.10fF
-C83 a_15_n150# a_n273_n150# 0.10fF
-C84 a_303_n150# a_687_n150# 0.07fF
-C85 a_n561_n150# a_n273_n150# 0.10fF
-C86 a_783_n150# a_687_n150# 0.43fF
-C87 a_591_n150# a_879_n150# 0.10fF
-C88 a_n753_n150# a_n561_n150# 0.16fF
-C89 a_n1137_n150# a_n1041_n150# 0.43fF
-C90 a_111_n150# a_495_n150# 0.07fF
-C91 a_n1137_n150# a_n849_n150# 0.10fF
-C92 a_n657_n150# a_n945_n150# 0.10fF
-C93 a_879_n150# a_687_n150# 0.16fF
-C94 a_n945_n150# a_n1041_n150# 0.43fF
-C95 a_783_n150# a_879_n150# 0.43fF
-C96 a_n849_n150# a_n945_n150# 0.43fF
-C97 a_n81_n150# a_n465_n150# 0.07fF
+C80 a_207_n150# a_15_n150# 0.16fF
+C81 a_495_n150# a_879_n150# 0.07fF
+C82 a_n465_n150# a_n561_n150# 0.43fF
+C83 a_975_n150# a_1167_n150# 0.16fF
+C84 a_n1041_n150# a_n657_n150# 0.07fF
+C85 a_n657_n150# a_n561_n150# 0.43fF
+C86 a_399_n150# a_111_n150# 0.10fF
+C87 a_495_n150# a_399_n150# 0.43fF
+C88 a_783_n150# a_1167_n150# 0.07fF
+C89 a_n1137_n150# a_n849_n150# 0.10fF
+C90 a_495_n150# a_591_n150# 0.43fF
+C91 a_n945_n150# a_n849_n150# 0.43fF
+C92 a_207_n150# a_303_n150# 0.43fF
+C93 a_n273_n150# a_111_n150# 0.07fF
+C94 a_303_n150# a_15_n150# 0.10fF
+C95 a_n177_n150# a_111_n150# 0.10fF
+C96 w_n1367_n369# a_1167_n150# 0.14fF
+C97 a_495_n150# a_687_n150# 0.16fF
 C98 a_1167_n150# VSUBS 0.03fF
 C99 a_1071_n150# VSUBS 0.03fF
 C100 a_975_n150# VSUBS 0.03fF
@@ -865,25 +4940,25 @@
 Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
 + biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
 + biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
-C0 biasp iref 0.80fF
-C1 pswitch vdd 3.98fF
-C2 Up pswitch 0.70fF
-C3 Down nDown 0.13fF
-C4 pswitch biasp 3.11fF
-C5 out nswitch 1.28fF
-C6 nswitch iref 1.91fF
-C7 biasp vdd 2.64fF
-C8 Down nswitch 2.27fF
-C9 pswitch nswitch 0.06fF
-C10 vdd nswitch 0.07fF
-C11 nUp out 0.31fF
-C12 Down nUp 0.25fF
-C13 biasp nswitch 0.03fF
-C14 nUp pswitch 5.66fF
-C15 nDown nswitch 0.31fF
-C16 Up nUp 0.15fF
-C17 pswitch out 4.91fF
-C18 out vdd 6.66fF
+C0 out vdd 6.66fF
+C1 Down nswitch 2.27fF
+C2 pswitch Up 0.70fF
+C3 biasp iref 0.80fF
+C4 Down nUp 0.25fF
+C5 vdd biasp 2.64fF
+C6 pswitch nswitch 0.06fF
+C7 Up nUp 0.15fF
+C8 pswitch nUp 5.66fF
+C9 out pswitch 4.91fF
+C10 out nswitch 1.28fF
+C11 pswitch biasp 3.11fF
+C12 Down nDown 0.13fF
+C13 out nUp 0.31fF
+C14 biasp nswitch 0.03fF
+C15 pswitch vdd 3.98fF
+C16 iref nswitch 1.91fF
+C17 vdd nswitch 0.07fF
+C18 nswitch nDown 0.31fF
 C19 vdd vss 35.71fF
 C20 Down vss 4.77fF
 C21 Up vss 1.17fF
@@ -896,346 +4971,14 @@
 C28 nUp vss 5.85fF
 .ends
 
-.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
-X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_15_n125# a_n81_n125# 0.36fF
-C1 a_n111_n156# a_n15_n156# 0.02fF
-C2 a_n173_n125# a_15_n125# 0.13fF
-C3 a_111_n125# w_n311_n344# 0.14fF
-C4 w_n311_n344# a_n81_n125# 0.09fF
-C5 a_n173_n125# w_n311_n344# 0.14fF
-C6 w_n311_n344# a_15_n125# 0.09fF
-C7 a_81_n156# a_n15_n156# 0.02fF
-C8 a_111_n125# a_n81_n125# 0.13fF
-C9 a_n173_n125# a_111_n125# 0.08fF
-C10 a_n173_n125# a_n81_n125# 0.36fF
-C11 a_111_n125# a_15_n125# 0.36fF
-C12 a_111_n125# VSUBS 0.03fF
-C13 a_15_n125# VSUBS 0.03fF
-C14 a_n81_n125# VSUBS 0.03fF
-C15 a_n173_n125# VSUBS 0.03fF
-C16 a_81_n156# VSUBS 0.05fF
-C17 a_n15_n156# VSUBS 0.05fF
-C18 a_n111_n156# VSUBS 0.05fF
-C19 w_n311_n344# VSUBS 2.21fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
-+ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_15_n125# 0.13fF
-C1 a_n111_n151# a_n15_n151# 0.02fF
-C2 a_15_n125# a_111_n125# 0.36fF
-C3 a_n81_n125# a_n173_n125# 0.36fF
-C4 a_n81_n125# a_111_n125# 0.13fF
-C5 a_n81_n125# a_15_n125# 0.36fF
-C6 a_n15_n151# a_81_n151# 0.02fF
-C7 a_n173_n125# a_111_n125# 0.08fF
-C8 a_111_n125# w_n311_n335# 0.17fF
-C9 a_15_n125# w_n311_n335# 0.12fF
-C10 a_n81_n125# w_n311_n335# 0.12fF
-C11 a_n173_n125# w_n311_n335# 0.17fF
-C12 a_81_n151# w_n311_n335# 0.05fF
-C13 a_n15_n151# w_n311_n335# 0.05fF
-C14 a_n111_n151# w_n311_n335# 0.05fF
-.ends
-
-.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
-Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
-+ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
-Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
-+ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
-C0 vdd m1_187_n605# 0.55fF
-C1 m1_45_n513# m1_187_n605# 0.36fF
-C2 m1_45_n513# vdd 0.69fF
-C3 m1_187_n605# vss 0.93fF
-C4 m1_45_n513# vss 1.31fF
-C5 vdd vss 3.36fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n81_n125#
-X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n81_n125# w_n311_n344# 0.09fF
-C1 a_n173_n125# a_n81_n125# 0.36fF
-C2 a_n81_n125# a_15_n125# 0.36fF
-C3 a_111_n125# a_n81_n125# 0.13fF
-C4 a_n173_n125# w_n311_n344# 0.14fF
-C5 w_n311_n344# a_15_n125# 0.09fF
-C6 a_111_n125# w_n311_n344# 0.14fF
-C7 a_n173_n125# a_15_n125# 0.13fF
-C8 a_n173_n125# a_111_n125# 0.08fF
-C9 a_111_n125# a_15_n125# 0.36fF
-C10 a_111_n125# VSUBS 0.03fF
-C11 a_15_n125# VSUBS 0.03fF
-C12 a_n81_n125# VSUBS 0.03fF
-C13 a_n173_n125# VSUBS 0.03fF
-C14 a_n111_n186# VSUBS 0.26fF
-C15 w_n311_n344# VSUBS 2.21fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
-+ a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_15_n125# 0.13fF
-C1 a_n81_n125# a_15_n125# 0.36fF
-C2 a_15_n125# a_111_n125# 0.36fF
-C3 a_n173_n125# a_n81_n125# 0.36fF
-C4 a_n173_n125# a_111_n125# 0.08fF
-C5 a_n81_n125# a_111_n125# 0.13fF
-C6 a_111_n125# w_n311_n335# 0.17fF
-C7 a_15_n125# w_n311_n335# 0.12fF
-C8 a_n81_n125# w_n311_n335# 0.12fF
-C9 a_n173_n125# w_n311_n335# 0.17fF
-C10 a_n111_n151# w_n311_n335# 0.25fF
-.ends
-
-.subckt inverter_cp_x1 out in vss vdd
-Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
-Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
-C0 in out 0.32fF
-C1 vdd out 0.10fF
-C2 out vss 0.77fF
-C3 in vss 0.95fF
-C4 vdd vss 3.13fF
-.ends
-
-.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
-+ nCLK_d
-Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
-Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
-Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
-Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
-C0 CLK_d vdd 0.03fF
-C1 CLK_d inverter_cp_x1_2/in 0.12fF
-C2 vdd CLK 0.36fF
-C3 inverter_cp_x1_2/in CLK 0.31fF
-C4 CLK inverter_cp_x1_0/out 0.31fF
-C5 nCLK_d vdd 0.03fF
-C6 nCLK_d inverter_cp_x1_0/out 0.11fF
-C7 inverter_cp_x1_2/in vdd 0.21fF
-C8 vdd inverter_cp_x1_0/out 0.28fF
-C9 CLK_d vss 0.96fF
-C10 inverter_cp_x1_2/in vss 2.01fF
-C11 inverter_cp_x1_0/out vss 1.97fF
-C12 CLK vss 3.03fF
-C13 nCLK_d vss 1.44fF
-C14 vdd vss 16.51fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
-+ a_n63_n192#
-X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 w_n263_n314# a_63_n95# 0.11fF
-C1 a_n125_n95# a_n33_n95# 0.28fF
-C2 a_n33_n95# a_63_n95# 0.28fF
-C3 a_n125_n95# a_63_n95# 0.10fF
-C4 a_n33_n95# w_n263_n314# 0.08fF
-C5 a_n125_n95# w_n263_n314# 0.11fF
-C6 a_63_n95# VSUBS 0.03fF
-C7 a_n33_n95# VSUBS 0.03fF
-C8 a_n125_n95# VSUBS 0.03fF
-C9 a_n63_n192# VSUBS 0.20fF
-C10 w_n263_n314# VSUBS 1.80fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
-+ a_n173_n125# a_n81_n125#
-X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_n129_n213# 0.02fF
-C1 a_n129_n213# a_111_n125# 0.01fF
-C2 a_n81_n125# a_15_n125# 0.36fF
-C3 a_n173_n125# a_15_n125# 0.13fF
-C4 a_15_n125# a_111_n125# 0.36fF
-C5 a_n173_n125# a_n81_n125# 0.36fF
-C6 a_n81_n125# a_111_n125# 0.13fF
-C7 a_n173_n125# a_111_n125# 0.08fF
-C8 a_15_n125# a_n129_n213# 0.10fF
-C9 a_n81_n125# a_n129_n213# 0.10fF
-C10 a_111_n125# w_n311_n335# 0.05fF
-C11 a_15_n125# w_n311_n335# 0.05fF
-C12 a_n81_n125# w_n311_n335# 0.05fF
-C13 a_n173_n125# w_n311_n335# 0.05fF
-C14 a_n129_n213# w_n311_n335# 0.49fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
-X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_n125_n95# a_n81_n183# 0.16fF
-C1 a_n125_n95# a_n33_n95# 0.88fF
-C2 a_n33_n95# a_n81_n183# 0.10fF
-C3 a_n33_n95# w_n263_n305# 0.07fF
-C4 a_n125_n95# w_n263_n305# 0.13fF
-C5 a_n81_n183# w_n263_n305# 0.31fF
-.ends
-
-.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
-Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
-Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
-C0 nQ Q 0.93fF
-C1 CLK m1_657_280# 0.24fF
-C2 Q D 0.05fF
-C3 Q m1_657_280# 0.94fF
-C4 Q nD 0.05fF
-C5 nQ D 0.05fF
-C6 Q vdd 0.16fF
-C7 nQ m1_657_280# 1.41fF
-C8 nQ nD 0.05fF
-C9 nQ vdd 0.16fF
-C10 nQ vss 1.16fF
-C11 D vss 0.53fF
-C12 Q vss -0.55fF
-C13 m1_657_280# vss 1.88fF
-C14 nD vss 0.16fF
-C15 CLK vss 0.87fF
-C16 vdd vss 5.98fF
-.ends
-
-.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
-+ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK latch_diff_0/nD
-Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
-+ latch_diff_0/D latch_diff_0/nD clock_inverter
-Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
-+ latch_diff_0/nD latch_diff_0/D latch_diff
-Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
-+ latch_diff
-C0 latch_diff_1/nD Q 0.01fF
-C1 latch_diff_1/D nQ 0.11fF
-C2 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
-C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
-C4 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
-C5 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
-C6 latch_diff_1/D latch_diff_1/nD 0.33fF
-C7 latch_diff_1/nD vdd 0.02fF
-C8 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
-C9 latch_diff_1/nD latch_diff_0/D 0.04fF
-C10 latch_diff_1/D latch_diff_0/nD 0.41fF
-C11 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
-C12 latch_diff_0/nD vdd 0.14fF
-C13 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
-C14 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C15 latch_diff_1/D vdd 0.03fF
-C16 latch_diff_1/D latch_diff_0/D 0.11fF
-C17 vdd latch_diff_0/D 0.09fF
-C18 nQ latch_diff_1/nD 0.08fF
-C19 nQ vss 0.57fF
-C20 Q vss -0.92fF
-C21 latch_diff_1/m1_657_280# vss 0.64fF
-C22 nCLK vss 0.83fF
-C23 latch_diff_1/nD vss 1.83fF
-C24 latch_diff_1/D vss -0.30fF
-C25 latch_diff_0/m1_657_280# vss 0.72fF
-C26 CLK vss 0.83fF
-C27 latch_diff_0/D vss 1.29fF
-C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
-C30 D vss 3.27fF
-C31 latch_diff_0/nD vss 1.74fF
-C32 vdd vss 32.62fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
-+ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
-X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n33_n84# a_n129_n84# 0.24fF
-C1 a_n221_n84# a_n129_n84# 0.24fF
-C2 w_n359_n303# a_n129_n84# 0.06fF
-C3 a_n129_n84# a_159_n84# 0.05fF
-C4 a_63_n84# a_n129_n84# 0.09fF
-C5 a_n63_n110# a_33_n110# 0.02fF
-C6 a_n159_n110# a_n63_n110# 0.02fF
-C7 a_129_n110# a_33_n110# 0.02fF
-C8 a_n221_n84# a_n33_n84# 0.09fF
-C9 w_n359_n303# a_n33_n84# 0.05fF
-C10 a_n221_n84# w_n359_n303# 0.08fF
-C11 a_n33_n84# a_159_n84# 0.09fF
-C12 a_63_n84# a_n33_n84# 0.24fF
-C13 a_n221_n84# a_159_n84# 0.04fF
-C14 a_n221_n84# a_63_n84# 0.05fF
-C15 w_n359_n303# a_159_n84# 0.08fF
-C16 a_63_n84# w_n359_n303# 0.06fF
-C17 a_63_n84# a_159_n84# 0.24fF
-C18 a_159_n84# VSUBS 0.03fF
-C19 a_63_n84# VSUBS 0.03fF
-C20 a_n33_n84# VSUBS 0.03fF
-C21 a_n129_n84# VSUBS 0.03fF
-C22 a_n221_n84# VSUBS 0.03fF
-C23 a_129_n110# VSUBS 0.05fF
-C24 a_33_n110# VSUBS 0.05fF
-C25 a_n63_n110# VSUBS 0.05fF
-C26 a_n159_n110# VSUBS 0.05fF
-C27 w_n359_n303# VSUBS 2.19fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
-+ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
-X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_33_n68# a_129_n68# 0.02fF
-C1 a_n33_n42# a_63_n42# 0.12fF
-C2 a_63_n42# a_n129_n42# 0.05fF
-C3 a_159_n42# a_n33_n42# 0.05fF
-C4 a_n33_n42# a_n221_n42# 0.05fF
-C5 a_159_n42# a_n129_n42# 0.03fF
-C6 a_n221_n42# a_n129_n42# 0.12fF
-C7 a_159_n42# a_63_n42# 0.12fF
-C8 a_63_n42# a_n221_n42# 0.03fF
-C9 a_33_n68# a_n63_n68# 0.02fF
-C10 a_159_n42# a_n221_n42# 0.02fF
-C11 a_n159_n68# a_n63_n68# 0.02fF
-C12 a_n33_n42# a_n129_n42# 0.12fF
-C13 a_159_n42# w_n359_n252# 0.07fF
-C14 a_63_n42# w_n359_n252# 0.06fF
-C15 a_n33_n42# w_n359_n252# 0.06fF
-C16 a_n129_n42# w_n359_n252# 0.06fF
-C17 a_n221_n42# w_n359_n252# 0.07fF
-C18 a_129_n68# w_n359_n252# 0.05fF
-C19 a_33_n68# w_n359_n252# 0.05fF
-C20 a_n63_n68# w_n359_n252# 0.05fF
-C21 a_n159_n68# w_n359_n252# 0.05fF
-.ends
-
-.subckt inverter_min_x4 in vss out vdd
-Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
-Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
-C0 vdd out 0.62fF
-C1 in out 0.67fF
-C2 vdd in 0.33fF
-C3 out vss 0.66fF
-C4 in vss 1.89fF
-C5 vdd vss 3.87fF
-.ends
-
 .subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
 + a_n125_n42# a_63_n42#
 X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
 X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_63_n42# a_n125_n42# 0.05fF
-C1 a_n125_n42# a_n33_n42# 0.12fF
-C2 a_33_n68# a_n63_n68# 0.02fF
-C3 a_63_n42# a_n33_n42# 0.12fF
+C0 a_n63_n68# a_33_n68# 0.02fF
+C1 a_n33_n42# a_n125_n42# 0.12fF
+C2 a_n33_n42# a_63_n42# 0.12fF
+C3 a_n125_n42# a_63_n42# 0.05fF
 C4 a_63_n42# w_n263_n252# 0.09fF
 C5 a_n33_n42# w_n263_n252# 0.07fF
 C6 a_n125_n42# w_n263_n252# 0.09fF
@@ -1247,13 +4990,13 @@
 + w_n263_n303# a_n33_n84#
 X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
 X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_63_n84# w_n263_n303# 0.10fF
-C1 a_63_n84# a_n33_n84# 0.24fF
-C2 a_63_n84# a_n125_n84# 0.09fF
+C0 a_n33_n84# a_n125_n84# 0.24fF
+C1 a_n125_n84# a_63_n84# 0.09fF
+C2 a_n33_n84# w_n263_n303# 0.07fF
 C3 a_33_n110# a_n63_n110# 0.02fF
-C4 a_n33_n84# w_n263_n303# 0.07fF
-C5 w_n263_n303# a_n125_n84# 0.10fF
-C6 a_n33_n84# a_n125_n84# 0.24fF
+C4 w_n263_n303# a_63_n84# 0.10fF
+C5 a_n125_n84# w_n263_n303# 0.10fF
+C6 a_n33_n84# a_63_n84# 0.24fF
 C7 a_63_n84# VSUBS 0.03fF
 C8 a_n33_n84# VSUBS 0.03fF
 C9 a_n125_n84# VSUBS 0.03fF
@@ -1265,77 +5008,78 @@
 .subckt inverter_min_x2 in out vss vdd
 Xsky130_fd_pr__nfet_01v8_5RJ8EK_0 vss in vss in out out sky130_fd_pr__nfet_01v8_5RJ8EK
 Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
-C0 out in 0.30fF
-C1 out vdd 0.15fF
-C2 in vdd 0.01fF
+C0 vdd in 0.01fF
+C1 out in 0.30fF
+C2 out vdd 0.15fF
 C3 vdd vss 2.93fF
 C4 out vss 0.66fF
 C5 in vss 0.72fF
 .ends
 
 .subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
-+ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
-+ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
++ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
 Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
 + DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
-Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
-Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
 Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
 Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
-C0 vdd o1 0.14fF
-C1 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
-C2 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
-C3 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
-C4 nCLK_2 vdd 0.08fF
-C5 o2 vdd 0.14fF
-C6 nout_div DFlipFlop_0/latch_diff_0/m1_657_280# 0.24fF
-C7 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
-C8 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
-C9 DFlipFlop_0/nCLK vdd 0.30fF
-C10 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
-C11 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
-C12 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/nD 0.12fF
-C13 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
-C14 out_div vdd 0.03fF
-C15 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
-C16 vdd CLK_2 0.08fF
-C17 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
-C18 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
-C19 DFlipFlop_0/nCLK nout_div 0.43fF
-C20 vdd DFlipFlop_0/CLK 0.40fF
-C21 o2 nCLK_2 0.11fF
-C22 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
-C23 out_div nout_div 0.22fF
-C24 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
-C25 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
-C26 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
-C27 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
-C28 out_div o1 0.01fF
-C29 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.26fF
-C30 o1 CLK_2 0.11fF
-C31 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C32 DFlipFlop_0/CLK nout_div 0.42fF
-C33 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
-C34 vdd nout_div 0.16fF
-C35 nCLK_2 vss 1.08fF
-C36 o2 vss 2.21fF
-C37 CLK_2 vss 1.08fF
-C38 o1 vss 2.21fF
-C39 DFlipFlop_0/CLK vss 1.03fF
-C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C42 CLK vss 3.27fF
-C43 DFlipFlop_0/nCLK vss 1.76fF
+C0 nout_div vdd 0.16fF
+C1 o1 vdd 0.14fF
+C2 o2 vdd 0.14fF
+C3 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C4 nout_div out_div 0.22fF
+C5 DFlipFlop_0/CLK vdd 0.40fF
+C6 DFlipFlop_0/nCLK nout_div 0.43fF
+C7 o1 out_div 0.01fF
+C8 vdd clock_inverter_0/inverter_cp_x1_0/out 0.10fF
+C9 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C10 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
+C11 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C12 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
+C13 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C15 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C16 o1 CLK_2 0.11fF
+C17 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/nD 0.11fF
+C18 o2 nCLK_2 0.11fF
+C19 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C20 vdd out_div 0.03fF
+C21 DFlipFlop_0/nCLK vdd 0.30fF
+C22 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C23 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C24 nout_div DFlipFlop_0/CLK 0.42fF
+C25 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C26 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C27 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.26fF
+C28 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C29 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C30 CLK_2 vdd 0.08fF
+C31 vdd nCLK_2 0.08fF
+C32 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C33 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C34 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C36 DFlipFlop_0/CLK vss 1.03fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
 C44 out_div vss -0.77fF
 C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
 C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
 C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
 C52 nout_div vss 4.41fF
 C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -1348,8 +5092,8 @@
 X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
 X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
 X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
-C0 a_n221_n600# a_n257_n777# 0.25fF
-C1 a_n221_n600# a_n129_n600# 7.87fF
+C0 a_n129_n600# a_n221_n600# 7.87fF
+C1 a_n221_n600# a_n257_n777# 0.25fF
 C2 a_n129_n600# a_n257_n777# 0.29fF
 C3 a_n129_n600# VSUBS 0.10fF
 C4 a_n221_n600# VSUBS 0.25fF
@@ -1362,9 +5106,9 @@
 X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
 X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
 X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
-C0 a_n129_n300# a_n257_n404# 0.30fF
+C0 a_n129_n300# a_n221_n300# 4.05fF
 C1 a_n257_n404# a_n221_n300# 0.21fF
-C2 a_n129_n300# a_n221_n300# 4.05fF
+C2 a_n129_n300# a_n257_n404# 0.30fF
 C3 a_n129_n300# w_n257_n327# 0.11fF
 C4 a_n221_n300# w_n257_n327# 0.25fF
 C5 a_n257_n404# w_n257_n327# 1.11fF
@@ -1517,25 +5261,25 @@
 Xsky130_fd_pr__pfet_01v8_58ZKDE_29 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
 Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
 Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
-C0 in vdd 0.02fF
-C1 in a_678_n100# 0.81fF
-C2 out a_3996_n100# 55.19fF
-C3 a_3996_n100# vdd 3.68fF
+C0 vdd in 0.02fF
+C1 vdd a_678_n100# 0.08fF
+C2 a_678_n100# a_3996_n100# 6.52fF
+C3 vdd a_3996_n100# 3.68fF
 C4 out vdd 47.17fF
-C5 a_3996_n100# a_678_n100# 6.52fF
-C6 a_678_n100# vdd 0.08fF
-C7 vdd vss 20.93fF
-C8 out vss 35.17fF
-C9 a_3996_n100# vss 49.53fF
+C5 out a_3996_n100# 55.19fF
+C6 a_678_n100# in 0.81fF
+C7 a_3996_n100# vss 49.53fF
+C8 vdd vss 20.93fF
+C9 out vss 35.17fF
 C10 a_678_n100# vss 13.08fF
 C11 in vss 0.87fF
 .ends
 
 .subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
 X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n33_n238# a_n73_n150# 0.02fF
-C1 a_15_n150# a_n33_n238# 0.02fF
-C2 a_15_n150# a_n73_n150# 0.51fF
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_n73_n150# a_15_n150# 0.51fF
 C3 a_15_n150# w_n211_n360# 0.23fF
 C4 a_n73_n150# w_n211_n360# 0.23fF
 C5 a_n33_n238# w_n211_n360# 0.17fF
@@ -1543,12 +5287,12 @@
 
 .subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
 X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 w_n211_n369# a_n33_181# 0.05fF
-C1 a_n73_n150# w_n211_n369# 0.20fF
-C2 a_n73_n150# a_n33_181# 0.01fF
-C3 a_15_n150# w_n211_n369# 0.20fF
-C4 a_15_n150# a_n33_181# 0.01fF
-C5 a_n73_n150# a_15_n150# 0.51fF
+C0 a_n73_n150# w_n211_n369# 0.20fF
+C1 a_n73_n150# a_n33_181# 0.01fF
+C2 a_15_n150# w_n211_n369# 0.20fF
+C3 a_15_n150# a_n33_181# 0.01fF
+C4 a_n73_n150# a_15_n150# 0.51fF
+C5 a_n33_181# w_n211_n369# 0.05fF
 C6 a_15_n150# VSUBS 0.03fF
 C7 a_n73_n150# VSUBS 0.03fF
 C8 a_n33_181# VSUBS 0.13fF
@@ -1568,51 +5312,51 @@
 X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n129_n150# a_63_n150# 0.16fF
-C1 a_159_n150# a_63_n150# 0.43fF
-C2 a_447_n150# a_63_n150# 0.07fF
-C3 a_255_n150# a_n465_172# 0.10fF
-C4 a_n129_n150# a_n225_n150# 0.43fF
-C5 a_159_n150# a_n225_n150# 0.07fF
-C6 a_255_n150# a_n33_n150# 0.10fF
-C7 a_n417_n150# a_n129_n150# 0.10fF
-C8 a_n465_172# a_n33_n150# 0.10fF
-C9 a_n465_172# a_n509_n150# 0.01fF
-C10 a_255_n150# a_63_n150# 0.16fF
-C11 a_351_n150# a_447_n150# 0.43fF
-C12 a_351_n150# a_159_n150# 0.16fF
-C13 a_n465_172# a_63_n150# 0.10fF
-C14 a_n33_n150# a_63_n150# 0.43fF
-C15 a_n321_n150# a_n129_n150# 0.16fF
-C16 a_n465_172# a_n225_n150# 0.10fF
-C17 a_n417_n150# a_n465_172# 0.10fF
-C18 a_n33_n150# a_n225_n150# 0.16fF
-C19 a_n417_n150# a_n33_n150# 0.07fF
-C20 a_n509_n150# a_n225_n150# 0.10fF
-C21 a_255_n150# a_351_n150# 0.43fF
-C22 a_n417_n150# a_n509_n150# 0.43fF
-C23 a_351_n150# a_n465_172# 0.10fF
-C24 a_n225_n150# a_63_n150# 0.10fF
-C25 a_351_n150# a_n33_n150# 0.07fF
-C26 a_n321_n150# a_n465_172# 0.10fF
-C27 a_n417_n150# a_n225_n150# 0.16fF
-C28 a_n321_n150# a_n33_n150# 0.10fF
-C29 a_159_n150# a_n129_n150# 0.10fF
-C30 a_159_n150# a_447_n150# 0.10fF
-C31 a_351_n150# a_63_n150# 0.10fF
-C32 a_n321_n150# a_n509_n150# 0.16fF
-C33 a_n321_n150# a_63_n150# 0.07fF
-C34 a_n321_n150# a_n225_n150# 0.43fF
-C35 a_255_n150# a_n129_n150# 0.07fF
-C36 a_n417_n150# a_n321_n150# 0.43fF
-C37 a_255_n150# a_447_n150# 0.16fF
-C38 a_255_n150# a_159_n150# 0.43fF
-C39 a_n465_172# a_n129_n150# 0.10fF
-C40 a_n465_172# a_447_n150# 0.01fF
-C41 a_159_n150# a_n465_172# 0.10fF
-C42 a_n33_n150# a_n129_n150# 0.43fF
-C43 a_159_n150# a_n33_n150# 0.16fF
-C44 a_n509_n150# a_n129_n150# 0.07fF
+C0 a_n321_n150# a_n417_n150# 0.43fF
+C1 a_n321_n150# a_n33_n150# 0.10fF
+C2 a_159_n150# a_n129_n150# 0.10fF
+C3 a_n465_172# a_63_n150# 0.10fF
+C4 a_n509_n150# a_n465_172# 0.01fF
+C5 a_63_n150# a_447_n150# 0.07fF
+C6 a_n225_n150# a_159_n150# 0.07fF
+C7 a_n465_172# a_447_n150# 0.01fF
+C8 a_n129_n150# a_63_n150# 0.16fF
+C9 a_n129_n150# a_n465_172# 0.10fF
+C10 a_n509_n150# a_n129_n150# 0.07fF
+C11 a_n225_n150# a_63_n150# 0.10fF
+C12 a_n225_n150# a_n465_172# 0.10fF
+C13 a_n509_n150# a_n225_n150# 0.10fF
+C14 a_255_n150# a_n33_n150# 0.10fF
+C15 a_n321_n150# a_63_n150# 0.07fF
+C16 a_n321_n150# a_n465_172# 0.10fF
+C17 a_n509_n150# a_n321_n150# 0.16fF
+C18 a_n225_n150# a_n129_n150# 0.43fF
+C19 a_159_n150# a_255_n150# 0.43fF
+C20 a_351_n150# a_255_n150# 0.43fF
+C21 a_n321_n150# a_n129_n150# 0.16fF
+C22 a_n321_n150# a_n225_n150# 0.43fF
+C23 a_n33_n150# a_n417_n150# 0.07fF
+C24 a_63_n150# a_255_n150# 0.16fF
+C25 a_n465_172# a_255_n150# 0.10fF
+C26 a_255_n150# a_447_n150# 0.16fF
+C27 a_n129_n150# a_255_n150# 0.07fF
+C28 a_159_n150# a_n33_n150# 0.16fF
+C29 a_351_n150# a_n33_n150# 0.07fF
+C30 a_n465_172# a_n417_n150# 0.10fF
+C31 a_159_n150# a_351_n150# 0.16fF
+C32 a_n509_n150# a_n417_n150# 0.43fF
+C33 a_63_n150# a_n33_n150# 0.43fF
+C34 a_n465_172# a_n33_n150# 0.10fF
+C35 a_n129_n150# a_n417_n150# 0.10fF
+C36 a_n129_n150# a_n33_n150# 0.43fF
+C37 a_159_n150# a_63_n150# 0.43fF
+C38 a_63_n150# a_351_n150# 0.10fF
+C39 a_159_n150# a_n465_172# 0.10fF
+C40 a_n465_172# a_351_n150# 0.10fF
+C41 a_n225_n150# a_n417_n150# 0.16fF
+C42 a_159_n150# a_447_n150# 0.10fF
+C43 a_351_n150# a_447_n150# 0.43fF
+C44 a_n225_n150# a_n33_n150# 0.16fF
 C45 a_447_n150# w_n647_n360# 0.17fF
 C46 a_351_n150# w_n647_n360# 0.10fF
 C47 a_255_n150# w_n647_n360# 0.08fF
@@ -1640,61 +5384,61 @@
 X7 a_159_n150# a_n465_n247# a_63_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_63_n150# a_n465_n247# 0.08fF
-C1 a_n465_n247# a_n321_n150# 0.08fF
-C2 a_351_n150# a_n33_n150# 0.07fF
-C3 a_255_n150# w_n647_n369# 0.05fF
-C4 a_255_n150# a_n129_n150# 0.07fF
-C5 a_351_n150# a_159_n150# 0.16fF
-C6 a_447_n150# a_159_n150# 0.10fF
-C7 a_n417_n150# a_n33_n150# 0.07fF
-C8 w_n647_n369# a_n33_n150# 0.02fF
-C9 a_n129_n150# a_n33_n150# 0.43fF
-C10 a_n509_n150# a_n417_n150# 0.43fF
-C11 a_n509_n150# w_n647_n369# 0.14fF
-C12 a_63_n150# a_255_n150# 0.16fF
-C13 a_n509_n150# a_n129_n150# 0.07fF
-C14 a_n465_n247# a_255_n150# 0.08fF
-C15 w_n647_n369# a_159_n150# 0.04fF
-C16 a_n129_n150# a_159_n150# 0.10fF
-C17 a_n225_n150# a_n33_n150# 0.16fF
-C18 a_351_n150# a_447_n150# 0.43fF
-C19 a_63_n150# a_n33_n150# 0.43fF
-C20 a_n321_n150# a_n33_n150# 0.10fF
-C21 a_n509_n150# a_n225_n150# 0.10fF
-C22 a_n465_n247# a_n33_n150# 0.08fF
-C23 a_n509_n150# a_n321_n150# 0.16fF
-C24 a_n225_n150# a_159_n150# 0.07fF
-C25 a_63_n150# a_159_n150# 0.43fF
-C26 a_351_n150# w_n647_n369# 0.07fF
-C27 a_447_n150# w_n647_n369# 0.14fF
-C28 a_n465_n247# a_159_n150# 0.08fF
-C29 w_n647_n369# a_n417_n150# 0.07fF
-C30 a_n129_n150# a_n417_n150# 0.10fF
-C31 a_n129_n150# w_n647_n369# 0.02fF
-C32 a_63_n150# a_351_n150# 0.10fF
-C33 a_63_n150# a_447_n150# 0.07fF
-C34 a_255_n150# a_n33_n150# 0.10fF
-C35 a_n465_n247# a_351_n150# 0.08fF
-C36 a_255_n150# a_159_n150# 0.43fF
-C37 a_n225_n150# a_n417_n150# 0.16fF
-C38 a_n225_n150# w_n647_n369# 0.04fF
-C39 a_n129_n150# a_n225_n150# 0.43fF
-C40 a_63_n150# w_n647_n369# 0.02fF
-C41 a_63_n150# a_n129_n150# 0.16fF
-C42 a_n417_n150# a_n321_n150# 0.43fF
-C43 w_n647_n369# a_n321_n150# 0.05fF
-C44 a_n129_n150# a_n321_n150# 0.16fF
-C45 a_n465_n247# a_n417_n150# 0.08fF
-C46 a_n465_n247# w_n647_n369# 0.47fF
-C47 a_n465_n247# a_n129_n150# 0.08fF
-C48 a_159_n150# a_n33_n150# 0.16fF
-C49 a_63_n150# a_n225_n150# 0.10fF
-C50 a_n225_n150# a_n321_n150# 0.43fF
-C51 a_351_n150# a_255_n150# 0.43fF
-C52 a_255_n150# a_447_n150# 0.16fF
-C53 a_63_n150# a_n321_n150# 0.07fF
-C54 a_n465_n247# a_n225_n150# 0.08fF
+C0 w_n647_n369# a_n129_n150# 0.02fF
+C1 a_n225_n150# w_n647_n369# 0.04fF
+C2 a_n33_n150# a_n465_n247# 0.08fF
+C3 a_n33_n150# a_n417_n150# 0.07fF
+C4 a_255_n150# a_n465_n247# 0.08fF
+C5 a_n321_n150# a_63_n150# 0.07fF
+C6 a_159_n150# a_n465_n247# 0.08fF
+C7 w_n647_n369# a_n465_n247# 0.47fF
+C8 a_n417_n150# w_n647_n369# 0.07fF
+C9 a_n321_n150# a_n129_n150# 0.16fF
+C10 a_n225_n150# a_n321_n150# 0.43fF
+C11 a_n509_n150# a_n129_n150# 0.07fF
+C12 a_n33_n150# a_255_n150# 0.10fF
+C13 a_n509_n150# a_n225_n150# 0.10fF
+C14 a_n33_n150# a_159_n150# 0.16fF
+C15 a_255_n150# a_447_n150# 0.16fF
+C16 a_351_n150# a_63_n150# 0.10fF
+C17 a_159_n150# a_447_n150# 0.10fF
+C18 a_159_n150# a_255_n150# 0.43fF
+C19 a_n33_n150# w_n647_n369# 0.02fF
+C20 a_n321_n150# a_n465_n247# 0.08fF
+C21 a_63_n150# a_n129_n150# 0.16fF
+C22 a_n417_n150# a_n321_n150# 0.43fF
+C23 w_n647_n369# a_447_n150# 0.14fF
+C24 a_255_n150# w_n647_n369# 0.05fF
+C25 a_n225_n150# a_63_n150# 0.10fF
+C26 a_159_n150# w_n647_n369# 0.04fF
+C27 a_n509_n150# a_n417_n150# 0.43fF
+C28 a_n225_n150# a_n129_n150# 0.43fF
+C29 a_n33_n150# a_n321_n150# 0.10fF
+C30 a_63_n150# a_n465_n247# 0.08fF
+C31 a_351_n150# a_n465_n247# 0.08fF
+C32 a_n129_n150# a_n465_n247# 0.08fF
+C33 a_n417_n150# a_n129_n150# 0.10fF
+C34 w_n647_n369# a_n321_n150# 0.05fF
+C35 a_n225_n150# a_n465_n247# 0.08fF
+C36 a_n417_n150# a_n225_n150# 0.16fF
+C37 a_n33_n150# a_63_n150# 0.43fF
+C38 a_n509_n150# w_n647_n369# 0.14fF
+C39 a_n33_n150# a_351_n150# 0.07fF
+C40 a_447_n150# a_63_n150# 0.07fF
+C41 a_255_n150# a_63_n150# 0.16fF
+C42 a_159_n150# a_63_n150# 0.43fF
+C43 a_447_n150# a_351_n150# 0.43fF
+C44 a_255_n150# a_351_n150# 0.43fF
+C45 a_n33_n150# a_n129_n150# 0.43fF
+C46 a_159_n150# a_351_n150# 0.16fF
+C47 a_n417_n150# a_n465_n247# 0.08fF
+C48 w_n647_n369# a_63_n150# 0.02fF
+C49 a_n33_n150# a_n225_n150# 0.16fF
+C50 a_255_n150# a_n129_n150# 0.07fF
+C51 w_n647_n369# a_351_n150# 0.07fF
+C52 a_159_n150# a_n129_n150# 0.10fF
+C53 a_n509_n150# a_n321_n150# 0.16fF
+C54 a_159_n150# a_n225_n150# 0.07fF
 C55 a_447_n150# VSUBS 0.03fF
 C56 a_351_n150# VSUBS 0.03fF
 C57 a_255_n150# VSUBS 0.03fF
@@ -1713,8 +5457,8 @@
 .subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
 X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
 C0 a_n33_n99# a_15_n11# 0.02fF
-C1 a_n33_n99# a_n73_n11# 0.02fF
-C2 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n73_n11# a_15_n11# 0.15fF
+C2 a_n33_n99# a_n73_n11# 0.02fF
 C3 a_15_n11# w_n211_n221# 0.09fF
 C4 a_n73_n11# w_n211_n221# 0.09fF
 C5 a_n33_n99# w_n211_n221# 0.17fF
@@ -1733,7 +5477,7 @@
 X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
 C0 w_n216_n334# a_n78_n114# 0.20fF
 C1 w_n216_n334# a_20_n114# 0.20fF
-C2 a_20_n114# a_n78_n114# 0.42fF
+C2 a_n78_n114# a_20_n114# 0.42fF
 C3 a_20_n114# VSUBS 0.03fF
 C4 a_n78_n114# VSUBS 0.03fF
 C5 a_n33_n211# VSUBS 0.12fF
@@ -1744,10 +5488,10 @@
 Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
 Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
 C0 out vbulkp 0.08fF
-C1 in out 0.11fF
-C2 vss in 0.01fF
-C3 vdd vbulkp 0.04fF
-C4 vdd in 0.01fF
+C1 in vdd 0.01fF
+C2 vdd vbulkp 0.04fF
+C3 in vss 0.01fF
+C4 in out 0.11fF
 C5 vbulkp vbulkn 2.49fF
 C6 out vbulkn 0.60fF
 C7 vdd vbulkn 0.06fF
@@ -1765,20 +5509,20 @@
 + vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
 Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
 Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
-C0 vdd inverter_csvco_0/vdd 1.89fF
-C1 out in 0.06fF
-C2 D0 inverter_csvco_0/vss 0.02fF
-C3 out D0 0.09fF
-C4 out cap_vco_0/t 0.70fF
-C5 inverter_csvco_0/vdd in 0.01fF
-C6 vctrl inverter_csvco_0/vss 0.87fF
-C7 out inverter_csvco_0/vdd 0.02fF
-C8 vbp inverter_csvco_0/vdd 0.75fF
-C9 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
-C10 vdd vbp 1.21fF
-C11 vdd cap_vco_0/t 0.04fF
-C12 in inverter_csvco_0/vss 0.01fF
-C13 out inverter_csvco_0/vss 0.03fF
+C0 inverter_csvco_0/vdd vdd 1.89fF
+C1 inverter_csvco_0/vdd out 0.02fF
+C2 inverter_csvco_0/vdd in 0.01fF
+C3 inverter_csvco_0/vss out 0.03fF
+C4 inverter_csvco_0/vss in 0.01fF
+C5 D0 inverter_csvco_0/vss 0.02fF
+C6 out in 0.06fF
+C7 D0 out 0.09fF
+C8 cap_vco_0/t inverter_csvco_0/vdd 0.10fF
+C9 inverter_csvco_0/vdd vbp 0.75fF
+C10 cap_vco_0/t vdd 0.04fF
+C11 vdd vbp 1.21fF
+C12 cap_vco_0/t out 0.70fF
+C13 inverter_csvco_0/vss vctrl 0.87fF
 C14 out vss 0.93fF
 C15 inverter_csvco_0/vdd vss 0.26fF
 C16 in vss 0.69fF
@@ -1805,21 +5549,21 @@
 Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
 + csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
 + vss vdd csvco_branch
-C0 out_vco csvco_branch_1/in 0.76fF
-C1 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
-C2 vctrl D0 4.41fF
-C3 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
-C4 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
-C5 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
-C6 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
-C7 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
-C8 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
-C9 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
-C10 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
-C11 vctrl csvco_branch_2/vbp 0.06fF
-C12 csvco_branch_2/vbp vdd 1.49fF
-C13 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
-C14 out_vco csvco_branch_2/in 0.58fF
+C0 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
+C1 D0 vctrl 4.41fF
+C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
+C3 csvco_branch_1/inverter_csvco_0/vss D0 0.68fF
+C4 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
+C5 vdd csvco_branch_2/vbp 1.49fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C8 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C9 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
+C10 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C11 vdd csvco_branch_2/inverter_csvco_0/vdd 0.10fF
+C12 out_vco csvco_branch_2/in 0.58fF
+C13 csvco_branch_2/vbp vctrl 0.06fF
+C14 out_vco csvco_branch_1/in 0.76fF
 C15 csvco_branch_2/in vss 1.60fF
 C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -1839,19 +5583,19 @@
 .ends
 
 .subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
-Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
-Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
 Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
-C0 out_pad out_div 0.15fF
-C1 vdd out_pad 0.10fF
+C0 vdd o1 0.09fF
+C1 vdd out_div 0.17fF
 C2 o1 out_div 0.11fF
-C3 vdd o1 0.09fF
-C4 vdd out_div 0.17fF
+C3 out_pad vdd 0.10fF
+C4 out_pad out_div 0.15fF
 C5 in_vco vss 0.83fF
-C6 out_pad vss 0.70fF
-C7 out_div vss 3.00fF
-C8 vdd vss 14.54fF
-C9 o1 vss 2.72fF
+C6 o1 vss 2.72fF
+C7 vdd vss 14.54fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
 .ends
 
 .subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
@@ -1866,27 +5610,27 @@
 X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
 X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
 X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-C0 VGND X 0.28fF
-C1 A a_355_368# 0.02fF
-C2 VGND VPWR 0.01fF
-C3 B a_194_125# 0.57fF
-C4 a_355_368# a_194_125# 0.51fF
-C5 a_355_368# B 0.08fF
-C6 A VPWR 0.15fF
-C7 a_158_392# a_194_125# 0.06fF
-C8 X a_194_125# 0.29fF
-C9 B X 0.13fF
-C10 a_194_125# VPWR 0.33fF
-C11 B VPWR 0.09fF
-C12 a_355_368# X 0.17fF
-C13 a_355_368# VPWR 0.37fF
-C14 X VPWR 0.07fF
-C15 A VGND 0.31fF
-C16 VGND a_194_125# 0.25fF
-C17 B VGND 0.10fF
-C18 VPB VPWR 0.06fF
-C19 A a_194_125# 0.18fF
-C20 A B 0.28fF
+C0 a_355_368# VPWR 0.37fF
+C1 a_355_368# B 0.08fF
+C2 a_355_368# X 0.17fF
+C3 a_194_125# a_158_392# 0.06fF
+C4 a_194_125# A 0.18fF
+C5 VPWR A 0.15fF
+C6 B A 0.28fF
+C7 a_194_125# VPWR 0.33fF
+C8 B a_194_125# 0.57fF
+C9 a_194_125# X 0.29fF
+C10 VGND A 0.31fF
+C11 a_194_125# VGND 0.25fF
+C12 a_355_368# A 0.02fF
+C13 a_355_368# a_194_125# 0.51fF
+C14 B VPWR 0.09fF
+C15 VPWR X 0.07fF
+C16 B X 0.13fF
+C17 VPB VPWR 0.06fF
+C18 VGND VPWR 0.01fF
+C19 B VGND 0.10fF
+C20 VGND X 0.28fF
 C21 VGND VNB 0.78fF
 C22 X VNB 0.21fF
 C23 VPWR VNB 0.78fF
@@ -1904,20 +5648,20 @@
 X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
 X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
 X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-C0 B A 0.08fF
-C1 VGND X 0.15fF
-C2 A VPWR 0.07fF
-C3 B a_56_136# 0.30fF
-C4 VPWR a_56_136# 0.57fF
-C5 X a_56_136# 0.26fF
-C6 VGND A 0.21fF
-C7 VGND a_56_136# 0.06fF
-C8 A a_56_136# 0.17fF
-C9 B VPWR 0.02fF
-C10 B X 0.02fF
-C11 VPB VPWR 0.04fF
-C12 X VPWR 0.20fF
-C13 B VGND 0.03fF
+C0 X VGND 0.15fF
+C1 B VGND 0.03fF
+C2 a_56_136# VPWR 0.57fF
+C3 A VPWR 0.07fF
+C4 X VPWR 0.20fF
+C5 B VPWR 0.02fF
+C6 VPB VPWR 0.04fF
+C7 A a_56_136# 0.17fF
+C8 X a_56_136# 0.26fF
+C9 B a_56_136# 0.30fF
+C10 A B 0.08fF
+C11 a_56_136# VGND 0.06fF
+C12 A VGND 0.21fF
+C13 B X 0.02fF
 C14 VGND VNB 0.50fF
 C15 X VNB 0.23fF
 C16 VPWR VNB 0.50fF
@@ -1934,20 +5678,20 @@
 X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
 X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
 X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-C0 B a_63_368# 0.14fF
-C1 X VGND 0.16fF
-C2 B VGND 0.11fF
-C3 X VPWR 0.18fF
-C4 B VPWR 0.01fF
-C5 VGND a_63_368# 0.27fF
-C6 VPWR a_63_368# 0.29fF
-C7 X A 0.02fF
-C8 B A 0.10fF
-C9 VPWR VPB 0.04fF
-C10 A a_63_368# 0.28fF
-C11 a_152_368# a_63_368# 0.03fF
-C12 A VPWR 0.05fF
-C13 X a_63_368# 0.33fF
+C0 VPB VPWR 0.04fF
+C1 X VPWR 0.18fF
+C2 A B 0.10fF
+C3 VGND B 0.11fF
+C4 A X 0.02fF
+C5 VGND X 0.16fF
+C6 a_63_368# VPWR 0.29fF
+C7 A a_63_368# 0.28fF
+C8 VGND a_63_368# 0.27fF
+C9 A VPWR 0.05fF
+C10 a_63_368# a_152_368# 0.03fF
+C11 B a_63_368# 0.14fF
+C12 X a_63_368# 0.33fF
+C13 B VPWR 0.01fF
 C14 VGND VNB 0.53fF
 C15 X VNB 0.24fF
 C16 A VNB 0.21fF
@@ -1957,202 +5701,204 @@
 C20 a_63_368# VNB 0.37fF
 .ends
 
-.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
-+ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
-+ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
-+ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
-+ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
-+ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
-+ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ sky130_fd_sc_hs__and2_1_0/a_143_136#
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
++ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
++ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
 Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
 + sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
-+ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
-XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
-+ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
-XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
-+ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
-XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
-+ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
 Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
 + sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
 + sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
 + sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
-C0 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
-C1 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
-C2 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
-C3 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
-C4 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
-C5 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
-C6 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
-C7 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
-C8 vdd nQ0 0.11fF
-C9 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C10 Q1 DFlipFlop_3/latch_diff_1/D 0.79fF
-C11 sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.02fF
-C12 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
-C13 sky130_fd_sc_hs__and2_1_1/a_56_136# DFlipFlop_1/D 0.04fF
-C14 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
-C15 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
-C16 CLK DFlipFlop_2/nQ 0.13fF
-C17 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
-C18 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ2 0.01fF
-C19 Q1 DFlipFlop_2/nQ 0.31fF
-C20 vdd DFlipFlop_1/D 0.25fF
-C21 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
-C22 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
-C23 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
-C24 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
-C25 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
-C26 vdd nQ2 0.04fF
-C27 Q0 nQ0 0.33fF
-C28 sky130_fd_sc_hs__and2_1_0/a_56_136# Q0 0.17fF
-C29 DFlipFlop_0/latch_diff_0/D Q0 0.42fF
-C30 Q1_shift vdd 0.10fF
-C31 vdd DFlipFlop_2/D 0.07fF
-C32 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
-C33 CLK nQ0 0.19fF
-C34 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C35 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
-C36 Q1 nQ0 0.06fF
-C37 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
-C38 vdd nCLK 0.34fF
-C39 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
-C40 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
-C41 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
-C42 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
-C43 DFlipFlop_0/Q nQ2 0.09fF
-C44 Q0 DFlipFlop_1/D 0.07fF
-C45 Q1 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
-C46 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
-C47 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
-C48 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
-C49 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
-C50 Q1_shift DFlipFlop_3/nQ 0.04fF
-C51 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
-C52 CLK DFlipFlop_1/D 0.21fF
-C53 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
-C54 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
-C55 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
-C56 Q0 nQ2 0.23fF
-C57 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
-C58 Q1 DFlipFlop_1/D 0.03fF
-C59 nCLK DFlipFlop_3/nQ 0.02fF
-C60 CLK nQ2 0.17fF
-C61 DFlipFlop_0/Q nCLK 0.11fF
-C62 DFlipFlop_1/latch_diff_1/nD Q0 0.21fF
-C63 DFlipFlop_2/D Q0 0.25fF
-C64 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
-C65 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
-C66 Q1 nQ2 0.07fF
-C67 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ2 0.01fF
-C68 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
-C69 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
-C70 CLK DFlipFlop_2/D 0.14fF
-C71 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
-C72 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
-C73 nCLK Q0 0.20fF
-C74 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C75 Q1 Q1_shift 0.36fF
-C76 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
-C77 Q1 DFlipFlop_2/D 0.10fF
-C78 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
-C79 DFlipFlop_0/D vdd 0.19fF
-C80 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
-C81 Q1 nCLK -0.01fF
-C82 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
-C83 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
-C84 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
-C85 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
-C86 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
-C87 nCLK DFlipFlop_1/latch_diff_1/m1_657_280# 0.28fF
-C88 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C89 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
-C90 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
-C91 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
-C92 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
-C93 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
-C94 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
-C95 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C96 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
-C97 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
-C98 DFlipFlop_0/D Q0 0.39fF
-C99 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
-C100 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
-C101 DFlipFlop_2/nQ nCLK 0.09fF
-C102 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
-C103 DFlipFlop_1/D nQ0 0.12fF
-C104 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
-C105 DFlipFlop_0/D Q1 0.13fF
-C106 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
-C107 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
-C108 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C109 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
-C110 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
-C111 vdd DFlipFlop_3/nQ 0.02fF
-C112 nQ0 nQ2 0.03fF
-C113 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
-C114 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
-C115 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
-C116 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
-C117 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
-C118 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
-C119 vdd Q0 5.33fF
-C120 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
-C121 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
-C122 nCLK nQ0 0.09fF
-C123 CLK vdd 0.41fF
-C124 Q1 vdd 9.49fF
-C125 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
-C126 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
-C127 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
-C128 DFlipFlop_0/Q Q0 0.21fF
-C129 nCLK DFlipFlop_1/D 0.14fF
-C130 CLK DFlipFlop_3/nQ 0.01fF
-C131 DFlipFlop_0/Q CLK 0.08fF
-C132 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
-C133 Q1 DFlipFlop_3/nQ 0.10fF
-C134 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
-C135 nCLK nQ2 0.10fF
-C136 DFlipFlop_0/Q Q1 0.13fF
-C137 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
-C138 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
-C139 vdd CLK_5 0.15fF
-C140 sky130_fd_sc_hs__and2_1_0/a_143_136# Q0 0.03fF
-C141 CLK Q0 0.08fF
-C142 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
-C143 DFlipFlop_2/D nCLK 0.41fF
-C144 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
-C145 Q1 Q0 9.65fF
-C146 DFlipFlop_2/nQ vdd 0.02fF
-C147 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
-C148 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
-C149 Q1 CLK -0.10fF
-C150 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
-C151 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
-C152 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
-C153 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
-C154 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
-C155 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
-C156 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
+C0 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C1 DFlipFlop_1/D nQ0 0.12fF
+C2 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C3 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C4 nCLK DFlipFlop_0/Q 0.11fF
+C5 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C6 vdd CLK_5 0.15fF
+C7 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C8 Q1 nCLK -0.01fF
+C9 DFlipFlop_1/latch_diff_0/D Q0 0.42fF
+C10 DFlipFlop_0/Q CLK 0.08fF
+C11 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C12 Q1 CLK -0.10fF
+C13 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
+C14 vdd Q1 9.49fF
+C15 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C16 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C17 vdd Q1_shift 0.10fF
+C18 DFlipFlop_2/nQ Q1 0.31fF
+C19 nQ2 nQ0 0.03fF
+C20 Q0 DFlipFlop_0/D 0.39fF
+C21 DFlipFlop_3/latch_diff_1/m1_657_280# CLK 0.27fF
+C22 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C23 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
+C24 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
+C25 DFlipFlop_1/latch_diff_0/D Q1 0.18fF
+C26 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C27 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
+C28 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
+C29 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C30 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C31 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C32 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C33 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C34 DFlipFlop_0/D Q1 0.13fF
+C35 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C36 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C37 nCLK nQ0 0.09fF
+C38 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C39 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C40 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C41 DFlipFlop_2/latch_diff_1/D nCLK 0.08fF
+C42 DFlipFlop_3/nQ Q1 0.10fF
+C43 nQ0 CLK 0.19fF
+C44 DFlipFlop_0/latch_diff_1/m1_657_280# nCLK 0.28fF
+C45 vdd nQ0 0.11fF
+C46 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C47 DFlipFlop_2/D Q0 0.25fF
+C48 DFlipFlop_3/nQ Q1_shift 0.04fF
+C49 DFlipFlop_2/latch_diff_1/D CLK 0.14fF
+C50 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
+C51 DFlipFlop_1/D nCLK 0.14fF
+C52 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C53 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C54 DFlipFlop_1/D CLK 0.21fF
+C55 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
+C56 vdd DFlipFlop_1/D 0.25fF
+C57 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.08fF
+C58 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q0 0.42fF
+C59 sky130_fd_sc_hs__and2_1_1/a_56_136# CLK 0.06fF
+C60 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C61 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C63 DFlipFlop_2/D Q1 0.10fF
+C64 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C65 Q0 DFlipFlop_0/Q 0.21fF
+C66 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C67 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C68 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C69 Q0 Q1 9.65fF
+C70 nQ2 nCLK 0.10fF
+C71 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.02fF
+C72 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C73 DFlipFlop_3/latch_diff_1/D CLK 0.08fF
+C74 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C75 nQ2 CLK 0.17fF
+C76 vdd nQ2 0.04fF
+C77 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C78 DFlipFlop_2/latch_diff_0/D nCLK 0.11fF
+C79 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C80 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in Q1 0.21fF
+C81 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C82 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C83 Q1 DFlipFlop_0/Q 0.13fF
+C84 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C85 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
+C86 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
+C87 Q1_shift Q1 0.36fF
+C88 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C89 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C90 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C91 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C92 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C93 Q1 DFlipFlop_0/latch_diff_1/D 0.06fF
+C94 DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.08fF
+C95 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
+C96 vdd nCLK 0.34fF
+C97 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C98 DFlipFlop_2/D DFlipFlop_1/latch_diff_1/m1_657_280# 0.04fF
+C99 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C100 DFlipFlop_2/nQ nCLK 0.09fF
+C101 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
+C102 vdd CLK 0.41fF
+C103 Q0 nQ0 0.33fF
+C104 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
+C105 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
+C106 DFlipFlop_1/latch_diff_0/nD CLK 0.08fF
+C107 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
+C108 DFlipFlop_2/nQ CLK 0.13fF
+C109 DFlipFlop_1/latch_diff_0/D nCLK 0.11fF
+C110 vdd DFlipFlop_2/nQ 0.02fF
+C111 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C112 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK -0.33fF
+C113 Q0 DFlipFlop_1/D 0.07fF
+C114 sky130_fd_sc_hs__or2_1_0/a_63_368# CLK_5 0.06fF
+C115 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C116 sky130_fd_sc_hs__and2_1_0/a_56_136# Q1 0.14fF
+C117 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C118 Q1 nQ0 0.06fF
+C119 DFlipFlop_3/latch_diff_0/m1_657_280# nCLK 0.27fF
+C120 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
+C121 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1 0.10fF
+C122 Q1 DFlipFlop_2/latch_diff_1/m1_657_280# 0.03fF
+C123 vdd DFlipFlop_0/D 0.19fF
+C124 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q0 0.33fF
+C125 DFlipFlop_3/nQ nCLK 0.02fF
+C126 sky130_fd_sc_hs__or2_1_0/a_63_368# Q1_shift -0.27fF
+C127 DFlipFlop_1/D Q1 0.03fF
+C128 nQ2 Q0 0.23fF
+C129 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C130 DFlipFlop_3/nQ CLK 0.01fF
+C131 vdd DFlipFlop_3/nQ 0.02fF
+C132 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C133 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out CLK 0.15fF
+C134 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C135 sky130_fd_sc_hs__and2_1_1/a_143_136# CLK 0.03fF
+C136 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in Q1 0.09fF
+C137 DFlipFlop_3/latch_diff_0/D CLK 0.11fF
+C138 nQ2 DFlipFlop_0/Q 0.09fF
+C139 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C140 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C141 DFlipFlop_2/D nCLK 0.41fF
+C142 nQ2 Q1 0.07fF
+C143 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C144 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C145 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C146 Q0 nCLK 0.20fF
+C147 DFlipFlop_2/D CLK 0.14fF
+C148 vdd DFlipFlop_2/D 0.07fF
+C149 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
+C150 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C151 DFlipFlop_2/latch_diff_0/D Q1 0.42fF
+C152 DFlipFlop_3/latch_diff_1/nD CLK 0.16fF
+C153 Q0 CLK 0.08fF
+C154 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
+C155 vdd Q0 5.33fF
+C156 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nCLK 0.14fF
 C157 CLK_5 vss -0.18fF
 C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
 C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
@@ -2163,32 +5909,32 @@
 C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C171 DFlipFlop_2/nQ vss 0.50fF
-C172 Q1 vss 8.55fF
-C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
-C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
-C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C180 DFlipFlop_2/D vss 5.34fF
-C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C182 nQ0 vss 3.42fF
-C183 Q0 vss 0.53fF
-C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
-C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
-C191 DFlipFlop_1/D vss 3.72fF
-C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 nQ0 vss 3.42fF
+C173 Q0 vss 0.53fF
+C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C183 DFlipFlop_2/nQ vss 0.50fF
+C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C193 nQ2 vss 2.05fF
 C194 DFlipFlop_0/Q vss -0.94fF
 C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
@@ -2197,8 +5943,8 @@
 C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C200 CLK vss 0.20fF
-C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C204 DFlipFlop_0/D vss 4.04fF
 C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -2216,29 +5962,29 @@
 X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n255_n151# a_n159_n151# 0.02fF
-C1 a_129_n151# a_225_n151# 0.02fF
-C2 a_63_n125# a_159_n125# 0.36fF
-C3 a_255_n125# a_159_n125# 0.36fF
-C4 a_255_n125# a_63_n125# 0.13fF
-C5 a_n129_n125# a_159_n125# 0.08fF
-C6 a_63_n125# a_n129_n125# 0.13fF
-C7 a_255_n125# a_n129_n125# 0.06fF
-C8 a_159_n125# a_n33_n125# 0.13fF
-C9 a_63_n125# a_n317_n125# 0.06fF
-C10 a_63_n125# a_n33_n125# 0.36fF
-C11 a_255_n125# a_n33_n125# 0.08fF
-C12 a_n159_n151# a_n63_n151# 0.02fF
-C13 a_n317_n125# a_n129_n125# 0.13fF
-C14 a_n129_n125# a_n33_n125# 0.36fF
-C15 a_n317_n125# a_n33_n125# 0.08fF
-C16 a_129_n151# a_33_n151# 0.02fF
-C17 a_159_n125# a_n225_n125# 0.06fF
-C18 a_63_n125# a_n225_n125# 0.08fF
-C19 a_n129_n125# a_n225_n125# 0.36fF
-C20 a_n317_n125# a_n225_n125# 0.36fF
-C21 a_n225_n125# a_n33_n125# 0.13fF
-C22 a_n63_n151# a_33_n151# 0.02fF
+C0 a_n317_n125# a_63_n125# 0.06fF
+C1 a_159_n125# a_63_n125# 0.36fF
+C2 a_255_n125# a_63_n125# 0.13fF
+C3 a_n33_n125# a_n129_n125# 0.36fF
+C4 a_n129_n125# a_n225_n125# 0.36fF
+C5 a_255_n125# a_159_n125# 0.36fF
+C6 a_n159_n151# a_n255_n151# 0.02fF
+C7 a_n33_n125# a_63_n125# 0.36fF
+C8 a_63_n125# a_n225_n125# 0.08fF
+C9 a_n317_n125# a_n33_n125# 0.08fF
+C10 a_n317_n125# a_n225_n125# 0.36fF
+C11 a_n33_n125# a_159_n125# 0.13fF
+C12 a_159_n125# a_n225_n125# 0.06fF
+C13 a_n33_n125# a_255_n125# 0.08fF
+C14 a_n129_n125# a_63_n125# 0.13fF
+C15 a_225_n151# a_129_n151# 0.02fF
+C16 a_n317_n125# a_n129_n125# 0.13fF
+C17 a_n33_n125# a_n225_n125# 0.13fF
+C18 a_159_n125# a_n129_n125# 0.08fF
+C19 a_33_n151# a_n63_n151# 0.02fF
+C20 a_255_n125# a_n129_n125# 0.06fF
+C21 a_33_n151# a_129_n151# 0.02fF
+C22 a_n63_n151# a_n159_n151# 0.02fF
 C23 a_255_n125# w_n455_n335# 0.14fF
 C24 a_159_n125# w_n455_n335# 0.08fF
 C25 a_63_n125# w_n455_n335# 0.07fF
@@ -2263,36 +6009,36 @@
 X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_159_n125# a_63_n125# 0.36fF
-C1 a_n317_n125# a_n33_n125# 0.08fF
-C2 a_159_n125# a_n129_n125# 0.08fF
-C3 a_63_n125# a_n225_n125# 0.08fF
-C4 a_n225_n125# a_n129_n125# 0.36fF
-C5 a_255_n125# a_n33_n125# 0.08fF
-C6 a_n159_n154# a_n63_n154# 0.02fF
-C7 a_33_n154# a_n63_n154# 0.02fF
-C8 a_33_n154# a_129_n154# 0.02fF
-C9 a_n317_n125# w_n455_n344# 0.11fF
-C10 a_255_n125# w_n455_n344# 0.11fF
-C11 a_129_n154# a_225_n154# 0.02fF
-C12 a_n317_n125# a_n225_n125# 0.36fF
-C13 a_159_n125# a_255_n125# 0.36fF
-C14 a_n33_n125# w_n455_n344# 0.05fF
-C15 a_n159_n154# a_n255_n154# 0.02fF
-C16 a_159_n125# a_n33_n125# 0.13fF
-C17 a_n225_n125# a_n33_n125# 0.13fF
+C0 a_n159_n154# a_n255_n154# 0.02fF
+C1 w_n455_n344# a_63_n125# 0.04fF
+C2 a_n129_n125# a_n33_n125# 0.36fF
+C3 a_n317_n125# w_n455_n344# 0.11fF
+C4 a_n317_n125# a_63_n125# 0.06fF
+C5 a_255_n125# w_n455_n344# 0.11fF
+C6 a_255_n125# a_63_n125# 0.13fF
+C7 a_n225_n125# a_n33_n125# 0.13fF
+C8 a_159_n125# a_n33_n125# 0.13fF
+C9 a_n129_n125# w_n455_n344# 0.04fF
+C10 a_n129_n125# a_63_n125# 0.13fF
+C11 a_33_n154# a_129_n154# 0.02fF
+C12 a_225_n154# a_129_n154# 0.02fF
+C13 a_n317_n125# a_n129_n125# 0.13fF
+C14 a_n129_n125# a_255_n125# 0.06fF
+C15 a_n159_n154# a_n63_n154# 0.02fF
+C16 a_n225_n125# w_n455_n344# 0.06fF
+C17 a_n225_n125# a_63_n125# 0.08fF
 C18 a_159_n125# w_n455_n344# 0.06fF
-C19 a_n225_n125# w_n455_n344# 0.06fF
-C20 a_63_n125# a_n129_n125# 0.13fF
-C21 a_159_n125# a_n225_n125# 0.06fF
-C22 a_63_n125# a_n317_n125# 0.06fF
-C23 a_n317_n125# a_n129_n125# 0.13fF
-C24 a_255_n125# a_63_n125# 0.13fF
-C25 a_255_n125# a_n129_n125# 0.06fF
+C19 a_159_n125# a_63_n125# 0.36fF
+C20 a_n317_n125# a_n225_n125# 0.36fF
+C21 a_159_n125# a_255_n125# 0.36fF
+C22 a_n63_n154# a_33_n154# 0.02fF
+C23 a_n129_n125# a_n225_n125# 0.36fF
+C24 a_159_n125# a_n129_n125# 0.08fF
+C25 w_n455_n344# a_n33_n125# 0.05fF
 C26 a_63_n125# a_n33_n125# 0.36fF
-C27 a_n33_n125# a_n129_n125# 0.36fF
-C28 a_63_n125# w_n455_n344# 0.04fF
-C29 a_n129_n125# w_n455_n344# 0.04fF
+C27 a_n317_n125# a_n33_n125# 0.08fF
+C28 a_255_n125# a_n33_n125# 0.08fF
+C29 a_159_n125# a_n225_n125# 0.06fF
 C30 a_255_n125# VSUBS 0.03fF
 C31 a_159_n125# VSUBS 0.03fF
 C32 a_63_n125# VSUBS 0.03fF
@@ -2316,33 +6062,33 @@
 + in sky130_fd_pr__pfet_01v8_XJXT7S
 C0 out vdd 0.29fF
 C1 out in 0.85fF
-C2 vdd in 0.04fF
+C2 in vdd 0.04fF
 C3 vdd vss 5.90fF
 C4 out vss 1.30fF
 C5 in vss 1.82fF
 .ends
 
-.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
 + QB nDown Up nUp
 Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
 Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
 Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
 Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
-Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
 Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
-C0 vdd nDown 0.80fF
-C1 inverter_cp_x1_2/in vdd 0.42fF
-C2 QA vdd 0.02fF
-C3 inverter_cp_x1_0/out Down 0.12fF
-C4 nDown Down 0.23fF
-C5 vdd Down 0.09fF
-C6 QB vdd 0.02fF
-C7 nUp Up 0.20fF
-C8 inverter_cp_x1_0/out nDown 0.11fF
-C9 inverter_cp_x1_0/out vdd 0.25fF
-C10 nUp vdd 0.14fF
-C11 vdd Up 0.60fF
-C12 inverter_cp_x1_2/in Up 0.12fF
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 inverter_cp_x1_2/in vdd 0.42fF
+C1 Down vdd 0.09fF
+C2 vdd nUp 0.14fF
+C3 Down inverter_cp_x1_0/out 0.12fF
+C4 inverter_cp_x1_2/in Up 0.12fF
+C5 nDown Down 0.23fF
+C6 vdd inverter_cp_x1_0/out 0.25fF
+C7 nDown vdd 0.80fF
+C8 nUp Up 0.20fF
+C9 vdd Up 0.60fF
+C10 vdd QB 0.02fF
+C11 nDown inverter_cp_x1_0/out 0.11fF
+C12 QA vdd 0.02fF
 C13 inverter_cp_x1_2/in vss 2.01fF
 C14 QA vss 1.09fF
 C15 inverter_cp_x1_0/out vss 2.00fF
@@ -2360,22 +6106,22 @@
 X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_n33_n90# a_n221_n90# 0.09fF
+C0 a_n33_n90# a_63_n90# 0.26fF
 C1 a_159_n90# a_n129_n90# 0.06fF
-C2 w_n359_n309# a_n129_n90# 0.06fF
-C3 a_n129_n90# a_n221_n90# 0.26fF
-C4 a_159_n90# a_63_n90# 0.26fF
+C2 a_n221_n90# w_n359_n309# 0.09fF
+C3 a_n33_n90# a_159_n90# 0.09fF
+C4 a_n221_n90# a_63_n90# 0.06fF
 C5 w_n359_n309# a_63_n90# 0.06fF
-C6 a_n33_n90# a_n129_n90# 0.26fF
-C7 a_n221_n90# a_63_n90# 0.06fF
-C8 a_n33_n90# a_63_n90# 0.26fF
-C9 a_n63_n116# a_n159_n207# 0.12fF
-C10 w_n359_n309# a_159_n90# 0.09fF
-C11 a_159_n90# a_n221_n90# 0.04fF
-C12 w_n359_n309# a_n221_n90# 0.09fF
-C13 a_n33_n90# a_159_n90# 0.09fF
-C14 a_n129_n90# a_63_n90# 0.09fF
-C15 w_n359_n309# a_n33_n90# 0.05fF
+C6 a_n221_n90# a_159_n90# 0.04fF
+C7 a_159_n90# w_n359_n309# 0.09fF
+C8 a_n33_n90# a_n129_n90# 0.26fF
+C9 a_159_n90# a_63_n90# 0.26fF
+C10 a_n221_n90# a_n129_n90# 0.26fF
+C11 a_n159_n207# a_n63_n116# 0.12fF
+C12 a_n129_n90# w_n359_n309# 0.06fF
+C13 a_n221_n90# a_n33_n90# 0.09fF
+C14 a_n33_n90# w_n359_n309# 0.05fF
+C15 a_n129_n90# a_63_n90# 0.09fF
 C16 a_159_n90# VSUBS 0.03fF
 C17 a_63_n90# VSUBS 0.03fF
 C18 a_n33_n90# VSUBS 0.03fF
@@ -2390,10 +6136,10 @@
 + a_n125_n45# a_63_n45#
 X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n129_71# a_33_n71# 0.04fF
-C1 a_n33_n45# a_n125_n45# 0.13fF
-C2 a_63_n45# a_n33_n45# 0.13fF
-C3 a_63_n45# a_n125_n45# 0.05fF
+C0 a_n33_n45# a_n125_n45# 0.13fF
+C1 a_33_n71# a_n129_71# 0.04fF
+C2 a_n33_n45# a_63_n45# 0.13fF
+C3 a_n125_n45# a_63_n45# 0.05fF
 C4 a_63_n45# w_n263_n255# 0.04fF
 C5 a_n33_n45# w_n263_n255# 0.04fF
 C6 a_n125_n45# w_n263_n255# 0.04fF
@@ -2406,14 +6152,14 @@
 Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
 + vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
 Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
-C0 B A 0.24fF
-C1 out B 0.40fF
-C2 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
-C3 vdd A 0.09fF
-C4 out vdd 0.11fF
-C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
-C6 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
-C7 out A 0.06fF
+C0 out vdd 0.11fF
+C1 A out 0.06fF
+C2 A vdd 0.09fF
+C3 B out 0.40fF
+C4 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
+C5 A B 0.24fF
+C6 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C7 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
 C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C9 out vss 0.45fF
 C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2431,37 +6177,37 @@
 + vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
 Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
 + vss vdd nor_pfd_3/A Reset nor_pfd
-C0 vdd nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
-C1 Q nor_pfd_2/A 1.38fF
-C2 nor_pfd_3/A Q 0.98fF
-C3 nor_pfd_2/B Q 2.22fF
-C4 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C5 nor_pfd_3/A nor_pfd_2/A 0.38fF
-C6 Q Reset 0.14fF
-C7 nor_pfd_2/B nor_pfd_2/A 0.05fF
-C8 CLK Q 0.04fF
+C0 Reset Q 0.14fF
+C1 Reset nor_pfd_3/A 0.12fF
+C2 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C3 CLK Q 0.04fF
+C4 nor_pfd_2/B Q 2.22fF
+C5 vdd nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
+C6 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C7 nor_pfd_2/B vdd 0.02fF
+C8 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
 C9 nor_pfd_2/B nor_pfd_3/A 0.58fF
-C10 nor_pfd_3/A Reset 0.12fF
-C11 nor_pfd_2/B Reset 0.43fF
-C12 Q vdd 0.08fF
-C13 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C14 nor_pfd_2/A vdd -0.01fF
-C15 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C16 nor_pfd_3/A vdd 0.09fF
-C17 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C18 nor_pfd_2/B vdd 0.02fF
-C19 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C10 vdd Q 0.08fF
+C11 nor_pfd_3/A Q 0.98fF
+C12 nor_pfd_3/A vdd 0.09fF
+C13 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C14 nor_pfd_2/B nor_pfd_2/A 0.05fF
+C15 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C16 nor_pfd_2/A Q 1.38fF
+C17 nor_pfd_2/A vdd -0.01fF
+C18 nor_pfd_3/A nor_pfd_2/A 0.38fF
+C19 Reset nor_pfd_2/B 0.43fF
 C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C21 nor_pfd_2/B vss 1.42fF
 C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C23 nor_pfd_3/A vss 3.16fF
-C24 Reset vss 1.48fF
-C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C27 nor_pfd_2/A vss 2.56fF
-C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C29 Q vss 2.77fF
-C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 Q vss 2.77fF
+C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 nor_pfd_3/A vss 3.16fF
 C31 vdd vss 16.42fF
 C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2474,17 +6220,17 @@
 X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_159_n45# a_n129_n45# 0.03fF
-C1 a_159_n45# a_n221_n45# 0.02fF
-C2 a_159_n45# a_n33_n45# 0.05fF
-C3 a_63_n45# a_n129_n45# 0.05fF
-C4 a_63_n45# a_n221_n45# 0.03fF
-C5 a_63_n45# a_n33_n45# 0.13fF
-C6 a_n129_n45# a_n221_n45# 0.13fF
-C7 a_159_n45# a_63_n45# 0.13fF
-C8 a_n129_n45# a_n33_n45# 0.13fF
-C9 a_n33_n45# a_n221_n45# 0.05fF
-C10 a_n63_n71# a_n159_n173# 0.10fF
+C0 a_n129_n45# a_n221_n45# 0.13fF
+C1 a_n159_n173# a_n63_n71# 0.10fF
+C2 a_n129_n45# a_159_n45# 0.03fF
+C3 a_n33_n45# a_n221_n45# 0.05fF
+C4 a_n33_n45# a_159_n45# 0.05fF
+C5 a_63_n45# a_n129_n45# 0.05fF
+C6 a_159_n45# a_n221_n45# 0.02fF
+C7 a_63_n45# a_n33_n45# 0.13fF
+C8 a_63_n45# a_n221_n45# 0.03fF
+C9 a_63_n45# a_159_n45# 0.13fF
+C10 a_n129_n45# a_n33_n45# 0.13fF
 C11 a_159_n45# w_n359_n255# 0.04fF
 C12 a_63_n45# w_n359_n255# 0.05fF
 C13 a_n33_n45# w_n359_n255# 0.05fF
@@ -2499,9 +6245,9 @@
 X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 C0 a_n33_n90# a_63_n90# 0.26fF
-C1 a_n125_n90# a_63_n90# 0.09fF
-C2 a_n125_n90# a_n33_n90# 0.26fF
-C3 a_33_n187# a_n99_n187# 0.04fF
+C1 a_n33_n90# a_n125_n90# 0.26fF
+C2 a_n99_n187# a_33_n187# 0.04fF
+C3 a_n125_n90# a_63_n90# 0.09fF
 C4 a_63_n90# VSUBS 0.03fF
 C5 a_n33_n90# VSUBS 0.03fF
 C6 a_n125_n90# VSUBS 0.03fF
@@ -2520,9 +6266,9 @@
 
 .subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
 X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_15_n90# w_n211_n309# 0.09fF
-C1 a_15_n90# a_n73_n90# 0.31fF
-C2 w_n211_n309# a_n73_n90# 0.04fF
+C0 w_n211_n309# a_n73_n90# 0.04fF
+C1 w_n211_n309# a_15_n90# 0.09fF
+C2 a_n73_n90# a_15_n90# 0.31fF
 C3 a_15_n90# VSUBS 0.03fF
 C4 a_n73_n90# VSUBS 0.03fF
 C5 a_n51_n187# VSUBS 0.12fF
@@ -2535,16 +6281,16 @@
 Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
 Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
 Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
-C0 out a_656_410# 0.20fF
-C1 B a_656_410# 0.30fF
-C2 a_656_410# A 0.04fF
-C3 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# B 0.02fF
-C4 out vdd 0.10fF
-C5 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
-C6 vdd A 0.05fF
-C7 vdd a_656_410# 0.20fF
-C8 B A 0.33fF
-C9 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C0 vdd A 0.05fF
+C1 a_656_410# A 0.04fF
+C2 B A 0.33fF
+C3 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
+C4 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
+C5 a_656_410# vdd 0.20fF
+C6 a_656_410# B 0.30fF
+C7 out vdd 0.10fF
+C8 out a_656_410# 0.20fF
+C9 a_656_410# sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.07fF
 C10 vdd vss 4.85fF
 C11 out vss 0.47fF
 C12 a_656_410# vss 1.00fF
@@ -2560,43 +6306,43 @@
 Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
 + Reset dff_pfd
 Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
-C0 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
-C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
-C2 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
-C3 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
-C4 vdd Down 0.08fF
-C5 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
-C6 Up vdd 1.62fF
-C7 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
-C8 Up Down 0.06fF
-C9 Reset vdd 0.02fF
+C0 dff_pfd_0/nor_pfd_2/B vdd 0.11fF
+C1 vdd Reset 0.02fF
+C2 dff_pfd_0/nor_pfd_2/A vdd 0.13fF
+C3 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C4 dff_pfd_1/nor_pfd_2/A vdd 0.13fF
+C5 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
+C6 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
+C7 Up vdd 1.62fF
+C8 Down vdd 0.08fF
+C9 Down Up 0.06fF
 C10 and_pfd_0/a_656_410# vss 0.99fF
 C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
 C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
 C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
-C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C21 Down vss 3.74fF
-C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C20 Down vss 3.74fF
+C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C25 B vss 1.07fF
 C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C29 dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C30 Reset vss 3.85fF
-C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C33 dff_pfd_0/nor_pfd_2/A vss 2.56fF
-C34 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C35 Up vss 3.18fF
-C36 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C29 Reset vss 3.85fF
+C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C34 Up vss 3.18fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C37 vdd vss 44.73fF
 C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2612,8 +6358,8 @@
 Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
 + iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
 Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
-+ n_out_div_2 div_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
 Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
 + vss vdd buffer_salida
 Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
@@ -2621,161 +6367,163 @@
 + ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
 + vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
-+ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
 + div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
 + div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
 + div_by_5
-Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
 + Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 vdd QA -0.04fF
-C1 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
-C2 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
-C3 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
-C4 out_by_2 div_5_Q0 0.09fF
-C5 vdd nUp 0.05fF
-C6 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
-C7 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
-C8 vdd out_to_div 0.21fF
-C9 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
-C10 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
-C11 Up nUp 2.72fF
-C12 div_5_nQ0 n_out_by_2 0.10fF
-C13 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
-C14 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
-C15 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
-C16 nDown biasp 0.26fF
-C17 vdd out_to_buffer 0.07fF
-C18 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
-C19 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
-C20 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
-C21 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
-C22 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
-C23 Up pswitch 1.98fF
-C24 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
-C25 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
-C26 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
-C27 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
-C28 n_out_by_2 div_5_Q0 -0.12fF
-C29 vco_vctrl div_5_Q0 0.48fF
-C30 vco_vctrl nUp 0.02fF
-C31 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C32 nswitch Down 0.54fF
-C33 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
-C34 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
-C35 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
-C36 vdd out_by_2 0.97fF
-C37 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
-C38 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
-C39 biasp nUp -0.17fF
-C40 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
-C41 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
-C42 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C43 out_by_2 div_5_Q1 0.42fF
-C44 vdd Up 0.28fF
-C45 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
-C46 nDown nUp -0.09fF
-C47 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
-C48 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
-C49 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C50 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
-C51 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
-C52 vdd vco_D0 0.03fF
-C53 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
-C54 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C55 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C56 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
-C57 iref_cp Down 0.09fF
-C58 Down biasp 1.24fF
-C59 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
-C60 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
-C61 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
-C62 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C63 nDown pswitch 0.53fF
-C64 nDown Down 2.55fF
-C65 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C66 out_by_2 div_5_nQ2 0.16fF
-C67 vco_vctrl out_by_2 0.53fF
-C68 vdd n_out_by_2 1.03fF
-C69 vdd vco_vctrl -1.02fF
-C70 vdd buffer_salida_0/a_678_n100# 0.24fF
-C71 out_div_by_5 div_5_Q1_shift 0.05fF
-C72 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
-C73 n_out_by_2 div_5_Q1 1.04fF
-C74 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
-C75 vco_vctrl div_5_Q1 0.14fF
-C76 vdd iref_cp 0.15fF
-C77 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
-C78 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
-C79 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
-C80 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
-C81 vco_vctrl nswitch -0.06fF
-C82 Up biasp 0.26fF
-C83 vdd nDown 0.22fF
-C84 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
-C85 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
-C86 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
-C87 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
-C88 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C89 div_5_nQ0 out_by_2 0.32fF
-C90 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
-C91 pswitch nUp 0.85fF
-C92 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
-C93 out_to_div out_to_buffer 0.13fF
-C94 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
-C95 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
-C96 nDown nswitch 0.76fF
-C97 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
-C98 vdd out_div_by_5 0.28fF
-C99 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
-C100 n_out_by_2 div_5_nQ2 0.10fF
-C101 vco_vctrl n_out_by_2 0.52fF
-C102 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
-C103 vdd lf_vc 0.02fF
-C104 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
-C105 out_div_by_5 div_5_Q1 0.01fF
-C106 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
-C107 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C0 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C1 div_5_nQ2 out_by_2 0.16fF
+C2 Up biasp 0.26fF
+C3 QA vdd -0.04fF
+C4 Down iref_cp 0.09fF
+C5 div_5_Q1 vco_vctrl 0.14fF
+C6 vco_vctrl div_5_Q0 0.48fF
+C7 div_5_Q1 out_div_by_5 0.01fF
+C8 vco_vctrl nswitch -0.06fF
+C9 nUp vdd 0.05fF
+C10 nDown vdd 0.22fF
+C11 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C12 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C13 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C14 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C15 vco_D0 vdd 0.03fF
+C16 pswitch Up 1.98fF
+C17 nDown nUp -0.09fF
+C18 n_out_by_2 vco_vctrl 0.52fF
+C19 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
+C20 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C21 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C22 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
+C23 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
+C24 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
+C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C26 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C27 out_to_div out_to_buffer 0.13fF
+C28 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C29 Up vdd 0.28fF
+C30 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C31 nDown Down 2.55fF
+C32 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C33 out_by_2 vco_vctrl 0.53fF
+C34 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C35 Up nUp 2.72fF
+C36 nswitch nDown 0.76fF
+C37 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C38 vdd lf_vc 0.02fF
+C39 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C40 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C41 n_out_by_2 vdd 1.03fF
+C42 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C43 out_div_by_5 div_5_Q1_shift 0.05fF
+C44 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C45 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C46 buffer_salida_0/a_678_n100# vdd 0.24fF
+C47 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C48 nswitch Down 0.54fF
+C49 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C50 out_to_div vdd 0.21fF
+C51 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C52 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C55 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C56 out_by_2 vdd 0.97fF
+C57 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C58 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C60 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
+C61 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C62 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
+C63 n_out_by_2 div_5_nQ0 0.10fF
+C64 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C65 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C66 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
+C67 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C68 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C69 div_5_Q1 n_out_by_2 1.04fF
+C70 n_out_by_2 div_5_Q0 -0.12fF
+C71 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C72 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C73 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C74 vdd out_to_buffer 0.07fF
+C75 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C76 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C77 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C78 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C79 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C80 vco_vctrl vdd -1.02fF
+C81 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C82 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C83 out_div_by_5 vdd 0.28fF
+C84 nUp biasp -0.17fF
+C85 nDown biasp 0.26fF
+C86 vdd iref_cp 0.15fF
+C87 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C88 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C89 out_by_2 div_5_nQ0 0.32fF
+C90 vco_vctrl nUp 0.02fF
+C91 n_out_by_2 div_5_nQ2 0.10fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C93 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C94 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
+C95 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C96 div_5_Q1 out_by_2 0.42fF
+C97 out_by_2 div_5_Q0 0.09fF
+C98 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C99 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C100 pswitch nUp 0.85fF
+C101 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C102 pswitch nDown 0.53fF
+C103 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C104 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C105 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C106 Down biasp 1.24fF
+C107 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
 C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
 C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
 C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
 C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C119 QB vss 4.46fF
-C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C123 out_div_by_5 vss -0.40fF
 C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C128 pfd_reset vss 2.17fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C133 QA vss 4.31fF
-C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C137 in_ref vss 1.19fF
@@ -2794,32 +6542,32 @@
 C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C158 div_5_Q1 vss 4.28fF
-C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C168 div_5_nQ0 vss 0.59fF
-C169 div_5_Q0 vss 0.01fF
-C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C179 div_5_nQ2 vss 1.24fF
 C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
 C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
@@ -2828,17 +6576,17 @@
 C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C186 out_by_2 vss -4.51fF
-C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
 C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
 C192 vdd vss 366.82fF
 C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
 C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
-C195 out_to_buffer vss 1.57fF
+C195 out_first_buffer vss 2.88fF
 C196 out_to_div vss 4.46fF
-C197 out_first_buffer vss 2.88fF
+C197 out_to_buffer vss 1.57fF
 C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
 C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -2853,22 +6601,22 @@
 C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
 C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
 C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 out_to_pad vss 7.50fF
-C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
 C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 n_out_buffer_div_2 vss 1.63fF
-C216 out_buffer_div_2 vss 1.60fF
-C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
 C221 out_div_2 vss -1.30fF
 C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
 C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C229 n_out_div_2 vss 1.95fF
 C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -2883,7 +6631,7 @@
 
 .subckt sky130_fd_pr__cap_mim_m3_2_2Y8F6P VSUBS c2_n3251_n3000# m4_n3351_n3100#
 X0 c2_n3251_n3000# m4_n3351_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u
-C0 c2_n3251_n3000# m4_n3351_n3100# 72.82fF
+C0 m4_n3351_n3100# c2_n3251_n3000# 72.82fF
 C1 m4_n3351_n3100# VSUBS 14.58fF
 .ends
 
@@ -2939,16 +6687,16 @@
 X47 w_n2018_n202# a_n2017_n61# a_n1731_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
 X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
 X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
-C0 a_n1879_n1219# a_n2017_n61# 0.16fF
-C1 a_n2017_n1317# a_n2017_n61# 2.88fF
-C2 a_n1879_n1219# a_n1731_n1219# 19.29fF
-C3 a_n2017_n1317# a_n1731_n1219# 4.73fF
-C4 a_n1879_n1219# w_n2018_n202# 0.25fF
-C5 a_n2017_n1317# w_n2018_n202# 0.16fF
-C6 a_n1731_n1219# a_n2017_n61# 5.23fF
-C7 a_n2017_n61# w_n2018_n202# 1.37fF
-C8 a_n2017_n1317# a_n1879_n1219# 2.66fF
-C9 a_n1731_n1219# w_n2018_n202# 19.90fF
+C0 a_n2017_n61# w_n2018_n202# 1.37fF
+C1 a_n1879_n1219# a_n1731_n1219# 19.29fF
+C2 a_n2017_n1317# a_n1731_n1219# 4.73fF
+C3 a_n2017_n1317# a_n1879_n1219# 2.66fF
+C4 a_n2017_n61# a_n1731_n1219# 5.23fF
+C5 a_n2017_n61# a_n1879_n1219# 0.16fF
+C6 a_n2017_n61# a_n2017_n1317# 2.88fF
+C7 w_n2018_n202# a_n1731_n1219# 19.90fF
+C8 w_n2018_n202# a_n1879_n1219# 0.25fF
+C9 w_n2018_n202# a_n2017_n1317# 0.16fF
 C10 a_n1879_n1219# VSUBS 1.53fF
 C11 a_n2017_n1317# VSUBS 5.03fF
 C12 a_n1731_n1219# VSUBS 2.60fF
@@ -2956,7 +6704,7 @@
 C14 w_n2018_n202# VSUBS 37.43fF
 .ends
 
-.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
 + vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
@@ -2979,57 +6727,57 @@
 + iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
 + iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
-C0 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
-C1 iref_1 iref_0 0.05fF
-C2 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
-C3 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C4 iref_6 iref_5 0.05fF
-C5 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# iref_7 0.24fF
-C6 iref_3 iref_2 0.05fF
-C7 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C8 iref_6 iref_7 0.05fF
-C9 iref_1 iref -0.02fF
-C10 iref_8 iref_9 0.05fF
-C11 iref_2 iref -0.01fF
-C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
-C13 iref_9 iref -0.01fF
-C14 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
-C15 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# -0.39fF
-C16 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C17 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
-C18 iref_3 iref_4 0.05fF
-C19 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
-C20 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
-C21 vdd m1_20168_984# 0.25fF
-C22 iref iref_5 0.05fF
-C23 vdd iref -0.07fF
-C24 iref_8 iref_7 0.05fF
-C25 iref_4 iref 0.30fF
-C26 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
-C27 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
-C28 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
-C29 iref_3 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
-C30 iref_1 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
-C31 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
-C32 iref_8 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
-C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref 0.02fF
-C34 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
-C35 iref_8 iref -0.03fF
-C36 iref_1 iref_2 0.05fF
-C37 m1_20168_984# iref 0.07fF
-C38 iref_4 VSUBS 1.17fF
-C39 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
-C40 iref_3 VSUBS 0.64fF
-C41 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
-C42 iref_2 VSUBS -1.26fF
-C43 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
-C44 iref_1 VSUBS -0.80fF
-C45 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
-C46 iref_0 VSUBS 1.88fF
-C47 iref VSUBS 32.42fF
-C48 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
-C49 m1_20168_984# VSUBS 56.92fF
-C50 vdd VSUBS 416.01fF
+C0 iref_2 iref_3 0.05fF
+C1 iref_5 iref_6 0.05fF
+C2 iref_9 iref -0.01fF
+C3 iref_7 iref_6 0.05fF
+C4 vdd iref -0.07fF
+C5 iref_5 iref 0.05fF
+C6 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
+C8 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vdd 0.24fF
+C9 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
+C10 iref_2 iref_1 0.05fF
+C11 iref_9 iref_8 0.05fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
+C13 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C14 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# 0.67fF
+C15 iref_1 iref_0 0.05fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
+C17 iref_4 iref 0.30fF
+C18 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C19 iref_8 iref_7 0.05fF
+C20 vdd m1_20168_984# 0.25fF
+C21 iref_3 iref_4 0.05fF
+C22 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C23 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
+C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# m1_20168_984# 0.54fF
+C25 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
+C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# iref_7 0.24fF
+C27 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C28 iref_8 iref -0.03fF
+C29 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref 0.02fF
+C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C31 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C32 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
+C34 iref_1 iref -0.02fF
+C35 m1_20168_984# iref 0.07fF
+C36 iref_2 iref -0.01fF
+C37 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
+C38 iref VSUBS 32.42fF
+C39 iref_4 VSUBS 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C41 iref_3 VSUBS 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C43 iref_2 VSUBS -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C45 iref_1 VSUBS -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C47 m1_20168_984# VSUBS 56.92fF
+C48 vdd VSUBS 416.01fF
+C49 iref_0 VSUBS 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
 C51 iref_9 VSUBS -1.13fF
 C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
 C53 iref_7 VSUBS -1.38fF
@@ -3057,13 +6805,13 @@
 X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C1 c1_n4209_n4150# m3_n4309_50# 38.10fF
-C2 m3_10_n4250# m3_n4309_n4250# 1.75fF
-C3 c1_110_n4150# m3_10_n4250# 81.11fF
-C4 m3_n4309_50# m3_10_n4250# 1.75fF
-C5 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
-C6 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C0 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
+C1 m3_n4309_50# m3_10_n4250# 1.75fF
+C2 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C3 m3_n4309_50# c1_n4209_n4150# 38.10fF
+C4 c1_110_n4150# m3_10_n4250# 81.11fF
+C5 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C6 m3_n4309_n4250# m3_10_n4250# 1.75fF
 C7 c1_110_n4150# VSUBS 0.12fF
 C8 c1_n4209_n4150# VSUBS 0.12fF
 C9 m3_n4309_n4250# VSUBS 8.68fF
@@ -3080,7 +6828,7 @@
 
 .subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
 X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_n88_n300# a_n118_n388# 0.11fF
+C0 a_n118_n388# a_n88_n300# 0.11fF
 C1 a_n88_n300# a_30_n300# 0.61fF
 C2 a_30_n300# w_n226_n510# 0.40fF
 C3 a_n88_n300# w_n226_n510# 0.40fF
@@ -3095,8 +6843,8 @@
 Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
 Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
 Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 in cap3_loop_filter_0/in 0.79fF
-C1 vc_pex in 0.18fF
+C0 in vc_pex 0.18fF
+C1 cap3_loop_filter_0/in in 0.79fF
 C2 in D0_cap 0.07fF
 C3 vc_pex vss -38.13fF
 C4 res_loop_filter_2/out vss 8.49fF
@@ -3113,8 +6861,8 @@
 + iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
 Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
 Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
-+ n_out_div_2 div_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
 Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
 + vss vdd buffer_salida
 Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
@@ -3122,161 +6870,163 @@
 + ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
 + vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
-+ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
 + div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
 + div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
 + div_by_5
-Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
 + Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 vdd out_div_by_5 0.28fF
-C1 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
-C2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
-C3 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
-C4 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
-C5 div_5_Q1 vco_vctrl 0.14fF
-C6 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
-C7 nUp biasp -0.17fF
-C8 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
-C9 vdd nUp 0.05fF
-C10 nDown biasp 0.26fF
-C11 pswitch nUp 0.85fF
-C12 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
-C13 nDown vdd 0.22fF
-C14 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
-C15 pswitch nDown 0.53fF
-C16 n_out_by_2 div_5_nQ2 0.10fF
-C17 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
-C18 nswitch Down 0.54fF
-C19 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
-C20 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
-C21 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
-C22 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
-C23 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
-C24 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C25 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C26 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
-C27 Up biasp 0.26fF
-C28 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
-C29 vdd out_by_2 0.97fF
-C30 Up vdd 0.28fF
-C31 nDown nUp -0.09fF
-C32 pswitch Up 1.98fF
-C33 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
-C34 out_to_buffer out_to_div 0.13fF
-C35 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
-C36 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
-C37 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
-C38 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C39 div_5_nQ0 out_by_2 0.32fF
-C40 n_out_by_2 vdd 1.03fF
-C41 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
-C42 Up nUp 2.72fF
-C43 n_out_by_2 div_5_nQ0 0.10fF
-C44 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
-C45 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
-C46 vdd vco_vctrl -1.02fF
-C47 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
-C48 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
-C49 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
-C50 out_by_2 div_5_Q0 0.09fF
-C51 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
-C52 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C53 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C54 lf_vc vdd 0.02fF
-C55 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
-C56 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
-C57 Down biasp 1.24fF
-C58 nUp vco_vctrl 0.02fF
-C59 vdd out_to_div 0.21fF
-C60 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
-C61 n_out_by_2 div_5_Q0 -0.12fF
-C62 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
-C63 Down iref_cp 0.09fF
-C64 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
-C65 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
-C66 out_to_buffer vdd 0.07fF
-C67 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
-C68 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
-C69 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C70 nDown nswitch 0.76fF
-C71 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
-C72 div_5_Q1 out_div_by_5 0.01fF
-C73 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
-C74 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C75 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
-C76 out_by_2 vco_vctrl 0.53fF
-C77 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
-C78 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
-C79 vco_vctrl div_5_Q0 0.48fF
-C80 nDown Down 2.55fF
-C81 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
-C82 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
-C83 n_out_by_2 vco_vctrl 0.52fF
-C84 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
-C85 div_5_Q1_shift out_div_by_5 0.05fF
-C86 QA vdd -0.04fF
-C87 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
-C88 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
-C89 out_by_2 div_5_Q1 0.42fF
-C90 vdd buffer_salida_0/a_678_n100# 0.24fF
-C91 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
-C92 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
-C93 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
-C94 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
-C95 D0_vco vdd 0.03fF
-C96 n_out_by_2 div_5_Q1 1.04fF
-C97 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
-C98 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C0 nUp biasp -0.17fF
+C1 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C2 Down biasp 1.24fF
+C3 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C4 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C5 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C6 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C7 nDown nswitch 0.76fF
+C8 nUp pswitch 0.85fF
+C9 vdd buffer_salida_0/a_678_n100# 0.24fF
+C10 div_5_Q1 out_by_2 0.42fF
+C11 nswitch vco_vctrl -0.06fF
+C12 out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out 0.09fF
+C13 vdd out_to_buffer 0.07fF
+C14 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C15 div_5_Q1 out_div_by_5 0.01fF
+C16 nDown nUp -0.09fF
+C17 vdd out_by_2 0.97fF
+C18 nDown Down 2.55fF
+C19 out_by_2 div_5_Q0 0.09fF
+C20 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C21 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C22 vdd out_div_by_5 0.28fF
+C23 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C24 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
+C25 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
+C26 vco_vctrl nUp 0.02fF
+C27 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C28 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
+C29 vdd nDown 0.22fF
+C30 div_5_Q1 vco_vctrl 0.14fF
+C31 div_5_nQ2 out_by_2 0.16fF
+C32 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C33 div_5_Q1_shift out_div_by_5 0.05fF
+C34 Up nUp 2.72fF
+C35 div_5_Q1 n_out_by_2 1.04fF
+C36 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
+C37 vdd vco_vctrl -1.02fF
+C38 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C39 nDown biasp 0.26fF
+C40 Down iref_cp 0.09fF
+C41 div_5_Q0 vco_vctrl 0.48fF
+C42 vdd n_out_by_2 1.03fF
+C43 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C44 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.17fF
+C45 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C46 div_5_Q0 n_out_by_2 -0.12fF
+C47 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C48 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C49 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C50 vdd Up 0.28fF
+C51 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C52 nDown pswitch 0.53fF
+C53 vdd iref_cp 0.15fF
+C54 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C55 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C56 out_by_2 vco_vctrl 0.53fF
+C57 out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.28fF
+C58 Up biasp 0.26fF
+C59 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C60 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
+C61 div_5_nQ2 n_out_by_2 0.10fF
+C62 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C63 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C64 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C65 vdd out_to_div 0.21fF
+C66 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C67 Up pswitch 1.98fF
+C68 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C69 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C70 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C71 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C72 out_to_div out_to_buffer 0.13fF
+C73 n_out_by_2 vco_vctrl 0.52fF
+C74 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C75 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C76 div_5_nQ0 out_by_2 0.32fF
+C77 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C78 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C79 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C80 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C81 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C82 Down nswitch 0.54fF
+C83 vdd QA -0.04fF
+C84 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C85 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
+C86 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C87 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C88 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C89 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C90 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C91 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C92 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
+C93 vdd D0_vco 0.03fF
+C94 vdd lf_vc 0.02fF
+C95 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
+C96 div_5_nQ0 n_out_by_2 0.10fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C98 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
 C99 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
-C100 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
-C101 vdd iref_cp 0.15fF
-C102 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C103 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
-C104 nswitch vco_vctrl -0.06fF
-C105 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
-C106 div_5_nQ2 out_by_2 0.16fF
-C107 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.09fF
+C100 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
+C101 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C102 vdd nUp 0.05fF
+C103 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
+C104 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C105 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C106 div_by_5_0/DFlipFlop_2/D n_out_by_2 0.19fF
+C107 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
 C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
 C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
 C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
 C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C119 QB vss 4.46fF
-C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C123 out_div_by_5 vss -0.40fF
 C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C128 pfd_reset vss 2.17fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C133 QA vss 4.31fF
-C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C137 in_ref vss 1.19fF
@@ -3295,32 +7045,32 @@
 C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C158 div_5_Q1 vss 4.28fF
-C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C168 div_5_nQ0 vss 0.59fF
-C169 div_5_Q0 vss 0.01fF
-C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C179 div_5_nQ2 vss 1.24fF
 C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
 C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
@@ -3329,17 +7079,17 @@
 C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C186 out_by_2 vss -4.51fF
-C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
 C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
 C192 vdd vss 366.82fF
 C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
 C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
-C195 out_to_buffer vss 1.57fF
+C195 out_first_buffer vss 2.88fF
 C196 out_to_div vss 4.46fF
-C197 out_first_buffer vss 2.88fF
+C197 out_to_buffer vss 1.57fF
 C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
 C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -3354,22 +7104,22 @@
 C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
 C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
 C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 out_to_pad vss 7.50fF
-C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
 C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 n_out_buffer_div_2 vss 1.63fF
-C216 out_buffer_div_2 vss 1.60fF
-C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
 C221 out_div_2 vss -1.30fF
 C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
 C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C229 n_out_div_2 vss 1.95fF
 C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -3391,8 +7141,8 @@
 + gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
 + gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
 + gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-+ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[7] io_analog[8] io_analog[9]
-+ io_analog[4] io_analog[6] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
 + io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
 + io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
 + io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
@@ -3489,6 +7239,33 @@
 + wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
 + wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
 + wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
++ bias_0/iref_6 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_top_0/res_amp_lin_prog_0/outn bias_0/iref_7 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ gpio_noesd[3] bias_0/iref_5 res_amp_top_0/res_amp_lin_prog_0/outp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB io_analog[2]
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828#
++ io_analog[3] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1]
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out res_amp_top_0/res_amp_lin_prog_0/outp_cap
++ gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA io_analog[6]
++ gpio_noesd[5] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out gpio_noesd[6]
++ res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
 Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
 + top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
 + top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
@@ -3510,7 +7287,8 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 io_analog[5] bias
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
@@ -3533,8 +7311,6 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
@@ -3547,1099 +7323,1347 @@
 Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xtop_pll_v2_0 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v2_0/pswitch
 + vdda1 top_pll_v2_0/charge_pump_0/w_2544_775# top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp
 + top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd io_analog[10] top_pll_v2_0/vco_vctrl
 + top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
 + top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
 + top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
-C0 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdda1 0.04fF
-C1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vdda1 0.12fF
-C2 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdda1 0.04fF
-C3 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C4 top_pll_v1_1/nDown bias_0/iref_0 0.74fF
-C5 top_pll_v1_0/QA io_analog[10] 0.03fF
-C6 io_analog[10] gpio_noesd[8] 20.65fF
-C7 top_pll_v1_1/Down bias_0/iref_0 1.08fF
-C8 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
-C9 m3_226242_702300# io_analog[5] 0.53fF
-C10 io_clamp_high[0] io_analog[4] 0.53fF
-C11 bias_0/iref_2 io_analog[9] 14.44fF
-C12 gpio_noesd[8] gpio_noesd[7] 1.88fF
-C13 top_pll_v1_1/Up bias_0/iref_0 0.74fF
-C14 io_analog[8] bias_0/iref_2 14.44fF
-C15 gpio_noesd[8] vdda1 76.96fF
-C16 top_pll_v2_0/Up bias_0/iref_1 0.54fF
-C17 top_pll_v2_0/buffer_salida_0/a_3996_n100# vdda1 0.05fF
-C18 top_pll_v2_0/vco_vctrl gpio_noesd[7] 0.05fF
-C19 top_pll_v2_0/vco_vctrl vdda1 0.59fF
-C20 top_pll_v1_0/nUp bias_0/iref_2 0.70fF
-C21 top_pll_v2_0/out_to_div gpio_noesd[7] 0.23fF
-C22 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vdda1 1.01fF
-C23 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
-C24 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
-C25 top_pll_v1_1/charge_pump_0/w_1008_774# bias_0/iref_0 0.21fF
-C26 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vdda1 1.14fF
-C27 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
-C28 io_clamp_low[2] io_analog[6] 0.53fF
-C29 top_pll_v1_1/vco_vctrl vdda1 0.54fF
-C30 top_pll_v2_0/pswitch vdda1 0.34fF
-C31 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vdda1 0.17fF
-C32 io_analog[5] m3_222594_702300# 0.53fF
-C33 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
-C34 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdda1 0.12fF
-C35 io_analog[7] bias_0/iref_2 13.22fF
-C36 bias_0/iref_2 vdda1 3.90fF
-C37 top_pll_v2_0/nUp bias_0/iref_1 0.22fF
-C38 top_pll_v1_0/biasp vdda1 0.03fF
-C39 top_pll_v1_1/charge_pump_0/w_2544_775# bias_0/iref_0 0.21fF
-C40 bias_0/iref_2 top_pll_v1_0/charge_pump_0/w_2544_775# 0.02fF
-C41 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdda1 0.12fF
-C42 top_pll_v2_0/nUp vdda1 0.01fF
-C43 top_pll_v2_0/nDown bias_0/iref_1 0.54fF
-C44 top_pll_v1_0/nDown bias_0/iref_2 0.70fF
-C45 io_clamp_low[0] io_analog[4] 0.53fF
-C46 top_pll_v1_1/out_to_div gpio_noesd[7] 0.15fF
+C0 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C1 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C2 bias_0/iref_9 gpio_noesd[4] -0.25fF
+C3 bias_0/iref_8 bias_0/iref_5 10.19fF
+C4 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C5 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C6 io_analog[7] bias_0/iref_1 13.22fF
+C7 io_analog[6] io_clamp_high[2] 0.53fF
+C8 vdda1 io_analog[2] 25.90fF
+C9 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C10 io_analog[6] vdda1 124.15fF
+C11 bias_0/iref_9 io_analog[4] 15.97fF
+C12 bias_0/iref_8 io_analog[3] 13.88fF
+C13 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C14 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C15 bias_0/iref_2 io_analog[8] 14.44fF
+C16 gpio_noesd[7] io_analog[10] 29.88fF
+C17 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C18 io_analog[2] bias_0/iref_6 13.88fF
+C19 io_analog[5] m3_226242_702300# 0.53fF
+C20 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
+C21 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C22 io_analog[4] io_clamp_high[0] 0.53fF
+C23 vdda1 top_pll_v1_0/nUp 0.01fF
+C24 vdda1 top_pll_v2_0/pswitch 0.34fF
+C25 io_analog[4] bias_0/iref_8 15.97fF
+C26 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C27 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C28 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C29 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C30 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C31 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C32 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C33 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C34 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C35 vdda1 bias_0/iref_6 29.75fF
+C36 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C37 io_analog[2] bias_0/iref_7 13.88fF
+C38 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
+C39 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
+C40 gpio_noesd[7] gpio_noesd[8] 1.88fF
+C41 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C42 vdda1 top_pll_v2_0/biasp 0.03fF
+C43 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C44 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C45 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C46 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
 C47 vdda1 io_analog[9] 30.05fF
-C48 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
-C49 io_analog[8] vdda1 29.93fF
-C50 gpio_noesd[7] top_pll_v1_0/vco_vctrl 0.05fF
-C51 top_pll_v1_0/vco_vctrl vdda1 0.43fF
-C52 top_pll_v2_0/biasp vdda1 0.03fF
-C53 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vdda1 2.10fF
-C54 top_pll_v1_1/nUp bias_0/iref_0 0.74fF
-C55 top_pll_v1_0/nUp vdda1 0.01fF
-C56 top_pll_v1_1/pswitch vdda1 0.48fF
-C57 top_pll_v1_0/pswitch vdda1 0.38fF
-C58 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdda1 0.17fF
-C59 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
-C60 io_analog[10] gpio_noesd[7] 29.88fF
-C61 io_analog[7] bias_0/iref_1 13.22fF
-C62 bias_0/iref_1 vdda1 15.26fF
-C63 io_analog[10] vdda1 0.01fF
-C64 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C65 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdda1 0.17fF
-C66 gpio_noesd[7] vdda1 120.83fF
-C67 top_pll_v1_0/Up bias_0/iref_2 0.70fF
-C68 io_analog[7] vdda1 29.48fF
-C69 io_clamp_high[2] io_analog[6] 0.53fF
-C70 top_pll_v1_0/Down bias_0/iref_2 1.11fF
-C71 bias_0/iref_0 vdda1 15.18fF
-C72 bias_0/iref_2 top_pll_v1_0/biasp 3.20fF
-C73 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
-C74 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
-C75 io_in_3v3[0] vssa1 0.41fF
-C76 io_oeb[26] vssa1 0.61fF
-C77 io_in[0] vssa1 0.41fF
-C78 io_out[26] vssa1 0.61fF
-C79 io_out[0] vssa1 0.41fF
-C80 io_in[26] vssa1 0.61fF
-C81 io_oeb[0] vssa1 0.41fF
-C82 io_in_3v3[26] vssa1 0.61fF
-C83 io_in_3v3[1] vssa1 0.41fF
-C84 io_oeb[25] vssa1 0.61fF
-C85 io_in[1] vssa1 0.41fF
-C86 io_out[25] vssa1 0.61fF
-C87 io_out[1] vssa1 0.41fF
-C88 io_in[25] vssa1 0.61fF
-C89 io_oeb[1] vssa1 0.41fF
-C90 io_in_3v3[25] vssa1 0.61fF
-C91 io_in_3v3[2] vssa1 0.41fF
-C92 io_oeb[24] vssa1 0.61fF
-C93 io_in[2] vssa1 0.41fF
-C94 io_out[24] vssa1 0.61fF
-C95 io_out[2] vssa1 0.41fF
-C96 io_in[24] vssa1 0.61fF
-C97 io_oeb[2] vssa1 -0.20fF
-C98 io_in_3v3[3] vssa1 0.41fF
-C99 gpio_noesd[17] vssa1 0.61fF
-C100 io_in[3] vssa1 0.41fF
-C101 gpio_analog[17] vssa1 0.61fF
-C102 io_out[3] vssa1 0.41fF
-C103 io_oeb[3] vssa1 0.41fF
-C104 io_in_3v3[4] vssa1 0.41fF
-C105 io_in[4] vssa1 0.41fF
-C106 io_out[4] vssa1 0.41fF
-C107 io_oeb[4] vssa1 0.41fF
-C108 io_oeb[23] vssa1 0.61fF
-C109 io_out[23] vssa1 0.61fF
-C110 io_in[23] vssa1 0.61fF
-C111 io_in_3v3[23] vssa1 0.61fF
-C112 gpio_noesd[16] vssa1 0.61fF
-C113 io_in_3v3[5] vssa1 0.41fF
-C114 io_in[5] vssa1 -0.20fF
-C115 io_out[5] vssa1 0.41fF
-C116 io_oeb[5] vssa1 0.41fF
-C117 io_oeb[22] vssa1 0.61fF
-C118 io_out[22] vssa1 0.61fF
-C119 io_in[22] vssa1 0.61fF
-C120 io_in_3v3[22] vssa1 0.61fF
-C121 gpio_analog[15] vssa1 0.61fF
-C122 io_in_3v3[6] vssa1 -0.20fF
-C123 io_in[6] vssa1 0.41fF
-C124 io_out[6] vssa1 0.41fF
-C125 io_oeb[6] vssa1 0.41fF
-C126 io_oeb[21] vssa1 0.61fF
-C127 io_out[21] vssa1 0.61fF
-C128 io_in[21] vssa1 0.61fF
-C129 io_in_3v3[21] vssa1 0.61fF
-C130 gpio_noesd[14] vssa1 0.61fF
-C131 gpio_analog[14] vssa1 0.61fF
-C132 vssd2 vssa1 -5.19fF
-C133 vssd1 vssa1 1.13fF
-C134 vdda2 vssa1 -5.19fF
-C135 io_oeb[20] vssa1 0.61fF
-C136 io_out[20] vssa1 0.61fF
-C137 io_in[20] vssa1 0.61fF
-C138 io_in_3v3[20] vssa1 0.61fF
-C139 gpio_noesd[13] vssa1 0.61fF
-C140 gpio_analog[13] vssa1 0.61fF
-C141 gpio_analog[0] vssa1 0.41fF
-C142 gpio_noesd[0] vssa1 0.41fF
-C143 io_in_3v3[7] vssa1 0.41fF
-C144 io_in[7] vssa1 0.41fF
-C145 io_out[7] vssa1 0.41fF
-C146 io_oeb[7] vssa1 0.41fF
-C147 io_oeb[19] vssa1 0.61fF
-C148 io_out[19] vssa1 0.61fF
-C149 io_in[19] vssa1 0.61fF
-C150 io_in_3v3[19] vssa1 0.61fF
-C151 gpio_noesd[12] vssa1 0.61fF
-C152 gpio_analog[12] vssa1 0.61fF
-C153 gpio_analog[1] vssa1 0.41fF
-C154 gpio_noesd[1] vssa1 0.41fF
-C155 io_in_3v3[8] vssa1 0.41fF
-C156 io_in[8] vssa1 0.41fF
-C157 io_out[8] vssa1 -0.20fF
-C158 io_oeb[8] vssa1 0.41fF
-C159 io_oeb[18] vssa1 0.61fF
-C160 io_out[18] vssa1 0.61fF
-C161 io_in_3v3[18] vssa1 0.61fF
-C162 gpio_noesd[11] vssa1 0.61fF
-C163 gpio_analog[11] vssa1 0.61fF
-C164 gpio_analog[2] vssa1 0.41fF
-C165 gpio_noesd[2] vssa1 0.41fF
-C166 io_in_3v3[9] vssa1 0.41fF
-C167 io_in[9] vssa1 0.41fF
-C168 io_out[9] vssa1 0.41fF
-C169 io_oeb[9] vssa1 0.41fF
-C170 io_oeb[17] vssa1 0.61fF
-C171 io_in[17] vssa1 0.61fF
-C172 io_in_3v3[17] vssa1 0.61fF
-C173 gpio_noesd[10] vssa1 0.61fF
-C174 gpio_analog[10] vssa1 0.61fF
-C175 gpio_analog[3] vssa1 0.41fF
-C176 gpio_noesd[3] vssa1 0.41fF
-C177 io_in_3v3[10] vssa1 0.41fF
-C178 io_in[10] vssa1 0.41fF
-C179 io_out[10] vssa1 0.41fF
-C180 io_oeb[10] vssa1 0.41fF
-C181 io_out[16] vssa1 0.61fF
-C182 io_in[16] vssa1 0.61fF
-C183 io_in_3v3[16] vssa1 0.61fF
-C184 gpio_noesd[9] vssa1 0.61fF
-C185 gpio_analog[9] vssa1 0.61fF
-C186 gpio_analog[4] vssa1 0.41fF
-C187 gpio_noesd[4] vssa1 0.41fF
-C188 io_in_3v3[11] vssa1 0.41fF
-C189 io_in[11] vssa1 0.41fF
-C190 io_out[11] vssa1 0.41fF
-C191 io_oeb[11] vssa1 0.41fF
-C192 io_oeb[15] vssa1 0.61fF
-C193 io_out[15] vssa1 0.61fF
-C194 io_in[15] vssa1 0.61fF
-C195 io_in_3v3[15] vssa1 0.61fF
-C196 gpio_analog[5] vssa1 0.41fF
-C197 gpio_noesd[5] vssa1 0.41fF
-C198 io_in_3v3[12] vssa1 0.41fF
-C199 io_in[12] vssa1 0.41fF
-C200 io_out[12] vssa1 0.41fF
-C201 io_oeb[12] vssa1 0.41fF
-C202 gpio_analog[6] vssa1 0.60fF
-C203 gpio_noesd[6] vssa1 0.60fF
-C204 io_in_3v3[13] vssa1 0.60fF
-C205 io_in[13] vssa1 0.60fF
-C206 io_out[13] vssa1 0.60fF
-C207 io_oeb[13] vssa1 0.60fF
-C208 vccd1 vssa1 0.85fF
-C209 gpio_analog[8] vssa1 0.61fF
-C210 io_oeb[14] vssa1 0.61fF
-C211 io_out[14] vssa1 0.61fF
-C212 io_in[14] vssa1 0.61fF
-C213 io_in_3v3[14] vssa1 0.61fF
-C214 io_analog[0] vssa1 -6.01fF
-C215 io_analog[1] vssa1 0.76fF
-C216 vssa2 vssa1 1.66fF
-C217 vccd2 vssa1 0.91fF
-C218 io_analog[2] vssa1 -5.85fF
-C219 io_analog[3] vssa1 -5.74fF
-C220 io_analog[4] vssa1 -5.03fF
-C221 io_clamp_high[0] vssa1 -2.60fF
-C222 io_clamp_low[0] vssa1 0.82fF
-C223 io_analog[6] vssa1 -4.92fF
-C224 io_clamp_high[2] vssa1 0.66fF
-C225 io_clamp_low[2] vssa1 0.50fF
-C226 user_irq[2] vssa1 0.63fF
-C227 user_irq[1] vssa1 0.63fF
-C228 user_irq[0] vssa1 0.63fF
-C229 user_clock2 vssa1 0.63fF
-C230 la_oenb[127] vssa1 0.63fF
-C231 la_data_in[127] vssa1 0.63fF
-C232 la_oenb[126] vssa1 0.63fF
-C233 la_data_out[126] vssa1 0.63fF
-C234 la_data_in[126] vssa1 0.63fF
-C235 la_oenb[125] vssa1 0.63fF
-C236 la_data_out[125] vssa1 0.63fF
-C237 la_data_in[125] vssa1 0.63fF
-C238 la_oenb[124] vssa1 0.63fF
-C239 la_data_out[124] vssa1 0.63fF
-C240 la_data_in[124] vssa1 0.63fF
-C241 la_oenb[123] vssa1 0.63fF
-C242 la_data_out[123] vssa1 0.63fF
-C243 la_oenb[122] vssa1 0.63fF
-C244 la_data_out[122] vssa1 0.63fF
-C245 la_data_in[122] vssa1 0.63fF
-C246 la_oenb[121] vssa1 0.63fF
-C247 la_data_out[121] vssa1 0.63fF
-C248 la_data_in[121] vssa1 0.63fF
-C249 la_oenb[120] vssa1 0.63fF
-C250 la_data_out[120] vssa1 0.63fF
-C251 la_data_in[120] vssa1 0.63fF
-C252 la_oenb[119] vssa1 0.63fF
-C253 la_data_out[119] vssa1 0.63fF
-C254 la_data_in[119] vssa1 0.63fF
-C255 la_oenb[118] vssa1 0.63fF
-C256 la_data_out[118] vssa1 0.63fF
-C257 la_data_in[118] vssa1 0.63fF
-C258 la_oenb[117] vssa1 0.63fF
-C259 la_data_out[117] vssa1 0.63fF
-C260 la_data_in[117] vssa1 0.63fF
-C261 la_data_out[116] vssa1 0.63fF
-C262 la_data_in[116] vssa1 0.63fF
-C263 la_oenb[115] vssa1 0.63fF
-C264 la_data_out[115] vssa1 0.63fF
-C265 la_data_in[115] vssa1 0.63fF
-C266 la_oenb[114] vssa1 0.63fF
-C267 la_data_out[114] vssa1 0.63fF
-C268 la_data_in[114] vssa1 0.63fF
-C269 la_oenb[113] vssa1 0.63fF
-C270 la_data_out[113] vssa1 0.63fF
-C271 la_data_in[113] vssa1 0.63fF
-C272 la_oenb[112] vssa1 0.63fF
-C273 la_data_in[112] vssa1 0.63fF
-C274 la_oenb[111] vssa1 0.63fF
-C275 la_data_out[111] vssa1 0.63fF
-C276 la_data_in[111] vssa1 0.63fF
-C277 la_oenb[110] vssa1 0.63fF
-C278 la_data_out[110] vssa1 0.63fF
-C279 la_data_in[110] vssa1 0.63fF
-C280 la_oenb[109] vssa1 0.63fF
-C281 la_data_out[109] vssa1 0.63fF
-C282 la_data_in[109] vssa1 0.63fF
-C283 la_oenb[108] vssa1 0.63fF
-C284 la_data_out[108] vssa1 0.63fF
-C285 la_oenb[107] vssa1 0.63fF
-C286 la_data_out[107] vssa1 0.63fF
-C287 la_data_in[107] vssa1 0.63fF
-C288 la_oenb[106] vssa1 0.63fF
-C289 la_data_out[106] vssa1 0.63fF
-C290 la_oenb[105] vssa1 0.63fF
-C291 la_data_out[105] vssa1 0.63fF
-C292 la_data_in[105] vssa1 0.63fF
-C293 la_oenb[104] vssa1 0.63fF
-C294 la_data_out[104] vssa1 0.63fF
-C295 la_data_in[104] vssa1 0.63fF
-C296 la_oenb[103] vssa1 0.63fF
-C297 la_data_out[103] vssa1 0.63fF
-C298 la_data_in[103] vssa1 0.63fF
-C299 la_oenb[102] vssa1 0.63fF
-C300 la_data_out[102] vssa1 0.63fF
-C301 la_data_in[102] vssa1 0.63fF
-C302 la_data_out[101] vssa1 0.63fF
-C303 la_data_in[101] vssa1 0.63fF
-C304 la_oenb[100] vssa1 0.63fF
-C305 la_data_out[100] vssa1 0.63fF
-C306 la_data_in[100] vssa1 0.63fF
-C307 la_oenb[99] vssa1 0.63fF
-C308 la_data_out[99] vssa1 0.63fF
-C309 la_data_in[99] vssa1 0.63fF
-C310 la_oenb[98] vssa1 0.63fF
-C311 la_data_out[98] vssa1 0.63fF
-C312 la_data_in[98] vssa1 0.63fF
-C313 la_oenb[97] vssa1 0.63fF
-C314 la_data_in[97] vssa1 0.63fF
-C315 la_oenb[96] vssa1 0.63fF
-C316 la_data_out[96] vssa1 0.63fF
-C317 la_data_in[96] vssa1 0.63fF
-C318 la_oenb[95] vssa1 0.63fF
-C319 la_data_out[95] vssa1 0.63fF
-C320 la_data_in[95] vssa1 0.63fF
-C321 la_oenb[94] vssa1 0.63fF
-C322 la_data_out[94] vssa1 0.63fF
-C323 la_data_in[94] vssa1 0.63fF
-C324 la_oenb[93] vssa1 0.63fF
-C325 la_data_out[93] vssa1 0.63fF
-C326 la_oenb[92] vssa1 0.63fF
-C327 la_data_out[92] vssa1 0.63fF
-C328 la_data_in[92] vssa1 0.63fF
-C329 la_oenb[91] vssa1 0.63fF
-C330 la_data_out[91] vssa1 0.63fF
-C331 la_oenb[90] vssa1 0.63fF
-C332 la_data_out[90] vssa1 0.63fF
-C333 la_data_in[90] vssa1 0.63fF
-C334 la_oenb[89] vssa1 0.63fF
-C335 la_data_out[89] vssa1 0.63fF
-C336 la_data_in[89] vssa1 0.63fF
-C337 la_oenb[88] vssa1 0.63fF
-C338 la_data_out[88] vssa1 0.63fF
-C339 la_data_in[88] vssa1 0.63fF
-C340 la_oenb[87] vssa1 0.63fF
-C341 la_data_out[87] vssa1 0.63fF
-C342 la_data_in[87] vssa1 0.63fF
-C343 la_data_out[86] vssa1 0.63fF
-C344 la_data_in[86] vssa1 0.63fF
-C345 la_oenb[85] vssa1 0.63fF
-C346 la_data_out[85] vssa1 0.63fF
-C347 la_data_in[85] vssa1 0.63fF
-C348 la_oenb[84] vssa1 0.63fF
-C349 la_data_out[84] vssa1 0.63fF
-C350 la_data_in[84] vssa1 0.63fF
-C351 la_oenb[83] vssa1 0.63fF
-C352 la_data_out[83] vssa1 0.63fF
-C353 la_data_in[83] vssa1 0.63fF
-C354 la_oenb[82] vssa1 0.63fF
-C355 la_data_in[82] vssa1 0.63fF
-C356 la_oenb[81] vssa1 0.63fF
-C357 la_data_out[81] vssa1 0.63fF
-C358 la_data_in[81] vssa1 0.63fF
-C359 la_oenb[80] vssa1 0.63fF
-C360 la_data_out[80] vssa1 0.63fF
-C361 la_data_in[80] vssa1 0.63fF
-C362 la_oenb[79] vssa1 0.63fF
-C363 la_data_out[79] vssa1 0.63fF
-C364 la_data_in[79] vssa1 0.63fF
-C365 la_oenb[78] vssa1 0.63fF
-C366 la_data_out[78] vssa1 0.63fF
-C367 la_data_in[78] vssa1 0.63fF
-C368 la_oenb[77] vssa1 0.63fF
-C369 la_data_out[77] vssa1 0.63fF
-C370 la_data_in[77] vssa1 0.63fF
-C371 la_oenb[76] vssa1 0.63fF
-C372 la_data_out[76] vssa1 0.63fF
-C373 la_oenb[75] vssa1 0.63fF
-C374 la_data_out[75] vssa1 0.63fF
-C375 la_data_in[75] vssa1 0.63fF
-C376 la_oenb[74] vssa1 0.63fF
-C377 la_data_out[74] vssa1 0.63fF
-C378 la_data_in[74] vssa1 0.63fF
-C379 la_oenb[73] vssa1 0.63fF
-C380 la_data_out[73] vssa1 0.63fF
-C381 la_data_in[73] vssa1 0.63fF
-C382 la_oenb[72] vssa1 0.63fF
-C383 la_data_out[72] vssa1 0.63fF
-C384 la_data_in[72] vssa1 0.63fF
-C385 la_data_out[71] vssa1 0.63fF
-C386 la_data_in[71] vssa1 0.63fF
-C387 la_oenb[70] vssa1 0.63fF
-C388 la_data_out[70] vssa1 0.63fF
-C389 la_data_in[70] vssa1 0.63fF
-C390 la_oenb[69] vssa1 0.63fF
-C391 la_data_out[69] vssa1 0.63fF
-C392 la_data_in[69] vssa1 0.63fF
-C393 la_oenb[68] vssa1 0.63fF
-C394 la_data_out[68] vssa1 0.63fF
-C395 la_data_in[68] vssa1 0.63fF
-C396 la_oenb[67] vssa1 0.63fF
-C397 la_data_in[67] vssa1 0.63fF
-C398 la_oenb[66] vssa1 0.63fF
-C399 la_data_out[66] vssa1 0.63fF
-C400 la_data_in[66] vssa1 0.63fF
-C401 la_oenb[65] vssa1 0.63fF
-C402 la_data_out[65] vssa1 0.26fF
-C403 la_data_in[65] vssa1 0.63fF
-C404 la_oenb[64] vssa1 0.63fF
-C405 la_data_out[64] vssa1 0.63fF
-C406 la_data_in[64] vssa1 0.63fF
-C407 la_oenb[63] vssa1 0.63fF
-C408 la_data_out[63] vssa1 0.63fF
-C409 la_data_in[63] vssa1 0.63fF
-C410 la_oenb[62] vssa1 0.63fF
-C411 la_data_out[62] vssa1 0.63fF
-C412 la_data_in[62] vssa1 0.63fF
-C413 la_oenb[61] vssa1 0.63fF
-C414 la_data_out[61] vssa1 0.63fF
-C415 la_oenb[60] vssa1 0.63fF
-C416 la_data_out[60] vssa1 0.63fF
-C417 la_data_in[60] vssa1 0.63fF
-C418 la_oenb[59] vssa1 0.63fF
-C419 la_data_out[59] vssa1 0.63fF
-C420 la_data_in[59] vssa1 0.63fF
-C421 la_oenb[58] vssa1 0.63fF
-C422 la_data_out[58] vssa1 0.63fF
-C423 la_data_in[58] vssa1 0.63fF
-C424 la_oenb[57] vssa1 0.63fF
-C425 la_data_out[57] vssa1 0.63fF
-C426 la_data_in[57] vssa1 0.63fF
-C427 la_data_out[56] vssa1 0.63fF
-C428 la_data_in[56] vssa1 0.63fF
-C429 la_oenb[55] vssa1 0.63fF
-C430 la_data_out[55] vssa1 0.63fF
-C431 la_data_in[55] vssa1 0.63fF
-C432 la_oenb[54] vssa1 0.63fF
-C433 la_data_out[54] vssa1 0.63fF
-C434 la_data_in[54] vssa1 0.63fF
-C435 la_oenb[53] vssa1 0.63fF
-C436 la_data_out[53] vssa1 0.63fF
-C437 la_data_in[53] vssa1 0.63fF
-C438 la_oenb[52] vssa1 0.63fF
-C439 la_data_in[52] vssa1 0.63fF
-C440 la_oenb[51] vssa1 0.63fF
-C441 la_data_out[51] vssa1 0.63fF
-C442 la_data_in[51] vssa1 0.63fF
-C443 la_oenb[50] vssa1 0.63fF
-C444 la_data_in[50] vssa1 0.63fF
-C445 la_oenb[49] vssa1 0.63fF
-C446 la_data_out[49] vssa1 0.63fF
-C447 la_data_in[49] vssa1 0.63fF
-C448 la_oenb[48] vssa1 0.63fF
-C449 la_data_out[48] vssa1 0.63fF
-C450 la_data_in[48] vssa1 0.63fF
-C451 la_oenb[47] vssa1 0.63fF
-C452 la_data_out[47] vssa1 0.63fF
-C453 la_data_in[47] vssa1 0.63fF
-C454 la_oenb[46] vssa1 0.63fF
-C455 la_data_out[46] vssa1 0.63fF
-C456 la_oenb[45] vssa1 0.63fF
-C457 la_data_out[45] vssa1 0.63fF
-C458 la_data_in[45] vssa1 0.63fF
-C459 la_oenb[44] vssa1 0.63fF
-C460 la_data_out[44] vssa1 0.63fF
-C461 la_data_in[44] vssa1 0.63fF
-C462 la_oenb[43] vssa1 0.63fF
-C463 la_data_out[43] vssa1 0.63fF
-C464 la_data_in[43] vssa1 0.63fF
-C465 la_oenb[42] vssa1 0.63fF
-C466 la_data_out[42] vssa1 0.63fF
-C467 la_data_in[42] vssa1 0.63fF
-C468 la_data_out[41] vssa1 0.63fF
-C469 la_data_in[41] vssa1 0.63fF
-C470 la_oenb[40] vssa1 0.63fF
-C471 la_data_out[40] vssa1 0.63fF
-C472 la_data_in[40] vssa1 0.63fF
-C473 la_oenb[39] vssa1 0.63fF
-C474 la_data_out[39] vssa1 0.63fF
-C475 la_data_in[39] vssa1 0.63fF
-C476 la_oenb[38] vssa1 0.63fF
-C477 la_data_out[38] vssa1 0.63fF
-C478 la_data_in[38] vssa1 0.63fF
-C479 la_oenb[37] vssa1 0.63fF
-C480 la_data_out[37] vssa1 0.26fF
-C481 la_data_in[37] vssa1 0.63fF
-C482 la_oenb[36] vssa1 0.63fF
-C483 la_data_out[36] vssa1 0.63fF
-C484 la_data_in[36] vssa1 0.63fF
-C485 la_oenb[35] vssa1 0.63fF
-C486 la_data_in[35] vssa1 0.63fF
-C487 la_oenb[34] vssa1 0.63fF
-C488 la_data_out[34] vssa1 0.63fF
-C489 la_data_in[34] vssa1 0.63fF
-C490 la_oenb[33] vssa1 0.63fF
-C491 la_data_out[33] vssa1 0.63fF
-C492 la_data_in[33] vssa1 0.63fF
-C493 la_oenb[32] vssa1 0.63fF
-C494 la_data_out[32] vssa1 0.63fF
-C495 la_data_in[32] vssa1 0.63fF
-C496 la_oenb[31] vssa1 0.63fF
-C497 la_data_out[31] vssa1 0.63fF
-C498 la_oenb[30] vssa1 0.63fF
-C499 la_data_out[30] vssa1 0.63fF
-C500 la_data_in[30] vssa1 0.63fF
-C501 la_oenb[29] vssa1 0.63fF
-C502 la_data_out[29] vssa1 0.63fF
-C503 la_data_in[29] vssa1 0.63fF
-C504 la_oenb[28] vssa1 0.63fF
-C505 la_data_out[28] vssa1 0.63fF
-C506 la_data_in[28] vssa1 0.63fF
-C507 la_oenb[27] vssa1 0.63fF
-C508 la_data_out[27] vssa1 0.63fF
-C509 la_data_in[27] vssa1 0.63fF
-C510 la_data_out[26] vssa1 0.63fF
-C511 la_data_in[26] vssa1 0.63fF
-C512 la_oenb[25] vssa1 0.63fF
-C513 la_data_out[25] vssa1 0.63fF
-C514 la_data_in[25] vssa1 0.63fF
-C515 la_oenb[24] vssa1 0.63fF
-C516 la_data_out[24] vssa1 0.63fF
-C517 la_data_in[24] vssa1 0.63fF
-C518 la_oenb[23] vssa1 0.63fF
-C519 la_data_out[23] vssa1 0.63fF
-C520 la_data_in[23] vssa1 0.63fF
-C521 la_oenb[22] vssa1 0.63fF
-C522 la_data_out[22] vssa1 0.63fF
-C523 la_data_in[22] vssa1 0.63fF
-C524 la_oenb[21] vssa1 0.63fF
-C525 la_data_out[21] vssa1 0.63fF
-C526 la_data_in[21] vssa1 0.63fF
-C527 la_oenb[20] vssa1 0.63fF
-C528 la_data_in[20] vssa1 0.63fF
-C529 la_oenb[19] vssa1 0.63fF
-C530 la_data_out[19] vssa1 0.63fF
-C531 la_data_in[19] vssa1 0.63fF
-C532 la_oenb[18] vssa1 0.63fF
-C533 la_data_out[18] vssa1 0.63fF
-C534 la_data_in[18] vssa1 0.63fF
-C535 la_oenb[17] vssa1 0.63fF
-C536 la_data_out[17] vssa1 0.63fF
-C537 la_data_in[17] vssa1 0.63fF
-C538 la_oenb[16] vssa1 0.63fF
-C539 la_data_out[16] vssa1 0.63fF
-C540 la_oenb[15] vssa1 0.63fF
-C541 la_data_out[15] vssa1 0.63fF
-C542 la_data_in[15] vssa1 0.63fF
-C543 la_oenb[14] vssa1 0.63fF
-C544 la_data_out[14] vssa1 0.63fF
-C545 la_data_in[14] vssa1 0.63fF
-C546 la_oenb[13] vssa1 0.63fF
-C547 la_data_out[13] vssa1 0.63fF
-C548 la_data_in[13] vssa1 0.63fF
-C549 la_oenb[12] vssa1 0.63fF
-C550 la_data_out[12] vssa1 0.63fF
-C551 la_data_in[12] vssa1 0.63fF
-C552 la_data_out[11] vssa1 0.63fF
-C553 la_data_in[11] vssa1 0.63fF
-C554 la_oenb[10] vssa1 0.63fF
-C555 la_data_out[10] vssa1 0.63fF
-C556 la_data_in[10] vssa1 0.63fF
-C557 la_data_out[9] vssa1 0.63fF
-C558 la_data_in[9] vssa1 0.63fF
-C559 la_oenb[8] vssa1 0.63fF
-C560 la_data_out[8] vssa1 0.63fF
-C561 la_data_in[8] vssa1 0.63fF
-C562 la_oenb[7] vssa1 0.63fF
-C563 la_data_out[7] vssa1 0.63fF
-C564 la_data_in[7] vssa1 0.63fF
-C565 la_oenb[6] vssa1 0.63fF
-C566 la_data_out[6] vssa1 0.63fF
-C567 la_data_in[6] vssa1 0.63fF
-C568 la_oenb[5] vssa1 0.63fF
-C569 la_data_in[5] vssa1 0.63fF
-C570 la_oenb[4] vssa1 0.63fF
-C571 la_data_out[4] vssa1 0.63fF
-C572 la_data_in[4] vssa1 0.63fF
-C573 la_oenb[3] vssa1 0.63fF
-C574 la_data_out[3] vssa1 0.63fF
-C575 la_data_in[3] vssa1 0.63fF
-C576 la_oenb[2] vssa1 0.63fF
-C577 la_data_out[2] vssa1 0.63fF
-C578 la_data_in[2] vssa1 0.63fF
-C579 la_oenb[1] vssa1 0.63fF
-C580 la_data_out[1] vssa1 0.63fF
-C581 la_oenb[0] vssa1 0.63fF
-C582 la_data_out[0] vssa1 0.63fF
-C583 la_data_in[0] vssa1 0.63fF
-C584 wbs_dat_o[31] vssa1 0.63fF
-C585 wbs_dat_i[31] vssa1 0.63fF
-C586 wbs_adr_i[31] vssa1 0.63fF
-C587 wbs_dat_o[30] vssa1 0.63fF
-C588 wbs_dat_i[30] vssa1 0.63fF
-C589 wbs_adr_i[30] vssa1 0.63fF
-C590 wbs_dat_o[29] vssa1 0.63fF
-C591 wbs_dat_i[29] vssa1 0.63fF
-C592 wbs_adr_i[29] vssa1 0.63fF
-C593 wbs_dat_i[28] vssa1 0.63fF
-C594 wbs_adr_i[28] vssa1 0.63fF
-C595 wbs_dat_o[27] vssa1 0.63fF
-C596 wbs_dat_i[27] vssa1 0.63fF
-C597 wbs_adr_i[27] vssa1 0.63fF
-C598 wbs_dat_i[26] vssa1 0.63fF
-C599 wbs_adr_i[26] vssa1 0.63fF
-C600 wbs_dat_o[25] vssa1 0.63fF
-C601 wbs_dat_i[25] vssa1 0.63fF
-C602 wbs_adr_i[25] vssa1 0.63fF
-C603 wbs_dat_o[24] vssa1 0.63fF
-C604 wbs_dat_i[24] vssa1 0.63fF
-C605 wbs_adr_i[24] vssa1 0.63fF
-C606 wbs_dat_o[23] vssa1 0.63fF
-C607 wbs_dat_i[23] vssa1 0.63fF
-C608 wbs_adr_i[23] vssa1 0.63fF
-C609 wbs_dat_o[22] vssa1 0.63fF
-C610 wbs_adr_i[22] vssa1 0.63fF
-C611 wbs_dat_o[21] vssa1 0.63fF
-C612 wbs_dat_i[21] vssa1 0.63fF
-C613 wbs_adr_i[21] vssa1 0.63fF
-C614 wbs_dat_o[20] vssa1 0.63fF
-C615 wbs_dat_i[20] vssa1 0.63fF
-C616 wbs_adr_i[20] vssa1 0.63fF
-C617 wbs_dat_o[19] vssa1 0.63fF
-C618 wbs_dat_i[19] vssa1 0.63fF
-C619 wbs_adr_i[19] vssa1 0.63fF
-C620 wbs_dat_o[18] vssa1 0.63fF
-C621 wbs_dat_i[18] vssa1 0.63fF
-C622 wbs_dat_o[17] vssa1 0.63fF
-C623 wbs_dat_i[17] vssa1 0.63fF
-C624 wbs_adr_i[17] vssa1 0.63fF
-C625 wbs_dat_o[16] vssa1 0.63fF
-C626 wbs_dat_i[16] vssa1 0.63fF
-C627 wbs_adr_i[16] vssa1 0.63fF
-C628 wbs_dat_o[15] vssa1 0.63fF
-C629 wbs_dat_i[15] vssa1 0.63fF
-C630 wbs_adr_i[15] vssa1 0.63fF
-C631 wbs_dat_o[14] vssa1 0.63fF
-C632 wbs_dat_i[14] vssa1 0.63fF
-C633 wbs_adr_i[14] vssa1 0.63fF
-C634 wbs_dat_o[13] vssa1 0.63fF
-C635 wbs_dat_i[13] vssa1 0.63fF
-C636 wbs_adr_i[13] vssa1 0.63fF
-C637 wbs_dat_o[12] vssa1 0.63fF
-C638 wbs_dat_i[12] vssa1 0.63fF
-C639 wbs_adr_i[12] vssa1 0.63fF
-C640 wbs_dat_i[11] vssa1 0.63fF
-C641 wbs_adr_i[11] vssa1 0.63fF
-C642 wbs_dat_o[10] vssa1 0.63fF
-C643 wbs_dat_i[10] vssa1 0.63fF
-C644 wbs_adr_i[10] vssa1 0.63fF
-C645 wbs_dat_o[9] vssa1 0.63fF
-C646 wbs_dat_i[9] vssa1 0.63fF
-C647 wbs_adr_i[9] vssa1 0.63fF
-C648 wbs_dat_o[8] vssa1 0.63fF
-C649 wbs_dat_i[8] vssa1 0.63fF
-C650 wbs_adr_i[8] vssa1 0.63fF
-C651 wbs_dat_o[7] vssa1 0.63fF
-C652 wbs_adr_i[7] vssa1 0.63fF
-C653 wbs_dat_o[6] vssa1 0.63fF
-C654 wbs_dat_i[6] vssa1 0.63fF
-C655 wbs_adr_i[6] vssa1 0.63fF
-C656 wbs_dat_o[5] vssa1 0.63fF
-C657 wbs_dat_i[5] vssa1 0.63fF
-C658 wbs_adr_i[5] vssa1 0.63fF
-C659 wbs_dat_o[4] vssa1 0.63fF
-C660 wbs_dat_i[4] vssa1 0.63fF
-C661 wbs_adr_i[4] vssa1 0.63fF
-C662 wbs_sel_i[3] vssa1 0.63fF
-C663 wbs_dat_o[3] vssa1 0.63fF
-C664 wbs_adr_i[3] vssa1 0.63fF
-C665 wbs_sel_i[2] vssa1 0.63fF
-C666 wbs_dat_o[2] vssa1 0.63fF
-C667 wbs_dat_i[2] vssa1 0.63fF
-C668 wbs_adr_i[2] vssa1 0.63fF
-C669 wbs_dat_o[1] vssa1 0.63fF
-C670 wbs_dat_i[1] vssa1 0.63fF
-C671 wbs_adr_i[1] vssa1 0.63fF
-C672 wbs_sel_i[0] vssa1 0.63fF
-C673 wbs_dat_o[0] vssa1 0.63fF
-C674 wbs_dat_i[0] vssa1 0.63fF
-C675 wbs_adr_i[0] vssa1 0.63fF
-C676 wbs_we_i vssa1 0.63fF
-C677 wbs_stb_i vssa1 0.63fF
-C678 wbs_cyc_i vssa1 0.63fF
-C679 wbs_ack_o vssa1 0.63fF
-C680 wb_rst_i vssa1 0.63fF
-C681 m3_226242_702300# vssa1 -1.31fF $ **FLOATING
-C682 m3_222594_702300# vssa1 0.55fF $ **FLOATING
-C683 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C684 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C685 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C686 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C687 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C688 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C689 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C690 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C691 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C692 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C693 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C694 top_pll_v2_0/QB vssa1 4.35fF
-C695 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C696 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C697 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C698 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
-C699 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C700 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C701 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C702 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C703 top_pll_v2_0/pfd_reset vssa1 2.17fF
-C704 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C705 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C706 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C707 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C708 top_pll_v2_0/QA vssa1 4.22fF
-C709 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C710 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C711 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C712 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C713 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C714 top_pll_v2_0/nUp vssa1 5.39fF
-C715 top_pll_v2_0/Up vssa1 1.85fF
-C716 top_pll_v2_0/Down vssa1 6.19fF
-C717 top_pll_v2_0/nDown vssa1 -3.53fF
-C718 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C719 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C720 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C721 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C722 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
-C723 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C724 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C725 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C726 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C727 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C728 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C729 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C730 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C731 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C732 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
-C733 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C734 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C735 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C736 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C737 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C738 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C739 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C740 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C741 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C742 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
-C743 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
-C744 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C745 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C746 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C747 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C748 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C749 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C750 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C751 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C752 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C753 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
-C754 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C755 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C756 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
-C757 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C758 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C759 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C760 top_pll_v2_0/out_by_2 vssa1 -5.01fF
-C761 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C762 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C763 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C764 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C765 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C766 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C767 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C768 top_pll_v2_0/out_to_buffer vssa1 1.54fF
-C769 top_pll_v2_0/out_to_div vssa1 4.23fF
-C770 top_pll_v2_0/out_first_buffer vssa1 2.88fF
-C771 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C772 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C773 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C774 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C775 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C776 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C777 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C778 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C779 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C780 top_pll_v2_0/vco_out vssa1 1.01fF
-C781 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C782 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C783 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C784 io_analog[8] vssa1 13.78fF
-C785 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C786 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C787 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
-C788 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
-C789 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C790 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C791 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C792 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C793 top_pll_v2_0/out_div_2 vssa1 -1.30fF
-C794 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C795 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C796 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C797 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C798 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C799 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C800 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C801 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
-C802 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C803 top_pll_v2_0/lf_vc vssa1 -59.89fF
-C804 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
-C805 gpio_noesd[8] vssa1 210.79fF
-C806 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
-C807 top_pll_v2_0/nswitch vssa1 3.73fF
-C808 top_pll_v2_0/biasp vssa1 5.44fF
-C809 bias_0/iref_1 vssa1 -93.46fF
-C810 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
-C811 top_pll_v2_0/pswitch vssa1 3.57fF
-C812 bias_0/iref_4 vssa1 1.17fF
-C813 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
-C814 bias_0/iref_3 vssa1 0.64fF
-C815 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
-C816 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
-C817 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
-C818 io_analog[5] vssa1 33.29fF
-C819 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
-C820 bias_0/m1_20168_984# vssa1 56.92fF
-C821 bias_0/iref_9 vssa1 -1.13fF
-C822 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
-C823 bias_0/iref_7 vssa1 -1.38fF
-C824 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
-C825 bias_0/iref_8 vssa1 -1.19fF
-C826 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
-C827 bias_0/iref_6 vssa1 -1.00fF
-C828 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
-C829 bias_0/iref_5 vssa1 1.40fF
-C830 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
-C831 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C832 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C833 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C834 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C835 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C836 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C837 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C838 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C839 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C840 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C841 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C842 top_pll_v1_1/QB vssa1 4.35fF
-C843 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C844 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C845 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C846 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
-C847 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C848 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C849 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C850 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C851 top_pll_v1_1/pfd_reset vssa1 2.17fF
-C852 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C853 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C854 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C855 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C856 top_pll_v1_1/QA vssa1 4.22fF
-C857 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C858 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C859 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C860 io_analog[10] vssa1 503.33fF
-C861 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C862 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C863 top_pll_v1_1/nUp vssa1 5.39fF
-C864 top_pll_v1_1/Up vssa1 1.85fF
-C865 top_pll_v1_1/Down vssa1 6.19fF
-C866 top_pll_v1_1/nDown vssa1 -3.53fF
-C867 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C868 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C869 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C870 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C871 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
-C872 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C873 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C874 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C875 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C876 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C877 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C878 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C879 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C880 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C881 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
-C882 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C883 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C884 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C885 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C886 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C887 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C888 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C889 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C890 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C891 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
-C892 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
-C893 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C894 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C895 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C896 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C897 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C898 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C899 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C900 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C901 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C902 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
-C903 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C904 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C905 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
-C906 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C907 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C908 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C909 top_pll_v1_1/out_by_2 vssa1 -5.01fF
-C910 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C911 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C912 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C913 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C914 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C915 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C916 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C917 top_pll_v1_1/out_to_buffer vssa1 1.54fF
-C918 top_pll_v1_1/out_to_div vssa1 4.23fF
-C919 top_pll_v1_1/out_first_buffer vssa1 2.88fF
-C920 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C921 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C922 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C923 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C924 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C925 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C926 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C927 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C928 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C929 top_pll_v1_1/vco_out vssa1 1.01fF
-C930 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C931 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C932 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C933 io_analog[7] vssa1 24.61fF
-C934 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
-C935 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C936 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
-C937 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
-C938 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C939 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C940 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C941 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C942 top_pll_v1_1/out_div_2 vssa1 -1.30fF
-C943 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C944 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C945 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C946 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C947 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C948 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C949 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C950 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
-C951 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C952 top_pll_v1_1/nswitch vssa1 3.73fF
-C953 top_pll_v1_1/biasp vssa1 5.44fF
-C954 bias_0/iref_0 vssa1 -81.35fF
-C955 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
-C956 top_pll_v1_1/pswitch vssa1 3.57fF
-C957 top_pll_v1_1/lf_vc vssa1 -59.89fF
-C958 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C959 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C960 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C961 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C962 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C963 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C964 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C965 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C966 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C967 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C968 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C969 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C970 top_pll_v1_0/QB vssa1 4.35fF
-C971 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C972 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C973 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C974 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
-C975 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C976 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C977 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C978 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C979 top_pll_v1_0/pfd_reset vssa1 2.17fF
-C980 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C981 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C982 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C983 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C984 top_pll_v1_0/QA vssa1 4.22fF
-C985 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C986 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C987 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C988 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C989 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C990 top_pll_v1_0/nUp vssa1 5.39fF
-C991 top_pll_v1_0/Up vssa1 1.85fF
-C992 top_pll_v1_0/Down vssa1 6.19fF
-C993 top_pll_v1_0/nDown vssa1 -3.53fF
-C994 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C995 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C996 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C997 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C998 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
-C999 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1000 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1001 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1002 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1003 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1004 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1005 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1006 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1007 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1008 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
-C1009 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1010 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1011 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1012 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1013 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1014 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1015 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1016 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1017 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1018 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
-C1019 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
-C1020 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1021 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1022 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1023 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1024 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1025 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1026 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1027 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C1028 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1029 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
-C1030 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1031 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1032 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
-C1033 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1034 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1035 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1036 top_pll_v1_0/out_by_2 vssa1 -5.01fF
-C1037 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1038 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1039 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1040 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1041 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1042 vdda1 vssa1 6838.97fF
-C1043 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1044 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1045 top_pll_v1_0/out_to_buffer vssa1 1.54fF
-C1046 top_pll_v1_0/out_to_div vssa1 4.23fF
-C1047 top_pll_v1_0/out_first_buffer vssa1 2.88fF
-C1048 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1049 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1050 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1051 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1052 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1053 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1054 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1055 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1056 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1057 top_pll_v1_0/vco_out vssa1 1.01fF
-C1058 gpio_noesd[7] vssa1 272.21fF
-C1059 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1060 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1061 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1062 io_analog[9] vssa1 7.89fF
-C1063 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C1064 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1065 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
-C1066 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
-C1067 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1068 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1069 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1070 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1071 top_pll_v1_0/out_div_2 vssa1 -1.30fF
-C1072 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1073 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1074 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1075 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1076 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1077 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1078 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1079 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
-C1080 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1081 top_pll_v1_0/nswitch vssa1 3.73fF
-C1082 top_pll_v1_0/biasp vssa1 5.44fF
-C1083 bias_0/iref_2 vssa1 -186.53fF
-C1084 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
-C1085 top_pll_v1_0/pswitch vssa1 3.57fF
-C1086 top_pll_v1_0/lf_vc vssa1 -59.89fF
-C1087 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C48 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C49 top_pll_v1_0/QA io_analog[10] 0.03fF
+C50 bias_0/iref_9 bias_0/iref_8 9.89fF
+C51 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C52 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
+C53 io_analog[6] bias_0/iref_1 13.22fF
+C54 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[3] 0.01fF
+C55 vdda1 bias_0/iref_7 33.08fF
+C56 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
+C57 io_analog[2] bias_0/iref_5 13.88fF
+C58 io_analog[6] bias_0/iref_0 6.93fF
+C59 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C60 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA gpio_noesd[4] 0.42fF
+C61 io_analog[2] io_analog[3] 0.14fF
+C62 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C63 vdda1 bias_0/iref_1 15.26fF
+C64 bias_0/iref_7 bias_0/iref_6 17.40fF
+C65 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C66 gpio_noesd[1] vdda1 214.54fF
+C67 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C68 io_analog[10] gpio_noesd[8] 20.65fF
+C69 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C70 bias_0/iref_2 io_analog[7] 13.22fF
+C71 gpio_noesd[2] vdda1 214.16fF
+C72 vdda1 bias_0/iref_0 15.18fF
+C73 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C74 gpio_noesd[4] io_analog[2] -0.21fF
+C75 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C76 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
+C77 vdda1 bias_0/iref_5 30.67fF
+C78 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C79 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA 0.29fF
+C80 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out 0.21fF
+C81 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C82 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C83 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
+C84 vdda1 io_analog[3] 25.90fF
+C85 io_analog[4] io_analog[6] 0.59fF
+C86 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C87 vdda1 gpio_noesd[3] 120.88fF
+C88 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
+C89 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
+C90 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C91 bias_0/iref_5 bias_0/iref_6 29.11fF
+C92 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C93 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
+C94 vdda1 gpio_noesd[4] 117.64fF
+C95 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
+C96 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C97 vdda1 io_analog[8] 29.93fF
+C98 io_analog[6] io_clamp_low[2] 0.53fF
+C99 io_analog[3] bias_0/iref_6 13.88fF
+C100 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[2] 0.21fF
+C101 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C102 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[4] -0.05fF
+C103 vdda1 gpio_noesd[6] 53.94fF
+C104 io_analog[4] vdda1 182.26fF
+C105 vdda1 top_pll_v1_1/pswitch 0.48fF
+C106 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[3] 0.21fF
+C107 vdda1 gpio_noesd[7] 120.83fF
+C108 bias_0/iref_9 res_amp_top_0/res_amp_sync_v2_0/rst 0.39fF
+C109 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
+C110 io_analog[2] gpio_noesd[5] 0.09fF
+C111 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
+C112 bias_0/iref_9 io_analog[2] 13.88fF
+C113 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
+C114 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C115 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C116 bias_0/iref_7 bias_0/iref_5 10.35fF
+C117 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[4] -0.01fF
+C118 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C119 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C120 io_analog[4] io_clamp_low[0] 0.53fF
+C121 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C122 io_analog[4] bias_0/iref_6 15.97fF
+C123 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C124 bias_0/iref_5 io_analog[5] 0.09fF
+C125 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C126 io_analog[3] bias_0/iref_7 13.88fF
+C127 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in gpio_noesd[4] 0.12fF
+C128 gpio_noesd[2] gpio_noesd[1] 0.30fF
+C129 io_analog[6] bias_0/iref_2 54.67fF
+C130 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# -0.08fF
+C131 io_analog[5] m3_222594_702300# 0.53fF
+C132 vdda1 io_analog[1] 76.56fF
+C133 vdda1 gpio_noesd[5] 124.75fF
+C134 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C135 bias_0/iref_9 vdda1 30.24fF
+C136 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C137 io_analog[2] bias_0/iref_8 13.88fF
+C138 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
+C139 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
+C140 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
+C142 vdda1 io_analog[10] 0.01fF
+C143 vdda1 io_analog[0] 76.77fF
+C144 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C145 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C146 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C147 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C148 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[3] 0.33fF
+C149 io_analog[4] bias_0/iref_7 15.97fF
+C150 vdda1 bias_0/iref_2 3.90fF
+C151 vdda1 top_pll_v1_0/pswitch 0.38fF
+C152 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C153 io_analog[3] bias_0/iref_5 13.88fF
+C154 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out gpio_noesd[4] 0.19fF
+C155 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C156 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C157 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out gpio_noesd[1] 0.57fF
+C158 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C159 vdda1 bias_0/iref_8 31.37fF
+C160 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C161 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C162 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C163 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C164 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C165 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C166 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C167 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C168 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C169 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C170 vdda1 io_analog[7] 29.48fF
+C171 io_analog[4] bias_0/iref_5 15.97fF
+C172 gpio_noesd[4] io_analog[3] -0.78fF
+C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
+C174 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C175 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
+C176 vdda1 gpio_noesd[8] 76.96fF
+C177 bias_0/iref_2 io_analog[9] 14.44fF
+C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
+C179 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[4] -0.13fF
+C180 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
+C181 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C182 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
+C183 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
+C184 vdda1 top_pll_v1_0/biasp 0.03fF
+C185 bias_0/iref_8 bias_0/iref_7 13.23fF
+C186 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C187 vdda1 top_pll_v2_0/nUp 0.01fF
+C188 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C189 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C190 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
+C191 io_analog[3] gpio_noesd[5] 0.12fF
+C192 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C193 bias_0/iref_9 io_analog[3] 13.88fF
+C194 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C195 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C196 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C197 io_in_3v3[0] vssa1 0.41fF
+C198 io_oeb[26] vssa1 0.61fF
+C199 io_in[0] vssa1 0.41fF
+C200 io_out[26] vssa1 0.61fF
+C201 io_out[0] vssa1 0.41fF
+C202 io_in[26] vssa1 0.61fF
+C203 io_oeb[0] vssa1 0.41fF
+C204 io_in_3v3[26] vssa1 0.61fF
+C205 io_in_3v3[1] vssa1 0.41fF
+C206 io_oeb[25] vssa1 0.61fF
+C207 io_in[1] vssa1 0.41fF
+C208 io_out[25] vssa1 0.61fF
+C209 io_out[1] vssa1 0.41fF
+C210 io_in[25] vssa1 0.61fF
+C211 io_oeb[1] vssa1 0.41fF
+C212 io_in_3v3[25] vssa1 0.61fF
+C213 io_in_3v3[2] vssa1 0.41fF
+C214 io_oeb[24] vssa1 0.61fF
+C215 io_in[2] vssa1 0.41fF
+C216 io_out[24] vssa1 0.61fF
+C217 io_out[2] vssa1 0.41fF
+C218 io_in[24] vssa1 0.61fF
+C219 io_oeb[2] vssa1 -0.20fF
+C220 io_in_3v3[3] vssa1 0.41fF
+C221 gpio_noesd[17] vssa1 0.61fF
+C222 io_in[3] vssa1 0.41fF
+C223 gpio_analog[17] vssa1 0.61fF
+C224 io_out[3] vssa1 0.41fF
+C225 io_oeb[3] vssa1 0.41fF
+C226 io_in_3v3[4] vssa1 0.41fF
+C227 io_in[4] vssa1 0.41fF
+C228 io_out[4] vssa1 0.41fF
+C229 io_oeb[4] vssa1 0.41fF
+C230 io_oeb[23] vssa1 0.61fF
+C231 io_out[23] vssa1 0.61fF
+C232 io_in[23] vssa1 0.61fF
+C233 io_in_3v3[23] vssa1 0.61fF
+C234 gpio_noesd[16] vssa1 0.61fF
+C235 io_in_3v3[5] vssa1 0.41fF
+C236 io_in[5] vssa1 -0.20fF
+C237 io_out[5] vssa1 0.41fF
+C238 io_oeb[5] vssa1 0.41fF
+C239 io_oeb[22] vssa1 0.61fF
+C240 io_out[22] vssa1 0.61fF
+C241 io_in[22] vssa1 0.61fF
+C242 io_in_3v3[22] vssa1 0.61fF
+C243 gpio_analog[15] vssa1 0.61fF
+C244 io_in_3v3[6] vssa1 -0.20fF
+C245 io_in[6] vssa1 0.41fF
+C246 io_out[6] vssa1 0.41fF
+C247 io_oeb[6] vssa1 0.41fF
+C248 io_oeb[21] vssa1 0.61fF
+C249 io_out[21] vssa1 0.61fF
+C250 io_in[21] vssa1 0.61fF
+C251 io_in_3v3[21] vssa1 0.61fF
+C252 gpio_noesd[14] vssa1 0.61fF
+C253 gpio_analog[14] vssa1 0.61fF
+C254 vssd2 vssa1 -5.19fF
+C255 vssd1 vssa1 1.13fF
+C256 vdda2 vssa1 -5.19fF
+C257 io_oeb[20] vssa1 0.61fF
+C258 io_out[20] vssa1 0.61fF
+C259 io_in[20] vssa1 0.61fF
+C260 io_in_3v3[20] vssa1 0.61fF
+C261 gpio_noesd[13] vssa1 0.61fF
+C262 gpio_analog[13] vssa1 0.61fF
+C263 gpio_analog[0] vssa1 0.41fF
+C264 gpio_noesd[0] vssa1 0.41fF
+C265 io_in_3v3[7] vssa1 0.41fF
+C266 io_in[7] vssa1 0.41fF
+C267 io_out[7] vssa1 0.41fF
+C268 io_oeb[7] vssa1 0.41fF
+C269 io_oeb[19] vssa1 0.61fF
+C270 io_out[19] vssa1 0.61fF
+C271 io_in[19] vssa1 0.61fF
+C272 io_in_3v3[19] vssa1 0.61fF
+C273 gpio_noesd[12] vssa1 0.61fF
+C274 gpio_analog[12] vssa1 0.61fF
+C275 gpio_analog[1] vssa1 0.41fF
+C276 io_in_3v3[8] vssa1 0.41fF
+C277 io_in[8] vssa1 0.41fF
+C278 io_out[8] vssa1 -0.20fF
+C279 io_oeb[8] vssa1 0.41fF
+C280 gpio_analog[2] vssa1 0.41fF
+C281 io_in_3v3[9] vssa1 0.41fF
+C282 io_in[9] vssa1 0.41fF
+C283 io_out[9] vssa1 0.41fF
+C284 io_oeb[9] vssa1 0.41fF
+C285 gpio_analog[3] vssa1 0.41fF
+C286 io_in_3v3[10] vssa1 0.41fF
+C287 io_in[10] vssa1 0.41fF
+C288 io_out[10] vssa1 0.41fF
+C289 io_oeb[10] vssa1 0.41fF
+C290 gpio_analog[4] vssa1 0.41fF
+C291 io_in_3v3[11] vssa1 0.41fF
+C292 io_in[11] vssa1 0.41fF
+C293 io_out[11] vssa1 0.41fF
+C294 io_oeb[11] vssa1 0.41fF
+C295 gpio_analog[5] vssa1 0.41fF
+C296 io_in_3v3[12] vssa1 0.41fF
+C297 io_in[12] vssa1 0.41fF
+C298 io_out[12] vssa1 0.41fF
+C299 io_oeb[12] vssa1 0.41fF
+C300 gpio_analog[6] vssa1 0.60fF
+C301 io_in_3v3[13] vssa1 0.60fF
+C302 io_in[13] vssa1 0.60fF
+C303 io_out[13] vssa1 0.60fF
+C304 io_oeb[13] vssa1 0.60fF
+C305 io_oeb[18] vssa1 0.61fF
+C306 io_out[18] vssa1 0.61fF
+C307 io_in_3v3[18] vssa1 0.61fF
+C308 gpio_noesd[11] vssa1 0.61fF
+C309 gpio_analog[11] vssa1 0.61fF
+C310 io_oeb[17] vssa1 0.61fF
+C311 io_in[17] vssa1 0.61fF
+C312 io_in_3v3[17] vssa1 0.61fF
+C313 gpio_noesd[10] vssa1 0.61fF
+C314 gpio_analog[10] vssa1 0.61fF
+C315 io_out[16] vssa1 0.61fF
+C316 io_in[16] vssa1 0.61fF
+C317 io_in_3v3[16] vssa1 0.61fF
+C318 gpio_noesd[9] vssa1 0.61fF
+C319 gpio_analog[9] vssa1 0.61fF
+C320 io_oeb[15] vssa1 0.61fF
+C321 io_out[15] vssa1 0.61fF
+C322 io_in[15] vssa1 0.61fF
+C323 io_in_3v3[15] vssa1 0.61fF
+C324 vccd1 vssa1 0.85fF
+C325 gpio_analog[8] vssa1 0.61fF
+C326 io_oeb[14] vssa1 0.61fF
+C327 io_out[14] vssa1 0.61fF
+C328 io_in[14] vssa1 0.61fF
+C329 io_in_3v3[14] vssa1 0.61fF
+C330 vssa2 vssa1 1.66fF
+C331 vccd2 vssa1 0.91fF
+C332 io_clamp_high[0] vssa1 -2.60fF
+C333 io_clamp_low[0] vssa1 0.82fF
+C334 io_clamp_high[2] vssa1 0.66fF
+C335 io_clamp_low[2] vssa1 0.50fF
+C336 user_irq[2] vssa1 0.63fF
+C337 user_irq[1] vssa1 0.63fF
+C338 user_irq[0] vssa1 0.63fF
+C339 user_clock2 vssa1 0.63fF
+C340 la_oenb[127] vssa1 0.63fF
+C341 la_data_in[127] vssa1 0.63fF
+C342 la_oenb[126] vssa1 0.63fF
+C343 la_data_out[126] vssa1 0.63fF
+C344 la_data_in[126] vssa1 0.63fF
+C345 la_oenb[125] vssa1 0.63fF
+C346 la_data_out[125] vssa1 0.63fF
+C347 la_data_in[125] vssa1 0.63fF
+C348 la_oenb[124] vssa1 0.63fF
+C349 la_data_out[124] vssa1 0.63fF
+C350 la_data_in[124] vssa1 0.63fF
+C351 la_oenb[123] vssa1 0.63fF
+C352 la_data_out[123] vssa1 0.63fF
+C353 la_oenb[122] vssa1 0.63fF
+C354 la_data_out[122] vssa1 0.63fF
+C355 la_data_in[122] vssa1 0.63fF
+C356 la_oenb[121] vssa1 0.63fF
+C357 la_data_out[121] vssa1 0.63fF
+C358 la_data_in[121] vssa1 0.63fF
+C359 la_oenb[120] vssa1 0.63fF
+C360 la_data_out[120] vssa1 0.63fF
+C361 la_data_in[120] vssa1 0.63fF
+C362 la_oenb[119] vssa1 0.63fF
+C363 la_data_out[119] vssa1 0.63fF
+C364 la_data_in[119] vssa1 0.63fF
+C365 la_oenb[118] vssa1 0.63fF
+C366 la_data_out[118] vssa1 0.63fF
+C367 la_data_in[118] vssa1 0.63fF
+C368 la_oenb[117] vssa1 0.63fF
+C369 la_data_out[117] vssa1 0.63fF
+C370 la_data_in[117] vssa1 0.63fF
+C371 la_data_out[116] vssa1 0.63fF
+C372 la_data_in[116] vssa1 0.63fF
+C373 la_oenb[115] vssa1 0.63fF
+C374 la_data_out[115] vssa1 0.63fF
+C375 la_data_in[115] vssa1 0.63fF
+C376 la_oenb[114] vssa1 0.63fF
+C377 la_data_out[114] vssa1 0.63fF
+C378 la_data_in[114] vssa1 0.63fF
+C379 la_oenb[113] vssa1 0.63fF
+C380 la_data_out[113] vssa1 0.63fF
+C381 la_data_in[113] vssa1 0.63fF
+C382 la_oenb[112] vssa1 0.63fF
+C383 la_data_in[112] vssa1 0.63fF
+C384 la_oenb[111] vssa1 0.63fF
+C385 la_data_out[111] vssa1 0.63fF
+C386 la_data_in[111] vssa1 0.63fF
+C387 la_oenb[110] vssa1 0.63fF
+C388 la_data_out[110] vssa1 0.63fF
+C389 la_data_in[110] vssa1 0.63fF
+C390 la_oenb[109] vssa1 0.63fF
+C391 la_data_out[109] vssa1 0.63fF
+C392 la_data_in[109] vssa1 0.63fF
+C393 la_oenb[108] vssa1 0.63fF
+C394 la_data_out[108] vssa1 0.63fF
+C395 la_oenb[107] vssa1 0.63fF
+C396 la_data_out[107] vssa1 0.63fF
+C397 la_data_in[107] vssa1 0.63fF
+C398 la_oenb[106] vssa1 0.63fF
+C399 la_data_out[106] vssa1 0.63fF
+C400 la_oenb[105] vssa1 0.63fF
+C401 la_data_out[105] vssa1 0.63fF
+C402 la_data_in[105] vssa1 0.63fF
+C403 la_oenb[104] vssa1 0.63fF
+C404 la_data_out[104] vssa1 0.63fF
+C405 la_data_in[104] vssa1 0.63fF
+C406 la_oenb[103] vssa1 0.63fF
+C407 la_data_out[103] vssa1 0.63fF
+C408 la_data_in[103] vssa1 0.63fF
+C409 la_oenb[102] vssa1 0.63fF
+C410 la_data_out[102] vssa1 0.63fF
+C411 la_data_in[102] vssa1 0.63fF
+C412 la_data_out[101] vssa1 0.63fF
+C413 la_data_in[101] vssa1 0.63fF
+C414 la_oenb[100] vssa1 0.63fF
+C415 la_data_out[100] vssa1 0.63fF
+C416 la_data_in[100] vssa1 0.63fF
+C417 la_oenb[99] vssa1 0.63fF
+C418 la_data_out[99] vssa1 0.63fF
+C419 la_data_in[99] vssa1 0.63fF
+C420 la_oenb[98] vssa1 0.63fF
+C421 la_data_out[98] vssa1 0.63fF
+C422 la_data_in[98] vssa1 0.63fF
+C423 la_oenb[97] vssa1 0.63fF
+C424 la_data_in[97] vssa1 0.63fF
+C425 la_oenb[96] vssa1 0.63fF
+C426 la_data_out[96] vssa1 0.63fF
+C427 la_data_in[96] vssa1 0.63fF
+C428 la_oenb[95] vssa1 0.63fF
+C429 la_data_out[95] vssa1 0.63fF
+C430 la_data_in[95] vssa1 0.63fF
+C431 la_oenb[94] vssa1 0.63fF
+C432 la_data_out[94] vssa1 0.63fF
+C433 la_data_in[94] vssa1 0.63fF
+C434 la_oenb[93] vssa1 0.63fF
+C435 la_data_out[93] vssa1 0.63fF
+C436 la_oenb[92] vssa1 0.63fF
+C437 la_data_out[92] vssa1 0.63fF
+C438 la_data_in[92] vssa1 0.63fF
+C439 la_oenb[91] vssa1 0.63fF
+C440 la_data_out[91] vssa1 0.63fF
+C441 la_oenb[90] vssa1 0.63fF
+C442 la_data_out[90] vssa1 0.63fF
+C443 la_data_in[90] vssa1 0.63fF
+C444 la_oenb[89] vssa1 0.63fF
+C445 la_data_out[89] vssa1 0.63fF
+C446 la_data_in[89] vssa1 0.63fF
+C447 la_oenb[88] vssa1 0.63fF
+C448 la_data_out[88] vssa1 0.63fF
+C449 la_data_in[88] vssa1 0.63fF
+C450 la_oenb[87] vssa1 0.63fF
+C451 la_data_out[87] vssa1 0.63fF
+C452 la_data_in[87] vssa1 0.63fF
+C453 la_data_out[86] vssa1 0.63fF
+C454 la_data_in[86] vssa1 0.63fF
+C455 la_oenb[85] vssa1 0.63fF
+C456 la_data_out[85] vssa1 0.63fF
+C457 la_data_in[85] vssa1 0.63fF
+C458 la_oenb[84] vssa1 0.63fF
+C459 la_data_out[84] vssa1 0.63fF
+C460 la_data_in[84] vssa1 0.63fF
+C461 la_oenb[83] vssa1 0.63fF
+C462 la_data_out[83] vssa1 0.63fF
+C463 la_data_in[83] vssa1 0.63fF
+C464 la_oenb[82] vssa1 0.63fF
+C465 la_data_in[82] vssa1 0.63fF
+C466 la_oenb[81] vssa1 0.63fF
+C467 la_data_out[81] vssa1 0.63fF
+C468 la_data_in[81] vssa1 0.63fF
+C469 la_oenb[80] vssa1 0.63fF
+C470 la_data_out[80] vssa1 0.63fF
+C471 la_data_in[80] vssa1 0.63fF
+C472 la_oenb[79] vssa1 0.63fF
+C473 la_data_out[79] vssa1 0.63fF
+C474 la_data_in[79] vssa1 0.63fF
+C475 la_oenb[78] vssa1 0.63fF
+C476 la_data_out[78] vssa1 0.63fF
+C477 la_data_in[78] vssa1 0.63fF
+C478 la_oenb[77] vssa1 0.63fF
+C479 la_data_out[77] vssa1 0.63fF
+C480 la_data_in[77] vssa1 0.63fF
+C481 la_oenb[76] vssa1 0.63fF
+C482 la_data_out[76] vssa1 0.63fF
+C483 la_oenb[75] vssa1 0.63fF
+C484 la_data_out[75] vssa1 0.63fF
+C485 la_data_in[75] vssa1 0.63fF
+C486 la_oenb[74] vssa1 0.63fF
+C487 la_data_out[74] vssa1 0.63fF
+C488 la_data_in[74] vssa1 0.63fF
+C489 la_oenb[73] vssa1 0.63fF
+C490 la_data_out[73] vssa1 0.63fF
+C491 la_data_in[73] vssa1 0.63fF
+C492 la_oenb[72] vssa1 0.63fF
+C493 la_data_out[72] vssa1 0.63fF
+C494 la_data_in[72] vssa1 0.63fF
+C495 la_data_out[71] vssa1 0.63fF
+C496 la_data_in[71] vssa1 0.63fF
+C497 la_oenb[70] vssa1 0.63fF
+C498 la_data_out[70] vssa1 0.63fF
+C499 la_data_in[70] vssa1 0.63fF
+C500 la_oenb[69] vssa1 0.63fF
+C501 la_data_out[69] vssa1 0.63fF
+C502 la_data_in[69] vssa1 0.63fF
+C503 la_oenb[68] vssa1 0.63fF
+C504 la_data_out[68] vssa1 0.63fF
+C505 la_data_in[68] vssa1 0.63fF
+C506 la_oenb[67] vssa1 0.63fF
+C507 la_data_in[67] vssa1 0.63fF
+C508 la_oenb[66] vssa1 0.63fF
+C509 la_data_out[66] vssa1 0.63fF
+C510 la_data_in[66] vssa1 0.63fF
+C511 la_oenb[65] vssa1 0.63fF
+C512 la_data_out[65] vssa1 0.26fF
+C513 la_data_in[65] vssa1 0.63fF
+C514 la_oenb[64] vssa1 0.63fF
+C515 la_data_out[64] vssa1 0.63fF
+C516 la_data_in[64] vssa1 0.63fF
+C517 la_oenb[63] vssa1 0.63fF
+C518 la_data_out[63] vssa1 0.63fF
+C519 la_data_in[63] vssa1 0.63fF
+C520 la_oenb[62] vssa1 0.63fF
+C521 la_data_out[62] vssa1 0.63fF
+C522 la_data_in[62] vssa1 0.63fF
+C523 la_oenb[61] vssa1 0.63fF
+C524 la_data_out[61] vssa1 0.63fF
+C525 la_oenb[60] vssa1 0.63fF
+C526 la_data_out[60] vssa1 0.63fF
+C527 la_data_in[60] vssa1 0.63fF
+C528 la_oenb[59] vssa1 0.63fF
+C529 la_data_out[59] vssa1 0.63fF
+C530 la_data_in[59] vssa1 0.63fF
+C531 la_oenb[58] vssa1 0.63fF
+C532 la_data_out[58] vssa1 0.63fF
+C533 la_data_in[58] vssa1 0.63fF
+C534 la_oenb[57] vssa1 0.63fF
+C535 la_data_out[57] vssa1 0.63fF
+C536 la_data_in[57] vssa1 0.63fF
+C537 la_data_out[56] vssa1 0.63fF
+C538 la_data_in[56] vssa1 0.63fF
+C539 la_oenb[55] vssa1 0.63fF
+C540 la_data_out[55] vssa1 0.63fF
+C541 la_data_in[55] vssa1 0.63fF
+C542 la_oenb[54] vssa1 0.63fF
+C543 la_data_out[54] vssa1 0.63fF
+C544 la_data_in[54] vssa1 0.63fF
+C545 la_oenb[53] vssa1 0.63fF
+C546 la_data_out[53] vssa1 0.63fF
+C547 la_data_in[53] vssa1 0.63fF
+C548 la_oenb[52] vssa1 0.63fF
+C549 la_data_in[52] vssa1 0.63fF
+C550 la_oenb[51] vssa1 0.63fF
+C551 la_data_out[51] vssa1 0.63fF
+C552 la_data_in[51] vssa1 0.63fF
+C553 la_oenb[50] vssa1 0.63fF
+C554 la_data_in[50] vssa1 0.63fF
+C555 la_oenb[49] vssa1 0.63fF
+C556 la_data_out[49] vssa1 0.63fF
+C557 la_data_in[49] vssa1 0.63fF
+C558 la_oenb[48] vssa1 0.63fF
+C559 la_data_out[48] vssa1 0.63fF
+C560 la_data_in[48] vssa1 0.63fF
+C561 la_oenb[47] vssa1 0.63fF
+C562 la_data_out[47] vssa1 0.63fF
+C563 la_data_in[47] vssa1 0.63fF
+C564 la_oenb[46] vssa1 0.63fF
+C565 la_data_out[46] vssa1 0.63fF
+C566 la_oenb[45] vssa1 0.63fF
+C567 la_data_out[45] vssa1 0.63fF
+C568 la_data_in[45] vssa1 0.63fF
+C569 la_oenb[44] vssa1 0.63fF
+C570 la_data_out[44] vssa1 0.63fF
+C571 la_data_in[44] vssa1 0.63fF
+C572 la_oenb[43] vssa1 0.63fF
+C573 la_data_out[43] vssa1 0.63fF
+C574 la_data_in[43] vssa1 0.63fF
+C575 la_oenb[42] vssa1 0.63fF
+C576 la_data_out[42] vssa1 0.63fF
+C577 la_data_in[42] vssa1 0.63fF
+C578 la_data_out[41] vssa1 0.63fF
+C579 la_data_in[41] vssa1 0.63fF
+C580 la_oenb[40] vssa1 0.63fF
+C581 la_data_out[40] vssa1 0.63fF
+C582 la_data_in[40] vssa1 0.63fF
+C583 la_oenb[39] vssa1 0.63fF
+C584 la_data_out[39] vssa1 0.63fF
+C585 la_data_in[39] vssa1 0.63fF
+C586 la_oenb[38] vssa1 0.63fF
+C587 la_data_out[38] vssa1 0.63fF
+C588 la_data_in[38] vssa1 0.63fF
+C589 la_oenb[37] vssa1 0.63fF
+C590 la_data_out[37] vssa1 0.26fF
+C591 la_data_in[37] vssa1 0.63fF
+C592 la_oenb[36] vssa1 0.63fF
+C593 la_data_out[36] vssa1 0.63fF
+C594 la_data_in[36] vssa1 0.63fF
+C595 la_oenb[35] vssa1 0.63fF
+C596 la_data_in[35] vssa1 0.63fF
+C597 la_oenb[34] vssa1 0.63fF
+C598 la_data_out[34] vssa1 0.63fF
+C599 la_data_in[34] vssa1 0.63fF
+C600 la_oenb[33] vssa1 0.63fF
+C601 la_data_out[33] vssa1 0.63fF
+C602 la_data_in[33] vssa1 0.63fF
+C603 la_oenb[32] vssa1 0.63fF
+C604 la_data_out[32] vssa1 0.63fF
+C605 la_data_in[32] vssa1 0.63fF
+C606 la_oenb[31] vssa1 0.63fF
+C607 la_data_out[31] vssa1 0.63fF
+C608 la_oenb[30] vssa1 0.63fF
+C609 la_data_out[30] vssa1 0.63fF
+C610 la_data_in[30] vssa1 0.63fF
+C611 la_oenb[29] vssa1 0.63fF
+C612 la_data_out[29] vssa1 0.63fF
+C613 la_data_in[29] vssa1 0.63fF
+C614 la_oenb[28] vssa1 0.63fF
+C615 la_data_out[28] vssa1 0.63fF
+C616 la_data_in[28] vssa1 0.63fF
+C617 la_oenb[27] vssa1 0.63fF
+C618 la_data_out[27] vssa1 0.63fF
+C619 la_data_in[27] vssa1 0.63fF
+C620 la_data_out[26] vssa1 0.63fF
+C621 la_data_in[26] vssa1 0.63fF
+C622 la_oenb[25] vssa1 0.63fF
+C623 la_data_out[25] vssa1 0.63fF
+C624 la_data_in[25] vssa1 0.63fF
+C625 la_oenb[24] vssa1 0.63fF
+C626 la_data_out[24] vssa1 0.63fF
+C627 la_data_in[24] vssa1 0.63fF
+C628 la_oenb[23] vssa1 0.63fF
+C629 la_data_out[23] vssa1 0.63fF
+C630 la_data_in[23] vssa1 0.63fF
+C631 la_oenb[22] vssa1 0.63fF
+C632 la_data_out[22] vssa1 0.63fF
+C633 la_data_in[22] vssa1 0.63fF
+C634 la_oenb[21] vssa1 0.63fF
+C635 la_data_out[21] vssa1 0.63fF
+C636 la_data_in[21] vssa1 0.63fF
+C637 la_oenb[20] vssa1 0.63fF
+C638 la_data_in[20] vssa1 0.63fF
+C639 la_oenb[19] vssa1 0.63fF
+C640 la_data_out[19] vssa1 0.63fF
+C641 la_data_in[19] vssa1 0.63fF
+C642 la_oenb[18] vssa1 0.63fF
+C643 la_data_out[18] vssa1 0.63fF
+C644 la_data_in[18] vssa1 0.63fF
+C645 la_oenb[17] vssa1 0.63fF
+C646 la_data_out[17] vssa1 0.63fF
+C647 la_data_in[17] vssa1 0.63fF
+C648 la_oenb[16] vssa1 0.63fF
+C649 la_data_out[16] vssa1 0.63fF
+C650 la_oenb[15] vssa1 0.63fF
+C651 la_data_out[15] vssa1 0.63fF
+C652 la_data_in[15] vssa1 0.63fF
+C653 la_oenb[14] vssa1 0.63fF
+C654 la_data_out[14] vssa1 0.63fF
+C655 la_data_in[14] vssa1 0.63fF
+C656 la_oenb[13] vssa1 0.63fF
+C657 la_data_out[13] vssa1 0.63fF
+C658 la_data_in[13] vssa1 0.63fF
+C659 la_oenb[12] vssa1 0.63fF
+C660 la_data_out[12] vssa1 0.63fF
+C661 la_data_in[12] vssa1 0.63fF
+C662 la_data_out[11] vssa1 0.63fF
+C663 la_data_in[11] vssa1 0.63fF
+C664 la_oenb[10] vssa1 0.63fF
+C665 la_data_out[10] vssa1 0.63fF
+C666 la_data_in[10] vssa1 0.63fF
+C667 la_data_out[9] vssa1 0.63fF
+C668 la_data_in[9] vssa1 0.63fF
+C669 la_oenb[8] vssa1 0.63fF
+C670 la_data_out[8] vssa1 0.63fF
+C671 la_data_in[8] vssa1 0.63fF
+C672 la_oenb[7] vssa1 0.63fF
+C673 la_data_out[7] vssa1 0.63fF
+C674 la_data_in[7] vssa1 0.63fF
+C675 la_oenb[6] vssa1 0.63fF
+C676 la_data_out[6] vssa1 0.63fF
+C677 la_data_in[6] vssa1 0.63fF
+C678 la_oenb[5] vssa1 0.63fF
+C679 la_data_in[5] vssa1 0.63fF
+C680 la_oenb[4] vssa1 0.63fF
+C681 la_data_out[4] vssa1 0.63fF
+C682 la_data_in[4] vssa1 0.63fF
+C683 la_oenb[3] vssa1 0.63fF
+C684 la_data_out[3] vssa1 0.63fF
+C685 la_data_in[3] vssa1 0.63fF
+C686 la_oenb[2] vssa1 0.63fF
+C687 la_data_out[2] vssa1 0.63fF
+C688 la_data_in[2] vssa1 0.63fF
+C689 la_oenb[1] vssa1 0.63fF
+C690 la_data_out[1] vssa1 0.63fF
+C691 la_oenb[0] vssa1 0.63fF
+C692 la_data_out[0] vssa1 0.63fF
+C693 la_data_in[0] vssa1 0.63fF
+C694 wbs_dat_o[31] vssa1 0.63fF
+C695 wbs_dat_i[31] vssa1 0.63fF
+C696 wbs_adr_i[31] vssa1 0.63fF
+C697 wbs_dat_o[30] vssa1 0.63fF
+C698 wbs_dat_i[30] vssa1 0.63fF
+C699 wbs_adr_i[30] vssa1 0.63fF
+C700 wbs_dat_o[29] vssa1 0.63fF
+C701 wbs_dat_i[29] vssa1 0.63fF
+C702 wbs_adr_i[29] vssa1 0.63fF
+C703 wbs_dat_i[28] vssa1 0.63fF
+C704 wbs_adr_i[28] vssa1 0.63fF
+C705 wbs_dat_o[27] vssa1 0.63fF
+C706 wbs_dat_i[27] vssa1 0.63fF
+C707 wbs_adr_i[27] vssa1 0.63fF
+C708 wbs_dat_i[26] vssa1 0.63fF
+C709 wbs_adr_i[26] vssa1 0.63fF
+C710 wbs_dat_o[25] vssa1 0.63fF
+C711 wbs_dat_i[25] vssa1 0.63fF
+C712 wbs_adr_i[25] vssa1 0.63fF
+C713 wbs_dat_o[24] vssa1 0.63fF
+C714 wbs_dat_i[24] vssa1 0.63fF
+C715 wbs_adr_i[24] vssa1 0.63fF
+C716 wbs_dat_o[23] vssa1 0.63fF
+C717 wbs_dat_i[23] vssa1 0.63fF
+C718 wbs_adr_i[23] vssa1 0.63fF
+C719 wbs_dat_o[22] vssa1 0.63fF
+C720 wbs_adr_i[22] vssa1 0.63fF
+C721 wbs_dat_o[21] vssa1 0.63fF
+C722 wbs_dat_i[21] vssa1 0.63fF
+C723 wbs_adr_i[21] vssa1 0.63fF
+C724 wbs_dat_o[20] vssa1 0.63fF
+C725 wbs_dat_i[20] vssa1 0.63fF
+C726 wbs_adr_i[20] vssa1 0.63fF
+C727 wbs_dat_o[19] vssa1 0.63fF
+C728 wbs_dat_i[19] vssa1 0.63fF
+C729 wbs_adr_i[19] vssa1 0.63fF
+C730 wbs_dat_o[18] vssa1 0.63fF
+C731 wbs_dat_i[18] vssa1 0.63fF
+C732 wbs_dat_o[17] vssa1 0.63fF
+C733 wbs_dat_i[17] vssa1 0.63fF
+C734 wbs_adr_i[17] vssa1 0.63fF
+C735 wbs_dat_o[16] vssa1 0.63fF
+C736 wbs_dat_i[16] vssa1 0.63fF
+C737 wbs_adr_i[16] vssa1 0.63fF
+C738 wbs_dat_o[15] vssa1 0.63fF
+C739 wbs_dat_i[15] vssa1 0.63fF
+C740 wbs_adr_i[15] vssa1 0.63fF
+C741 wbs_dat_o[14] vssa1 0.63fF
+C742 wbs_dat_i[14] vssa1 0.63fF
+C743 wbs_adr_i[14] vssa1 0.63fF
+C744 wbs_dat_o[13] vssa1 0.63fF
+C745 wbs_dat_i[13] vssa1 0.63fF
+C746 wbs_adr_i[13] vssa1 0.63fF
+C747 wbs_dat_o[12] vssa1 0.63fF
+C748 wbs_dat_i[12] vssa1 0.63fF
+C749 wbs_adr_i[12] vssa1 0.63fF
+C750 wbs_dat_i[11] vssa1 0.63fF
+C751 wbs_adr_i[11] vssa1 0.63fF
+C752 wbs_dat_o[10] vssa1 0.63fF
+C753 wbs_dat_i[10] vssa1 0.63fF
+C754 wbs_adr_i[10] vssa1 0.63fF
+C755 wbs_dat_o[9] vssa1 0.63fF
+C756 wbs_dat_i[9] vssa1 0.63fF
+C757 wbs_adr_i[9] vssa1 0.63fF
+C758 wbs_dat_o[8] vssa1 0.63fF
+C759 wbs_dat_i[8] vssa1 0.63fF
+C760 wbs_adr_i[8] vssa1 0.63fF
+C761 wbs_dat_o[7] vssa1 0.63fF
+C762 wbs_adr_i[7] vssa1 0.63fF
+C763 wbs_dat_o[6] vssa1 0.63fF
+C764 wbs_dat_i[6] vssa1 0.63fF
+C765 wbs_adr_i[6] vssa1 0.63fF
+C766 wbs_dat_o[5] vssa1 0.63fF
+C767 wbs_dat_i[5] vssa1 0.63fF
+C768 wbs_adr_i[5] vssa1 0.63fF
+C769 wbs_dat_o[4] vssa1 0.63fF
+C770 wbs_dat_i[4] vssa1 0.63fF
+C771 wbs_adr_i[4] vssa1 0.63fF
+C772 wbs_sel_i[3] vssa1 0.63fF
+C773 wbs_dat_o[3] vssa1 0.63fF
+C774 wbs_adr_i[3] vssa1 0.63fF
+C775 wbs_sel_i[2] vssa1 0.63fF
+C776 wbs_dat_o[2] vssa1 0.63fF
+C777 wbs_dat_i[2] vssa1 0.63fF
+C778 wbs_adr_i[2] vssa1 0.63fF
+C779 wbs_dat_o[1] vssa1 0.63fF
+C780 wbs_dat_i[1] vssa1 0.63fF
+C781 wbs_adr_i[1] vssa1 0.63fF
+C782 wbs_sel_i[0] vssa1 0.63fF
+C783 wbs_dat_o[0] vssa1 0.63fF
+C784 wbs_dat_i[0] vssa1 0.63fF
+C785 wbs_adr_i[0] vssa1 0.63fF
+C786 wbs_we_i vssa1 0.63fF
+C787 wbs_stb_i vssa1 0.63fF
+C788 wbs_cyc_i vssa1 0.63fF
+C789 wbs_ack_o vssa1 0.63fF
+C790 wb_rst_i vssa1 0.63fF
+C791 m3_226242_702300# vssa1 -1.31fF
+C792 m3_222594_702300# vssa1 0.55fF
+C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C803 top_pll_v2_0/QB vssa1 4.35fF
+C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C817 top_pll_v2_0/QA vssa1 4.22fF
+C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C824 top_pll_v2_0/nUp vssa1 5.39fF
+C825 top_pll_v2_0/Up vssa1 1.85fF
+C826 top_pll_v2_0/Down vssa1 6.19fF
+C827 top_pll_v2_0/nDown vssa1 -3.53fF
+C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C879 top_pll_v2_0/out_to_div vssa1 4.23fF
+C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C890 top_pll_v2_0/vco_out vssa1 1.01fF
+C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C895 io_analog[8] vssa1 13.78fF
+C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C915 gpio_noesd[8] vssa1 210.79fF
+C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C917 top_pll_v2_0/nswitch vssa1 3.73fF
+C918 top_pll_v2_0/biasp vssa1 5.44fF
+C919 bias_0/iref_1 vssa1 -91.53fF
+C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C921 top_pll_v2_0/pswitch vssa1 3.57fF
+C922 io_analog[5] vssa1 33.29fF
+C923 bias_0/iref_4 vssa1 1.17fF
+C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C925 bias_0/iref_3 vssa1 0.64fF
+C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C929 bias_0/m1_20168_984# vssa1 56.92fF
+C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C946 top_pll_v1_1/QB vssa1 4.35fF
+C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
+C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
+C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C960 top_pll_v1_1/QA vssa1 4.22fF
+C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C965 io_analog[10] vssa1 503.33fF
+C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C968 top_pll_v1_1/nUp vssa1 5.39fF
+C969 top_pll_v1_1/Up vssa1 1.85fF
+C970 top_pll_v1_1/Down vssa1 6.19fF
+C971 top_pll_v1_1/nDown vssa1 -3.53fF
+C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
+C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
+C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
+C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
+C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
+C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
+C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
+C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
+C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
+C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
+C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1034 top_pll_v1_1/vco_out vssa1 1.01fF
+C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
+C1039 io_analog[7] vssa1 24.61fF
+C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
+C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
+C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
+C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
+C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1057 top_pll_v1_1/nswitch vssa1 3.73fF
+C1058 top_pll_v1_1/biasp vssa1 5.44fF
+C1059 bias_0/iref_0 vssa1 -81.35fF
+C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
+C1061 top_pll_v1_1/pswitch vssa1 3.57fF
+C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
+C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1074 top_pll_v1_0/QB vssa1 4.35fF
+C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1088 top_pll_v1_0/QA vssa1 4.22fF
+C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1095 top_pll_v1_0/nUp vssa1 5.39fF
+C1096 top_pll_v1_0/Up vssa1 1.85fF
+C1097 top_pll_v1_0/Down vssa1 6.19fF
+C1098 top_pll_v1_0/nDown vssa1 -3.53fF
+C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1161 top_pll_v1_0/vco_out vssa1 1.01fF
+C1162 gpio_noesd[7] vssa1 272.21fF
+C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1167 io_analog[9] vssa1 7.89fF
+C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1185 top_pll_v1_0/nswitch vssa1 3.73fF
+C1186 top_pll_v1_0/biasp vssa1 5.44fF
+C1187 bias_0/iref_2 vssa1 -178.91fF
+C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1189 top_pll_v1_0/pswitch vssa1 3.57fF
+C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1192 bias_0/iref_6 vssa1 -645.65fF
+C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1194 io_analog[1] vssa1 74.58fF
+C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1196 bias_0/iref_5 vssa1 -623.45fF
+C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1198 io_analog[0] vssa1 -154.61fF
+C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1201 bias_0/iref_8 vssa1 -189.06fF
+C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1203 bias_0/iref_7 vssa1 -205.18fF
+C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1206 gpio_noesd[5] vssa1 122.09fF
+C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1210 gpio_noesd[6] vssa1 325.91fF
+C1211 gpio_noesd[4] vssa1 116.78fF
+C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1214 bias_0/iref_9 vssa1 -181.57fF
+C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1216 io_analog[3] vssa1 -119.52fF
+C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1219 io_analog[2] vssa1 -131.04fF
+C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1246 gpio_noesd[3] vssa1 213.06fF
+C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1258 gpio_noesd[2] vssa1 216.13fF
+C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1263 gpio_noesd[1] vssa1 230.09fF
+C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1293 io_analog[4] vssa1 -253.69fF
+C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1297 io_analog[6] vssa1 -26.69fF
+C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1303 vdda1 vssa1 7275.97fF
+C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
 .ends
 
diff --git a/mag/extractions/user_analog_project_wrapper_pex_rc.spice b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
index dc4db9c..73f3f79 100644
--- a/mag/extractions/user_analog_project_wrapper_pex_rc.spice
+++ b/mag/extractions/user_analog_project_wrapper_pex_rc.spice
@@ -1,5 +1,4080 @@
 * NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130A
 
+.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
+X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_111_n125# 0.13fF
+C1 a_81_n156# a_n15_n156# 0.02fF
+C2 w_n311_n344# a_15_n125# 0.09fF
+C3 a_15_n125# a_n173_n125# 0.13fF
+C4 a_n81_n125# a_15_n125# 0.36fF
+C5 w_n311_n344# a_n173_n125# 0.14fF
+C6 a_111_n125# a_15_n125# 0.36fF
+C7 a_n81_n125# w_n311_n344# 0.09fF
+C8 a_111_n125# w_n311_n344# 0.14fF
+C9 a_n15_n156# a_n111_n156# 0.02fF
+C10 a_n81_n125# a_n173_n125# 0.36fF
+C11 a_111_n125# a_n173_n125# 0.08fF
+C12 a_111_n125# VSUBS 0.03fF
+C13 a_15_n125# VSUBS 0.03fF
+C14 a_n81_n125# VSUBS 0.03fF
+C15 a_n173_n125# VSUBS 0.03fF
+C16 a_81_n156# VSUBS 0.05fF
+C17 a_n15_n156# VSUBS 0.05fF
+C18 a_n111_n156# VSUBS 0.05fF
+C19 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
++ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n173_n125# a_111_n125# 0.08fF
+C1 a_n111_n151# a_n15_n151# 0.02fF
+C2 a_n81_n125# a_n173_n125# 0.36fF
+C3 a_111_n125# a_15_n125# 0.36fF
+C4 a_n15_n151# a_81_n151# 0.02fF
+C5 a_n81_n125# a_15_n125# 0.36fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 a_111_n125# w_n311_n335# 0.17fF
+C9 a_15_n125# w_n311_n335# 0.12fF
+C10 a_n81_n125# w_n311_n335# 0.12fF
+C11 a_n173_n125# w_n311_n335# 0.17fF
+C12 a_81_n151# w_n311_n335# 0.05fF
+C13 a_n15_n151# w_n311_n335# 0.05fF
+C14 a_n111_n151# w_n311_n335# 0.05fF
+.ends
+
+.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
+Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
++ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
+Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
++ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
+C0 m1_45_n513# vdd 0.69fF
+C1 m1_187_n605# vdd 0.55fF
+C2 m1_187_n605# m1_45_n513# 0.36fF
+C3 m1_187_n605# vss 0.93fF
+C4 m1_45_n513# vss 1.31fF
+C5 vdd vss 3.36fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
++ w_n311_n344# a_n81_n125#
+X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_15_n125# 0.36fF
+C1 a_n173_n125# a_n81_n125# 0.36fF
+C2 a_n81_n125# w_n311_n344# 0.09fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_n173_n125# a_111_n125# 0.08fF
+C5 w_n311_n344# a_111_n125# 0.14fF
+C6 a_n81_n125# a_111_n125# 0.13fF
+C7 a_n173_n125# a_15_n125# 0.13fF
+C8 w_n311_n344# a_15_n125# 0.09fF
+C9 a_n173_n125# w_n311_n344# 0.14fF
+C10 a_111_n125# VSUBS 0.03fF
+C11 a_15_n125# VSUBS 0.03fF
+C12 a_n81_n125# VSUBS 0.03fF
+C13 a_n173_n125# VSUBS 0.03fF
+C14 a_n111_n186# VSUBS 0.26fF
+C15 w_n311_n344# VSUBS 2.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
++ a_n111_n151# a_n81_n125#
+X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_n81_n125# a_n173_n125# 0.36fF
+C1 a_n173_n125# a_111_n125# 0.08fF
+C2 a_n81_n125# a_15_n125# 0.36fF
+C3 a_15_n125# a_111_n125# 0.36fF
+C4 a_15_n125# a_n173_n125# 0.13fF
+C5 a_n81_n125# a_111_n125# 0.13fF
+C6 a_111_n125# w_n311_n335# 0.17fF
+C7 a_15_n125# w_n311_n335# 0.12fF
+C8 a_n81_n125# w_n311_n335# 0.12fF
+C9 a_n173_n125# w_n311_n335# 0.17fF
+C10 a_n111_n151# w_n311_n335# 0.25fF
+.ends
+
+.subckt inverter_cp_x1 out in vss vdd
+Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
+Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
+C0 out vdd 0.10fF
+C1 out in 0.32fF
+C2 out vss 0.77fF
+C3 in vss 0.95fF
+C4 vdd vss 3.13fF
+.ends
+
+.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
++ nCLK_d
+Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
+Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
+Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
+Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
+C0 nCLK_d vdd 0.03fF
+C1 inverter_cp_x1_2/in vdd 0.21fF
+C2 CLK_d vdd 0.03fF
+C3 inverter_cp_x1_0/out CLK 0.31fF
+C4 CLK_d inverter_cp_x1_2/in 0.12fF
+C5 inverter_cp_x1_0/out nCLK_d 0.11fF
+C6 inverter_cp_x1_0/out vdd 0.28fF
+C7 CLK vdd 0.36fF
+C8 inverter_cp_x1_2/in CLK 0.31fF
+C9 inverter_cp_x1_2/in vss 2.01fF
+C10 CLK_d vss 0.96fF
+C11 inverter_cp_x1_0/out vss 1.97fF
+C12 CLK vss 3.03fF
+C13 nCLK_d vss 1.44fF
+C14 vdd vss 16.51fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
++ a_n63_n192#
+X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 w_n263_n314# a_n33_n95# 0.08fF
+C1 a_63_n95# a_n33_n95# 0.28fF
+C2 w_n263_n314# a_63_n95# 0.11fF
+C3 a_n125_n95# a_n33_n95# 0.28fF
+C4 a_n125_n95# w_n263_n314# 0.11fF
+C5 a_n125_n95# a_63_n95# 0.10fF
+C6 a_63_n95# VSUBS 0.03fF
+C7 a_n33_n95# VSUBS 0.03fF
+C8 a_n125_n95# VSUBS 0.03fF
+C9 a_n63_n192# VSUBS 0.20fF
+C10 w_n263_n314# VSUBS 1.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
++ a_n173_n125# a_n81_n125#
+X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
+C0 a_15_n125# a_n81_n125# 0.36fF
+C1 a_15_n125# a_111_n125# 0.36fF
+C2 a_15_n125# a_n129_n213# 0.10fF
+C3 a_n81_n125# a_n173_n125# 0.36fF
+C4 a_111_n125# a_n173_n125# 0.08fF
+C5 a_n129_n213# a_n173_n125# 0.02fF
+C6 a_111_n125# a_n81_n125# 0.13fF
+C7 a_n129_n213# a_n81_n125# 0.10fF
+C8 a_111_n125# a_n129_n213# 0.01fF
+C9 a_15_n125# a_n173_n125# 0.13fF
+C10 a_111_n125# w_n311_n335# 0.05fF
+C11 a_15_n125# w_n311_n335# 0.05fF
+C12 a_n81_n125# w_n311_n335# 0.05fF
+C13 a_n173_n125# w_n311_n335# 0.05fF
+C14 a_n129_n213# w_n311_n335# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
+X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
+C0 a_n125_n95# a_n33_n95# 0.88fF
+C1 a_n125_n95# a_n81_n183# 0.16fF
+C2 a_n33_n95# a_n81_n183# 0.10fF
+C3 a_n33_n95# w_n263_n305# 0.07fF
+C4 a_n125_n95# w_n263_n305# 0.13fF
+C5 a_n81_n183# w_n263_n305# 0.31fF
+.ends
+
+.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
+Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
+Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
+Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
+C0 m1_657_280# Q 0.94fF
+C1 m1_657_280# nQ 1.41fF
+C2 Q nD 0.05fF
+C3 nD nQ 0.05fF
+C4 Q nQ 0.93fF
+C5 m1_657_280# CLK 0.24fF
+C6 Q D 0.05fF
+C7 nQ D 0.05fF
+C8 Q vdd 0.16fF
+C9 vdd nQ 0.16fF
+C10 nQ vss 1.16fF
+C11 D vss 0.53fF
+C12 Q vss -0.55fF
+C13 m1_657_280# vss 1.88fF
+C14 nD vss 0.16fF
+C15 CLK vss 0.87fF
+C16 vdd vss 5.98fF
+.ends
+
+.subckt DFlipFlop latch_diff_0/m1_657_280# vss vdd latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
++ nQ latch_diff_0/nD Q latch_diff_1/nD latch_diff_1/m1_657_280# D latch_diff_0/D CLK
++ clock_inverter_0/inverter_cp_x1_0/out nCLK
+Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
++ latch_diff_0/D latch_diff_0/nD clock_inverter
+Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
++ latch_diff_0/nD latch_diff_0/D latch_diff
+Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
++ latch_diff
+C0 latch_diff_0/m1_657_280# latch_diff_1/m1_657_280# 0.18fF
+C1 latch_diff_1/D latch_diff_1/nD 0.33fF
+C2 vdd latch_diff_0/D 0.09fF
+C3 latch_diff_1/m1_657_280# latch_diff_1/nD 0.42fF
+C4 vdd latch_diff_1/D 0.03fF
+C5 latch_diff_0/nD vdd 0.14fF
+C6 latch_diff_0/D latch_diff_1/D 0.11fF
+C7 vdd clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C8 nQ latch_diff_1/nD 0.08fF
+C9 latch_diff_0/m1_657_280# latch_diff_1/nD 0.14fF
+C10 latch_diff_0/nD latch_diff_1/D 0.41fF
+C11 Q latch_diff_1/nD 0.01fF
+C12 latch_diff_1/m1_657_280# latch_diff_1/D 0.32fF
+C13 latch_diff_0/m1_657_280# latch_diff_0/D 0.37fF
+C14 nQ latch_diff_1/D 0.11fF
+C15 latch_diff_0/m1_657_280# latch_diff_1/D 0.43fF
+C16 vdd latch_diff_1/nD 0.02fF
+C17 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
+C18 latch_diff_0/D latch_diff_1/nD 0.04fF
+C19 nQ vss 0.57fF
+C20 Q vss -0.92fF
+C21 latch_diff_1/m1_657_280# vss 0.64fF
+C22 nCLK vss 0.83fF
+C23 latch_diff_1/nD vss 1.83fF
+C24 latch_diff_1/D vss -0.30fF
+C25 latch_diff_0/m1_657_280# vss 0.72fF
+C26 CLK vss 0.83fF
+C27 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C28 latch_diff_0/D vss 1.29fF
+C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C30 D vss 3.27fF
+C31 latch_diff_0/nD vss 1.74fF
+C32 vdd vss 32.62fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
++ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
+X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n221_n84# w_n359_n303# 0.08fF
+C1 a_63_n84# w_n359_n303# 0.06fF
+C2 w_n359_n303# a_n33_n84# 0.05fF
+C3 a_n129_n84# w_n359_n303# 0.06fF
+C4 a_n221_n84# a_63_n84# 0.05fF
+C5 a_n221_n84# a_n33_n84# 0.09fF
+C6 a_n129_n84# a_n221_n84# 0.24fF
+C7 a_63_n84# a_n33_n84# 0.24fF
+C8 a_159_n84# w_n359_n303# 0.08fF
+C9 a_n129_n84# a_63_n84# 0.09fF
+C10 a_n159_n110# a_n63_n110# 0.02fF
+C11 a_n129_n84# a_n33_n84# 0.24fF
+C12 a_159_n84# a_n221_n84# 0.04fF
+C13 a_159_n84# a_63_n84# 0.24fF
+C14 a_159_n84# a_n33_n84# 0.09fF
+C15 a_n129_n84# a_159_n84# 0.05fF
+C16 a_33_n110# a_n63_n110# 0.02fF
+C17 a_33_n110# a_129_n110# 0.02fF
+C18 a_159_n84# VSUBS 0.03fF
+C19 a_63_n84# VSUBS 0.03fF
+C20 a_n33_n84# VSUBS 0.03fF
+C21 a_n129_n84# VSUBS 0.03fF
+C22 a_n221_n84# VSUBS 0.03fF
+C23 a_129_n110# VSUBS 0.05fF
+C24 a_33_n110# VSUBS 0.05fF
+C25 a_n63_n110# VSUBS 0.05fF
+C26 a_n159_n110# VSUBS 0.05fF
+C27 w_n359_n303# VSUBS 2.19fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
++ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
+X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n33_n42# a_n129_n42# 0.12fF
+C1 a_n159_n68# a_n63_n68# 0.02fF
+C2 a_n33_n42# a_n221_n42# 0.05fF
+C3 a_63_n42# a_n33_n42# 0.12fF
+C4 a_159_n42# a_n33_n42# 0.05fF
+C5 a_n129_n42# a_n221_n42# 0.12fF
+C6 a_63_n42# a_n129_n42# 0.05fF
+C7 a_159_n42# a_n129_n42# 0.03fF
+C8 a_63_n42# a_n221_n42# 0.03fF
+C9 a_159_n42# a_n221_n42# 0.02fF
+C10 a_63_n42# a_159_n42# 0.12fF
+C11 a_129_n68# a_33_n68# 0.02fF
+C12 a_33_n68# a_n63_n68# 0.02fF
+C13 a_159_n42# w_n359_n252# 0.07fF
+C14 a_63_n42# w_n359_n252# 0.06fF
+C15 a_n33_n42# w_n359_n252# 0.06fF
+C16 a_n129_n42# w_n359_n252# 0.06fF
+C17 a_n221_n42# w_n359_n252# 0.07fF
+C18 a_129_n68# w_n359_n252# 0.05fF
+C19 a_33_n68# w_n359_n252# 0.05fF
+C20 a_n63_n68# w_n359_n252# 0.05fF
+C21 a_n159_n68# w_n359_n252# 0.05fF
+.ends
+
+.subckt inverter_min_x4 vdd in vss out
+Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
+Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
+C0 in out 0.67fF
+C1 out vdd 0.62fF
+C2 in vdd 0.33fF
+C3 in vss 1.89fF
+C4 out vss 0.66fF
+C5 vdd vss 3.87fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_BDRUME VSUBS a_351_n84# a_n513_n84# a_639_n84# a_159_n84#
++ a_n321_n84# a_447_n84# a_n753_n181# a_n609_n84# w_n935_n303# a_n129_n84# a_735_n84#
++ a_255_n84# a_n417_n84# a_63_n84# a_543_n84# a_n705_n84# a_n225_n84# a_n797_n84#
++ a_n33_n84#
+X0 a_n705_n84# a_n753_n181# a_n797_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X1 a_n513_n84# a_n753_n181# a_n609_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X2 a_n417_n84# a_n753_n181# a_n513_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X3 a_n321_n84# a_n753_n181# a_n417_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X4 a_n225_n84# a_n753_n181# a_n321_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X5 a_n129_n84# a_n753_n181# a_n225_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X6 a_n609_n84# a_n753_n181# a_n705_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X7 a_63_n84# a_n753_n181# a_n33_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X8 a_n33_n84# a_n753_n181# a_n129_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X9 a_159_n84# a_n753_n181# a_63_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X10 a_255_n84# a_n753_n181# a_159_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X11 a_351_n84# a_n753_n181# a_255_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X12 a_543_n84# a_n753_n181# a_447_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X13 a_447_n84# a_n753_n181# a_351_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X14 a_639_n84# a_n753_n181# a_543_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+X15 a_735_n84# a_n753_n181# a_639_n84# w_n935_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_543_n84# a_639_n84# 0.24fF
+C1 a_n417_n84# a_n321_n84# 0.24fF
+C2 a_447_n84# a_639_n84# 0.09fF
+C3 a_n129_n84# a_n417_n84# 0.05fF
+C4 a_n129_n84# a_159_n84# 0.05fF
+C5 a_n33_n84# a_n225_n84# 0.09fF
+C6 a_159_n84# a_63_n84# 0.24fF
+C7 w_n935_n303# a_n797_n84# 0.08fF
+C8 a_255_n84# a_159_n84# 0.24fF
+C9 a_735_n84# w_n935_n303# 0.08fF
+C10 a_351_n84# a_735_n84# 0.04fF
+C11 a_n513_n84# a_n705_n84# 0.09fF
+C12 a_n417_n84# a_n225_n84# 0.09fF
+C13 a_159_n84# a_n225_n84# 0.04fF
+C14 a_351_n84# a_63_n84# 0.05fF
+C15 a_n609_n84# a_n705_n84# 0.24fF
+C16 a_n513_n84# a_n417_n84# 0.24fF
+C17 a_255_n84# a_351_n84# 0.24fF
+C18 a_n129_n84# a_n321_n84# 0.09fF
+C19 a_n609_n84# a_n417_n84# 0.09fF
+C20 a_n321_n84# a_63_n84# 0.04fF
+C21 a_543_n84# a_159_n84# 0.04fF
+C22 a_n129_n84# a_63_n84# 0.09fF
+C23 a_447_n84# a_159_n84# 0.05fF
+C24 a_n129_n84# a_255_n84# 0.04fF
+C25 a_n513_n84# w_n935_n303# 0.02fF
+C26 a_255_n84# a_63_n84# 0.09fF
+C27 a_n513_n84# a_n797_n84# 0.05fF
+C28 a_n609_n84# w_n935_n303# 0.03fF
+C29 a_n609_n84# a_n797_n84# 0.09fF
+C30 a_n321_n84# a_n225_n84# 0.24fF
+C31 a_543_n84# w_n935_n303# 0.03fF
+C32 a_351_n84# a_543_n84# 0.09fF
+C33 a_n129_n84# a_n225_n84# 0.24fF
+C34 a_n513_n84# a_n321_n84# 0.09fF
+C35 a_447_n84# w_n935_n303# 0.02fF
+C36 a_447_n84# a_351_n84# 0.24fF
+C37 a_n129_n84# a_n513_n84# 0.04fF
+C38 a_735_n84# a_543_n84# 0.09fF
+C39 a_n225_n84# a_63_n84# 0.05fF
+C40 a_n609_n84# a_n321_n84# 0.05fF
+C41 a_447_n84# a_735_n84# 0.05fF
+C42 a_639_n84# w_n935_n303# 0.04fF
+C43 a_351_n84# a_639_n84# 0.05fF
+C44 a_735_n84# a_639_n84# 0.24fF
+C45 a_n33_n84# a_n417_n84# 0.04fF
+C46 a_n33_n84# a_159_n84# 0.09fF
+C47 a_255_n84# a_543_n84# 0.05fF
+C48 a_447_n84# a_63_n84# 0.04fF
+C49 a_447_n84# a_255_n84# 0.09fF
+C50 a_n513_n84# a_n225_n84# 0.05fF
+C51 a_n417_n84# a_n705_n84# 0.05fF
+C52 a_n609_n84# a_n225_n84# 0.04fF
+C53 a_255_n84# a_639_n84# 0.04fF
+C54 a_n513_n84# a_n609_n84# 0.24fF
+C55 a_n33_n84# a_351_n84# 0.04fF
+C56 w_n935_n303# a_n705_n84# 0.04fF
+C57 a_n33_n84# a_n321_n84# 0.05fF
+C58 a_n797_n84# a_n705_n84# 0.24fF
+C59 a_n129_n84# a_n33_n84# 0.24fF
+C60 a_447_n84# a_543_n84# 0.24fF
+C61 a_351_n84# a_159_n84# 0.09fF
+C62 a_n417_n84# a_n797_n84# 0.04fF
+C63 a_n33_n84# a_63_n84# 0.24fF
+C64 a_n33_n84# a_255_n84# 0.05fF
+C65 a_n321_n84# a_n705_n84# 0.04fF
+C66 a_735_n84# VSUBS 0.03fF
+C67 a_639_n84# VSUBS 0.03fF
+C68 a_543_n84# VSUBS 0.03fF
+C69 a_447_n84# VSUBS 0.03fF
+C70 a_351_n84# VSUBS 0.03fF
+C71 a_255_n84# VSUBS 0.03fF
+C72 a_159_n84# VSUBS 0.03fF
+C73 a_63_n84# VSUBS 0.03fF
+C74 a_n33_n84# VSUBS 0.03fF
+C75 a_n129_n84# VSUBS 0.03fF
+C76 a_n225_n84# VSUBS 0.03fF
+C77 a_n321_n84# VSUBS 0.03fF
+C78 a_n417_n84# VSUBS 0.03fF
+C79 a_n513_n84# VSUBS 0.03fF
+C80 a_n609_n84# VSUBS 0.03fF
+C81 a_n705_n84# VSUBS 0.03fF
+C82 a_n797_n84# VSUBS 0.03fF
+C83 a_n753_n181# VSUBS 2.56fF
+C84 w_n935_n303# VSUBS 4.96fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQE8KM a_543_n42# a_n705_n42# a_n225_n42# a_n797_n42#
++ a_n33_n42# a_351_n42# a_n513_n42# a_639_n42# a_159_n42# w_n935_n252# a_n757_64#
++ a_n321_n42# a_447_n42# a_n609_n42# a_n129_n42# a_735_n42# a_255_n42# a_n417_n42#
++ a_63_n42#
+X0 a_63_n42# a_n757_64# a_n33_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X1 a_n33_n42# a_n757_64# a_n129_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X2 a_351_n42# a_n757_64# a_255_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X3 a_159_n42# a_n757_64# a_63_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X4 a_255_n42# a_n757_64# a_159_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X5 a_447_n42# a_n757_64# a_351_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X6 a_543_n42# a_n757_64# a_447_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X7 a_735_n42# a_n757_64# a_639_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X8 a_639_n42# a_n757_64# a_543_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X9 a_n321_n42# a_n757_64# a_n417_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X10 a_n705_n42# a_n757_64# a_n797_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X11 a_n513_n42# a_n757_64# a_n609_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X12 a_n417_n42# a_n757_64# a_n513_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X13 a_n225_n42# a_n757_64# a_n321_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X14 a_n129_n42# a_n757_64# a_n225_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+X15 a_n609_n42# a_n757_64# a_n705_n42# w_n935_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_159_n42# a_543_n42# 0.02fF
+C1 a_n705_n42# a_n417_n42# 0.03fF
+C2 a_n129_n42# a_n321_n42# 0.05fF
+C3 a_n797_n42# a_n513_n42# 0.03fF
+C4 a_n321_n42# a_63_n42# 0.02fF
+C5 a_639_n42# a_543_n42# 0.12fF
+C6 a_n321_n42# a_n225_n42# 0.12fF
+C7 a_735_n42# a_351_n42# 0.02fF
+C8 a_n321_n42# a_n417_n42# 0.12fF
+C9 a_n705_n42# a_n513_n42# 0.05fF
+C10 a_n797_n42# a_n705_n42# 0.12fF
+C11 a_447_n42# a_159_n42# 0.03fF
+C12 a_255_n42# a_543_n42# 0.03fF
+C13 a_447_n42# a_639_n42# 0.05fF
+C14 a_n321_n42# a_n513_n42# 0.05fF
+C15 a_159_n42# a_n33_n42# 0.05fF
+C16 a_351_n42# a_543_n42# 0.05fF
+C17 a_447_n42# a_63_n42# 0.02fF
+C18 a_n225_n42# a_n609_n42# 0.02fF
+C19 a_n129_n42# a_n33_n42# 0.12fF
+C20 a_n129_n42# a_159_n42# 0.03fF
+C21 a_n417_n42# a_n609_n42# 0.05fF
+C22 a_n33_n42# a_63_n42# 0.12fF
+C23 a_159_n42# a_63_n42# 0.12fF
+C24 a_n321_n42# a_n705_n42# 0.02fF
+C25 a_n225_n42# a_n33_n42# 0.05fF
+C26 a_159_n42# a_n225_n42# 0.02fF
+C27 a_735_n42# a_543_n42# 0.05fF
+C28 a_255_n42# a_447_n42# 0.05fF
+C29 a_n417_n42# a_n33_n42# 0.02fF
+C30 a_n129_n42# a_63_n42# 0.05fF
+C31 a_n129_n42# a_n225_n42# 0.12fF
+C32 a_447_n42# a_351_n42# 0.12fF
+C33 a_n225_n42# a_63_n42# 0.03fF
+C34 a_n513_n42# a_n609_n42# 0.12fF
+C35 a_n797_n42# a_n609_n42# 0.05fF
+C36 a_n129_n42# a_n417_n42# 0.03fF
+C37 a_255_n42# a_n33_n42# 0.03fF
+C38 a_255_n42# a_159_n42# 0.12fF
+C39 a_351_n42# a_n33_n42# 0.02fF
+C40 a_351_n42# a_159_n42# 0.05fF
+C41 a_n417_n42# a_n225_n42# 0.05fF
+C42 a_255_n42# a_639_n42# 0.02fF
+C43 a_735_n42# a_447_n42# 0.03fF
+C44 a_255_n42# a_n129_n42# 0.02fF
+C45 a_n705_n42# a_n609_n42# 0.12fF
+C46 a_255_n42# a_63_n42# 0.05fF
+C47 a_351_n42# a_639_n42# 0.03fF
+C48 a_n129_n42# a_n513_n42# 0.02fF
+C49 a_351_n42# a_63_n42# 0.03fF
+C50 a_n513_n42# a_n225_n42# 0.03fF
+C51 a_n321_n42# a_n609_n42# 0.03fF
+C52 a_n513_n42# a_n417_n42# 0.12fF
+C53 a_735_n42# a_639_n42# 0.12fF
+C54 a_n797_n42# a_n417_n42# 0.02fF
+C55 a_447_n42# a_543_n42# 0.12fF
+C56 a_255_n42# a_351_n42# 0.12fF
+C57 a_n321_n42# a_n33_n42# 0.03fF
+C58 a_735_n42# w_n935_n252# 0.07fF
+C59 a_639_n42# w_n935_n252# 0.05fF
+C60 a_543_n42# w_n935_n252# 0.05fF
+C61 a_447_n42# w_n935_n252# 0.04fF
+C62 a_351_n42# w_n935_n252# 0.04fF
+C63 a_255_n42# w_n935_n252# 0.04fF
+C64 a_159_n42# w_n935_n252# 0.04fF
+C65 a_63_n42# w_n935_n252# 0.04fF
+C66 a_n33_n42# w_n935_n252# 0.04fF
+C67 a_n129_n42# w_n935_n252# 0.04fF
+C68 a_n225_n42# w_n935_n252# 0.04fF
+C69 a_n321_n42# w_n935_n252# 0.04fF
+C70 a_n417_n42# w_n935_n252# 0.04fF
+C71 a_n513_n42# w_n935_n252# 0.04fF
+C72 a_n609_n42# w_n935_n252# 0.05fF
+C73 a_n705_n42# w_n935_n252# 0.05fF
+C74 a_n797_n42# w_n935_n252# 0.07fF
+C75 a_n757_64# w_n935_n252# 2.44fF
+.ends
+
+.subckt inverter_min_x16 in out vss vdd
+Xsky130_fd_pr__pfet_01v8_BDRUME_0 vss out vdd vdd out vdd vdd in out vdd vdd out vdd
++ out vdd out vdd out out out sky130_fd_pr__pfet_01v8_BDRUME
+Xsky130_fd_pr__nfet_01v8_QQE8KM_0 out vss out out out out vss vss out vss in vss vss
++ out vss out vss out vss sky130_fd_pr__nfet_01v8_QQE8KM
+C0 vdd in 1.15fF
+C1 in out 1.40fF
+C2 vdd out 1.63fF
+C3 out vss 0.98fF
+C4 in vss 7.30fF
+C5 vdd vss 10.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_75PKJG VSUBS a_n33_n102# w_n359_n321# a_n177_n199#
++ a_63_n102# a_n129_n102# a_n221_n102# a_25_n199# a_159_n102#
+X0 a_159_n102# a_25_n199# a_63_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_25_n199# a_n33_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X2 a_n129_n102# a_n177_n199# a_n221_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X3 a_n33_n102# a_n177_n199# a_n129_n102# w_n359_n321# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_159_n102# a_n33_n102# 0.11fF
+C1 w_n359_n321# a_n33_n102# 0.06fF
+C2 a_n129_n102# a_63_n102# 0.11fF
+C3 a_159_n102# a_n221_n102# 0.05fF
+C4 w_n359_n321# a_n221_n102# 0.10fF
+C5 a_63_n102# a_n33_n102# 0.30fF
+C6 w_n359_n321# a_159_n102# 0.10fF
+C7 a_n129_n102# a_n33_n102# 0.30fF
+C8 a_63_n102# a_n221_n102# 0.07fF
+C9 a_25_n199# a_n177_n199# 0.07fF
+C10 a_63_n102# a_159_n102# 0.30fF
+C11 a_n129_n102# a_n221_n102# 0.30fF
+C12 a_63_n102# w_n359_n321# 0.07fF
+C13 a_n129_n102# a_159_n102# 0.07fF
+C14 a_n33_n102# a_n221_n102# 0.11fF
+C15 a_n129_n102# w_n359_n321# 0.07fF
+C16 a_159_n102# VSUBS 0.03fF
+C17 a_63_n102# VSUBS 0.03fF
+C18 a_n33_n102# VSUBS 0.03fF
+C19 a_n129_n102# VSUBS 0.03fF
+C20 a_n221_n102# VSUBS 0.03fF
+C21 a_25_n199# VSUBS 0.22fF
+C22 a_n177_n199# VSUBS 0.22fF
+C23 w_n359_n321# VSUBS 2.35fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XRJ78J a_n33_n102# w_n263_n312# a_63_n102# a_n125_n102#
++ a_n81_124#
+X0 a_n33_n102# a_n81_124# a_n125_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+X1 a_63_n102# a_n81_124# a_n33_n102# w_n263_n312# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.02e+06u l=150000u
+C0 a_n33_n102# a_n125_n102# 0.30fF
+C1 a_n125_n102# a_63_n102# 0.11fF
+C2 a_n33_n102# a_63_n102# 0.30fF
+C3 a_63_n102# w_n263_n312# 0.06fF
+C4 a_n33_n102# w_n263_n312# 0.08fF
+C5 a_n125_n102# w_n263_n312# 0.12fF
+C6 a_n81_124# w_n263_n312# 0.21fF
+.ends
+
+.subckt nand_logic avss1p8 in1 avdd1p8 in2 out m1_21_n341#
+Xsky130_fd_pr__pfet_01v8_75PKJG_0 avss1p8 avdd1p8 avdd1p8 in1 out out avdd1p8 in2
++ avdd1p8 sky130_fd_pr__pfet_01v8_75PKJG
+Xsky130_fd_pr__nfet_01v8_XRJ78J_0 m1_21_n341# avss1p8 avss1p8 avss1p8 in1 sky130_fd_pr__nfet_01v8_XRJ78J
+Xsky130_fd_pr__nfet_01v8_XRJ78J_1 out avss1p8 m1_21_n341# m1_21_n341# in2 sky130_fd_pr__nfet_01v8_XRJ78J
+C0 m1_21_n341# avdd1p8 0.01fF
+C1 in2 out 0.37fF
+C2 in1 in2 0.07fF
+C3 in2 avdd1p8 0.02fF
+C4 m1_21_n341# out 0.13fF
+C5 in1 out 0.10fF
+C6 out avdd1p8 0.20fF
+C7 in1 m1_21_n341# 0.25fF
+C8 m1_21_n341# avss1p8 0.92fF
+C9 out avss1p8 0.47fF
+C10 in2 avss1p8 0.91fF
+C11 in1 avss1p8 0.93fF
+C12 avdd1p8 avss1p8 2.37fF
+.ends
+
+.subckt res_amp_sync_v2 avdd1p8 DFlipFlop_4/Q vss clkn DFlipFlop_4/latch_diff_1/m1_657_280#
++ DFlipFlop_4/nQ DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_0/D DFlipFlop_3/Q
++ DFlipFlop_3/D DFlipFlop_4/D DFlipFlop_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_1/D DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_4/latch_diff_0/D DFlipFlop_3/latch_diff_1/D clk_amp DFlipFlop_3/nQ clkp
++ rst
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nQ DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_0/latch_diff_0/D clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/nQ DFlipFlop_1/latch_diff_0/nD
++ DFlipFlop_2/D DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D DFlipFlop_3/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/Q DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ DFlipFlop_2/Q DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D clkp DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ DFlipFlop_3/Q DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# DFlipFlop_3/D
++ DFlipFlop_3/latch_diff_0/D clkp DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_0 avdd1p8 DFlipFlop_0/Q vss DFlipFlop_3/D inverter_min_x4
+Xinverter_min_x4_1 avdd1p8 nand_logic_0/out vss DFlipFlop_4/D inverter_min_x4
+XDFlipFlop_4 DFlipFlop_4/latch_diff_0/m1_657_280# vss avdd1p8 DFlipFlop_4/latch_diff_1/D
++ DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_4/nQ DFlipFlop_4/latch_diff_0/nD
++ DFlipFlop_4/Q DFlipFlop_4/latch_diff_1/nD DFlipFlop_4/latch_diff_1/m1_657_280# DFlipFlop_4/D
++ DFlipFlop_4/latch_diff_0/D clkp DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out
++ clkn DFlipFlop
+Xinverter_min_x4_2 avdd1p8 DFlipFlop_2/D vss DFlipFlop_1/D inverter_min_x4
+Xinverter_min_x4_3 avdd1p8 nand_logic_1/out vss rst inverter_min_x4
+Xinverter_min_x4_4 avdd1p8 DFlipFlop_4/Q vss inverter_min_x4_4/out inverter_min_x4
+Xinverter_min_x16_0 inverter_min_x4_4/out clk_amp vss avdd1p8 inverter_min_x16
+Xnand_logic_0 vss DFlipFlop_2/Q avdd1p8 DFlipFlop_3/Q nand_logic_0/out nand_logic_0/m1_21_n341#
++ nand_logic
+Xnand_logic_1 vss DFlipFlop_4/D avdd1p8 clkp nand_logic_1/out nand_logic_1/m1_21_n341#
++ nand_logic
+C0 DFlipFlop_2/latch_diff_1/nD clkn 0.17fF
+C1 clkp DFlipFlop_2/latch_diff_1/D 0.15fF
+C2 DFlipFlop_3/latch_diff_1/D clkp 0.15fF
+C3 clkp DFlipFlop_4/Q 0.20fF
+C4 nand_logic_0/m1_21_n341# DFlipFlop_3/Q 0.07fF
+C5 DFlipFlop_0/latch_diff_0/D clkn 0.12fF
+C6 DFlipFlop_2/latch_diff_1/D clkn 0.08fF
+C7 DFlipFlop_3/latch_diff_1/D clkn 0.08fF
+C8 DFlipFlop_2/latch_diff_1/D DFlipFlop_3/Q 0.03fF
+C9 avdd1p8 DFlipFlop_2/D 4.16fF
+C10 DFlipFlop_3/Q DFlipFlop_4/Q 0.11fF
+C11 inverter_min_x4_4/out clk_amp 0.12fF
+C12 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.54fF
+C13 DFlipFlop_3/D avdd1p8 4.16fF
+C14 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out clkp -0.31fF
+C15 avdd1p8 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.01fF
+C16 nand_logic_1/out nand_logic_1/m1_21_n341# 0.01fF
+C17 DFlipFlop_3/nQ avdd1p8 0.03fF
+C18 avdd1p8 DFlipFlop_4/D 0.52fF
+C19 DFlipFlop_0/Q DFlipFlop_1/latch_diff_0/D 0.74fF
+C20 DFlipFlop_1/D DFlipFlop_1/latch_diff_1/D 0.02fF
+C21 DFlipFlop_2/D DFlipFlop_2/latch_diff_1/D 0.03fF
+C22 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/Q 0.55fF
+C23 DFlipFlop_3/D DFlipFlop_0/latch_diff_0/D 0.31fF
+C24 nand_logic_0/out avdd1p8 0.03fF
+C25 nand_logic_0/m1_21_n341# DFlipFlop_4/D 0.02fF
+C26 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in clkn -0.33fF
+C27 DFlipFlop_4/D DFlipFlop_4/Q 0.27fF
+C28 DFlipFlop_4/latch_diff_0/m1_657_280# clkp 0.30fF
+C29 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C30 clkp clkn 0.22fF
+C31 clkp DFlipFlop_3/Q 0.17fF
+C32 nand_logic_0/out nand_logic_0/m1_21_n341# 0.01fF
+C33 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
+C34 DFlipFlop_2/Q clkp 0.11fF
+C35 avdd1p8 inverter_min_x4_4/out 0.09fF
+C36 clkp DFlipFlop_0/latch_diff_0/nD 0.08fF
+C37 DFlipFlop_3/Q clkn 0.12fF
+C38 nand_logic_1/out avdd1p8 0.04fF
+C39 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_4/D 0.42fF
+C40 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/D 0.03fF
+C41 clkp DFlipFlop_0/latch_diff_0/m1_657_280# 0.32fF
+C42 DFlipFlop_0/Q avdd1p8 0.66fF
+C43 DFlipFlop_2/Q DFlipFlop_3/Q 0.09fF
+C44 clkp DFlipFlop_3/latch_diff_0/m1_657_280# 0.30fF
+C45 clkn DFlipFlop_2/latch_diff_0/D 0.12fF
+C46 DFlipFlop_1/D DFlipFlop_2/D 0.02fF
+C47 DFlipFlop_3/D DFlipFlop_1/D 0.28fF
+C48 DFlipFlop_2/D clkp 0.15fF
+C49 DFlipFlop_3/D clkp 0.35fF
+C50 inverter_min_x4_4/out DFlipFlop_4/Q 0.01fF
+C51 DFlipFlop_2/D clkn 0.15fF
+C52 clkp DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.16fF
+C53 DFlipFlop_3/D clkn 0.35fF
+C54 avdd1p8 clk_amp 0.10fF
+C55 DFlipFlop_3/nQ clkp 0.13fF
+C56 DFlipFlop_4/D clkp 0.24fF
+C57 clkn DFlipFlop_3/latch_diff_0/D 0.12fF
+C58 DFlipFlop_4/latch_diff_0/D clkn 0.12fF
+C59 clkp DFlipFlop_4/latch_diff_0/nD 0.08fF
+C60 DFlipFlop_3/nQ clkn 0.10fF
+C61 clkp DFlipFlop_0/latch_diff_1/nD 0.10fF
+C62 DFlipFlop_4/D clkn 0.15fF
+C63 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.02fF
+C64 DFlipFlop_2/D DFlipFlop_2/latch_diff_0/D -0.07fF
+C65 DFlipFlop_1/D DFlipFlop_1/nQ 0.02fF
+C66 DFlipFlop_4/D DFlipFlop_3/Q 0.94fF
+C67 clkn DFlipFlop_0/latch_diff_1/nD 0.17fF
+C68 DFlipFlop_2/latch_diff_0/nD clkp 0.08fF
+C69 DFlipFlop_3/D DFlipFlop_2/D 0.06fF
+C70 DFlipFlop_3/D DFlipFlop_1/latch_diff_1/nD 0.02fF
+C71 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out clkp 0.16fF
+C72 nand_logic_0/out DFlipFlop_3/Q 0.01fF
+C73 nand_logic_0/out DFlipFlop_2/Q 0.02fF
+C74 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/D 0.10fF
+C75 DFlipFlop_3/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.43fF
+C76 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/m1_657_280# 0.25fF
+C77 clkp inverter_min_x4_4/out 0.43fF
+C78 nand_logic_1/out clkp 0.03fF
+C79 DFlipFlop_0/Q DFlipFlop_1/D 0.72fF
+C80 DFlipFlop_2/latch_diff_1/m1_657_280# clkn 0.30fF
+C81 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/nD 0.17fF
+C82 DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_3/Q 0.04fF
+C83 DFlipFlop_4/nQ DFlipFlop_4/Q 0.06fF
+C84 DFlipFlop_3/D DFlipFlop_1/nQ 0.05fF
+C85 DFlipFlop_0/nQ clkp 0.02fF
+C86 DFlipFlop_4/latch_diff_1/D clkp 0.15fF
+C87 DFlipFlop_0/latch_diff_1/m1_657_280# clkn 0.30fF
+C88 DFlipFlop_2/nQ clkp 0.13fF
+C89 DFlipFlop_0/nQ clkn 0.02fF
+C90 DFlipFlop_4/latch_diff_1/D clkn 0.08fF
+C91 nand_logic_1/out rst 0.04fF
+C92 clkp DFlipFlop_4/latch_diff_1/nD 0.10fF
+C93 DFlipFlop_2/nQ clkn 0.02fF
+C94 DFlipFlop_2/nQ DFlipFlop_3/Q 0.02fF
+C95 nand_logic_0/out DFlipFlop_4/D 0.04fF
+C96 clkp clk_amp 0.52fF
+C97 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C98 DFlipFlop_4/latch_diff_1/nD clkn 0.17fF
+C99 avdd1p8 DFlipFlop_4/Q 4.03fF
+C100 nand_logic_1/m1_21_n341# clkp 0.09fF
+C101 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/D 0.41fF
+C102 DFlipFlop_3/D DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
+C103 DFlipFlop_2/latch_diff_0/m1_657_280# clkp 0.30fF
+C104 DFlipFlop_3/D DFlipFlop_0/Q 0.38fF
+C105 DFlipFlop_3/latch_diff_1/m1_657_280# clkn 0.30fF
+C106 DFlipFlop_0/Q DFlipFlop_1/latch_diff_1/nD 0.19fF
+C107 DFlipFlop_0/latch_diff_1/D clkp 0.15fF
+C108 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.03fF
+C109 DFlipFlop_3/D DFlipFlop_0/nQ 0.08fF
+C110 DFlipFlop_2/nQ DFlipFlop_2/D 0.03fF
+C111 nand_logic_1/m1_21_n341# rst 0.02fF
+C112 nand_logic_1/out DFlipFlop_4/D 0.01fF
+C113 DFlipFlop_0/latch_diff_1/D clkn 0.08fF
+C114 DFlipFlop_4/nQ clkp 0.02fF
+C115 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/D 0.49fF
+C116 DFlipFlop_4/nQ clkn 0.02fF
+C117 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avdd1p8 0.03fF
+C118 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C119 DFlipFlop_0/Q DFlipFlop_1/nQ 0.01fF
+C120 DFlipFlop_3/latch_diff_0/nD clkp 0.08fF
+C121 DFlipFlop_1/D avdd1p8 2.55fF
+C122 avdd1p8 clkp 0.53fF
+C123 DFlipFlop_3/D DFlipFlop_0/latch_diff_1/D 0.08fF
+C124 clkp DFlipFlop_3/latch_diff_1/nD 0.10fF
+C125 nand_logic_1/m1_21_n341# DFlipFlop_4/D 0.09fF
+C126 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in clkn 0.14fF
+C127 avdd1p8 clkn -1.00fF
+C128 clkn DFlipFlop_4/latch_diff_1/m1_657_280# 0.30fF
+C129 avdd1p8 DFlipFlop_3/Q 0.76fF
+C130 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avdd1p8 0.01fF
+C131 DFlipFlop_2/latch_diff_1/nD clkp 0.20fF
+C132 clkn DFlipFlop_3/latch_diff_1/nD 0.17fF
+C133 avdd1p8 DFlipFlop_2/Q 0.05fF
+C134 avdd1p8 rst 0.02fF
+C135 nand_logic_1/m1_21_n341# vss 0.86fF
+C136 nand_logic_0/m1_21_n341# vss 0.90fF
+C137 clk_amp vss 0.43fF
+C138 inverter_min_x4_4/out vss 5.90fF
+C139 nand_logic_1/out vss 1.76fF
+C140 rst vss 0.71fF
+C141 DFlipFlop_4/nQ vss 0.48fF
+C142 DFlipFlop_4/Q vss -2.08fF
+C143 DFlipFlop_4/latch_diff_1/m1_657_280# vss 0.57fF
+C144 DFlipFlop_4/latch_diff_1/nD vss 0.57fF
+C145 DFlipFlop_4/latch_diff_1/D vss -1.73fF
+C146 DFlipFlop_4/latch_diff_0/m1_657_280# vss 0.57fF
+C147 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C148 DFlipFlop_4/latch_diff_0/D vss 0.96fF
+C149 DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
+C150 DFlipFlop_4/D vss 4.59fF
+C151 DFlipFlop_4/latch_diff_0/nD vss 1.14fF
+C152 nand_logic_0/out vss 1.26fF
+C153 DFlipFlop_0/Q vss -3.86fF
+C154 DFlipFlop_3/nQ vss 0.50fF
+C155 DFlipFlop_3/Q vss -2.01fF
+C156 DFlipFlop_3/latch_diff_1/m1_657_280# vss 0.72fF
+C157 clkn vss -2.25fF
+C158 DFlipFlop_3/latch_diff_1/nD vss 0.58fF
+C159 DFlipFlop_3/latch_diff_1/D vss -1.72fF
+C160 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
+C161 clkp vss -22.80fF
+C162 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C163 DFlipFlop_3/latch_diff_0/D vss 0.96fF
+C164 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C165 DFlipFlop_3/D vss 1.64fF
+C166 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C167 avdd1p8 vss 196.01fF
+C168 DFlipFlop_2/nQ vss 0.48fF
+C169 DFlipFlop_2/Q vss -1.05fF
+C170 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.65fF
+C171 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C172 DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 DFlipFlop_2/D vss -0.35fF
+C178 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
+C179 DFlipFlop_1/nQ vss 0.48fF
+C180 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.59fF
+C181 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C182 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C183 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C184 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C185 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C186 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C187 DFlipFlop_1/D vss -1.00fF
+C188 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C189 DFlipFlop_0/nQ vss 0.48fF
+C190 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.59fF
+C191 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
+C192 DFlipFlop_0/latch_diff_1/D vss -1.73fF
+C193 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
+C194 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C195 DFlipFlop_0/latch_diff_0/D vss 0.96fF
+C196 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C197 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_4L9VGG VSUBS a_291_n200# w_n487_n419# a_35_n200#
++ a_n291_n238# a_n93_n200# a_163_n200# a_n349_n200# a_n221_n200#
+X0 a_291_n200# a_n291_n238# a_163_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_n221_n200# a_n291_n238# a_n349_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_35_n200# a_n291_n238# a_n93_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_163_n200# a_n291_n238# a_35_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_n93_n200# a_n291_n238# a_n221_n200# w_n487_n419# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_163_n200# a_n221_n200# 0.09fF
+C1 a_n349_n200# a_n221_n200# 0.36fF
+C2 a_n221_n200# a_n291_n238# 0.08fF
+C3 w_n487_n419# a_n221_n200# 0.08fF
+C4 a_35_n200# a_n221_n200# 0.15fF
+C5 a_n93_n200# a_n221_n200# 0.36fF
+C6 a_163_n200# a_n291_n238# 0.08fF
+C7 a_163_n200# w_n487_n419# 0.08fF
+C8 a_163_n200# a_291_n200# 0.36fF
+C9 a_n349_n200# w_n487_n419# 0.18fF
+C10 w_n487_n419# a_n291_n238# 0.30fF
+C11 a_163_n200# a_35_n200# 0.36fF
+C12 a_291_n200# w_n487_n419# 0.18fF
+C13 a_n349_n200# a_35_n200# 0.09fF
+C14 a_35_n200# a_n291_n238# 0.08fF
+C15 a_163_n200# a_n93_n200# 0.15fF
+C16 a_35_n200# w_n487_n419# 0.06fF
+C17 a_35_n200# a_291_n200# 0.15fF
+C18 a_n349_n200# a_n93_n200# 0.15fF
+C19 a_n93_n200# a_n291_n238# 0.08fF
+C20 a_n93_n200# w_n487_n419# 0.06fF
+C21 a_n93_n200# a_291_n200# 0.09fF
+C22 a_n93_n200# a_35_n200# 0.36fF
+C23 a_291_n200# VSUBS 0.03fF
+C24 a_163_n200# VSUBS 0.03fF
+C25 a_35_n200# VSUBS 0.03fF
+C26 a_n93_n200# VSUBS 0.03fF
+C27 a_n221_n200# VSUBS 0.03fF
+C28 a_n349_n200# VSUBS 0.03fF
+C29 a_n291_n238# VSUBS 0.72fF
+C30 w_n487_n419# VSUBS 4.21fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_L78GGD a_n73_n73# w_n211_n221# a_15_n73# a_n33_33#
+X0 a_15_n73# a_n33_33# a_n73_n73# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
+C0 a_n73_n73# a_n33_33# 0.02fF
+C1 a_15_n73# a_n73_n73# 0.15fF
+C2 a_15_n73# a_n33_33# 0.02fF
+C3 a_15_n73# w_n211_n221# 0.11fF
+C4 a_n73_n73# w_n211_n221# 0.11fF
+C5 a_n33_33# w_n211_n221# 0.18fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_6RX2PQ VSUBS w_n211_n268# a_15_n48# a_n33_n145# a_n73_n48#
+X0 a_15_n48# a_n33_n145# a_n73_n48# w_n211_n268# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
+C0 a_n73_n48# a_15_n48# 0.29fF
+C1 w_n211_n268# a_n33_n145# 0.06fF
+C2 a_n73_n48# a_n33_n145# 0.01fF
+C3 a_n73_n48# w_n211_n268# 0.13fF
+C4 a_n33_n145# a_15_n48# 0.01fF
+C5 w_n211_n268# a_15_n48# 0.13fF
+C6 a_15_n48# VSUBS 0.03fF
+C7 a_n73_n48# VSUBS 0.03fF
+C8 a_n33_n145# VSUBS 0.12fF
+C9 w_n211_n268# VSUBS 1.50fF
+.ends
+
+.subckt inverter_min vdd out in vss
+XXM1 vss vss out in sky130_fd_pr__nfet_01v8_L78GGD
+XXM2 vss vdd out in vdd sky130_fd_pr__pfet_01v8_6RX2PQ
+C0 vdd in 0.13fF
+C1 vdd out 0.20fF
+C2 in out 0.67fF
+C3 out vss 0.52fF
+C4 in vss 0.72fF
+C5 vdd vss 2.55fF
+.ends
+
+.subckt buffer_no_inv_x05 VSUBS in avdd1p8 inverter_min_1/in out
+Xinverter_min_1 avdd1p8 out inverter_min_1/in VSUBS inverter_min
+Xinverter_min_0 avdd1p8 inverter_min_1/in in VSUBS inverter_min
+C0 inverter_min_1/in out 0.12fF
+C1 avdd1p8 inverter_min_1/in 0.09fF
+C2 inverter_min_1/in in 0.07fF
+C3 avdd1p8 out 0.02fF
+C4 in VSUBS 0.63fF
+C5 avdd1p8 VSUBS 4.78fF
+C6 out VSUBS 0.45fF
+C7 inverter_min_1/in VSUBS 1.08fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XA7ZMQ VSUBS a_21_142# a_63_n111# a_n87_142# a_n125_n111#
++ w_n263_n330# a_n33_n111#
+X0 a_n33_n111# a_n87_142# a_n125_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+X1 a_63_n111# a_21_142# a_n33_n111# w_n263_n330# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n125_n111# a_n87_142# 0.02fF
+C1 a_21_142# a_63_n111# 0.02fF
+C2 a_n125_n111# w_n263_n330# 0.14fF
+C3 a_n87_142# w_n263_n330# 0.05fF
+C4 a_n125_n111# a_n33_n111# 0.32fF
+C5 a_n125_n111# a_63_n111# 0.12fF
+C6 w_n263_n330# a_n33_n111# 0.10fF
+C7 w_n263_n330# a_63_n111# 0.14fF
+C8 a_n87_142# a_21_142# 0.14fF
+C9 a_n33_n111# a_63_n111# 0.32fF
+C10 w_n263_n330# a_21_142# 0.05fF
+C11 a_63_n111# VSUBS 0.03fF
+C12 a_n33_n111# VSUBS 0.03fF
+C13 a_n125_n111# VSUBS 0.03fF
+C14 a_21_142# VSUBS 0.16fF
+C15 a_n87_142# VSUBS 0.16fF
+C16 w_n263_n330# VSUBS 2.11fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_HAN8QX a_15_n142# a_n33_102# a_n73_n142# w_n211_n290#
+X0 a_15_n142# a_n33_102# a_n73_n142# w_n211_n290# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.11e+06u l=150000u
+C0 a_n33_102# a_n73_n142# 0.03fF
+C1 a_n33_102# a_15_n142# 0.03fF
+C2 a_15_n142# a_n73_n142# 0.38fF
+C3 a_15_n142# w_n211_n290# 0.19fF
+C4 a_n73_n142# w_n211_n290# 0.19fF
+C5 a_n33_102# w_n211_n290# 0.21fF
+.ends
+
+.subckt mux_2to1_logic sel avdd1p8 sel_b w_947_n633# avss1p8 out DinA DinB
+Xinverter_min_0 avdd1p8 sel_b sel avss1p8 inverter_min
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_0 avss1p8 sel DinA sel DinA avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__pfet_01v8_XA7ZMQ_1 avss1p8 sel_b DinB sel_b DinB avdd1p8 out sky130_fd_pr__pfet_01v8_XA7ZMQ
+Xsky130_fd_pr__nfet_01v8_HAN8QX_0 out sel_b DinA avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+Xsky130_fd_pr__nfet_01v8_HAN8QX_1 out sel DinB avss1p8 sky130_fd_pr__nfet_01v8_HAN8QX
+C0 out DinB 0.37fF
+C1 avdd1p8 DinA 0.26fF
+C2 out sel 0.53fF
+C3 out sel_b 0.58fF
+C4 out DinA 0.30fF
+C5 DinB sel 0.02fF
+C6 DinB sel_b 0.27fF
+C7 out avdd1p8 0.23fF
+C8 sel sel_b 0.32fF
+C9 DinB DinA 0.07fF
+C10 avdd1p8 DinB 0.16fF
+C11 sel DinA 0.07fF
+C12 DinA sel_b 0.56fF
+C13 avdd1p8 sel 0.72fF
+C14 avdd1p8 sel_b 0.74fF
+C15 DinA avss1p8 0.63fF
+C16 sel_b avss1p8 2.16fF
+C17 out avss1p8 1.11fF
+C18 DinB avss1p8 -0.09fF
+C19 sel avss1p8 2.55fF
+C20 avdd1p8 avss1p8 8.26fF
+.ends
+
+.subckt delay_cell_buff buffer_no_inv_x05_2/inverter_min_1/in reg2 avss1p8 mux_2to1_logic_4/DinA
++ avdd1p8 buffer_no_inv_x05_13/in clk mux_2to1_logic_3/DinA clk_out mux_2to1_logic_3/DinB
++ reg0 buffer_no_inv_x05_10/inverter_min_1/in reg1 buffer_no_inv_x05_7/inverter_min_1/in
++ nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b mux_2to1_logic_4/out
++ mux_2to1_logic_1/DinA mux_2to1_logic_1/sel_b buffer_no_inv_x05_3/in mux_2to1_logic_5/out
++ mux_2to1_logic_0/out mux_2to1_logic_4/DinB mux_2to1_logic_3/out buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_1/out mux_2to1_logic_5/w_947_n633# buffer_no_inv_x05_12/inverter_min_1/in
++ nand_logic_0/m1_21_n341#
+Xbuffer_no_inv_x05_8 avss1p8 mux_2to1_logic_3/DinA avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in
++ buffer_no_inv_x05_9/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_9 avss1p8 buffer_no_inv_x05_9/in avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in
++ mux_2to1_logic_3/DinB buffer_no_inv_x05
+Xmux_2to1_logic_0 reg2 avdd1p8 mux_2to1_logic_0/sel_b mux_2to1_logic_0/w_947_n633#
++ avss1p8 mux_2to1_logic_0/out clk mux_2to1_logic_0/DinB mux_2to1_logic
+Xmux_2to1_logic_1 reg2 avdd1p8 mux_2to1_logic_1/sel_b mux_2to1_logic_1/w_947_n633#
++ avss1p8 mux_2to1_logic_1/out mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB mux_2to1_logic
+Xmux_2to1_logic_2 reg1 avdd1p8 mux_2to1_logic_2/sel_b mux_2to1_logic_2/w_947_n633#
++ avss1p8 mux_2to1_logic_2/out mux_2to1_logic_0/out mux_2to1_logic_1/out mux_2to1_logic
+Xmux_2to1_logic_3 reg2 avdd1p8 mux_2to1_logic_3/sel_b mux_2to1_logic_3/w_947_n633#
++ avss1p8 mux_2to1_logic_3/out mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB mux_2to1_logic
+Xmux_2to1_logic_4 reg2 avdd1p8 mux_2to1_logic_4/sel_b mux_2to1_logic_4/w_947_n633#
++ avss1p8 mux_2to1_logic_4/out mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB mux_2to1_logic
+Xmux_2to1_logic_5 reg1 avdd1p8 mux_2to1_logic_5/sel_b mux_2to1_logic_5/w_947_n633#
++ avss1p8 mux_2to1_logic_5/out mux_2to1_logic_3/out mux_2to1_logic_4/out mux_2to1_logic
+Xmux_2to1_logic_6 reg0 avdd1p8 mux_2to1_logic_6/sel_b mux_2to1_logic_6/w_947_n633#
++ avss1p8 nand_logic_0/in1 mux_2to1_logic_2/out mux_2to1_logic_5/out mux_2to1_logic
+Xbuffer_no_inv_x05_10 avss1p8 mux_2to1_logic_3/DinB avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in
++ buffer_no_inv_x05_11/in buffer_no_inv_x05
+Xnand_logic_0 avss1p8 nand_logic_0/in1 avdd1p8 clk clk_out nand_logic_0/m1_21_n341#
++ nand_logic
+Xbuffer_no_inv_x05_11 avss1p8 buffer_no_inv_x05_11/in avdd1p8 buffer_no_inv_x05_11/inverter_min_1/in
++ mux_2to1_logic_4/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_12 avss1p8 mux_2to1_logic_4/DinA avdd1p8 buffer_no_inv_x05_12/inverter_min_1/in
++ buffer_no_inv_x05_13/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_13 avss1p8 buffer_no_inv_x05_13/in avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in
++ mux_2to1_logic_4/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_0 avss1p8 clk avdd1p8 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in
++ buffer_no_inv_x05
+Xbuffer_no_inv_x05_2 avss1p8 mux_2to1_logic_0/DinB avdd1p8 buffer_no_inv_x05_2/inverter_min_1/in
++ buffer_no_inv_x05_3/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_1 avss1p8 buffer_no_inv_x05_1/in avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in
++ mux_2to1_logic_0/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_3 avss1p8 buffer_no_inv_x05_3/in avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in
++ mux_2to1_logic_1/DinA buffer_no_inv_x05
+Xbuffer_no_inv_x05_4 avss1p8 mux_2to1_logic_1/DinA avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in
++ buffer_no_inv_x05_5/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_5 avss1p8 buffer_no_inv_x05_5/in avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in
++ mux_2to1_logic_1/DinB buffer_no_inv_x05
+Xbuffer_no_inv_x05_6 avss1p8 mux_2to1_logic_1/DinB avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in
++ buffer_no_inv_x05_7/in buffer_no_inv_x05
+Xbuffer_no_inv_x05_7 avss1p8 buffer_no_inv_x05_7/in avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in
++ mux_2to1_logic_3/DinA buffer_no_inv_x05
+C0 reg0 mux_2to1_logic_2/out 0.44fF
+C1 mux_2to1_logic_4/sel_b buffer_no_inv_x05_8/inverter_min_1/in 0.01fF
+C2 reg0 mux_2to1_logic_5/out 0.23fF
+C3 buffer_no_inv_x05_0/inverter_min_1/in buffer_no_inv_x05_1/in 0.07fF
+C4 buffer_no_inv_x05_12/inverter_min_1/in buffer_no_inv_x05_13/in 0.07fF
+C5 reg1 reg2 2.15fF
+C6 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_1/DinA 0.10fF
+C7 buffer_no_inv_x05_1/in buffer_no_inv_x05_1/inverter_min_1/in 0.12fF
+C8 avdd1p8 reg2 0.14fF
+C9 mux_2to1_logic_3/DinA reg2 0.33fF
+C10 buffer_no_inv_x05_1/inverter_min_1/in mux_2to1_logic_0/DinB 0.08fF
+C11 clk mux_2to1_logic_0/DinB 0.01fF
+C12 mux_2to1_logic_0/out reg1 0.63fF
+C13 mux_2to1_logic_2/out nand_logic_0/in1 0.06fF
+C14 clk mux_2to1_logic_1/DinB 0.01fF
+C15 mux_2to1_logic_5/out mux_2to1_logic_2/out 1.29fF
+C16 reg2 mux_2to1_logic_2/sel_b 0.07fF
+C17 buffer_no_inv_x05_2/inverter_min_1/in buffer_no_inv_x05_3/in 0.07fF
+C18 mux_2to1_logic_0/out avdd1p8 0.43fF
+C19 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/DinB 0.02fF
+C20 mux_2to1_logic_0/out mux_2to1_logic_1/out 1.27fF
+C21 mux_2to1_logic_5/out nand_logic_0/in1 0.38fF
+C22 buffer_no_inv_x05_9/in mux_2to1_logic_3/DinB 0.10fF
+C23 mux_2to1_logic_3/out mux_2to1_logic_5/sel_b 0.37fF
+C24 buffer_no_inv_x05_7/in buffer_no_inv_x05_6/inverter_min_1/in 0.07fF
+C25 mux_2to1_logic_1/DinA mux_2to1_logic_0/DinB 0.11fF
+C26 mux_2to1_logic_4/sel_b mux_2to1_logic_3/DinB 0.04fF
+C27 mux_2to1_logic_4/DinA mux_2to1_logic_6/sel_b 0.01fF
+C28 mux_2to1_logic_1/DinA mux_2to1_logic_1/DinB 0.66fF
+C29 mux_2to1_logic_0/sel_b mux_2to1_logic_0/DinB 0.06fF
+C30 mux_2to1_logic_0/out mux_2to1_logic_2/sel_b 0.15fF
+C31 mux_2to1_logic_3/out mux_2to1_logic_4/DinA 0.12fF
+C32 avdd1p8 buffer_no_inv_x05_6/inverter_min_1/in 0.03fF
+C33 mux_2to1_logic_3/DinA buffer_no_inv_x05_6/inverter_min_1/in 0.04fF
+C34 buffer_no_inv_x05_2/inverter_min_1/in avdd1p8 0.03fF
+C35 avdd1p8 buffer_no_inv_x05_9/in 0.10fF
+C36 avdd1p8 buffer_no_inv_x05_5/inverter_min_1/in 0.03fF
+C37 avdd1p8 mux_2to1_logic_4/sel_b 0.07fF
+C38 buffer_no_inv_x05_3/in mux_2to1_logic_1/DinB 0.03fF
+C39 mux_2to1_logic_2/out reg2 0.85fF
+C40 buffer_no_inv_x05_3/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C41 mux_2to1_logic_4/DinB mux_2to1_logic_6/sel_b 0.28fF
+C42 mux_2to1_logic_3/out mux_2to1_logic_4/DinB 0.18fF
+C43 mux_2to1_logic_4/DinB mux_2to1_logic_5/sel_b 0.31fF
+C44 avdd1p8 buffer_no_inv_x05_1/in 0.09fF
+C45 mux_2to1_logic_0/out mux_2to1_logic_2/out 0.05fF
+C46 avdd1p8 mux_2to1_logic_0/DinB 1.33fF
+C47 mux_2to1_logic_4/DinA mux_2to1_logic_4/DinB 1.68fF
+C48 buffer_no_inv_x05_4/inverter_min_1/in mux_2to1_logic_1/DinB 0.15fF
+C49 buffer_no_inv_x05_3/in mux_2to1_logic_1/sel_b 0.01fF
+C50 avdd1p8 mux_2to1_logic_1/DinB 1.09fF
+C51 mux_2to1_logic_3/DinA mux_2to1_logic_1/DinB 0.07fF
+C52 mux_2to1_logic_1/out mux_2to1_logic_1/DinB 0.23fF
+C53 clk mux_2to1_logic_4/DinA 0.01fF
+C54 mux_2to1_logic_4/DinB buffer_no_inv_x05_13/inverter_min_1/in 0.11fF
+C55 buffer_no_inv_x05_9/inverter_min_1/in buffer_no_inv_x05_9/in 0.12fF
+C56 mux_2to1_logic_2/sel_b mux_2to1_logic_1/DinB 0.04fF
+C57 buffer_no_inv_x05_7/inverter_min_1/in mux_2to1_logic_3/DinB 0.10fF
+C58 avdd1p8 mux_2to1_logic_1/sel_b 0.09fF
+C59 buffer_no_inv_x05_7/inverter_min_1/in buffer_no_inv_x05_7/in 0.12fF
+C60 mux_2to1_logic_2/out mux_2to1_logic_4/sel_b 0.22fF
+C61 clk mux_2to1_logic_4/DinB 0.12fF
+C62 mux_2to1_logic_3/out mux_2to1_logic_3/DinB 0.13fF
+C63 mux_2to1_logic_3/DinB mux_2to1_logic_5/sel_b 0.01fF
+C64 avdd1p8 buffer_no_inv_x05_7/inverter_min_1/in 0.04fF
+C65 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/inverter_min_1/in 0.21fF
+C66 buffer_no_inv_x05_11/inverter_min_1/in mux_2to1_logic_4/DinA 0.08fF
+C67 mux_2to1_logic_0/out reg2 0.45fF
+C68 mux_2to1_logic_3/DinB mux_2to1_logic_3/sel_b 0.21fF
+C69 mux_2to1_logic_4/DinA mux_2to1_logic_3/DinB 0.90fF
+C70 buffer_no_inv_x05_4/inverter_min_1/in buffer_no_inv_x05_5/in 0.07fF
+C71 reg1 mux_2to1_logic_3/out 0.47fF
+C72 reg1 mux_2to1_logic_5/sel_b 0.06fF
+C73 avdd1p8 mux_2to1_logic_6/sel_b 0.05fF
+C74 avdd1p8 buffer_no_inv_x05_5/in 0.09fF
+C75 mux_2to1_logic_4/out mux_2to1_logic_6/sel_b 0.04fF
+C76 mux_2to1_logic_3/out avdd1p8 0.39fF
+C77 mux_2to1_logic_1/DinA clk 0.01fF
+C78 mux_2to1_logic_3/out mux_2to1_logic_3/DinA 0.05fF
+C79 avdd1p8 mux_2to1_logic_5/sel_b 0.09fF
+C80 mux_2to1_logic_3/out mux_2to1_logic_4/out 1.18fF
+C81 mux_2to1_logic_4/out mux_2to1_logic_5/sel_b 0.20fF
+C82 mux_2to1_logic_0/sel_b buffer_no_inv_x05_1/inverter_min_1/in 0.01fF
+C83 avdd1p8 mux_2to1_logic_3/sel_b 0.09fF
+C84 mux_2to1_logic_1/out mux_2to1_logic_3/sel_b 0.04fF
+C85 avdd1p8 mux_2to1_logic_4/DinA 1.95fF
+C86 mux_2to1_logic_3/DinA mux_2to1_logic_4/DinA 0.07fF
+C87 buffer_no_inv_x05_5/in mux_2to1_logic_2/sel_b 0.01fF
+C88 mux_2to1_logic_4/out mux_2to1_logic_4/DinA 0.27fF
+C89 mux_2to1_logic_4/DinB mux_2to1_logic_3/DinB 0.29fF
+C90 reg2 mux_2to1_logic_4/sel_b 0.06fF
+C91 mux_2to1_logic_3/DinB buffer_no_inv_x05_8/inverter_min_1/in 0.10fF
+C92 clk mux_2to1_logic_3/DinB 0.01fF
+C93 reg0 mux_2to1_logic_6/sel_b 0.06fF
+C94 avdd1p8 buffer_no_inv_x05_13/inverter_min_1/in 0.03fF
+C95 reg1 mux_2to1_logic_4/DinB 0.40fF
+C96 clk clk_out 0.33fF
+C97 reg2 buffer_no_inv_x05_1/in 0.01fF
+C98 buffer_no_inv_x05_0/inverter_min_1/in avdd1p8 0.01fF
+C99 avdd1p8 mux_2to1_logic_4/DinB 2.49fF
+C100 reg2 mux_2to1_logic_0/DinB 0.06fF
+C101 mux_2to1_logic_4/out mux_2to1_logic_4/DinB 0.65fF
+C102 nand_logic_0/m1_21_n341# clk_out 0.02fF
+C103 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/in 0.16fF
+C104 mux_2to1_logic_1/DinA buffer_no_inv_x05_3/inverter_min_1/in 0.23fF
+C105 reg2 mux_2to1_logic_1/DinB 0.07fF
+C106 avdd1p8 buffer_no_inv_x05_8/inverter_min_1/in 0.03fF
+C107 avdd1p8 buffer_no_inv_x05_1/inverter_min_1/in 0.03fF
+C108 mux_2to1_logic_3/DinA buffer_no_inv_x05_8/inverter_min_1/in 0.12fF
+C109 avdd1p8 clk 1.01fF
+C110 clk mux_2to1_logic_3/DinA 0.01fF
+C111 mux_2to1_logic_2/out mux_2to1_logic_6/sel_b 0.31fF
+C112 mux_2to1_logic_3/out mux_2to1_logic_2/out 0.99fF
+C113 mux_2to1_logic_2/out mux_2to1_logic_5/sel_b 0.20fF
+C114 mux_2to1_logic_0/out mux_2to1_logic_0/DinB 0.14fF
+C115 mux_2to1_logic_5/out mux_2to1_logic_6/sel_b 0.20fF
+C116 mux_2to1_logic_3/DinB buffer_no_inv_x05_10/inverter_min_1/in 0.12fF
+C117 mux_2to1_logic_3/out mux_2to1_logic_5/out 0.07fF
+C118 mux_2to1_logic_1/DinA buffer_no_inv_x05_4/inverter_min_1/in 0.12fF
+C119 mux_2to1_logic_0/out mux_2to1_logic_1/DinB 0.12fF
+C120 buffer_no_inv_x05_13/in buffer_no_inv_x05_13/inverter_min_1/in 0.12fF
+C121 mux_2to1_logic_2/out mux_2to1_logic_3/sel_b 0.33fF
+C122 buffer_no_inv_x05_3/in buffer_no_inv_x05_3/inverter_min_1/in 0.12fF
+C123 mux_2to1_logic_1/DinA avdd1p8 0.55fF
+C124 mux_2to1_logic_1/out mux_2to1_logic_1/DinA 0.05fF
+C125 reg2 mux_2to1_logic_1/sel_b 0.13fF
+C126 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinA 0.12fF
+C127 reg0 mux_2to1_logic_4/DinB -0.24fF
+C128 mux_2to1_logic_0/sel_b avdd1p8 0.05fF
+C129 mux_2to1_logic_5/out mux_2to1_logic_4/DinA 0.23fF
+C130 buffer_no_inv_x05_13/in mux_2to1_logic_4/DinB 0.11fF
+C131 buffer_no_inv_x05_7/in mux_2to1_logic_3/DinB 0.10fF
+C132 buffer_no_inv_x05_11/in buffer_no_inv_x05_10/inverter_min_1/in 0.07fF
+C133 buffer_no_inv_x05_2/inverter_min_1/in mux_2to1_logic_0/DinB 0.12fF
+C134 avdd1p8 buffer_no_inv_x05_10/inverter_min_1/in 0.03fF
+C135 buffer_no_inv_x05_11/inverter_min_1/in buffer_no_inv_x05_11/in 0.14fF
+C136 clk buffer_no_inv_x05_13/in 0.07fF
+C137 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_1/DinB 0.12fF
+C138 buffer_no_inv_x05_11/inverter_min_1/in avdd1p8 0.03fF
+C139 mux_2to1_logic_0/out mux_2to1_logic_1/sel_b 0.26fF
+C140 avdd1p8 buffer_no_inv_x05_3/in 0.11fF
+C141 avdd1p8 buffer_no_inv_x05_3/inverter_min_1/in 0.03fF
+C142 avdd1p8 mux_2to1_logic_3/DinB 0.82fF
+C143 mux_2to1_logic_3/DinA mux_2to1_logic_3/DinB 1.18fF
+C144 mux_2to1_logic_2/out mux_2to1_logic_4/DinB 0.07fF
+C145 buffer_no_inv_x05_5/inverter_min_1/in mux_2to1_logic_1/DinB 0.23fF
+C146 buffer_no_inv_x05_12/inverter_min_1/in mux_2to1_logic_4/DinB 0.07fF
+C147 avdd1p8 buffer_no_inv_x05_7/in 0.09fF
+C148 mux_2to1_logic_3/DinA buffer_no_inv_x05_7/in 0.13fF
+C149 avdd1p8 clk_out 0.04fF
+C150 mux_2to1_logic_5/out mux_2to1_logic_4/DinB 0.52fF
+C151 reg1 buffer_no_inv_x05_4/inverter_min_1/in 0.01fF
+C152 mux_2to1_logic_3/out reg2 0.36fF
+C153 reg1 avdd1p8 0.08fF
+C154 mux_2to1_logic_1/out reg1 0.36fF
+C155 avdd1p8 buffer_no_inv_x05_4/inverter_min_1/in 0.03fF
+C156 reg1 mux_2to1_logic_4/out 0.37fF
+C157 avdd1p8 buffer_no_inv_x05_11/in 0.10fF
+C158 reg2 mux_2to1_logic_3/sel_b 0.13fF
+C159 avdd1p8 mux_2to1_logic_3/DinA 0.81fF
+C160 mux_2to1_logic_1/out avdd1p8 0.84fF
+C161 reg2 mux_2to1_logic_4/DinA 0.31fF
+C162 avdd1p8 mux_2to1_logic_4/out 0.76fF
+C163 reg0 buffer_no_inv_x05_11/inverter_min_1/in 0.01fF
+C164 reg1 mux_2to1_logic_2/sel_b 0.06fF
+C165 avdd1p8 mux_2to1_logic_2/sel_b 0.07fF
+C166 mux_2to1_logic_1/out mux_2to1_logic_2/sel_b 0.19fF
+C167 reg0 reg1 0.01fF
+C168 mux_2to1_logic_1/sel_b mux_2to1_logic_0/DinB 0.04fF
+C169 reg2 mux_2to1_logic_4/DinB 0.05fF
+C170 buffer_no_inv_x05_9/inverter_min_1/in mux_2to1_logic_3/DinB 0.18fF
+C171 reg0 avdd1p8 0.05fF
+C172 mux_2to1_logic_1/sel_b mux_2to1_logic_1/DinB -0.06fF
+C173 buffer_no_inv_x05_5/in buffer_no_inv_x05_5/inverter_min_1/in 0.12fF
+C174 avdd1p8 buffer_no_inv_x05_13/in 0.10fF
+C175 clk reg2 0.12fF
+C176 buffer_no_inv_x05_6/inverter_min_1/in mux_2to1_logic_3/sel_b 0.01fF
+C177 mux_2to1_logic_3/out mux_2to1_logic_4/sel_b 0.23fF
+C178 reg1 mux_2to1_logic_2/out 1.41fF
+C179 avdd1p8 buffer_no_inv_x05_9/inverter_min_1/in 0.03fF
+C180 mux_2to1_logic_0/out clk 0.05fF
+C181 avdd1p8 mux_2to1_logic_2/out 0.41fF
+C182 mux_2to1_logic_1/out mux_2to1_logic_2/out 0.35fF
+C183 mux_2to1_logic_1/DinA reg2 0.18fF
+C184 mux_2to1_logic_2/out mux_2to1_logic_4/out 0.26fF
+C185 buffer_no_inv_x05_12/inverter_min_1/in avdd1p8 0.03fF
+C186 mux_2to1_logic_0/sel_b reg2 0.14fF
+C187 avdd1p8 mux_2to1_logic_5/out 0.64fF
+C188 mux_2to1_logic_5/out mux_2to1_logic_4/out 0.45fF
+C189 buffer_no_inv_x05_5/in mux_2to1_logic_1/DinB 0.15fF
+C190 mux_2to1_logic_0/out mux_2to1_logic_1/DinA 0.12fF
+C191 buffer_no_inv_x05_9/in buffer_no_inv_x05_8/inverter_min_1/in 0.07fF
+C192 mux_2to1_logic_4/sel_b mux_2to1_logic_4/DinB 0.20fF
+C193 reg2 mux_2to1_logic_3/DinB 0.08fF
+C194 buffer_no_inv_x05_7/in avss1p8 1.12fF
+C195 buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.05fF
+C196 buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.04fF
+C197 buffer_no_inv_x05_5/in avss1p8 1.12fF
+C198 buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.04fF
+C199 buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.04fF
+C200 buffer_no_inv_x05_3/in avss1p8 1.13fF
+C201 buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.04fF
+C202 buffer_no_inv_x05_1/in avss1p8 1.12fF
+C203 buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.04fF
+C204 buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.05fF
+C205 clk avss1p8 2.54fF
+C206 buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C207 buffer_no_inv_x05_13/in avss1p8 1.12fF
+C208 mux_2to1_logic_4/DinB avss1p8 -7.83fF
+C209 buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.04fF
+C210 buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.04fF
+C211 buffer_no_inv_x05_11/in avss1p8 1.12fF
+C212 buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.04fF
+C213 nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C214 clk_out avss1p8 0.27fF
+C215 buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.04fF
+C216 mux_2to1_logic_6/sel_b avss1p8 2.08fF
+C217 nand_logic_0/in1 avss1p8 1.63fF
+C218 reg0 avss1p8 3.16fF
+C219 mux_2to1_logic_5/sel_b avss1p8 2.05fF
+C220 mux_2to1_logic_5/out avss1p8 -1.59fF
+C221 mux_2to1_logic_4/DinA avss1p8 -2.53fF
+C222 mux_2to1_logic_4/sel_b avss1p8 2.05fF
+C223 mux_2to1_logic_4/out avss1p8 -2.14fF
+C224 mux_2to1_logic_3/DinA avss1p8 0.02fF
+C225 mux_2to1_logic_3/sel_b avss1p8 2.05fF
+C226 mux_2to1_logic_3/out avss1p8 -2.13fF
+C227 mux_2to1_logic_3/DinB avss1p8 -4.89fF
+C228 mux_2to1_logic_2/sel_b avss1p8 2.05fF
+C229 mux_2to1_logic_2/out avss1p8 -1.34fF
+C230 reg1 avss1p8 4.95fF
+C231 mux_2to1_logic_1/DinA avss1p8 0.68fF
+C232 mux_2to1_logic_1/sel_b avss1p8 2.05fF
+C233 mux_2to1_logic_1/out avss1p8 -2.38fF
+C234 mux_2to1_logic_1/DinB avss1p8 -3.84fF
+C235 reg2 avss1p8 13.29fF
+C236 avdd1p8 avss1p8 125.49fF
+C237 mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C238 mux_2to1_logic_0/out avss1p8 0.32fF
+C239 mux_2to1_logic_0/DinB avss1p8 -0.89fF
+C240 buffer_no_inv_x05_9/in avss1p8 1.12fF
+C241 buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.04fF
+C242 buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.04fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_72JNYZ a_n81_n100# w_n311_n310# a_n128_122# a_111_n100#
++ a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n128_122# a_n81_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n81_n100# a_n128_122# a_n173_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n128_122# a_15_n100# w_n311_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n81_n100# a_n128_122# 0.10fF
+C1 a_n128_122# a_15_n100# 0.10fF
+C2 a_n81_n100# a_n173_n100# 0.29fF
+C3 a_n81_n100# a_15_n100# 0.29fF
+C4 a_n81_n100# a_111_n100# 0.11fF
+C5 a_n173_n100# a_15_n100# 0.11fF
+C6 a_111_n100# a_n173_n100# 0.06fF
+C7 a_111_n100# a_15_n100# 0.29fF
+C8 a_111_n100# w_n311_n310# 0.15fF
+C9 a_15_n100# w_n311_n310# 0.11fF
+C10 a_n81_n100# w_n311_n310# 0.11fF
+C11 a_n173_n100# w_n311_n310# 0.15fF
+C12 a_n128_122# w_n311_n310# 0.49fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XL9AN VSUBS w_n311_n319# a_n81_n100# a_111_n100#
++ a_n129_131# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_131# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_131# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_131# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_15_n100# a_n81_n100# 0.29fF
+C1 a_111_n100# a_n173_n100# 0.06fF
+C2 a_15_n100# w_n311_n319# 0.08fF
+C3 a_n173_n100# a_n81_n100# 0.29fF
+C4 a_n173_n100# w_n311_n319# 0.12fF
+C5 a_n173_n100# a_15_n100# 0.11fF
+C6 a_111_n100# a_n81_n100# 0.11fF
+C7 a_n81_n100# a_n129_131# 0.08fF
+C8 a_111_n100# w_n311_n319# 0.12fF
+C9 w_n311_n319# a_n129_131# 0.16fF
+C10 a_n81_n100# w_n311_n319# 0.08fF
+C11 a_111_n100# a_15_n100# 0.29fF
+C12 a_15_n100# a_n129_131# 0.08fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_131# VSUBS 0.32fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_2XUYGK VSUBS a_n269_n100# a_n81_n100# w_n407_n319#
++ a_111_n100# a_n177_n100# a_15_n100# a_207_n100# a_n225_131#
+X0 a_207_n100# a_n225_131# a_111_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_131# a_n81_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_111_n100# a_n225_131# a_15_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n81_n100# a_n225_131# a_n177_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_131# a_n269_n100# w_n407_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_111_n100# 0.05fF
+C1 w_n407_n319# a_n81_n100# 0.06fF
+C2 a_15_n100# a_n177_n100# 0.11fF
+C3 w_n407_n319# a_n269_n100# 0.10fF
+C4 a_n177_n100# a_111_n100# 0.06fF
+C5 a_15_n100# a_n225_131# 0.08fF
+C6 a_n225_131# a_111_n100# 0.08fF
+C7 a_15_n100# a_207_n100# 0.11fF
+C8 a_207_n100# a_111_n100# 0.29fF
+C9 w_n407_n319# a_n177_n100# 0.05fF
+C10 w_n407_n319# a_n225_131# 0.25fF
+C11 a_n81_n100# a_n269_n100# 0.11fF
+C12 w_n407_n319# a_207_n100# 0.10fF
+C13 a_15_n100# a_111_n100# 0.29fF
+C14 a_n81_n100# a_n177_n100# 0.29fF
+C15 a_n81_n100# a_n225_131# 0.08fF
+C16 w_n407_n319# a_15_n100# 0.06fF
+C17 a_n81_n100# a_207_n100# 0.06fF
+C18 w_n407_n319# a_111_n100# 0.05fF
+C19 a_n269_n100# a_n177_n100# 0.29fF
+C20 a_n81_n100# a_15_n100# 0.29fF
+C21 a_n225_131# a_n177_n100# 0.08fF
+C22 a_n81_n100# a_111_n100# 0.11fF
+C23 a_207_n100# a_n177_n100# 0.05fF
+C24 a_15_n100# a_n269_n100# 0.06fF
+C25 a_207_n100# VSUBS 0.03fF
+C26 a_111_n100# VSUBS 0.03fF
+C27 a_15_n100# VSUBS 0.03fF
+C28 a_n81_n100# VSUBS 0.03fF
+C29 a_n177_n100# VSUBS 0.03fF
+C30 a_n269_n100# VSUBS 0.03fF
+C31 a_n225_131# VSUBS 0.54fF
+C32 w_n407_n319# VSUBS 2.92fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_2AP43D a_15_n81# a_n33_41# w_n211_n229# a_n73_n81#
+X0 a_15_n81# a_n33_41# a_n73_n81# w_n211_n229# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=500000u l=150000u
+C0 a_n73_n81# a_n33_41# 0.02fF
+C1 a_n33_41# a_15_n81# 0.02fF
+C2 a_n73_n81# a_15_n81# 0.17fF
+C3 a_15_n81# w_n211_n229# 0.12fF
+C4 a_n73_n81# w_n211_n229# 0.12fF
+C5 a_n33_41# w_n211_n229# 0.18fF
+.ends
+
+.subckt res_amp_lin clk vctrl avdd1p8 avss1p8 a_3747_261# vp inn outn outp inp
+Xsky130_fd_pr__pfet_01v8_2XL9AN_0 avss1p8 avdd1p8 a_3747_261# a_3747_261# clk avdd1p8
++ avdd1p8 sky130_fd_pr__pfet_01v8_2XL9AN
+Xsky130_fd_pr__pfet_01v8_2XUYGK_0 avss1p8 a_3747_261# a_3747_261# avdd1p8 a_3747_261#
++ vp vp vp vctrl sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_1 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_0 avss1p8 clk avss1p8 outp sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_2 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__nfet_01v8_lvt_2AP43D_1 avss1p8 clk avss1p8 outn sky130_fd_pr__nfet_01v8_lvt_2AP43D
+Xsky130_fd_pr__pfet_01v8_2XUYGK_3 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_4 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_5 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_6 avss1p8 vp vp avdd1p8 vp outp outp outp inn sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_7 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+Xsky130_fd_pr__pfet_01v8_2XUYGK_8 avss1p8 vp vp avdd1p8 vp outn outn outn inp sky130_fd_pr__pfet_01v8_2XUYGK
+C0 avdd1p8 outn 1.33fF
+C1 vp avdd1p8 6.92fF
+C2 inn inp 2.67fF
+C3 clk inp 0.06fF
+C4 vp outn 4.23fF
+C5 outp inp 1.28fF
+C6 avdd1p8 inp 1.02fF
+C7 vctrl a_3747_261# 0.76fF
+C8 inp outn 5.59fF
+C9 vp inp 0.78fF
+C10 vctrl clk 0.02fF
+C11 clk a_3747_261# 0.44fF
+C12 vctrl avdd1p8 1.19fF
+C13 inn outp 5.76fF
+C14 clk outp 0.56fF
+C15 avdd1p8 a_3747_261# 1.24fF
+C16 avdd1p8 inn 1.05fF
+C17 clk avdd1p8 2.36fF
+C18 vp a_3747_261# 1.08fF
+C19 avdd1p8 outp 1.56fF
+C20 inn outn 1.15fF
+C21 vp inn 0.84fF
+C22 clk outn 0.71fF
+C23 clk vp 0.79fF
+C24 outp outn 4.18fF
+C25 vp outp 4.81fF
+C26 outn avss1p8 0.69fF
+C27 inp avss1p8 -0.11fF
+C28 outp avss1p8 -0.62fF
+C29 vp avss1p8 -4.89fF
+C30 inn avss1p8 0.23fF
+C31 avdd1p8 avss1p8 31.50fF
+C32 clk avss1p8 1.49fF
+C33 a_3747_261# avss1p8 -0.95fF
+C34 vctrl avss1p8 -0.82fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_595QY5 a_n269_n100# a_n81_n100# a_111_n100# a_n177_n100#
++ a_15_n100# w_n407_n310# a_207_n100# a_n225_n188#
+X0 a_207_n100# a_n225_n188# a_111_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_15_n100# a_n225_n188# a_n81_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n225_n188# a_n177_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_111_n100# a_n225_n188# a_15_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n177_n100# a_n225_n188# a_n269_n100# w_n407_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n269_n100# a_15_n100# 0.06fF
+C1 a_15_n100# a_207_n100# 0.11fF
+C2 a_111_n100# a_15_n100# 0.29fF
+C3 a_n225_n188# a_n81_n100# 0.10fF
+C4 a_n81_n100# a_n177_n100# 0.29fF
+C5 a_n81_n100# a_n269_n100# 0.11fF
+C6 a_n81_n100# a_207_n100# 0.06fF
+C7 a_n225_n188# a_n177_n100# 0.10fF
+C8 a_111_n100# a_n81_n100# 0.11fF
+C9 a_n177_n100# a_n269_n100# 0.29fF
+C10 a_n225_n188# a_111_n100# 0.10fF
+C11 a_n81_n100# a_15_n100# 0.29fF
+C12 a_n177_n100# a_207_n100# 0.05fF
+C13 a_111_n100# a_n177_n100# 0.06fF
+C14 a_111_n100# a_n269_n100# 0.05fF
+C15 a_n225_n188# a_15_n100# 0.10fF
+C16 a_111_n100# a_207_n100# 0.29fF
+C17 a_n177_n100# a_15_n100# 0.11fF
+C18 a_207_n100# w_n407_n310# 0.13fF
+C19 a_111_n100# w_n407_n310# 0.08fF
+C20 a_15_n100# w_n407_n310# 0.09fF
+C21 a_n81_n100# w_n407_n310# 0.09fF
+C22 a_n177_n100# w_n407_n310# 0.08fF
+C23 a_n269_n100# w_n407_n310# 0.13fF
+C24 a_n225_n188# w_n407_n310# 0.80fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_9B2JY7 a_n317_n100# a_n33_n100# a_n225_n100# a_n271_122#
++ a_63_n100# a_n129_n100# w_n455_n310# a_255_n100# a_159_n100#
+X0 a_63_n100# a_n271_122# a_n33_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n271_122# a_n129_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n271_122# a_63_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n271_122# a_159_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n225_n100# a_n271_122# a_n317_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n129_n100# a_n271_122# a_n225_n100# w_n455_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# a_n317_n100# 0.06fF
+C1 a_n33_n100# a_63_n100# 0.29fF
+C2 a_n129_n100# a_159_n100# 0.06fF
+C3 a_159_n100# a_255_n100# 0.29fF
+C4 a_n129_n100# a_n271_122# 0.10fF
+C5 a_159_n100# a_63_n100# 0.29fF
+C6 a_n129_n100# a_n225_n100# 0.29fF
+C7 a_n317_n100# a_n225_n100# 0.29fF
+C8 a_n271_122# a_63_n100# 0.10fF
+C9 a_63_n100# a_n225_n100# 0.06fF
+C10 a_159_n100# a_n33_n100# 0.11fF
+C11 a_n129_n100# a_255_n100# 0.05fF
+C12 a_n271_122# a_n33_n100# 0.10fF
+C13 a_n129_n100# a_n317_n100# 0.11fF
+C14 a_n33_n100# a_n225_n100# 0.11fF
+C15 a_n129_n100# a_63_n100# 0.11fF
+C16 a_63_n100# a_255_n100# 0.11fF
+C17 a_159_n100# a_n271_122# 0.10fF
+C18 a_63_n100# a_n317_n100# 0.05fF
+C19 a_159_n100# a_n225_n100# 0.05fF
+C20 a_n271_122# a_n225_n100# 0.10fF
+C21 a_n129_n100# a_n33_n100# 0.29fF
+C22 a_n33_n100# a_255_n100# 0.06fF
+C23 a_255_n100# w_n455_n310# 0.13fF
+C24 a_159_n100# w_n455_n310# 0.08fF
+C25 a_63_n100# w_n455_n310# 0.07fF
+C26 a_n33_n100# w_n455_n310# 0.08fF
+C27 a_n129_n100# w_n455_n310# 0.07fF
+C28 a_n225_n100# w_n455_n310# 0.08fF
+C29 a_n317_n100# w_n455_n310# 0.13fF
+C30 a_n271_122# w_n455_n310# 0.95fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_MVT43V a_n33_n100# w_n263_n310# a_63_n100# a_n79_122#
++ a_n125_n100#
+X0 a_63_n100# a_n79_122# a_n33_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n79_122# a_n125_n100# w_n263_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_63_n100# a_n125_n100# 0.11fF
+C1 a_n125_n100# a_n33_n100# 0.29fF
+C2 a_n125_n100# a_n79_122# 0.02fF
+C3 a_63_n100# a_n33_n100# 0.29fF
+C4 a_63_n100# a_n79_122# 0.02fF
+C5 a_n33_n100# a_n79_122# 0.11fF
+C6 a_63_n100# w_n263_n310# 0.16fF
+C7 a_n33_n100# w_n263_n310# 0.12fF
+C8 a_n125_n100# w_n263_n310# 0.16fF
+C9 a_n79_122# w_n263_n310# 0.37fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_NMSMYT a_n33_n100# a_n321_n100# a_n225_n100# w_n551_n310#
++ a_63_n100# a_n368_122# a_n129_n100# a_351_n100# a_255_n100# a_n413_n100# a_159_n100#
+X0 a_63_n100# a_n368_122# a_n33_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n368_122# a_n129_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n368_122# a_63_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_255_n100# a_n368_122# a_159_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_351_n100# a_n368_122# a_255_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n321_n100# a_n368_122# a_n413_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n225_n100# a_n368_122# a_n321_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n129_n100# a_n368_122# a_n225_n100# w_n551_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n33_n100# a_n368_122# 0.10fF
+C1 a_n129_n100# a_n33_n100# 0.29fF
+C2 a_159_n100# a_351_n100# 0.11fF
+C3 a_n321_n100# a_n33_n100# 0.06fF
+C4 a_63_n100# a_159_n100# 0.29fF
+C5 a_n225_n100# a_n413_n100# 0.11fF
+C6 a_159_n100# a_n368_122# 0.10fF
+C7 a_n129_n100# a_159_n100# 0.06fF
+C8 a_n225_n100# a_63_n100# 0.06fF
+C9 a_255_n100# a_351_n100# 0.29fF
+C10 a_63_n100# a_255_n100# 0.11fF
+C11 a_n225_n100# a_n368_122# 0.10fF
+C12 a_n225_n100# a_n129_n100# 0.29fF
+C13 a_255_n100# a_n368_122# 0.10fF
+C14 a_n225_n100# a_n321_n100# 0.29fF
+C15 a_255_n100# a_n129_n100# 0.05fF
+C16 a_159_n100# a_n33_n100# 0.11fF
+C17 a_n225_n100# a_n33_n100# 0.11fF
+C18 a_255_n100# a_n33_n100# 0.06fF
+C19 a_63_n100# a_351_n100# 0.06fF
+C20 a_n225_n100# a_159_n100# 0.05fF
+C21 a_255_n100# a_159_n100# 0.29fF
+C22 a_n129_n100# a_n413_n100# 0.06fF
+C23 a_n321_n100# a_n413_n100# 0.29fF
+C24 a_63_n100# a_n368_122# 0.10fF
+C25 a_63_n100# a_n129_n100# 0.11fF
+C26 a_63_n100# a_n321_n100# 0.05fF
+C27 a_n129_n100# a_n368_122# 0.10fF
+C28 a_n33_n100# a_n413_n100# 0.05fF
+C29 a_n321_n100# a_n368_122# 0.10fF
+C30 a_n321_n100# a_n129_n100# 0.11fF
+C31 a_n33_n100# a_351_n100# 0.05fF
+C32 a_63_n100# a_n33_n100# 0.29fF
+C33 a_351_n100# w_n551_n310# 0.13fF
+C34 a_255_n100# w_n551_n310# 0.08fF
+C35 a_159_n100# w_n551_n310# 0.07fF
+C36 a_63_n100# w_n551_n310# 0.06fF
+C37 a_n33_n100# w_n551_n310# 0.04fF
+C38 a_n129_n100# w_n551_n310# 0.06fF
+C39 a_n225_n100# w_n551_n310# 0.07fF
+C40 a_n321_n100# w_n551_n310# 0.08fF
+C41 a_n413_n100# w_n551_n310# 0.13fF
+C42 a_n368_122# w_n551_n310# 1.26fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XAYTAL VSUBS w_n311_n319# a_n81_n100# a_n129_n197#
++ a_111_n100# a_15_n100# a_n173_n100#
+X0 a_15_n100# a_n129_n197# a_n81_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_111_n100# a_n129_n197# a_15_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n197# w_n311_n319# 0.17fF
+C1 a_15_n100# a_111_n100# 0.29fF
+C2 a_15_n100# w_n311_n319# 0.08fF
+C3 a_n173_n100# a_15_n100# 0.11fF
+C4 a_111_n100# a_n81_n100# 0.11fF
+C5 w_n311_n319# a_n81_n100# 0.08fF
+C6 a_15_n100# a_n129_n197# 0.08fF
+C7 a_n173_n100# a_n81_n100# 0.29fF
+C8 a_n129_n197# a_n81_n100# 0.08fF
+C9 a_111_n100# w_n311_n319# 0.12fF
+C10 a_n173_n100# a_111_n100# 0.06fF
+C11 a_n173_n100# w_n311_n319# 0.12fF
+C12 a_15_n100# a_n81_n100# 0.29fF
+C13 a_111_n100# VSUBS 0.03fF
+C14 a_15_n100# VSUBS 0.03fF
+C15 a_n81_n100# VSUBS 0.03fF
+C16 a_n173_n100# VSUBS 0.03fF
+C17 a_n129_n197# VSUBS 0.34fF
+C18 w_n311_n319# VSUBS 2.34fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_B2JNY3 a_n33_n100# a_63_n100# a_n221_n100# a_n129_n100#
++ w_n359_n310# a_n176_122# a_159_n100#
+X0 a_63_n100# a_n176_122# a_n33_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n176_122# a_n129_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n176_122# a_63_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n176_122# a_n221_n100# w_n359_n310# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n129_n100# a_n176_122# 0.10fF
+C1 a_n221_n100# a_n33_n100# 0.11fF
+C2 a_63_n100# a_159_n100# 0.29fF
+C3 a_n33_n100# a_n176_122# 0.10fF
+C4 a_n129_n100# a_63_n100# 0.11fF
+C5 a_n129_n100# a_159_n100# 0.06fF
+C6 a_63_n100# a_n33_n100# 0.29fF
+C7 a_n33_n100# a_159_n100# 0.11fF
+C8 a_n129_n100# a_n33_n100# 0.29fF
+C9 a_63_n100# a_n221_n100# 0.06fF
+C10 a_n221_n100# a_159_n100# 0.05fF
+C11 a_63_n100# a_n176_122# 0.10fF
+C12 a_n129_n100# a_n221_n100# 0.29fF
+C13 a_159_n100# w_n359_n310# 0.13fF
+C14 a_63_n100# w_n359_n310# 0.10fF
+C15 a_n33_n100# w_n359_n310# 0.10fF
+C16 a_n129_n100# w_n359_n310# 0.10fF
+C17 a_n221_n100# w_n359_n310# 0.13fF
+C18 a_n176_122# w_n359_n310# 0.64fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_XACJHL VSUBS a_n81_n197# w_n263_n319# a_n33_n100#
++ a_63_n100# a_n125_n100#
+X0 a_63_n100# a_n81_n197# a_n33_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n33_n100# a_n81_n197# a_n125_n100# w_n263_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n263_n319# a_63_n100# 0.13fF
+C1 a_n33_n100# a_n81_n197# 0.08fF
+C2 a_n33_n100# a_n125_n100# 0.29fF
+C3 a_n81_n197# w_n263_n319# 0.11fF
+C4 a_63_n100# a_n125_n100# 0.11fF
+C5 w_n263_n319# a_n125_n100# 0.13fF
+C6 a_n33_n100# a_63_n100# 0.29fF
+C7 a_n33_n100# w_n263_n319# 0.09fF
+C8 a_63_n100# VSUBS 0.03fF
+C9 a_n33_n100# VSUBS 0.03fF
+C10 a_n125_n100# VSUBS 0.03fF
+C11 a_n81_n197# VSUBS 0.23fF
+C12 w_n263_n319# VSUBS 2.05fF
+.ends
+
+.subckt iref_ctrl_res_amp m1_n356_n363# avss1p8 vctrl reg2 avdd1p8 reg0 m1_1996_n363#
++ reg1 iref m1_964_n363# m1_511_801# m1_1384_n363#
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 iref m1_n356_n363# m1_n356_n363# iref iref iref
++ avss1p8 iref m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_n356_n363# m1_n356_n363# avdd1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 m1_n356_n363# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_0 m1_964_n363# avss1p8 vctrl iref vctrl sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_MVT43V_1 m1_964_n363# avss1p8 avss1p8 reg0 avss1p8 sky130_fd_pr__nfet_01v8_lvt_MVT43V
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_0 vctrl m1_1996_n363# vctrl avss1p8 m1_1996_n363#
++ iref m1_1996_n363# vctrl m1_1996_n363# vctrl vctrl sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_NMSMYT_1 avss1p8 m1_1996_n363# avss1p8 avss1p8 m1_1996_n363#
++ reg2 m1_1996_n363# avss1p8 m1_1996_n363# avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt_NMSMYT
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 m1_448_n363# avss1p8 iref m1_448_n363# vctrl
++ vctrl sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 m1_448_n363# avss1p8 avdd1p8 m1_448_n363# avss1p8
++ avss1p8 sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__pfet_01v8_XAYTAL_0 avss1p8 avdd1p8 m1_511_801# avss1p8 m1_511_801#
++ avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8_XAYTAL
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_0 vctrl m1_1384_n363# vctrl m1_1384_n363# avss1p8
++ iref vctrl sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__nfet_01v8_lvt_B2JNY3_1 avss1p8 m1_1384_n363# avss1p8 m1_1384_n363#
++ avss1p8 reg1 avss1p8 sky130_fd_pr__nfet_01v8_lvt_B2JNY3
+Xsky130_fd_pr__pfet_01v8_XACJHL_0 avss1p8 vctrl avdd1p8 m1_511_801# vctrl vctrl sky130_fd_pr__pfet_01v8_XACJHL
+C0 reg1 vctrl 0.06fF
+C1 iref avdd1p8 0.32fF
+C2 iref m1_n356_n363# 1.89fF
+C3 iref vctrl 2.27fF
+C4 reg0 m1_964_n363# 0.47fF
+C5 m1_1384_n363# vctrl 0.95fF
+C6 reg2 reg1 0.04fF
+C7 m1_1996_n363# vctrl 1.72fF
+C8 reg2 iref 0.03fF
+C9 reg0 avdd1p8 0.03fF
+C10 reg0 vctrl 0.04fF
+C11 iref m1_448_n363# 0.29fF
+C12 iref reg1 0.03fF
+C13 m1_511_801# avdd1p8 1.05fF
+C14 m1_511_801# vctrl 1.08fF
+C15 m1_1996_n363# reg2 1.30fF
+C16 m1_1384_n363# reg1 0.85fF
+C17 iref m1_1384_n363# 0.22fF
+C18 m1_964_n363# vctrl 0.52fF
+C19 m1_1996_n363# reg1 0.06fF
+C20 m1_1996_n363# iref 0.41fF
+C21 reg0 reg1 0.04fF
+C22 reg0 iref 0.02fF
+C23 avdd1p8 m1_n356_n363# 1.41fF
+C24 avdd1p8 vctrl 0.52fF
+C25 m1_n356_n363# vctrl 0.08fF
+C26 m1_1996_n363# m1_1384_n363# 0.18fF
+C27 reg0 m1_1384_n363# 0.06fF
+C28 m1_511_801# iref 0.05fF
+C29 m1_448_n363# m1_964_n363# 0.24fF
+C30 iref m1_964_n363# 0.11fF
+C31 reg2 vctrl 0.07fF
+C32 avdd1p8 m1_448_n363# 0.77fF
+C33 m1_448_n363# m1_n356_n363# 0.17fF
+C34 m1_448_n363# vctrl 1.16fF
+C35 m1_1384_n363# m1_964_n363# 0.18fF
+C36 m1_511_801# avss1p8 -1.62fF
+C37 m1_1384_n363# avss1p8 1.30fF
+C38 reg1 avss1p8 1.36fF
+C39 m1_448_n363# avss1p8 -0.27fF
+C40 vctrl avss1p8 2.17fF
+C41 m1_1996_n363# avss1p8 -0.61fF
+C42 reg2 avss1p8 1.98fF
+C43 reg0 avss1p8 0.44fF
+C44 m1_964_n363# avss1p8 -0.38fF
+C45 avdd1p8 avss1p8 6.02fF
+C46 m1_n356_n363# avss1p8 1.89fF
+C47 iref avss1p8 2.30fF
+.ends
+
+.subckt res_amp_lin_prog delay_cell_buff_0/mux_2to1_logic_0/out iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp delay_cell_buff_0/mux_2to1_logic_3/DinA delay_cell_buff_0/mux_2to1_logic_3/out
++ res_amp_lin_0/vctrl iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_0/clk delay_cell_buff_0/nand_logic_0/in1
++ outp_cap avss1p8 outn_cap clk delay_cell_buff_0/mux_2to1_logic_1/sel_b delay_reg0
++ delay_cell_buff_0/mux_2to1_logic_4/DinA delay_cell_buff_0/mux_2to1_logic_4/DinB
++ outn delay_cell_buff_0/mux_2to1_logic_1/DinA outp delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in iref_reg1 iref_reg2
++ iref_ctrl_res_amp_0/m1_1384_n363# delay_cell_buff_0/buffer_no_inv_x05_3/in res_amp_lin_0/vp
++ delay_cell_buff_0/nand_logic_0/m1_21_n341# delay_cell_buff_0/mux_2to1_logic_1/out
++ delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ iref delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_0/a_3747_261# delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_13/in inn
++ delay_cell_buff_0/mux_2to1_logic_4/out iref_ctrl_res_amp_0/m1_1996_n363# delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ inverter_min_x4_0/out delay_cell_buff_0/mux_2to1_logic_4/sel_b rst
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_0 avss1p8 outn_cap avdd1p8 outn_cap res_amp_lin_0/clk
++ outn outn outn outn_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xsky130_fd_pr__pfet_01v8_lvt_4L9VGG_1 avss1p8 outp_cap avdd1p8 outp_cap res_amp_lin_0/clk
++ outp outp outp outp_cap sky130_fd_pr__pfet_01v8_lvt_4L9VGG
+Xdelay_cell_buff_0 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in delay_reg2
++ avss1p8 delay_cell_buff_0/mux_2to1_logic_4/DinA avdd1p8 delay_cell_buff_0/buffer_no_inv_x05_13/in
++ clk delay_cell_buff_0/mux_2to1_logic_3/DinA res_amp_lin_0/clk delay_cell_buff_0/mux_2to1_logic_3/DinB
++ delay_reg0 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in delay_reg1 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_cell_buff_0/nand_logic_0/in1 delay_cell_buff_0/mux_2to1_logic_2/out delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ delay_cell_buff_0/mux_2to1_logic_4/out delay_cell_buff_0/mux_2to1_logic_1/DinA delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_cell_buff_0/buffer_no_inv_x05_3/in delay_cell_buff_0/mux_2to1_logic_5/out
++ delay_cell_buff_0/mux_2to1_logic_0/out delay_cell_buff_0/mux_2to1_logic_4/DinB delay_cell_buff_0/mux_2to1_logic_3/out
++ delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in delay_cell_buff_0/mux_2to1_logic_1/out
++ avss1p8 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ delay_cell_buff
+Xinverter_min_x4_0 avdd1p8 res_amp_lin_0/clk avss1p8 inverter_min_x4_0/out inverter_min_x4
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_0 outn_cap avss1p8 rst outn_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xres_amp_lin_0 res_amp_lin_0/clk res_amp_lin_0/vctrl avdd1p8 avss1p8 res_amp_lin_0/a_3747_261#
++ res_amp_lin_0/vp inn outn outp inp res_amp_lin
+Xsky130_fd_pr__nfet_01v8_lvt_72JNYZ_1 outp_cap avss1p8 rst outp_cap avss1p8 avss1p8
++ sky130_fd_pr__nfet_01v8_lvt_72JNYZ
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_0 outn outn outn outn_cap outn_cap avss1p8 outn_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xsky130_fd_pr__nfet_01v8_lvt_595QY5_1 outp outp outp outp_cap outp_cap avss1p8 outp_cap
++ inverter_min_x4_0/out sky130_fd_pr__nfet_01v8_lvt_595QY5
+Xiref_ctrl_res_amp_0 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 res_amp_lin_0/vctrl
++ iref_reg2 avdd1p8 iref_reg0 iref_ctrl_res_amp_0/m1_1996_n363# iref_reg1 iref iref_ctrl_res_amp_0/m1_964_n363#
++ iref_ctrl_res_amp_0/m1_511_801# iref_ctrl_res_amp_0/m1_1384_n363# iref_ctrl_res_amp
+C0 rst outn_cap 0.34fF
+C1 inverter_min_x4_0/out res_amp_lin_0/clk 0.14fF
+C2 outp_cap avdd1p8 0.25fF
+C3 iref res_amp_lin_0/vctrl 0.10fF
+C4 outn res_amp_lin_0/clk 0.09fF
+C5 outp_cap outp 1.90fF
+C6 inverter_min_x4_0/out outn_cap 0.57fF
+C7 outp_cap rst 0.34fF
+C8 outn avdd1p8 0.36fF
+C9 outp inverter_min_x4_0/out 0.32fF
+C10 rst inverter_min_x4_0/out 0.01fF
+C11 outn outn_cap 1.90fF
+C12 outp_cap inverter_min_x4_0/out 0.57fF
+C13 res_amp_lin_0/clk avdd1p8 1.99fF
+C14 outn_cap res_amp_lin_0/clk 1.04fF
+C15 outp res_amp_lin_0/clk 0.09fF
+C16 outn_cap avdd1p8 0.26fF
+C17 outn inverter_min_x4_0/out 0.32fF
+C18 outp avdd1p8 0.34fF
+C19 outp_cap res_amp_lin_0/clk 1.04fF
+C20 res_amp_lin_0/vctrl avdd1p8 1.42fF
+C21 iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C22 iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C23 iref_reg1 avss1p8 0.47fF
+C24 iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C25 res_amp_lin_0/vctrl avss1p8 -1.88fF
+C26 iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.23fF
+C27 iref_reg2 avss1p8 -0.15fF
+C28 iref_reg0 avss1p8 -0.42fF
+C29 iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C30 iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.51fF
+C31 iref avss1p8 0.07fF
+C32 outn avss1p8 1.87fF
+C33 inp avss1p8 -0.35fF
+C34 outp avss1p8 -4.58fF
+C35 res_amp_lin_0/vp avss1p8 -4.89fF
+C36 inn avss1p8 0.17fF
+C37 res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C38 outn_cap avss1p8 -1.33fF
+C39 rst avss1p8 0.58fF
+C40 res_amp_lin_0/clk avss1p8 5.34fF
+C41 inverter_min_x4_0/out avss1p8 7.53fF
+C42 delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C43 delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C44 delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C45 delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C46 delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C47 delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C48 delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C49 delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C50 delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C51 delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C52 delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C53 clk avss1p8 -4.09fF
+C54 delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.03fF
+C55 delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C56 delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C57 delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C58 delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C59 delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C60 delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C61 delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C62 delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C63 delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C64 delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C65 delay_reg0 avss1p8 2.77fF
+C66 delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C67 delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C68 delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C69 delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C70 delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C71 delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C72 delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C73 delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C74 delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C75 delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C76 delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C77 delay_reg1 avss1p8 3.80fF
+C78 delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C79 delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C80 delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C81 delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C82 delay_reg2 avss1p8 11.07fF
+C83 avdd1p8 avss1p8 177.60fF
+C84 delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.03fF
+C85 delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C86 delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C87 delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C88 delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C89 delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C90 outp_cap avss1p8 -6.93fF
+.ends
+
+.subckt sky130_fd_pr__cap_mim_m3_1_U5ZKVF VSUBS m3_n700_n850# c1_n600_n750#
+X0 c1_n600_n750# m3_n700_n850# sky130_fd_pr__cap_mim_m3_1 l=7.5e+06u w=5.5e+06u
+C0 m3_n700_n850# c1_n600_n750# 5.48fF
+C1 m3_n700_n850# VSUBS 1.98fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_lvt_D3F744 VSUBS a_n285_n236# a_355_n236# a_n29_n236#
++ a_n413_n236# a_99_n236# a_n611_n262# a_483_n236# a_n669_n236# w_n807_n384# a_n157_n236#
++ a_n541_n236# a_227_n236# a_611_n236#
+X0 a_n157_n236# a_n611_n262# a_n285_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X1 a_611_n236# a_n611_n262# a_483_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X2 a_227_n236# a_n611_n262# a_99_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X3 a_n285_n236# a_n611_n262# a_n413_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X4 a_99_n236# a_n611_n262# a_n29_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X5 a_355_n236# a_n611_n262# a_227_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X6 a_483_n236# a_n611_n262# a_355_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X7 a_n29_n236# a_n611_n262# a_n157_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X8 a_n413_n236# a_n611_n262# a_n541_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+X9 a_n541_n236# a_n611_n262# a_n669_n236# w_n807_n384# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=2e+06u l=350000u
+C0 a_n611_n262# w_n807_n384# 0.60fF
+C1 a_483_n236# a_355_n236# 0.36fF
+C2 a_227_n236# a_483_n236# 0.15fF
+C3 a_n157_n236# a_n29_n236# 0.36fF
+C4 a_99_n236# a_n29_n236# 0.36fF
+C5 a_n157_n236# a_n541_n236# 0.09fF
+C6 a_n413_n236# a_n29_n236# 0.09fF
+C7 a_n413_n236# a_n541_n236# 0.36fF
+C8 a_355_n236# a_n29_n236# 0.09fF
+C9 a_611_n236# w_n807_n384# 0.19fF
+C10 a_227_n236# a_n29_n236# 0.15fF
+C11 a_n285_n236# a_n29_n236# 0.15fF
+C12 a_n285_n236# a_n541_n236# 0.15fF
+C13 a_n157_n236# w_n807_n384# 0.02fF
+C14 a_99_n236# w_n807_n384# 0.02fF
+C15 a_n413_n236# w_n807_n384# 0.06fF
+C16 a_355_n236# w_n807_n384# 0.06fF
+C17 a_227_n236# w_n807_n384# 0.02fF
+C18 a_n285_n236# w_n807_n384# 0.02fF
+C19 a_n413_n236# a_n669_n236# 0.15fF
+C20 a_483_n236# w_n807_n384# 0.09fF
+C21 a_n669_n236# a_n285_n236# 0.09fF
+C22 a_n157_n236# a_n611_n262# 0.08fF
+C23 a_n611_n262# a_99_n236# 0.08fF
+C24 a_n413_n236# a_n611_n262# 0.08fF
+C25 a_n611_n262# a_355_n236# 0.08fF
+C26 a_227_n236# a_n611_n262# 0.08fF
+C27 a_n285_n236# a_n611_n262# 0.08fF
+C28 a_n29_n236# w_n807_n384# 0.02fF
+C29 a_483_n236# a_n611_n262# 0.08fF
+C30 a_n541_n236# w_n807_n384# 0.09fF
+C31 a_n669_n236# a_n541_n236# 0.36fF
+C32 a_355_n236# a_611_n236# 0.15fF
+C33 a_227_n236# a_611_n236# 0.09fF
+C34 a_n157_n236# a_99_n236# 0.15fF
+C35 a_n413_n236# a_n157_n236# 0.15fF
+C36 a_n611_n262# a_n29_n236# 0.08fF
+C37 a_n611_n262# a_n541_n236# 0.08fF
+C38 a_355_n236# a_99_n236# 0.15fF
+C39 a_483_n236# a_611_n236# 0.36fF
+C40 a_n669_n236# w_n807_n384# 0.19fF
+C41 a_n157_n236# a_227_n236# 0.09fF
+C42 a_227_n236# a_99_n236# 0.36fF
+C43 a_n157_n236# a_n285_n236# 0.36fF
+C44 a_n285_n236# a_99_n236# 0.09fF
+C45 a_n413_n236# a_n285_n236# 0.36fF
+C46 a_227_n236# a_355_n236# 0.36fF
+C47 a_483_n236# a_99_n236# 0.09fF
+C48 a_611_n236# VSUBS 0.03fF
+C49 a_483_n236# VSUBS 0.03fF
+C50 a_355_n236# VSUBS 0.03fF
+C51 a_227_n236# VSUBS 0.03fF
+C52 a_99_n236# VSUBS 0.03fF
+C53 a_n29_n236# VSUBS 0.03fF
+C54 a_n157_n236# VSUBS 0.03fF
+C55 a_n285_n236# VSUBS 0.03fF
+C56 a_n413_n236# VSUBS 0.03fF
+C57 a_n541_n236# VSUBS 0.03fF
+C58 a_n669_n236# VSUBS 0.03fF
+C59 a_n611_n262# VSUBS 1.37fF
+C60 w_n807_n384# VSUBS 6.11fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_VCU74W VSUBS a_495_n100# a_n81_n100# a_399_n100# a_687_n100#
++ a_n749_n100# a_n273_n100# a_111_n100# a_n177_n100# a_n561_n100# a_15_n100# a_n465_n100#
++ a_n705_n197# a_303_n100# a_n369_n100# w_n887_n319# a_207_n100# a_n657_n100# a_591_n100#
+X0 a_303_n100# a_n705_n197# a_207_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_591_n100# a_n705_n197# a_495_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_207_n100# a_n705_n197# a_111_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_399_n100# a_n705_n197# a_303_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_495_n100# a_n705_n197# a_399_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_687_n100# a_n705_n197# a_591_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n561_n100# a_n705_n197# a_n657_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n465_n100# a_n705_n197# a_n561_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n657_n100# a_n705_n197# a_n749_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n369_n100# a_n705_n197# a_n465_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_15_n100# a_n705_n197# a_n81_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_111_n100# a_n705_n197# a_15_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n273_n100# a_n705_n197# a_n369_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n81_n100# a_n705_n197# a_n177_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n177_n100# a_n705_n197# a_n273_n100# w_n887_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_303_n100# a_n705_n197# 0.08fF
+C1 a_n177_n100# a_n273_n100# 0.29fF
+C2 a_n81_n100# a_303_n100# 0.05fF
+C3 a_399_n100# a_303_n100# 0.29fF
+C4 a_207_n100# a_495_n100# 0.06fF
+C5 w_n887_n319# a_303_n100# 0.02fF
+C6 a_n465_n100# a_n705_n197# 0.08fF
+C7 a_n465_n100# a_n81_n100# 0.05fF
+C8 a_n465_n100# w_n887_n319# 0.03fF
+C9 a_303_n100# a_15_n100# 0.06fF
+C10 a_n465_n100# a_n657_n100# 0.11fF
+C11 a_n81_n100# a_n705_n197# 0.08fF
+C12 a_399_n100# a_n705_n197# 0.08fF
+C13 w_n887_n319# a_n705_n197# 0.82fF
+C14 a_n81_n100# w_n887_n319# 0.02fF
+C15 a_399_n100# w_n887_n319# 0.03fF
+C16 a_303_n100# a_687_n100# 0.05fF
+C17 a_n657_n100# a_n705_n197# 0.08fF
+C18 w_n887_n319# a_n657_n100# 0.05fF
+C19 a_n705_n197# a_15_n100# 0.08fF
+C20 a_n81_n100# a_15_n100# 0.29fF
+C21 a_111_n100# a_495_n100# 0.05fF
+C22 a_399_n100# a_15_n100# 0.05fF
+C23 a_n465_n100# a_n749_n100# 0.06fF
+C24 w_n887_n319# a_15_n100# 0.02fF
+C25 a_207_n100# a_591_n100# 0.05fF
+C26 a_399_n100# a_687_n100# 0.06fF
+C27 w_n887_n319# a_687_n100# 0.10fF
+C28 a_n465_n100# a_n177_n100# 0.06fF
+C29 w_n887_n319# a_n749_n100# 0.10fF
+C30 a_n561_n100# a_n273_n100# 0.06fF
+C31 a_n657_n100# a_n749_n100# 0.29fF
+C32 a_n705_n197# a_n177_n100# 0.08fF
+C33 a_n81_n100# a_n177_n100# 0.29fF
+C34 w_n887_n319# a_n177_n100# 0.02fF
+C35 a_n369_n100# a_n273_n100# 0.29fF
+C36 a_n177_n100# a_15_n100# 0.11fF
+C37 a_303_n100# a_495_n100# 0.11fF
+C38 a_207_n100# a_111_n100# 0.29fF
+C39 a_n465_n100# a_n561_n100# 0.29fF
+C40 a_n705_n197# a_495_n100# 0.08fF
+C41 a_399_n100# a_495_n100# 0.29fF
+C42 w_n887_n319# a_495_n100# 0.04fF
+C43 a_n465_n100# a_n369_n100# 0.29fF
+C44 a_n705_n197# a_n561_n100# 0.08fF
+C45 w_n887_n319# a_n561_n100# 0.04fF
+C46 a_n657_n100# a_n561_n100# 0.29fF
+C47 a_n705_n197# a_n369_n100# 0.08fF
+C48 a_303_n100# a_591_n100# 0.06fF
+C49 a_n81_n100# a_n369_n100# 0.06fF
+C50 w_n887_n319# a_n369_n100# 0.02fF
+C51 a_687_n100# a_495_n100# 0.11fF
+C52 a_n657_n100# a_n369_n100# 0.06fF
+C53 a_111_n100# a_n273_n100# 0.05fF
+C54 a_n369_n100# a_15_n100# 0.05fF
+C55 a_n705_n197# a_591_n100# 0.08fF
+C56 a_399_n100# a_591_n100# 0.11fF
+C57 a_n561_n100# a_n749_n100# 0.11fF
+C58 w_n887_n319# a_591_n100# 0.05fF
+C59 a_207_n100# a_303_n100# 0.29fF
+C60 a_n369_n100# a_n749_n100# 0.05fF
+C61 a_n177_n100# a_n561_n100# 0.05fF
+C62 a_687_n100# a_591_n100# 0.29fF
+C63 a_207_n100# a_n705_n197# 0.08fF
+C64 a_n369_n100# a_n177_n100# 0.11fF
+C65 a_207_n100# a_n81_n100# 0.06fF
+C66 a_399_n100# a_207_n100# 0.11fF
+C67 a_207_n100# w_n887_n319# 0.02fF
+C68 a_111_n100# a_303_n100# 0.11fF
+C69 a_207_n100# a_15_n100# 0.11fF
+C70 a_111_n100# a_n705_n197# 0.08fF
+C71 a_n81_n100# a_111_n100# 0.11fF
+C72 a_399_n100# a_111_n100# 0.06fF
+C73 a_n465_n100# a_n273_n100# 0.11fF
+C74 w_n887_n319# a_111_n100# 0.02fF
+C75 a_207_n100# a_n177_n100# 0.05fF
+C76 a_111_n100# a_15_n100# 0.29fF
+C77 a_n705_n197# a_n273_n100# 0.08fF
+C78 a_n81_n100# a_n273_n100# 0.11fF
+C79 w_n887_n319# a_n273_n100# 0.02fF
+C80 a_n369_n100# a_n561_n100# 0.11fF
+C81 a_n657_n100# a_n273_n100# 0.05fF
+C82 a_n273_n100# a_15_n100# 0.06fF
+C83 a_591_n100# a_495_n100# 0.29fF
+C84 a_111_n100# a_n177_n100# 0.06fF
+C85 a_687_n100# VSUBS 0.03fF
+C86 a_591_n100# VSUBS 0.03fF
+C87 a_495_n100# VSUBS 0.03fF
+C88 a_399_n100# VSUBS 0.03fF
+C89 a_303_n100# VSUBS 0.03fF
+C90 a_207_n100# VSUBS 0.03fF
+C91 a_111_n100# VSUBS 0.03fF
+C92 a_15_n100# VSUBS 0.03fF
+C93 a_n81_n100# VSUBS 0.03fF
+C94 a_n177_n100# VSUBS 0.03fF
+C95 a_n273_n100# VSUBS 0.03fF
+C96 a_n369_n100# VSUBS 0.03fF
+C97 a_n465_n100# VSUBS 0.03fF
+C98 a_n561_n100# VSUBS 0.03fF
+C99 a_n657_n100# VSUBS 0.03fF
+C100 a_n749_n100# VSUBS 0.03fF
+C101 a_n705_n197# VSUBS 1.60fF
+C102 w_n887_n319# VSUBS 5.82fF
+.ends
+
+.subckt source_follower_buff_pmos m1_957_828# in avss1p8 avdd1p8 out iref
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 avss1p8 iref iref iref avss1p8 avss1p8 avss1p8
++ avss1p8 iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_957_828# m1_957_828# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_957_828# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__pfet_01v8_lvt_D3F744_0 avss1p8 out avss1p8 out avss1p8 avss1p8 in out
++ avss1p8 avdd1p8 avss1p8 out out avss1p8 sky130_fd_pr__pfet_01v8_lvt_D3F744
+Xsky130_fd_pr__pfet_01v8_VCU74W_0 avss1p8 m1_957_828# m1_957_828# avdd1p8 m1_957_828#
++ avdd1p8 m1_957_828# m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# m1_957_828#
++ m1_957_828# avdd1p8 avdd1p8 avdd1p8 m1_957_828# avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+Xsky130_fd_pr__pfet_01v8_VCU74W_1 avss1p8 out out avdd1p8 out avdd1p8 out out avdd1p8
++ avdd1p8 avdd1p8 out m1_957_828# out avdd1p8 avdd1p8 avdd1p8 out avdd1p8 sky130_fd_pr__pfet_01v8_VCU74W
+C0 out avdd1p8 3.96fF
+C1 out m1_957_828# 1.52fF
+C2 iref avdd1p8 0.29fF
+C3 in avdd1p8 0.32fF
+C4 m1_957_828# iref 0.88fF
+C5 m1_957_828# in 0.52fF
+C6 out in 1.16fF
+C7 m1_957_828# avdd1p8 1.12fF
+C8 out avss1p8 -1.64fF
+C9 in avss1p8 1.94fF
+C10 avdd1p8 avss1p8 15.90fF
+C11 m1_957_828# avss1p8 -34.25fF
+C12 iref avss1p8 4.22fF
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CFLRKA a_n993_109# a_n1473_n309# a_63_n309# a_1215_n309#
++ a_1215_109# a_n129_n309# a_735_109# a_1599_109# a_n513_n309# a_255_109# a_n1377_n309#
++ a_n1949_109# a_n1761_n309# a_1119_n309# a_1503_n309# a_n1761_109# a_n417_109# a_n417_n309#
++ a_n1281_109# a_n801_n309# a_351_n309# a_63_109# a_1503_109# a_n1665_n309# a_1023_109#
++ a_1887_109# a_1407_n309# a_543_109# a_n705_n309# a_255_n309# a_1791_n309# a_n1569_109#
++ a_n705_109# a_n1569_n309# a_n1089_109# w_n2087_n519# a_n225_109# a_n609_n309# a_159_n309#
++ a_543_n309# a_1695_n309# a_1311_109# a_831_109# a_1695_109# a_n1857_n309# a_n993_n309#
++ a_n33_109# a_351_109# a_n1857_109# a_447_n309# a_831_n309# a_1599_n309# a_n1377_109#
++ a_n897_n309# a_n897_109# a_n513_109# a_1119_109# a_639_109# a_n33_n309# a_735_n309#
++ a_1887_n309# a_159_109# a_n1665_109# a_n1281_n309# a_1023_n309# a_n1185_109# a_n801_109#
++ a_639_n309# a_n321_109# a_1407_109# a_n321_n309# a_927_109# a_447_109# a_1791_109#
++ a_n1185_n309# a_1311_n309# a_n1905_n87# a_927_n309# a_n609_109# a_n225_n309# a_n1473_109#
++ a_n129_109# a_n1949_n309# a_n1089_n309#
+X0 a_n1569_n309# a_n1905_n87# a_n1665_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n87# a_n993_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_927_n309# a_n1905_n87# a_831_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1023_109# a_n1905_n87# a_927_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_255_n309# a_n1905_n87# a_159_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n87# a_1119_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_927_109# a_n1905_n87# a_831_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_n1857_n309# a_n1905_n87# a_n1949_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n321_n309# a_n1905_n87# a_n417_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n1761_109# a_n1905_n87# a_n1857_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_543_n309# a_n1905_n87# a_447_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_1503_n309# a_n1905_n87# a_1407_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n1857_109# a_n1905_n87# a_n1949_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_n1665_109# a_n1905_n87# a_n1761_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1569_109# a_n1905_n87# a_n1665_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1215_109# a_n1905_n87# a_1119_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_1311_109# a_n1905_n87# a_1215_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_1503_109# a_n1905_n87# a_1407_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_1791_109# a_n1905_n87# a_1695_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n87# a_n1281_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_1119_109# a_n1905_n87# a_1023_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1407_109# a_n1905_n87# a_1311_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_1599_109# a_n1905_n87# a_1503_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1695_109# a_n1905_n87# a_1599_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1887_109# a_n1905_n87# a_1791_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_n1473_n309# a_n1905_n87# a_n1569_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_831_n309# a_n1905_n87# a_735_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1791_n309# a_n1905_n87# a_1695_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n33_109# a_n1905_n87# a_n129_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_351_109# a_n1905_n87# a_255_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_159_n309# a_n1905_n87# a_63_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1119_n309# a_n1905_n87# a_1023_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_159_109# a_n1905_n87# a_63_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_255_109# a_n1905_n87# a_159_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_447_109# a_n1905_n87# a_351_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_543_109# a_n1905_n87# a_447_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_735_109# a_n1905_n87# a_639_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_831_109# a_n1905_n87# a_735_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n225_n309# a_n1905_n87# a_n321_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_639_109# a_n1905_n87# a_543_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_447_n309# a_n1905_n87# a_351_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_1407_n309# a_n1905_n87# a_1311_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_n1473_109# a_n1905_n87# a_n1569_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_n1281_109# a_n1905_n87# a_n1377_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_n1185_109# a_n1905_n87# a_n1281_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_n993_109# a_n1905_n87# a_n1089_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_n1089_n309# a_n1905_n87# a_n1185_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n1377_109# a_n1905_n87# a_n1473_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n1089_109# a_n1905_n87# a_n1185_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_n321_109# a_n1905_n87# a_n417_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n513_n309# a_n1905_n87# a_n609_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_63_n309# a_n1905_n87# a_n33_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_n801_109# a_n1905_n87# a_n897_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_n705_109# a_n1905_n87# a_n801_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_n513_109# a_n1905_n87# a_n609_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_n417_109# a_n1905_n87# a_n513_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n225_109# a_n1905_n87# a_n321_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n129_109# a_n1905_n87# a_n225_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n1377_n309# a_n1905_n87# a_n1473_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_735_n309# a_n1905_n87# a_639_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_1695_n309# a_n1905_n87# a_1599_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n897_109# a_n1905_n87# a_n993_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n609_109# a_n1905_n87# a_n705_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n801_n309# a_n1905_n87# a_n897_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n129_n309# a_n1905_n87# a_n225_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n1761_n309# a_n1905_n87# a_n1857_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n417_n309# a_n1905_n87# a_n513_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_109# a_n1905_n87# a_n33_109# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_639_n309# a_n1905_n87# a_543_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_1599_n309# a_n1905_n87# a_1503_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n705_n309# a_n1905_n87# a_n801_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1887_n309# a_n1905_n87# a_1791_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n1665_n309# a_n1905_n87# a_n1761_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_1023_n309# a_n1905_n87# a_927_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n993_n309# a_n1905_n87# a_n1089_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_n33_n309# a_n1905_n87# a_n129_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_351_n309# a_n1905_n87# a_255_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_1311_n309# a_n1905_n87# a_1215_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n1281_n309# a_n1905_n87# a_n1377_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_n609_n309# a_n1905_n87# a_n705_n309# w_n2087_n519# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n1089_109# a_n1473_109# 0.05fF
+C1 a_447_109# a_639_109# 0.11fF
+C2 a_n609_109# a_n513_109# 0.29fF
+C3 a_1407_109# a_1407_n309# 0.01fF
+C4 a_543_109# a_543_n309# 0.01fF
+C5 a_1503_109# a_1695_109# 0.11fF
+C6 a_n1857_109# a_n1569_109# 0.06fF
+C7 a_1695_n309# a_1791_n309# 0.29fF
+C8 a_n993_n309# a_n801_n309# 0.11fF
+C9 a_1119_n309# a_1215_n309# 0.29fF
+C10 a_n609_n309# a_n513_n309# 0.29fF
+C11 a_n1473_109# a_n1377_109# 0.29fF
+C12 a_1887_n309# a_1599_n309# 0.06fF
+C13 a_63_109# a_351_109# 0.06fF
+C14 a_n417_n309# a_n417_109# 0.01fF
+C15 a_63_109# a_n321_109# 0.05fF
+C16 a_639_n309# a_639_109# 0.01fF
+C17 a_159_n309# a_255_n309# 0.29fF
+C18 a_n993_n309# a_n705_n309# 0.06fF
+C19 a_1311_109# a_1599_109# 0.06fF
+C20 a_n33_n309# a_159_n309# 0.11fF
+C21 a_n513_109# a_n513_n309# 0.01fF
+C22 a_351_n309# a_159_n309# 0.11fF
+C23 a_n225_109# a_n417_109# 0.11fF
+C24 a_n993_109# a_n897_109# 0.29fF
+C25 a_n993_109# a_n1089_109# 0.29fF
+C26 a_1311_109# a_1695_109# 0.05fF
+C27 a_1695_n309# a_1311_n309# 0.05fF
+C28 a_927_109# a_639_109# 0.06fF
+C29 a_n1185_n309# a_n1569_n309# 0.05fF
+C30 a_n609_109# a_n897_109# 0.06fF
+C31 a_n321_n309# a_n321_109# 0.01fF
+C32 a_n993_109# a_n1377_109# 0.05fF
+C33 a_831_109# a_1023_109# 0.11fF
+C34 a_n609_109# a_n417_109# 0.11fF
+C35 a_1023_n309# a_1119_n309# 0.29fF
+C36 a_n225_109# a_n321_109# 0.29fF
+C37 a_n705_109# a_n513_109# 0.11fF
+C38 a_n1665_n309# a_n1665_109# 0.01fF
+C39 a_1791_n309# a_1407_n309# 0.05fF
+C40 a_63_109# a_n33_109# 0.29fF
+C41 a_n1185_109# a_n897_109# 0.06fF
+C42 a_1503_109# a_1791_109# 0.06fF
+C43 a_n993_109# a_n993_n309# 0.01fF
+C44 a_n1185_109# a_n1089_109# 0.29fF
+C45 a_n129_n309# a_255_n309# 0.05fF
+C46 a_n609_109# a_n321_109# 0.06fF
+C47 a_543_109# a_351_109# 0.11fF
+C48 a_1599_109# a_1695_109# 0.29fF
+C49 a_n129_n309# a_n33_n309# 0.29fF
+C50 a_n1185_109# a_n1377_109# 0.11fF
+C51 a_n1185_109# a_n1185_n309# 0.01fF
+C52 a_n1473_n309# a_n1377_n309# 0.29fF
+C53 a_1119_n309# a_1503_n309# 0.05fF
+C54 a_n129_n309# a_n129_109# 0.01fF
+C55 a_1215_109# a_1023_109# 0.11fF
+C56 a_351_109# a_159_109# 0.11fF
+C57 a_1887_n309# a_1503_n309# 0.05fF
+C58 a_639_n309# a_543_n309# 0.29fF
+C59 a_1215_109# a_1215_n309# 0.01fF
+C60 a_n225_109# a_n33_109# 0.11fF
+C61 a_447_n309# a_543_n309# 0.29fF
+C62 a_1311_n309# a_1407_n309# 0.29fF
+C63 a_63_109# a_255_109# 0.11fF
+C64 a_n705_109# a_n897_109# 0.11fF
+C65 a_n705_109# a_n1089_109# 0.05fF
+C66 a_1695_n309# a_1407_n309# 0.06fF
+C67 a_639_n309# a_927_n309# 0.06fF
+C68 a_n705_109# a_n417_109# 0.06fF
+C69 a_1503_109# a_1215_109# 0.06fF
+C70 a_831_n309# a_543_n309# 0.06fF
+C71 a_n1857_109# a_n1665_109# 0.11fF
+C72 a_n897_n309# a_n801_n309# 0.29fF
+C73 a_351_109# a_735_109# 0.05fF
+C74 a_n225_n309# a_n417_n309# 0.11fF
+C75 a_831_n309# a_927_n309# 0.29fF
+C76 a_n705_109# a_n321_109# 0.05fF
+C77 a_255_n309# a_543_n309# 0.06fF
+C78 a_n129_n309# a_159_n309# 0.06fF
+C79 a_n897_n309# a_n705_n309# 0.11fF
+C80 a_927_109# a_927_n309# 0.01fF
+C81 a_1599_109# a_1791_109# 0.11fF
+C82 a_159_109# a_n33_109# 0.11fF
+C83 a_n321_n309# a_n225_n309# 0.29fF
+C84 a_351_n309# a_543_n309# 0.11fF
+C85 a_1023_109# a_735_109# 0.06fF
+C86 a_447_109# a_351_109# 0.29fF
+C87 a_n225_109# a_n225_n309# 0.01fF
+C88 a_1311_109# a_1215_109# 0.29fF
+C89 a_n1473_n309# a_n1473_109# 0.01fF
+C90 a_735_n309# a_543_n309# 0.11fF
+C91 a_n129_109# a_n513_109# 0.05fF
+C92 a_1791_109# a_1695_109# 0.29fF
+C93 a_n1761_109# a_n1473_109# 0.06fF
+C94 a_n1569_109# a_n1665_109# 0.29fF
+C95 a_n1281_109# a_n1473_109# 0.11fF
+C96 a_n1377_n309# a_n1761_n309# 0.05fF
+C97 a_255_109# a_543_109# 0.06fF
+C98 a_1407_109# a_1023_109# 0.05fF
+C99 a_735_n309# a_927_n309# 0.11fF
+C100 a_n1377_n309# a_n1569_n309# 0.11fF
+C101 a_n1857_109# a_n1949_109# 0.29fF
+C102 a_n801_109# a_n801_n309# 0.01fF
+C103 a_n1473_n309# a_n1761_n309# 0.06fF
+C104 a_1887_109# a_1503_109# 0.05fF
+C105 a_255_109# a_159_109# 0.29fF
+C106 a_n801_n309# a_n705_n309# 0.29fF
+C107 a_1599_109# a_1215_109# 0.05fF
+C108 a_1311_n309# a_927_n309# 0.05fF
+C109 a_n1761_n309# a_n1761_109# 0.01fF
+C110 a_n1473_n309# a_n1569_n309# 0.29fF
+C111 a_1503_109# a_1407_109# 0.29fF
+C112 a_n225_n309# a_n513_n309# 0.06fF
+C113 a_159_n309# a_543_n309# 0.05fF
+C114 a_n993_109# a_n1281_109# 0.06fF
+C115 a_n801_n309# a_n417_n309# 0.05fF
+C116 a_n225_n309# a_63_n309# 0.06fF
+C117 a_n129_109# a_n417_109# 0.06fF
+C118 a_n1569_109# a_n1949_109# 0.05fF
+C119 a_351_109# a_351_n309# 0.01fF
+C120 a_927_109# a_1023_109# 0.29fF
+C121 a_n417_n309# a_n705_n309# 0.06fF
+C122 a_n897_n309# a_n513_n309# 0.05fF
+C123 a_831_n309# a_1215_n309# 0.05fF
+C124 a_n1949_109# a_n1949_n309# 0.01fF
+C125 a_n321_109# a_n129_109# 0.11fF
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+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_lvt_CAF2P9 a_63_n309# a_n1473_n309# a_159_527# a_1215_n309#
++ a_n993_109# a_1215_109# a_n129_n309# a_n513_n309# a_1599_109# a_735_109# a_n1665_527#
++ a_n1281_n727# a_n801_527# a_1023_n727# a_639_n727# a_255_109# a_n1185_527# a_n1377_n309#
++ a_n1949_109# a_1119_n309# a_n1761_n309# a_n321_527# a_1503_n309# a_1407_527# a_n321_n727#
++ a_927_527# a_n1761_109# a_n417_109# a_n417_n309# a_351_n309# a_n801_n309# a_n1905_n505#
++ a_n1281_109# a_n1185_n727# a_447_527# a_1791_527# a_63_109# a_1311_n727# a_927_n727#
++ a_1503_109# a_n1665_n309# a_1407_n309# a_1887_109# a_n225_n727# a_1023_109# a_n609_527#
++ a_543_109# a_255_n309# a_n1473_527# a_n1949_n727# a_1791_n309# a_n705_n309# a_n129_527#
++ a_n1089_n727# a_n1473_n727# a_1215_n727# a_63_n727# a_n993_527# a_n1569_109# a_n1569_n309#
++ a_n705_109# a_1215_527# a_n129_n727# a_n1089_109# a_1599_527# a_n513_n727# a_735_527#
++ a_n225_109# a_1695_n309# a_159_n309# a_n609_n309# a_543_n309# a_255_527# a_n1377_n727#
++ a_n1949_527# a_1119_n727# a_n1761_n727# a_1503_n727# a_1311_109# a_n993_n309# a_1695_109#
++ a_n1857_n309# a_831_109# a_n1761_527# a_n33_109# a_n417_n727# a_n417_527# a_351_109#
++ a_351_n727# a_n801_n727# a_n1281_527# a_n1857_109# a_1599_n309# a_447_n309# a_63_527#
++ a_831_n309# a_1503_527# a_n1377_109# a_n1665_n727# a_1887_527# a_1407_n727# a_n897_n309#
++ a_1023_527# a_n513_109# a_n897_109# a_543_527# a_1791_n727# a_255_n727# a_n705_n727#
++ a_1119_109# a_1887_n309# a_639_109# a_735_n309# a_n33_n309# a_n1569_527# a_n1569_n727#
++ a_n705_527# a_159_109# a_n1089_527# a_n225_527# w_n2087_n937# a_1695_n727# a_159_n727#
++ a_n609_n727# a_543_n727# a_n1665_109# a_n1281_n309# a_1023_n309# a_1311_527# a_n801_109#
++ a_639_n309# a_1695_527# a_n1185_109# a_n993_n727# a_831_527# a_n1857_n727# a_n321_109#
++ a_1407_109# a_n33_527# a_n321_n309# a_351_527# a_927_109# a_1599_n727# a_n1857_527#
++ a_447_n727# a_831_n727# a_447_109# a_n1185_n309# a_n1377_527# a_1791_109# a_1311_n309#
++ a_n897_n727# a_927_n309# a_n513_527# a_n897_527# a_n225_n309# a_n609_109# a_1119_527#
++ a_1887_n727# a_n1949_n309# a_639_527# a_n1473_109# a_n129_109# a_735_n727# a_n33_n727#
++ a_n1089_n309#
+X0 a_927_n309# a_n1905_n505# a_831_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X1 a_n897_n309# a_n1905_n505# a_n993_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n1569_n309# a_n1905_n505# a_n1665_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n727# a_n1905_n505# a_n225_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X4 a_n1761_n727# a_n1905_n505# a_n1857_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n309# a_n1905_n505# a_1119_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_255_n309# a_n1905_n505# a_159_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1023_109# a_n1905_n505# a_927_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n1857_n309# a_n1905_n505# a_n1949_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_927_109# a_n1905_n505# a_831_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 a_n417_n727# a_n1905_n505# a_n513_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 a_n321_n309# a_n1905_n505# a_n417_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_1599_n727# a_n1905_n505# a_1503_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 a_63_527# a_n1905_n505# a_n33_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n1761_109# a_n1905_n505# a_n1857_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_1503_n309# a_n1905_n505# a_1407_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 a_639_n727# a_n1905_n505# a_543_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_543_n309# a_n1905_n505# a_447_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_n1665_109# a_n1905_n505# a_n1761_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 a_n1185_n309# a_n1905_n505# a_n1281_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 a_n1569_109# a_n1905_n505# a_n1665_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_1311_109# a_n1905_n505# a_1215_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1857_109# a_n1905_n505# a_n1949_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_1791_109# a_n1905_n505# a_1695_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 a_1503_109# a_n1905_n505# a_1407_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 a_1215_109# a_n1905_n505# a_1119_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_n705_n727# a_n1905_n505# a_n801_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X27 a_1119_109# a_n1905_n505# a_1023_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_1695_109# a_n1905_n505# a_1599_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 a_1407_109# a_n1905_n505# a_1311_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_1599_109# a_n1905_n505# a_1503_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_1887_109# a_n1905_n505# a_1791_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 a_1887_n727# a_n1905_n505# a_1791_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 a_1791_n309# a_n1905_n505# a_1695_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 a_831_n309# a_n1905_n505# a_735_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 a_n1473_n309# a_n1905_n505# a_n1569_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 a_n33_109# a_n1905_n505# a_n129_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 a_1023_n727# a_n1905_n505# a_927_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 a_n1665_n727# a_n1905_n505# a_n1761_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 a_1119_n309# a_n1905_n505# a_1023_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 a_159_n309# a_n1905_n505# a_63_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 a_351_109# a_n1905_n505# a_255_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_1311_n727# a_n1905_n505# a_1215_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_255_109# a_n1905_n505# a_159_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 a_351_n727# a_n1905_n505# a_255_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 a_831_109# a_n1905_n505# a_735_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 a_543_109# a_n1905_n505# a_447_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 a_n33_n727# a_n1905_n505# a_n129_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 a_n993_n727# a_n1905_n505# a_n1089_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_159_109# a_n1905_n505# a_63_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 a_n225_n309# a_n1905_n505# a_n321_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_735_109# a_n1905_n505# a_639_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 a_447_109# a_n1905_n505# a_351_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_639_109# a_n1905_n505# a_543_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 a_1407_n309# a_n1905_n505# a_1311_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 a_447_n309# a_n1905_n505# a_351_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 a_n1089_n309# a_n1905_n505# a_n1185_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 a_n1281_109# a_n1905_n505# a_n1377_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 a_n993_109# a_n1905_n505# a_n1089_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 a_n1473_109# a_n1905_n505# a_n1569_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 a_n1185_109# a_n1905_n505# a_n1281_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 a_n609_n727# a_n1905_n505# a_n705_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 a_n1377_109# a_n1905_n505# a_n1473_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 a_n1089_109# a_n1905_n505# a_n1185_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 a_n1281_n727# a_n1905_n505# a_n1377_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_n513_n309# a_n1905_n505# a_n609_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 a_n321_109# a_n1905_n505# a_n417_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_63_n309# a_n1905_n505# a_n33_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 a_n225_109# a_n1905_n505# a_n321_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 a_n801_109# a_n1905_n505# a_n897_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 a_n513_109# a_n1905_n505# a_n609_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 a_1695_n309# a_n1905_n505# a_1599_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 a_n705_109# a_n1905_n505# a_n801_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 a_n417_109# a_n1905_n505# a_n513_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 a_n129_109# a_n1905_n505# a_n225_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 a_735_n309# a_n1905_n505# a_639_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 a_n1377_n309# a_n1905_n505# a_n1473_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 a_n897_109# a_n1905_n505# a_n993_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 a_n609_109# a_n1905_n505# a_n705_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_927_n727# a_n1905_n505# a_831_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 a_n1569_n727# a_n1905_n505# a_n1665_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 a_n897_n727# a_n1905_n505# a_n993_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 a_n801_n309# a_n1905_n505# a_n897_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 a_1215_n727# a_n1905_n505# a_1119_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 a_255_n727# a_n1905_n505# a_159_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_1023_527# a_n1905_n505# a_927_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 a_n129_n309# a_n1905_n505# a_n225_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 a_927_527# a_n1905_n505# a_831_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 a_n1857_n727# a_n1905_n505# a_n1949_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_n1761_n309# a_n1905_n505# a_n1857_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 a_n321_n727# a_n1905_n505# a_n417_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_n1761_527# a_n1905_n505# a_n1857_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 a_1503_n727# a_n1905_n505# a_1407_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 a_n1665_527# a_n1905_n505# a_n1761_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 a_543_n727# a_n1905_n505# a_447_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 a_n1185_n727# a_n1905_n505# a_n1281_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 a_n417_n309# a_n1905_n505# a_n513_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 a_n1857_527# a_n1905_n505# a_n1949_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 a_n1569_527# a_n1905_n505# a_n1665_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 a_1311_527# a_n1905_n505# a_1215_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 a_1215_527# a_n1905_n505# a_1119_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_1503_527# a_n1905_n505# a_1407_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 a_1791_527# a_n1905_n505# a_1695_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 a_1119_527# a_n1905_n505# a_1023_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 a_1407_527# a_n1905_n505# a_1311_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 a_1695_527# a_n1905_n505# a_1599_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 a_1599_n309# a_n1905_n505# a_1503_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 a_63_109# a_n1905_n505# a_n33_109# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 a_639_n309# a_n1905_n505# a_543_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 a_1599_527# a_n1905_n505# a_1503_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 a_1887_527# a_n1905_n505# a_1791_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 a_1791_n727# a_n1905_n505# a_1695_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_831_n727# a_n1905_n505# a_735_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 a_n1473_n727# a_n1905_n505# a_n1569_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_n705_n309# a_n1905_n505# a_n801_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 a_n33_527# a_n1905_n505# a_n129_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 a_1887_n309# a_n1905_n505# a_1791_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 a_1119_n727# a_n1905_n505# a_1023_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_159_n727# a_n1905_n505# a_63_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 a_351_527# a_n1905_n505# a_255_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 a_1023_n309# a_n1905_n505# a_927_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 a_n1665_n309# a_n1905_n505# a_n1761_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 a_255_527# a_n1905_n505# a_159_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 a_543_527# a_n1905_n505# a_447_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 a_831_527# a_n1905_n505# a_735_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 a_159_527# a_n1905_n505# a_63_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 a_447_527# a_n1905_n505# a_351_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 a_n225_n727# a_n1905_n505# a_n321_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 a_735_527# a_n1905_n505# a_639_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 a_639_527# a_n1905_n505# a_543_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 a_1407_n727# a_n1905_n505# a_1311_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 a_447_n727# a_n1905_n505# a_351_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 a_1311_n309# a_n1905_n505# a_1215_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 a_n1089_n727# a_n1905_n505# a_n1185_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 a_351_n309# a_n1905_n505# a_255_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_n33_n309# a_n1905_n505# a_n129_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 a_n1281_527# a_n1905_n505# a_n1377_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 a_n993_527# a_n1905_n505# a_n1089_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 a_n993_n309# a_n1905_n505# a_n1089_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 a_n1473_527# a_n1905_n505# a_n1569_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 a_n1185_527# a_n1905_n505# a_n1281_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 a_n1377_527# a_n1905_n505# a_n1473_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 a_n1089_527# a_n1905_n505# a_n1185_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 a_n513_n727# a_n1905_n505# a_n609_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 a_n321_527# a_n1905_n505# a_n417_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 a_63_n727# a_n1905_n505# a_n33_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 a_n801_527# a_n1905_n505# a_n897_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_n513_527# a_n1905_n505# a_n609_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 a_n225_527# a_n1905_n505# a_n321_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 a_1695_n727# a_n1905_n505# a_1599_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 a_735_n727# a_n1905_n505# a_639_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_n705_527# a_n1905_n505# a_n801_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_n417_527# a_n1905_n505# a_n513_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X153 a_n129_527# a_n1905_n505# a_n225_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X154 a_n1377_n727# a_n1905_n505# a_n1473_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X155 a_n609_n309# a_n1905_n505# a_n705_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X156 a_n1281_n309# a_n1905_n505# a_n1377_n309# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X157 a_n897_527# a_n1905_n505# a_n993_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X158 a_n609_527# a_n1905_n505# a_n705_527# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X159 a_n801_n727# a_n1905_n505# a_n897_n727# w_n2087_n937# sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 a_n225_n309# a_n609_n309# 0.05fF
+C1 a_n321_527# a_n417_527# 0.29fF
+C2 a_1311_109# a_1503_109# 0.11fF
+C3 a_1311_109# a_1695_109# 0.05fF
+C4 a_n225_n309# a_63_n309# 0.06fF
+C5 a_1599_n727# a_1407_n727# 0.11fF
+C6 a_1215_527# a_1311_527# 0.29fF
+C7 a_639_n727# a_639_n309# 0.01fF
+C8 a_n129_527# a_255_527# 0.05fF
+C9 a_63_109# a_63_527# 0.01fF
+C10 a_n1857_527# a_n1761_527# 0.29fF
+C11 a_1503_n727# a_1503_n309# 0.01fF
+C12 a_543_n727# a_351_n727# 0.11fF
+C13 a_1311_527# a_1503_527# 0.11fF
+C14 a_351_n309# a_255_n309# 0.29fF
+C15 a_n1377_527# a_n993_527# 0.05fF
+C16 a_n1281_n309# a_n1665_n309# 0.05fF
+C17 a_n897_n727# a_n1089_n727# 0.11fF
+C18 a_927_n309# a_831_n309# 0.29fF
+C19 a_n1281_n727# a_n1377_n727# 0.29fF
+C20 a_n33_527# a_n33_109# 0.01fF
+C21 a_n801_n309# a_n705_n309# 0.29fF
+C22 a_159_n309# a_447_n309# 0.06fF
+C23 a_n1569_527# a_n1185_527# 0.05fF
+C24 a_n1569_n727# a_n1569_n309# 0.01fF
+C25 a_n1569_n309# a_n1665_n309# 0.29fF
+C26 a_n801_n309# a_n801_n727# 0.01fF
+C27 a_n1569_527# a_n1949_527# 0.05fF
+C28 a_1791_109# a_1503_109# 0.06fF
+C29 a_1791_109# a_1695_109# 0.29fF
+C30 a_n1473_n309# a_n1473_n727# 0.01fF
+C31 a_n225_109# a_159_109# 0.05fF
+C32 a_63_109# a_n321_109# 0.05fF
+C33 a_1407_n309# a_1407_n727# 0.01fF
+C34 a_n33_527# a_159_527# 0.11fF
+C35 a_1887_n309# a_1791_n309# 0.29fF
+C36 a_n897_n727# a_n1185_n727# 0.06fF
+C37 a_n1761_n309# a_n1377_n309# 0.05fF
+C38 a_735_n727# a_447_n727# 0.06fF
+C39 a_n129_109# a_n513_109# 0.05fF
+C40 a_n321_n309# a_n513_n309# 0.11fF
+C41 a_351_527# a_639_527# 0.06fF
+C42 a_927_527# a_1311_527# 0.05fF
+C43 a_159_n309# a_n33_n309# 0.11fF
+C44 a_n1473_n309# a_n1473_109# 0.01fF
+C45 a_n1857_527# a_n1857_109# 0.01fF
+C46 a_n33_527# a_n417_527# 0.05fF
+C47 a_1119_527# a_831_527# 0.06fF
+C48 a_1695_n309# a_1887_n309# 0.11fF
+C49 a_n801_109# a_n705_109# 0.29fF
+C50 a_n1473_n309# a_n1665_n309# 0.11fF
+C51 a_n1377_n309# a_n1377_109# 0.01fF
+C52 a_n1761_n309# a_n1857_n309# 0.29fF
+C53 a_n417_109# a_n129_109# 0.06fF
+C54 a_1215_109# a_1503_109# 0.06fF
+C55 a_n1569_527# a_n1377_527# 0.11fF
+C56 a_735_n727# a_351_n727# 0.05fF
+C57 a_255_109# a_n129_109# 0.05fF
+C58 a_n609_527# a_n705_527# 0.29fF
+C59 a_n1281_n309# a_n1377_n309# 0.29fF
+C60 a_447_109# a_447_n309# 0.01fF
+C61 a_351_n309# a_735_n309# 0.05fF
+C62 a_1119_n727# a_1407_n727# 0.06fF
+C63 a_n705_n727# a_n321_n727# 0.05fF
+C64 a_735_527# a_735_109# 0.01fF
+C65 a_n609_n309# a_n897_n309# 0.06fF
+C66 a_63_527# a_n321_527# 0.05fF
+C67 a_n801_527# a_n417_527# 0.05fF
+C68 a_n1089_109# a_n1473_109# 0.05fF
+C69 a_1887_n309# a_1887_109# 0.01fF
+C70 a_n1377_n309# a_n1569_n309# 0.11fF
+C71 a_n129_n309# a_n129_109# 0.01fF
+C72 a_1215_n727# a_1023_n727# 0.11fF
+C73 a_1023_n309# a_927_n309# 0.29fF
+C74 a_543_527# a_735_527# 0.11fF
+C75 a_n1761_n309# a_n1761_109# 0.01fF
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+C728 a_1887_n309# a_1599_n309# 0.06fF
+C729 a_447_n727# a_543_n727# 0.29fF
+C730 a_n1473_n309# a_n1185_n309# 0.06fF
+C731 a_n705_109# a_n321_109# 0.05fF
+C732 a_n1761_n309# a_n1665_n309# 0.29fF
+C733 a_1311_n309# a_1695_n309# 0.05fF
+C734 a_n801_527# a_n609_527# 0.11fF
+C735 a_n801_n727# a_n1185_n727# 0.05fF
+C736 a_n705_n727# a_n1089_n727# 0.05fF
+C737 a_n1089_527# a_n993_527# 0.29fF
+C738 a_n1377_109# a_n1473_109# 0.29fF
+C739 a_1887_n727# w_n2087_n937# 0.12fF
+C740 a_1791_n727# w_n2087_n937# 0.08fF
+C741 a_1695_n727# w_n2087_n937# 0.06fF
+C742 a_1599_n727# w_n2087_n937# 0.06fF
+C743 a_1503_n727# w_n2087_n937# 0.04fF
+C744 a_1407_n727# w_n2087_n937# 0.04fF
+C745 a_1311_n727# w_n2087_n937# 0.04fF
+C746 a_1215_n727# w_n2087_n937# 0.04fF
+C747 a_1119_n727# w_n2087_n937# 0.04fF
+C748 a_1023_n727# w_n2087_n937# 0.04fF
+C749 a_927_n727# w_n2087_n937# 0.04fF
+C750 a_831_n727# w_n2087_n937# 0.04fF
+C751 a_735_n727# w_n2087_n937# 0.04fF
+C752 a_639_n727# w_n2087_n937# 0.04fF
+C753 a_543_n727# w_n2087_n937# 0.04fF
+C754 a_447_n727# w_n2087_n937# 0.04fF
+C755 a_351_n727# w_n2087_n937# 0.04fF
+C756 a_255_n727# w_n2087_n937# 0.04fF
+C757 a_159_n727# w_n2087_n937# 0.04fF
+C758 a_63_n727# w_n2087_n937# 0.04fF
+C759 a_n33_n727# w_n2087_n937# 0.04fF
+C760 a_n129_n727# w_n2087_n937# 0.04fF
+C761 a_n225_n727# w_n2087_n937# 0.04fF
+C762 a_n321_n727# w_n2087_n937# 0.04fF
+C763 a_n417_n727# w_n2087_n937# 0.04fF
+C764 a_n513_n727# w_n2087_n937# 0.04fF
+C765 a_n609_n727# w_n2087_n937# 0.04fF
+C766 a_n705_n727# w_n2087_n937# 0.04fF
+C767 a_n801_n727# w_n2087_n937# 0.04fF
+C768 a_n897_n727# w_n2087_n937# 0.04fF
+C769 a_n993_n727# w_n2087_n937# 0.04fF
+C770 a_n1089_n727# w_n2087_n937# 0.04fF
+C771 a_n1185_n727# w_n2087_n937# 0.04fF
+C772 a_n1281_n727# w_n2087_n937# 0.04fF
+C773 a_n1377_n727# w_n2087_n937# 0.04fF
+C774 a_n1473_n727# w_n2087_n937# 0.04fF
+C775 a_n1569_n727# w_n2087_n937# 0.04fF
+C776 a_n1665_n727# w_n2087_n937# 0.04fF
+C777 a_n1761_n727# w_n2087_n937# 0.04fF
+C778 a_n1857_n727# w_n2087_n937# 0.04fF
+C779 a_n1949_n727# w_n2087_n937# 0.04fF
+C780 a_1887_n309# w_n2087_n937# 0.11fF
+C781 a_1791_n309# w_n2087_n937# 0.07fF
+C782 a_1695_n309# w_n2087_n937# 0.05fF
+C783 a_1599_n309# w_n2087_n937# 0.05fF
+C784 a_1503_n309# w_n2087_n937# 0.03fF
+C785 a_1407_n309# w_n2087_n937# 0.03fF
+C786 a_1311_n309# w_n2087_n937# 0.03fF
+C787 a_1215_n309# w_n2087_n937# 0.03fF
+C788 a_1119_n309# w_n2087_n937# 0.03fF
+C789 a_1023_n309# w_n2087_n937# 0.03fF
+C790 a_927_n309# w_n2087_n937# 0.03fF
+C791 a_831_n309# w_n2087_n937# 0.03fF
+C792 a_735_n309# w_n2087_n937# 0.03fF
+C793 a_639_n309# w_n2087_n937# 0.03fF
+C794 a_543_n309# w_n2087_n937# 0.03fF
+C795 a_447_n309# w_n2087_n937# 0.03fF
+C796 a_351_n309# w_n2087_n937# 0.03fF
+C797 a_255_n309# w_n2087_n937# 0.03fF
+C798 a_159_n309# w_n2087_n937# 0.03fF
+C799 a_63_n309# w_n2087_n937# 0.03fF
+C800 a_n33_n309# w_n2087_n937# 0.03fF
+C801 a_n129_n309# w_n2087_n937# 0.03fF
+C802 a_n225_n309# w_n2087_n937# 0.03fF
+C803 a_n321_n309# w_n2087_n937# 0.03fF
+C804 a_n417_n309# w_n2087_n937# 0.03fF
+C805 a_n513_n309# w_n2087_n937# 0.03fF
+C806 a_n609_n309# w_n2087_n937# 0.03fF
+C807 a_n705_n309# w_n2087_n937# 0.03fF
+C808 a_n801_n309# w_n2087_n937# 0.03fF
+C809 a_n897_n309# w_n2087_n937# 0.03fF
+C810 a_n993_n309# w_n2087_n937# 0.03fF
+C811 a_n1089_n309# w_n2087_n937# 0.03fF
+C812 a_n1185_n309# w_n2087_n937# 0.03fF
+C813 a_n1281_n309# w_n2087_n937# 0.03fF
+C814 a_n1377_n309# w_n2087_n937# 0.03fF
+C815 a_n1473_n309# w_n2087_n937# 0.03fF
+C816 a_n1569_n309# w_n2087_n937# 0.03fF
+C817 a_n1665_n309# w_n2087_n937# 0.03fF
+C818 a_n1761_n309# w_n2087_n937# 0.03fF
+C819 a_n1857_n309# w_n2087_n937# 0.03fF
+C820 a_n1949_n309# w_n2087_n937# 0.03fF
+C821 a_1887_109# w_n2087_n937# 0.11fF
+C822 a_1791_109# w_n2087_n937# 0.07fF
+C823 a_1695_109# w_n2087_n937# 0.05fF
+C824 a_1599_109# w_n2087_n937# 0.05fF
+C825 a_1503_109# w_n2087_n937# 0.03fF
+C826 a_1407_109# w_n2087_n937# 0.03fF
+C827 a_1311_109# w_n2087_n937# 0.03fF
+C828 a_1215_109# w_n2087_n937# 0.03fF
+C829 a_1119_109# w_n2087_n937# 0.03fF
+C830 a_1023_109# w_n2087_n937# 0.03fF
+C831 a_927_109# w_n2087_n937# 0.03fF
+C832 a_831_109# w_n2087_n937# 0.03fF
+C833 a_735_109# w_n2087_n937# 0.03fF
+C834 a_639_109# w_n2087_n937# 0.03fF
+C835 a_543_109# w_n2087_n937# 0.03fF
+C836 a_447_109# w_n2087_n937# 0.03fF
+C837 a_351_109# w_n2087_n937# 0.03fF
+C838 a_255_109# w_n2087_n937# 0.03fF
+C839 a_159_109# w_n2087_n937# 0.03fF
+C840 a_63_109# w_n2087_n937# 0.03fF
+C841 a_n33_109# w_n2087_n937# 0.03fF
+C842 a_n129_109# w_n2087_n937# 0.03fF
+C843 a_n225_109# w_n2087_n937# 0.03fF
+C844 a_n321_109# w_n2087_n937# 0.03fF
+C845 a_n417_109# w_n2087_n937# 0.03fF
+C846 a_n513_109# w_n2087_n937# 0.03fF
+C847 a_n609_109# w_n2087_n937# 0.03fF
+C848 a_n705_109# w_n2087_n937# 0.03fF
+C849 a_n801_109# w_n2087_n937# 0.03fF
+C850 a_n897_109# w_n2087_n937# 0.03fF
+C851 a_n993_109# w_n2087_n937# 0.03fF
+C852 a_n1089_109# w_n2087_n937# 0.03fF
+C853 a_n1185_109# w_n2087_n937# 0.03fF
+C854 a_n1281_109# w_n2087_n937# 0.03fF
+C855 a_n1377_109# w_n2087_n937# 0.03fF
+C856 a_n1473_109# w_n2087_n937# 0.03fF
+C857 a_n1569_109# w_n2087_n937# 0.03fF
+C858 a_n1665_109# w_n2087_n937# 0.03fF
+C859 a_n1761_109# w_n2087_n937# 0.03fF
+C860 a_n1857_109# w_n2087_n937# 0.03fF
+C861 a_n1949_109# w_n2087_n937# 0.03fF
+C862 a_1887_527# w_n2087_n937# 0.12fF
+C863 a_1791_527# w_n2087_n937# 0.08fF
+C864 a_1695_527# w_n2087_n937# 0.06fF
+C865 a_1599_527# w_n2087_n937# 0.06fF
+C866 a_1503_527# w_n2087_n937# 0.04fF
+C867 a_1407_527# w_n2087_n937# 0.04fF
+C868 a_1311_527# w_n2087_n937# 0.04fF
+C869 a_1215_527# w_n2087_n937# 0.04fF
+C870 a_1119_527# w_n2087_n937# 0.04fF
+C871 a_1023_527# w_n2087_n937# 0.04fF
+C872 a_927_527# w_n2087_n937# 0.04fF
+C873 a_831_527# w_n2087_n937# 0.04fF
+C874 a_735_527# w_n2087_n937# 0.04fF
+C875 a_639_527# w_n2087_n937# 0.04fF
+C876 a_543_527# w_n2087_n937# 0.04fF
+C877 a_447_527# w_n2087_n937# 0.04fF
+C878 a_351_527# w_n2087_n937# 0.04fF
+C879 a_255_527# w_n2087_n937# 0.04fF
+C880 a_159_527# w_n2087_n937# 0.04fF
+C881 a_63_527# w_n2087_n937# 0.04fF
+C882 a_n33_527# w_n2087_n937# 0.04fF
+C883 a_n129_527# w_n2087_n937# 0.04fF
+C884 a_n225_527# w_n2087_n937# 0.04fF
+C885 a_n321_527# w_n2087_n937# 0.04fF
+C886 a_n417_527# w_n2087_n937# 0.04fF
+C887 a_n513_527# w_n2087_n937# 0.04fF
+C888 a_n609_527# w_n2087_n937# 0.04fF
+C889 a_n705_527# w_n2087_n937# 0.04fF
+C890 a_n801_527# w_n2087_n937# 0.04fF
+C891 a_n897_527# w_n2087_n937# 0.04fF
+C892 a_n993_527# w_n2087_n937# 0.04fF
+C893 a_n1089_527# w_n2087_n937# 0.04fF
+C894 a_n1185_527# w_n2087_n937# 0.04fF
+C895 a_n1281_527# w_n2087_n937# 0.04fF
+C896 a_n1377_527# w_n2087_n937# 0.04fF
+C897 a_n1473_527# w_n2087_n937# 0.04fF
+C898 a_n1569_527# w_n2087_n937# 0.04fF
+C899 a_n1665_527# w_n2087_n937# 0.04fF
+C900 a_n1761_527# w_n2087_n937# 0.04fF
+C901 a_n1857_527# w_n2087_n937# 0.04fF
+C902 a_n1949_527# w_n2087_n937# 0.04fF
+C903 a_n1905_n505# w_n2087_n937# 14.96fF
+.ends
+
+.subckt source_follower_buff_nmos w_2250_n1147# out avdd1p8 avss1p8 in m1_460_n1129#
++ iref w_2049_850# w_2250_1287# w_2250_355#
+Xsky130_fd_pr__nfet_01v8_lvt_CFLRKA_0 avdd1p8 out out out out out avdd1p8 out out
++ out avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8
++ avdd1p8 out avdd1p8 out out avdd1p8 out avdd1p8 out out out avdd1p8 out avdd1p8
++ out avss1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 avdd1p8 out avdd1p8 out avdd1p8
++ avdd1p8 avdd1p8 out out out out avdd1p8 out out out avdd1p8 out avdd1p8 avdd1p8
++ avdd1p8 avdd1p8 out out out avdd1p8 avdd1p8 out out out out avdd1p8 out out avdd1p8
++ avdd1p8 in avdd1p8 avdd1p8 avdd1p8 out out avdd1p8 out sky130_fd_pr__nfet_01v8_lvt_CFLRKA
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_0 m1_460_n1129# iref iref iref m1_460_n1129# m1_460_n1129#
++ avss1p8 m1_460_n1129# iref sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_9B2JY7_1 avss1p8 m1_460_n1129# m1_460_n1129# iref avss1p8
++ avss1p8 avss1p8 avss1p8 m1_460_n1129# sky130_fd_pr__nfet_01v8_lvt_9B2JY7
+Xsky130_fd_pr__nfet_01v8_lvt_CAF2P9_0 out out avss1p8 out avss1p8 out out out out
++ avss1p8 out out avss1p8 out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out
++ avss1p8 out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 iref out avss1p8
++ out out out avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 out avss1p8 avss1p8
++ out out avss1p8 out out out out out out out avss1p8 avss1p8 avss1p8 out out out
++ out out out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out avss1p8 avss1p8 avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out out out out avss1p8 avss1p8 out avss1p8
++ out out out out out avss1p8 out out out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8
++ avss1p8 out avss1p8 out avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 avss1p8 out out
++ out avss1p8 avss1p8 out avss1p8 avss1p8 avss1p8 out out out out avss1p8 out avss1p8
++ avss1p8 out out out out out avss1p8 avss1p8 out avss1p8 out avss1p8 out out avss1p8
++ avss1p8 avss1p8 avss1p8 avss1p8 out out out avss1p8 avss1p8 out sky130_fd_pr__nfet_01v8_lvt_CAF2P9
+C0 in out 10.03fF
+C1 iref in 0.11fF
+C2 in avdd1p8 2.17fF
+C3 iref m1_460_n1129# 2.64fF
+C4 iref out 22.08fF
+C5 avdd1p8 out 9.98fF
+C6 iref avss1p8 18.70fF
+C7 in avss1p8 -31.17fF
+C8 out avss1p8 -28.37fF
+C9 m1_460_n1129# avss1p8 2.61fF
+C10 avdd1p8 avss1p8 2.63fF
+.ends
+
+.subckt source_follower_buff_diff outn VSUBS avdd1p8 inp source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_nmos_1/m1_460_n1129# source_follower_buff_pmos_1/m1_957_828#
++ source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_nmos_1/in
++ source_follower_buff_nmos_0/w_2250_355# inn
+Xsource_follower_buff_pmos_0 source_follower_buff_pmos_0/m1_957_828# inn VSUBS avdd1p8
++ source_follower_buff_nmos_0/in iref3 source_follower_buff_pmos
+Xsource_follower_buff_pmos_1 source_follower_buff_pmos_1/m1_957_828# inp VSUBS avdd1p8
++ source_follower_buff_nmos_1/in iref1 source_follower_buff_pmos
+Xsource_follower_buff_nmos_0 source_follower_buff_nmos_0/w_2250_n1147# outn avdd1p8
++ VSUBS source_follower_buff_nmos_0/in source_follower_buff_nmos_0/m1_460_n1129# iref4
++ source_follower_buff_nmos_0/w_2049_850# source_follower_buff_nmos_0/w_2250_1287#
++ source_follower_buff_nmos_0/w_2250_355# source_follower_buff_nmos
+Xsource_follower_buff_nmos_1 source_follower_buff_nmos_1/w_2250_n1147# outp avdd1p8
++ VSUBS source_follower_buff_nmos_1/in source_follower_buff_nmos_1/m1_460_n1129# iref2
++ source_follower_buff_nmos_1/w_2049_850# source_follower_buff_nmos_1/w_2250_1287#
++ source_follower_buff_nmos_1/w_2250_355# source_follower_buff_nmos
+C0 avdd1p8 outn 0.18fF
+C1 inn avdd1p8 0.07fF
+C2 source_follower_buff_nmos_1/in outp 0.11fF
+C3 source_follower_buff_nmos_1/w_2250_n1147# outp 0.09fF
+C4 avdd1p8 source_follower_buff_nmos_0/w_2049_850# 0.16fF
+C5 inp source_follower_buff_pmos_1/m1_957_828# 0.08fF
+C6 avdd1p8 inp 0.07fF
+C7 source_follower_buff_nmos_0/w_2250_1287# avdd1p8 0.18fF
+C8 avdd1p8 source_follower_buff_nmos_1/in 0.63fF
+C9 inp iref1 0.01fF
+C10 inp source_follower_buff_nmos_1/in -0.25fF
+C11 source_follower_buff_nmos_0/in outn 0.11fF
+C12 source_follower_buff_nmos_0/in inn -0.25fF
+C13 source_follower_buff_nmos_0/in avdd1p8 0.63fF
+C14 inn source_follower_buff_pmos_0/m1_957_828# 0.08fF
+C15 inn iref3 0.01fF
+C16 iref2 VSUBS 11.84fF
+C17 source_follower_buff_nmos_1/in VSUBS -32.98fF
+C18 outp VSUBS 0.56fF
+C19 source_follower_buff_nmos_1/m1_460_n1129# VSUBS 1.47fF
+C20 iref4 VSUBS 12.04fF
+C21 source_follower_buff_nmos_0/in VSUBS -32.98fF
+C22 outn VSUBS 2.12fF
+C23 source_follower_buff_nmos_0/m1_460_n1129# VSUBS 1.50fF
+C24 avdd1p8 VSUBS 35.96fF
+C25 inp VSUBS 2.70fF
+C26 source_follower_buff_pmos_1/m1_957_828# VSUBS -35.44fF
+C27 iref1 VSUBS 3.02fF
+C28 inn VSUBS 4.09fF
+C29 source_follower_buff_pmos_0/m1_957_828# VSUBS -35.44fF
+C30 iref3 VSUBS 3.13fF
+.ends
+
+.subckt res_amp_top avss1p8 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ avdd1p8 iref0 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# iref1 res_amp_lin_prog_0/res_amp_lin_0/vp
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out iref2 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_lin_prog_0/outn iref3 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ delay_reg0 iref4 res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ inn source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# inp res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA delay_reg2 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/outp_cap iref_reg0 res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_sync_v2_0/clkp iref_reg1 source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ delay_reg1 outn source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ outp clkn res_amp_sync_v2_0/rst
+Xres_amp_sync_v2_0 avdd1p8 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 clkn res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280#
++ res_amp_sync_v2_0/DFlipFlop_4/nQ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_sync_v2_0/DFlipFlop_3/D res_amp_sync_v2_0/DFlipFlop_4/D
++ res_amp_sync_v2_0/DFlipFlop_1/D res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD
++ res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D
++ res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ
++ res_amp_sync_v2_0/clkp res_amp_sync_v2_0/rst res_amp_sync_v2
+Xres_amp_lin_prog_0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363#
++ delay_reg2 avdd1p8 inp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_lin_prog_0/res_amp_lin_0/clk
++ res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 res_amp_lin_prog_0/outp_cap
++ avss1p8 res_amp_lin_prog_0/outn_cap res_amp_lin_prog_0/clk res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB
++ res_amp_lin_prog_0/outn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA
++ res_amp_lin_prog_0/outp res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ iref_reg0 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ iref_reg1 iref_reg2 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in iref0
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363#
++ res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# delay_reg1 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ inn res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363#
++ res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in res_amp_lin_prog_0/inverter_min_x4_0/out
++ res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b res_amp_sync_v2_0/rst
++ res_amp_lin_prog
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_0 avss1p8 avss1p8 res_amp_lin_prog_0/outp_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsky130_fd_pr__cap_mim_m3_1_U5ZKVF_1 avss1p8 avss1p8 res_amp_lin_prog_0/outn_cap sky130_fd_pr__cap_mim_m3_1_U5ZKVF
+Xsource_follower_buff_diff_0 outn avss1p8 avdd1p8 res_amp_lin_prog_0/outp_cap source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ iref1 outp iref2 iref3 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# source_follower_buff_diff_0/source_follower_buff_nmos_1/in
++ source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# res_amp_lin_prog_0/outn_cap
++ source_follower_buff_diff
+C0 res_amp_lin_prog_0/outn_cap res_amp_sync_v2_0/rst 0.06fF
+C1 clkn res_amp_lin_prog_0/clk 0.07fF
+C2 res_amp_sync_v2_0/DFlipFlop_3/D avdd1p8 0.89fF
+C3 avdd1p8 iref0 -0.63fF
+C4 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C5 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# res_amp_lin_prog_0/clk 0.06fF
+C6 avdd1p8 delay_reg2 0.08fF
+C7 res_amp_sync_v2_0/DFlipFlop_3/Q res_amp_lin_prog_0/clk 0.25fF
+C8 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in res_amp_lin_prog_0/clk 0.48fF
+C9 res_amp_sync_v2_0/clkp avdd1p8 1.19fF
+C10 avdd1p8 clkn 0.74fF
+C11 avdd1p8 outp 0.31fF
+C12 delay_reg0 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.04fF
+C13 iref1 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.10fF
+C14 res_amp_sync_v2_0/rst res_amp_lin_prog_0/outp_cap 0.13fF
+C15 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.39fF
+C16 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/nQ 0.20fF
+C17 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C18 res_amp_sync_v2_0/rst inp 0.09fF
+C19 avdd1p8 iref_reg1 0.05fF
+C20 iref4 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# 0.13fF
+C21 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D res_amp_lin_prog_0/clk 0.23fF
+C22 avdd1p8 res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.03fF
+C23 avdd1p8 res_amp_lin_prog_0/clk 9.77fF
+C24 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D res_amp_lin_prog_0/clk 0.20fF
+C25 avdd1p8 inp 0.46fF
+C26 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD 0.25fF
+C27 delay_reg1 avdd1p8 0.04fF
+C28 avdd1p8 iref_reg2 -0.57fF
+C29 avdd1p8 res_amp_sync_v2_0/rst 0.80fF
+C30 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avdd1p8 0.02fF
+C31 res_amp_sync_v2_0/DFlipFlop_4/Q res_amp_lin_prog_0/clk 0.44fF
+C32 res_amp_sync_v2_0/DFlipFlop_4/D res_amp_lin_prog_0/clk 0.08fF
+C33 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out delay_reg2 0.03fF
+C34 outn source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# 0.15fF
+C35 inn inp 1.68fF
+C36 avdd1p8 res_amp_sync_v2_0/DFlipFlop_1/D 0.29fF
+C37 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# iref3 0.10fF
+C38 outn avdd1p8 0.30fF
+C39 res_amp_sync_v2_0/clkp clkn 0.06fF
+C40 res_amp_sync_v2_0/DFlipFlop_3/D res_amp_lin_prog_0/clk 0.07fF
+C41 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D res_amp_lin_prog_0/clk 0.47fF
+C42 res_amp_lin_prog_0/res_amp_lin_0/vctrl iref0 -0.03fF
+C43 res_amp_sync_v2_0/rst inn 0.09fF
+C44 iref0 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.02fF
+C45 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD res_amp_lin_prog_0/clk 0.28fF
+C46 avdd1p8 source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.40fF
+C47 avdd1p8 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# 1.10fF
+C48 res_amp_lin_prog_0/clk res_amp_sync_v2_0/DFlipFlop_4/nQ 0.22fF
+C49 avdd1p8 inn 0.46fF
+C50 avdd1p8 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# 0.02fF
+C51 iref2 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# 0.12fF
+C52 delay_reg1 delay_reg2 0.23fF
+C53 iref2 avss1p8 12.17fF
+C54 source_follower_buff_diff_0/source_follower_buff_nmos_1/in avss1p8 -32.88fF
+C55 outp avss1p8 -1.74fF
+C56 source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# avss1p8 1.82fF
+C57 iref4 avss1p8 12.36fF
+C58 source_follower_buff_diff_0/source_follower_buff_nmos_0/in avss1p8 -32.87fF
+C59 source_follower_buff_diff_0/source_follower_buff_nmos_0/w_2250_355# avss1p8 0.08fF
+C60 outn avss1p8 -1.13fF
+C61 source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# avss1p8 1.84fF
+C62 source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# avss1p8 -35.44fF
+C63 iref1 avss1p8 3.33fF
+C64 source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# avss1p8 -35.44fF
+C65 iref3 avss1p8 3.02fF
+C66 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# avss1p8 -1.87fF
+C67 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# avss1p8 0.47fF
+C68 iref_reg1 avss1p8 0.41fF
+C69 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# avss1p8 -1.10fF
+C70 res_amp_lin_prog_0/res_amp_lin_0/vctrl avss1p8 -1.99fF
+C71 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# avss1p8 -2.18fF
+C72 iref_reg2 avss1p8 0.06fF
+C73 iref_reg0 avss1p8 -0.21fF
+C74 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# avss1p8 -1.03fF
+C75 res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# avss1p8 0.55fF
+C76 iref0 avss1p8 0.37fF
+C77 res_amp_lin_prog_0/outn avss1p8 1.55fF
+C78 inp avss1p8 0.21fF
+C79 res_amp_lin_prog_0/outp avss1p8 -4.89fF
+C80 res_amp_lin_prog_0/res_amp_lin_0/vp avss1p8 -4.89fF
+C81 inn avss1p8 -6.68fF
+C82 res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# avss1p8 -0.95fF
+C83 res_amp_lin_prog_0/outn_cap avss1p8 1.00fF
+C84 res_amp_lin_prog_0/res_amp_lin_0/clk avss1p8 4.30fF
+C85 res_amp_lin_prog_0/inverter_min_x4_0/out avss1p8 4.87fF
+C86 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in avss1p8 1.07fF
+C87 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in avss1p8 1.03fF
+C88 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in avss1p8 1.03fF
+C89 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in avss1p8 1.07fF
+C90 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in avss1p8 1.03fF
+C91 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in avss1p8 1.03fF
+C92 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in avss1p8 1.07fF
+C93 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in avss1p8 1.03fF
+C94 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in avss1p8 1.07fF
+C95 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in avss1p8 1.03fF
+C96 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in avss1p8 1.03fF
+C97 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in avss1p8 1.04fF
+C98 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in avss1p8 1.07fF
+C99 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB avss1p8 -7.88fF
+C100 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in avss1p8 1.03fF
+C101 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in avss1p8 1.03fF
+C102 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in avss1p8 1.07fF
+C103 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in avss1p8 1.03fF
+C104 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C105 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in avss1p8 1.03fF
+C106 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b avss1p8 2.03fF
+C107 res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 avss1p8 1.54fF
+C108 delay_reg0 avss1p8 2.90fF
+C109 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b avss1p8 2.03fF
+C110 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out avss1p8 -1.67fF
+C111 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA avss1p8 -2.58fF
+C112 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b avss1p8 2.03fF
+C113 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out avss1p8 -2.25fF
+C114 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA avss1p8 -0.04fF
+C115 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b avss1p8 2.03fF
+C116 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out avss1p8 -2.69fF
+C117 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB avss1p8 -4.96fF
+C118 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b avss1p8 2.03fF
+C119 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out avss1p8 -4.71fF
+C120 delay_reg1 avss1p8 3.97fF
+C121 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA avss1p8 0.63fF
+C122 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b avss1p8 2.03fF
+C123 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out avss1p8 -2.49fF
+C124 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB avss1p8 -3.92fF
+C125 delay_reg2 avss1p8 11.33fF
+C126 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b avss1p8 2.04fF
+C127 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out avss1p8 -0.27fF
+C128 res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB avss1p8 -0.97fF
+C129 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in avss1p8 1.07fF
+C130 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in avss1p8 1.03fF
+C131 res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in avss1p8 1.03fF
+C132 res_amp_lin_prog_0/outp_cap avss1p8 -6.67fF
+C133 res_amp_sync_v2_0/nand_logic_1/m1_21_n341# avss1p8 0.72fF
+C134 res_amp_sync_v2_0/nand_logic_0/m1_21_n341# avss1p8 0.72fF
+C135 res_amp_lin_prog_0/clk avss1p8 -6.90fF
+C136 res_amp_sync_v2_0/inverter_min_x4_4/out avss1p8 5.85fF
+C137 res_amp_sync_v2_0/nand_logic_1/out avss1p8 1.70fF
+C138 res_amp_sync_v2_0/rst avss1p8 -3.03fF
+C139 res_amp_sync_v2_0/DFlipFlop_4/nQ avss1p8 0.48fF
+C140 res_amp_sync_v2_0/DFlipFlop_4/Q avss1p8 -2.08fF
+C141 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C142 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD avss1p8 0.57fF
+C143 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D avss1p8 -1.73fF
+C144 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C145 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C146 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D avss1p8 0.96fF
+C147 res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C148 res_amp_sync_v2_0/DFlipFlop_4/D avss1p8 1.83fF
+C149 res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD avss1p8 1.14fF
+C150 res_amp_sync_v2_0/nand_logic_0/out avss1p8 1.20fF
+C151 res_amp_sync_v2_0/DFlipFlop_0/Q avss1p8 -4.73fF
+C152 res_amp_sync_v2_0/DFlipFlop_3/nQ avss1p8 0.48fF
+C153 res_amp_sync_v2_0/DFlipFlop_3/Q avss1p8 -2.94fF
+C154 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C155 clkn avss1p8 -7.50fF
+C156 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD avss1p8 0.57fF
+C157 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D avss1p8 -1.73fF
+C158 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C159 res_amp_sync_v2_0/clkp avss1p8 -28.00fF
+C160 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C161 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D avss1p8 0.96fF
+C162 res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C163 res_amp_sync_v2_0/DFlipFlop_3/D avss1p8 1.33fF
+C164 res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD avss1p8 1.14fF
+C165 avdd1p8 avss1p8 415.30fF
+C166 res_amp_sync_v2_0/DFlipFlop_2/nQ avss1p8 0.48fF
+C167 res_amp_sync_v2_0/DFlipFlop_2/Q avss1p8 -1.08fF
+C168 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C169 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD avss1p8 0.57fF
+C170 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D avss1p8 -1.73fF
+C171 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C172 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C173 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D avss1p8 0.96fF
+C174 res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C175 res_amp_sync_v2_0/DFlipFlop_2/D avss1p8 -0.38fF
+C176 res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD avss1p8 1.14fF
+C177 res_amp_sync_v2_0/DFlipFlop_1/nQ avss1p8 0.48fF
+C178 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C179 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD avss1p8 0.57fF
+C180 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D avss1p8 -1.73fF
+C181 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C182 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C183 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D avss1p8 0.96fF
+C184 res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C185 res_amp_sync_v2_0/DFlipFlop_1/D avss1p8 -1.02fF
+C186 res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD avss1p8 1.14fF
+C187 res_amp_sync_v2_0/DFlipFlop_0/nQ avss1p8 0.48fF
+C188 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# avss1p8 0.57fF
+C189 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD avss1p8 0.57fF
+C190 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D avss1p8 -1.73fF
+C191 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# avss1p8 0.57fF
+C192 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in avss1p8 1.86fF
+C193 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D avss1p8 0.96fF
+C194 res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out avss1p8 1.76fF
+C195 res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD avss1p8 1.14fF
+.ends
+
 .subckt sky130_fd_pr__cap_mim_m3_1_MACBVW VSUBS m3_n2650_n13200# m3_n7969_n2600# m3_7988_8000#
 + m3_2669_n7900# m3_n13288_n2600# m3_n2650_2700# m3_2669_2700# m3_n13288_n13200# m3_n7969_n13200#
 + m3_n13288_8000# m3_7988_2700# m3_n2650_n7900# m3_7988_n7900# m3_2669_n13200# m3_n7969_8000#
@@ -30,71 +4105,71 @@
 X22 c1_n13188_n13100# m3_n7969_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
 X23 c1_n13188_n13100# m3_n2650_n2600# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
 X24 c1_n13188_n13100# m3_2669_2700# sky130_fd_pr__cap_mim_m3_1 l=2.5e+07u w=2.5e+07u
-C0 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
-C1 m3_7988_n2600# m3_7988_n7900# 3.39fF
-C2 m3_2669_n7900# m3_7988_n7900# 2.73fF
-C3 m3_2669_2700# m3_7988_2700# 2.73fF
-C4 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
-C5 m3_7988_8000# m3_7988_2700# 3.39fF
-C6 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
-C7 m3_n7969_8000# m3_n7969_2700# 3.28fF
-C8 m3_2669_8000# m3_n2650_8000# 2.73fF
-C9 m3_n13288_8000# m3_n7969_8000# 2.73fF
-C10 m3_2669_8000# c1_n13188_n13100# 58.61fF
-C11 m3_n13288_n13200# c1_n13188_n13100# 58.36fF
-C12 m3_7988_n13200# m3_7988_n7900# 3.39fF
-C13 m3_n7969_n2600# m3_n7969_2700# 3.28fF
-C14 m3_2669_n7900# m3_n2650_n7900# 2.73fF
-C15 m3_n2650_8000# m3_n2650_2700# 3.28fF
-C16 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
-C17 m3_n13288_n13200# m3_n7969_n13200# 2.73fF
-C18 m3_n13288_2700# m3_n13288_n2600# 3.28fF
-C19 c1_n13188_n13100# m3_n2650_2700# 58.86fF
-C20 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
-C21 m3_n13288_2700# c1_n13188_n13100# 58.61fF
-C22 m3_n13288_n13200# m3_n13288_n7900# 3.28fF
-C23 m3_n2650_8000# c1_n13188_n13100# 58.61fF
-C24 m3_2669_n13200# c1_n13188_n13100# 58.61fF
-C25 c1_n13188_n13100# m3_2669_n2600# 58.86fF
-C26 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
-C27 m3_n7969_n7900# c1_n13188_n13100# 58.86fF
-C28 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
-C29 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
-C30 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
-C31 m3_2669_n2600# m3_7988_n2600# 2.73fF
-C32 c1_n13188_n13100# m3_7988_2700# 61.01fF
-C33 m3_2669_n7900# m3_2669_n13200# 3.28fF
-C34 m3_2669_8000# m3_2669_2700# 3.28fF
-C35 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
-C36 m3_2669_n7900# m3_2669_n2600# 3.28fF
-C37 m3_7988_8000# m3_2669_8000# 2.73fF
-C38 c1_n13188_n13100# m3_7988_n2600# 61.01fF
-C39 m3_n7969_2700# m3_n2650_2700# 2.73fF
-C40 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
-C41 m3_n2650_n13200# m3_2669_n13200# 2.73fF
-C42 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
-C43 m3_n13288_2700# m3_n7969_2700# 2.73fF
-C44 m3_2669_n7900# c1_n13188_n13100# 58.86fF
-C45 m3_n2650_n13200# c1_n13188_n13100# 58.61fF
-C46 m3_n7969_8000# m3_n2650_8000# 2.73fF
-C47 m3_n13288_8000# m3_n13288_2700# 3.28fF
-C48 c1_n13188_n13100# m3_n7969_2700# 58.86fF
-C49 m3_7988_n2600# m3_7988_2700# 3.39fF
-C50 c1_n13188_n13100# m3_7988_n7900# 61.01fF
-C51 m3_2669_2700# m3_n2650_2700# 2.73fF
-C52 m3_n2650_n2600# m3_n2650_2700# 3.28fF
-C53 m3_n7969_8000# c1_n13188_n13100# 58.61fF
-C54 m3_n13288_8000# c1_n13188_n13100# 58.36fF
-C55 m3_n2650_n13200# m3_n7969_n13200# 2.73fF
-C56 m3_2669_2700# m3_2669_n2600# 3.28fF
-C57 m3_n2650_n2600# m3_2669_n2600# 2.73fF
-C58 m3_7988_n13200# m3_2669_n13200# 2.73fF
-C59 m3_2669_2700# c1_n13188_n13100# 58.86fF
-C60 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
-C61 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
-C62 m3_7988_8000# c1_n13188_n13100# 60.75fF
-C63 m3_7988_n13200# c1_n13188_n13100# 60.75fF
-C64 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C0 m3_7988_n13200# m3_2669_n13200# 2.73fF
+C1 c1_n13188_n13100# m3_n13288_n7900# 58.61fF
+C2 c1_n13188_n13100# m3_n7969_n7900# 58.86fF
+C3 m3_2669_n7900# m3_2669_n13200# 3.28fF
+C4 c1_n13188_n13100# m3_7988_n13200# 60.75fF
+C5 m3_n13288_2700# m3_n13288_n2600# 3.28fF
+C6 c1_n13188_n13100# m3_2669_n7900# 58.86fF
+C7 m3_n7969_n2600# m3_n13288_n2600# 2.73fF
+C8 c1_n13188_n13100# m3_n13288_2700# 58.61fF
+C9 m3_n7969_n2600# c1_n13188_n13100# 58.86fF
+C10 m3_n7969_n7900# m3_n2650_n7900# 2.73fF
+C11 m3_n7969_n7900# m3_n13288_n7900# 2.73fF
+C12 m3_7988_n7900# m3_7988_n2600# 3.39fF
+C13 m3_2669_n7900# m3_n2650_n7900# 2.73fF
+C14 c1_n13188_n13100# m3_n13288_n13200# 58.36fF
+C15 m3_n7969_n2600# m3_n7969_n7900# 3.28fF
+C16 m3_n2650_2700# m3_n7969_2700# 2.73fF
+C17 m3_7988_n7900# c1_n13188_n13100# 61.01fF
+C18 m3_n13288_n7900# m3_n13288_n13200# 3.28fF
+C19 c1_n13188_n13100# m3_7988_8000# 60.75fF
+C20 m3_n13288_8000# m3_n7969_8000# 2.73fF
+C21 c1_n13188_n13100# m3_2669_8000# 58.61fF
+C22 m3_n7969_2700# m3_n7969_8000# 3.28fF
+C23 m3_n2650_8000# m3_2669_8000# 2.73fF
+C24 m3_n2650_n2600# c1_n13188_n13100# 58.86fF
+C25 m3_7988_n7900# m3_7988_n13200# 3.39fF
+C26 m3_2669_8000# m3_2669_2700# 3.28fF
+C27 m3_7988_n7900# m3_2669_n7900# 2.73fF
+C28 m3_2669_n2600# m3_7988_n2600# 2.73fF
+C29 m3_n2650_n13200# m3_2669_n13200# 2.73fF
+C30 m3_7988_2700# m3_7988_n2600# 3.39fF
+C31 m3_n2650_n2600# m3_n2650_n7900# 3.28fF
+C32 c1_n13188_n13100# m3_n2650_n13200# 58.61fF
+C33 c1_n13188_n13100# m3_n7969_n13200# 58.61fF
+C34 c1_n13188_n13100# m3_n13288_8000# 58.36fF
+C35 m3_n7969_n2600# m3_n2650_n2600# 2.73fF
+C36 m3_n2650_n13200# m3_n2650_n7900# 3.28fF
+C37 c1_n13188_n13100# m3_2669_n2600# 58.86fF
+C38 c1_n13188_n13100# m3_n7969_2700# 58.86fF
+C39 c1_n13188_n13100# m3_7988_2700# 61.01fF
+C40 m3_n7969_n7900# m3_n7969_n13200# 3.28fF
+C41 m3_2669_n2600# m3_2669_2700# 3.28fF
+C42 c1_n13188_n13100# m3_n2650_2700# 58.86fF
+C43 m3_7988_2700# m3_2669_2700# 2.73fF
+C44 m3_n2650_8000# m3_n2650_2700# 3.28fF
+C45 m3_n13288_2700# m3_n13288_8000# 3.28fF
+C46 m3_n2650_2700# m3_2669_2700# 2.73fF
+C47 m3_2669_n2600# m3_2669_n7900# 3.28fF
+C48 m3_2669_8000# m3_7988_8000# 2.73fF
+C49 m3_n13288_2700# m3_n7969_2700# 2.73fF
+C50 m3_n7969_n2600# m3_n7969_2700# 3.28fF
+C51 m3_n7969_n13200# m3_n13288_n13200# 2.73fF
+C52 c1_n13188_n13100# m3_n7969_8000# 58.61fF
+C53 m3_n2650_8000# m3_n7969_8000# 2.73fF
+C54 c1_n13188_n13100# m3_7988_n2600# 61.01fF
+C55 c1_n13188_n13100# m3_2669_n13200# 58.61fF
+C56 c1_n13188_n13100# m3_n13288_n2600# 58.61fF
+C57 m3_7988_2700# m3_7988_8000# 3.39fF
+C58 m3_n2650_n2600# m3_2669_n2600# 2.73fF
+C59 c1_n13188_n13100# m3_n2650_8000# 58.61fF
+C60 m3_n7969_n13200# m3_n2650_n13200# 2.73fF
+C61 c1_n13188_n13100# m3_2669_2700# 58.86fF
+C62 m3_n13288_n7900# m3_n13288_n2600# 3.28fF
+C63 c1_n13188_n13100# m3_n2650_n7900# 58.86fF
+C64 m3_n2650_n2600# m3_n2650_2700# 3.28fF
 C65 c1_n13188_n13100# VSUBS 2.51fF
 C66 m3_7988_n13200# VSUBS 12.57fF
 C67 m3_2669_n13200# VSUBS 12.37fF
@@ -143,25 +4218,25 @@
 X6 c1_n2050_n6300# m3_n2150_n2100# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X7 c1_n2050_n6300# m3_n2150_n6400# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X8 c1_n6369_n6300# m3_n6469_2200# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
-C1 m3_n2150_2200# c1_n2050_n6300# 38.10fF
-C2 c1_n6369_n6300# c1_n2050_n6300# 1.99fF
-C3 c1_2269_n6300# c1_n2050_n6300# 1.99fF
-C4 m3_2169_n6400# m3_n2150_n6400# 1.75fF
-C5 m3_2169_n6400# m3_n2150_2200# 1.75fF
-C6 m3_2169_n6400# c1_2269_n6300# 121.67fF
-C7 m3_n6469_n2100# m3_n6469_2200# 2.63fF
-C8 m3_n6469_n2100# m3_n6469_n6400# 2.63fF
-C9 m3_n6469_n2100# m3_n2150_n2100# 1.75fF
-C10 m3_n2150_n2100# c1_n2050_n6300# 38.10fF
-C11 m3_2169_n6400# m3_n2150_n2100# 1.75fF
-C12 m3_n6469_2200# m3_n2150_2200# 1.75fF
-C13 m3_n6469_n6400# m3_n2150_n6400# 1.75fF
-C14 m3_n2150_n2100# m3_n2150_n6400# 2.63fF
-C15 m3_n6469_2200# c1_n6369_n6300# 38.10fF
-C16 m3_n2150_2200# m3_n2150_n2100# 2.63fF
-C17 m3_n6469_n6400# c1_n6369_n6300# 38.10fF
-C18 m3_n6469_n2100# c1_n6369_n6300# 38.10fF
+C0 c1_n2050_n6300# m3_n2150_n2100# 38.10fF
+C1 m3_2169_n6400# m3_n2150_2200# 1.75fF
+C2 c1_n2050_n6300# c1_n6369_n6300# 1.99fF
+C3 c1_n6369_n6300# m3_n6469_n6400# 38.10fF
+C4 m3_n2150_n6400# m3_n2150_n2100# 2.63fF
+C5 m3_n6469_2200# c1_n6369_n6300# 38.10fF
+C6 m3_n2150_n6400# c1_n2050_n6300# 38.10fF
+C7 m3_n2150_n6400# m3_n6469_n6400# 1.75fF
+C8 m3_2169_n6400# c1_2269_n6300# 121.67fF
+C9 m3_n2150_n2100# m3_2169_n6400# 1.75fF
+C10 m3_n2150_n2100# m3_n2150_2200# 2.63fF
+C11 c1_n2050_n6300# m3_n2150_2200# 38.10fF
+C12 m3_n2150_n2100# m3_n6469_n2100# 1.75fF
+C13 m3_n2150_n6400# m3_2169_n6400# 1.75fF
+C14 m3_n6469_2200# m3_n2150_2200# 1.75fF
+C15 m3_n6469_n6400# m3_n6469_n2100# 2.63fF
+C16 m3_n6469_2200# m3_n6469_n2100# 2.63fF
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@@ -218,17 +4293,17 @@
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-C35 a_687_n150# a_591_n150# 0.43fF
-C36 a_495_n150# a_879_n150# 0.07fF
-C37 a_n81_n150# a_207_n150# 0.10fF
-C38 a_n561_n150# a_n945_n150# 0.07fF
-C39 a_n81_n150# a_n273_n150# 0.16fF
-C40 a_879_n150# a_1167_n150# 0.10fF
-C41 a_n177_n150# a_111_n150# 0.10fF
+C0 a_n81_n150# a_n177_n150# 0.43fF
+C1 a_n561_n150# a_n945_n150# 0.07fF
+C2 a_n1229_n150# a_n945_n150# 0.10fF
+C3 a_1071_n150# w_n1367_n369# 0.07fF
+C4 a_n657_n150# a_n465_n150# 0.16fF
+C5 a_111_n150# a_n177_n150# 0.10fF
+C6 a_15_n150# a_207_n150# 0.16fF
+C7 a_495_n150# a_591_n150# 0.43fF
+C8 a_15_n150# a_n369_n150# 0.07fF
+C9 a_n465_n150# a_n369_n150# 0.43fF
+C10 a_399_n150# a_687_n150# 0.10fF
+C11 a_n81_n150# a_n273_n150# 0.16fF
+C12 a_495_n150# a_303_n150# 0.16fF
+C13 a_n753_n150# a_n1137_n150# 0.07fF
+C14 a_111_n150# a_399_n150# 0.10fF
+C15 a_1071_n150# a_975_n150# 0.43fF
+C16 a_111_n150# a_n273_n150# 0.07fF
+C17 a_207_n150# a_n177_n150# 0.07fF
+C18 a_n657_n150# a_n753_n150# 0.43fF
+C19 a_n369_n150# a_n177_n150# 0.16fF
+C20 a_879_n150# w_n1367_n369# 0.04fF
+C21 a_n1137_n150# a_n849_n150# 0.10fF
+C22 a_591_n150# a_687_n150# 0.43fF
+C23 a_n753_n150# a_n369_n150# 0.07fF
+C24 a_n1041_n150# a_n753_n150# 0.10fF
+C25 a_n657_n150# a_n273_n150# 0.07fF
+C26 a_399_n150# a_207_n150# 0.16fF
+C27 a_1167_n150# w_n1367_n369# 0.14fF
+C28 a_n81_n150# a_303_n150# 0.07fF
+C29 a_15_n150# a_n177_n150# 0.16fF
+C30 a_n657_n150# a_n849_n150# 0.16fF
+C31 a_n465_n150# a_n177_n150# 0.10fF
+C32 a_879_n150# a_591_n150# 0.10fF
+C33 a_303_n150# a_687_n150# 0.07fF
+C34 a_687_n150# a_975_n150# 0.10fF
+C35 a_n273_n150# a_n369_n150# 0.43fF
+C36 a_783_n150# a_399_n150# 0.07fF
+C37 a_111_n150# a_303_n150# 0.16fF
+C38 a_n465_n150# a_n753_n150# 0.10fF
+C39 a_n1041_n150# a_n849_n150# 0.16fF
+C40 a_879_n150# a_975_n150# 0.43fF
+C41 a_n1229_n150# a_n1137_n150# 0.43fF
 C42 a_399_n150# a_15_n150# 0.07fF
-C43 a_n465_n150# a_n369_n150# 0.43fF
-C44 a_n561_n150# a_n369_n150# 0.16fF
-C45 a_495_n150# a_111_n150# 0.07fF
-C46 a_n465_n150# a_n561_n150# 0.43fF
-C47 a_975_n150# a_783_n150# 0.16fF
-C48 a_1071_n150# a_1167_n150# 0.43fF
-C49 a_687_n150# a_303_n150# 0.07fF
-C50 a_n177_n150# a_15_n150# 0.16fF
-C51 a_591_n150# a_303_n150# 0.10fF
-C52 a_111_n150# a_15_n150# 0.43fF
-C53 a_591_n150# a_207_n150# 0.07fF
-C54 a_879_n150# a_975_n150# 0.43fF
-C55 a_n657_n150# a_n945_n150# 0.10fF
-C56 a_n273_n150# a_n369_n150# 0.43fF
-C57 a_n1137_n150# a_n945_n150# 0.16fF
-C58 a_n657_n150# a_n1041_n150# 0.07fF
-C59 a_n465_n150# a_n273_n150# 0.16fF
-C60 a_n657_n150# a_n369_n150# 0.10fF
-C61 a_1071_n150# a_975_n150# 0.43fF
-C62 a_n561_n150# a_n273_n150# 0.10fF
-C63 a_n177_n150# a_n81_n150# 0.43fF
-C64 a_n657_n150# a_n465_n150# 0.16fF
-C65 a_n1137_n150# a_n1041_n150# 0.43fF
-C66 a_n849_n150# a_n945_n150# 0.43fF
-C67 a_687_n150# a_783_n150# 0.43fF
-C68 a_n657_n150# a_n561_n150# 0.43fF
-C69 a_111_n150# a_n81_n150# 0.16fF
-C70 a_591_n150# a_783_n150# 0.16fF
-C71 a_687_n150# a_399_n150# 0.10fF
-C72 a_n1041_n150# a_n849_n150# 0.16fF
-C73 a_303_n150# a_207_n150# 0.43fF
-C74 a_399_n150# a_591_n150# 0.16fF
-C75 a_879_n150# a_687_n150# 0.16fF
-C76 a_975_n150# a_1167_n150# 0.16fF
-C77 a_n1229_n150# a_n945_n150# 0.10fF
-C78 a_n465_n150# a_n849_n150# 0.07fF
-C79 a_879_n150# a_591_n150# 0.10fF
-C80 a_n561_n150# a_n849_n150# 0.10fF
-C81 a_879_n150# w_n1367_n369# 0.04fF
-C82 a_n753_n150# a_n945_n150# 0.16fF
-C83 a_n81_n150# a_15_n150# 0.43fF
-C84 a_n1041_n150# a_n1229_n150# 0.16fF
-C85 a_687_n150# a_1071_n150# 0.07fF
-C86 a_n753_n150# a_n1041_n150# 0.10fF
-C87 a_n657_n150# a_n273_n150# 0.07fF
-C88 a_n753_n150# a_n369_n150# 0.07fF
-C89 a_1071_n150# w_n1367_n369# 0.07fF
-C90 a_495_n150# a_687_n150# 0.16fF
-C91 a_n177_n150# a_n369_n150# 0.16fF
-C92 a_n465_n150# a_n753_n150# 0.10fF
-C93 a_n177_n150# a_n465_n150# 0.10fF
-C94 a_495_n150# a_591_n150# 0.43fF
-C95 a_n753_n150# a_n561_n150# 0.16fF
-C96 a_399_n150# a_303_n150# 0.43fF
-C97 a_n177_n150# a_n561_n150# 0.07fF
+C43 a_n1137_n150# a_n945_n150# 0.16fF
+C44 a_n273_n150# a_15_n150# 0.10fF
+C45 a_n465_n150# a_n273_n150# 0.16fF
+C46 a_207_n150# a_591_n150# 0.07fF
+C47 a_1167_n150# a_975_n150# 0.16fF
+C48 a_n657_n150# a_n561_n150# 0.43fF
+C49 a_n465_n150# a_n849_n150# 0.07fF
+C50 a_495_n150# a_687_n150# 0.16fF
+C51 a_n657_n150# a_n945_n150# 0.10fF
+C52 a_1071_n150# a_687_n150# 0.07fF
+C53 a_303_n150# a_207_n150# 0.43fF
+C54 a_783_n150# a_591_n150# 0.16fF
+C55 a_495_n150# a_111_n150# 0.07fF
+C56 a_n561_n150# a_n369_n150# 0.16fF
+C57 a_n1229_n150# a_n1041_n150# 0.16fF
+C58 a_879_n150# a_495_n150# 0.07fF
+C59 a_n1041_n150# a_n945_n150# 0.43fF
+C60 a_879_n150# a_1071_n150# 0.16fF
+C61 a_n273_n150# a_n177_n150# 0.43fF
+C62 a_783_n150# a_975_n150# 0.16fF
+C63 a_n561_n150# a_n465_n150# 0.43fF
+C64 a_303_n150# a_15_n150# 0.10fF
+C65 a_1167_n150# a_1071_n150# 0.43fF
+C66 a_n753_n150# a_n849_n150# 0.43fF
+C67 a_495_n150# a_207_n150# 0.10fF
+C68 a_n81_n150# a_111_n150# 0.16fF
+C69 a_879_n150# a_687_n150# 0.16fF
+C70 a_783_n150# a_495_n150# 0.10fF
+C71 a_n561_n150# a_n177_n150# 0.07fF
+C72 a_783_n150# a_1071_n150# 0.10fF
+C73 a_399_n150# a_591_n150# 0.16fF
+C74 a_n561_n150# a_n753_n150# 0.16fF
+C75 a_n753_n150# a_n945_n150# 0.16fF
+C76 a_n81_n150# a_207_n150# 0.10fF
+C77 a_399_n150# a_303_n150# 0.43fF
+C78 a_n81_n150# a_n369_n150# 0.10fF
+C79 a_879_n150# a_1167_n150# 0.10fF
+C80 a_n561_n150# a_n273_n150# 0.10fF
+C81 a_111_n150# a_207_n150# 0.43fF
+C82 a_n561_n150# a_n849_n150# 0.10fF
+C83 a_n1229_n150# a_n849_n150# 0.07fF
+C84 w_n1367_n369# a_975_n150# 0.05fF
+C85 a_783_n150# a_687_n150# 0.43fF
+C86 a_n849_n150# a_n945_n150# 0.43fF
+C87 a_n81_n150# a_15_n150# 0.43fF
+C88 a_n1041_n150# a_n1137_n150# 0.43fF
+C89 a_n81_n150# a_n465_n150# 0.07fF
+C90 a_879_n150# a_783_n150# 0.43fF
+C91 a_495_n150# a_399_n150# 0.43fF
+C92 a_303_n150# a_591_n150# 0.10fF
+C93 a_111_n150# a_15_n150# 0.43fF
+C94 a_591_n150# a_975_n150# 0.07fF
+C95 a_n657_n150# a_n369_n150# 0.10fF
+C96 a_n657_n150# a_n1041_n150# 0.07fF
+C97 a_783_n150# a_1167_n150# 0.07fF
 C98 a_1167_n150# VSUBS 0.03fF
 C99 a_1071_n150# VSUBS 0.03fF
 C100 a_975_n150# VSUBS 0.03fF
@@ -865,25 +4940,25 @@
 Xsky130_fd_pr__pfet_01v8_ND88ZC_1 vss biasp vdd vdd vdd vdd biasp vdd biasp vdd biasp
 + biasp biasp biasp vdd vdd biasp biasp vdd vdd biasp biasp biasp vdd vdd vdd vdd
 + biasp biasp sky130_fd_pr__pfet_01v8_ND88ZC
-C0 Down nswitch 2.27fF
-C1 Up nUp 0.15fF
-C2 pswitch Up 0.70fF
-C3 pswitch nUp 5.66fF
-C4 pswitch biasp 3.11fF
-C5 Down nUp 0.25fF
-C6 out vdd 6.66fF
-C7 nDown nswitch 0.31fF
-C8 iref nswitch 1.91fF
-C9 nswitch vdd 0.07fF
-C10 out nswitch 1.28fF
-C11 iref biasp 0.80fF
-C12 vdd biasp 2.64fF
-C13 out nUp 0.31fF
-C14 pswitch vdd 3.98fF
-C15 nDown Down 0.13fF
-C16 pswitch out 4.91fF
-C17 nswitch biasp 0.03fF
-C18 pswitch nswitch 0.06fF
+C0 nswitch biasp 0.03fF
+C1 nswitch iref 1.91fF
+C2 nswitch vdd 0.07fF
+C3 Down nUp 0.25fF
+C4 nUp pswitch 5.66fF
+C5 Up pswitch 0.70fF
+C6 out pswitch 4.91fF
+C7 nDown Down 0.13fF
+C8 Up nUp 0.15fF
+C9 out nUp 0.31fF
+C10 biasp pswitch 3.11fF
+C11 nswitch Down 2.27fF
+C12 vdd pswitch 3.98fF
+C13 nswitch pswitch 0.06fF
+C14 out vdd 6.66fF
+C15 out nswitch 1.28fF
+C16 iref biasp 0.80fF
+C17 vdd biasp 2.64fF
+C18 nDown nswitch 0.31fF
 C19 vdd vss 35.71fF
 C20 Down vss 4.77fF
 C21 Up vss 1.17fF
@@ -896,345 +4971,13 @@
 C28 nUp vss 5.85fF
 .ends
 
-.subckt sky130_fd_pr__pfet_01v8_4798MH VSUBS a_81_n156# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n111_n156# a_n15_n156# a_n81_n125#
-X0 a_n81_n125# a_n111_n156# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n15_n156# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_81_n156# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 w_n311_n344# a_n81_n125# 0.09fF
-C1 a_n173_n125# a_n81_n125# 0.36fF
-C2 a_111_n125# w_n311_n344# 0.14fF
-C3 a_111_n125# a_n173_n125# 0.08fF
-C4 a_111_n125# a_n81_n125# 0.13fF
-C5 a_81_n156# a_n15_n156# 0.02fF
-C6 w_n311_n344# a_15_n125# 0.09fF
-C7 a_15_n125# a_n173_n125# 0.13fF
-C8 w_n311_n344# a_n173_n125# 0.14fF
-C9 a_15_n125# a_n81_n125# 0.36fF
-C10 a_n111_n156# a_n15_n156# 0.02fF
-C11 a_111_n125# a_15_n125# 0.36fF
-C12 a_111_n125# VSUBS 0.03fF
-C13 a_15_n125# VSUBS 0.03fF
-C14 a_n81_n125# VSUBS 0.03fF
-C15 a_n173_n125# VSUBS 0.03fF
-C16 a_81_n156# VSUBS 0.05fF
-C17 a_n15_n156# VSUBS 0.05fF
-C18 a_n111_n156# VSUBS 0.05fF
-C19 w_n311_n344# VSUBS 2.21fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_BHR94T a_n15_n151# w_n311_n335# a_81_n151# a_111_n125#
-+ a_15_n125# a_n173_n125# a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_81_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n15_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_15_n125# a_n81_n125# 0.36fF
-C1 a_15_n125# a_111_n125# 0.36fF
-C2 a_n173_n125# a_n81_n125# 0.36fF
-C3 a_n15_n151# a_81_n151# 0.02fF
-C4 a_n173_n125# a_111_n125# 0.08fF
-C5 a_n15_n151# a_n111_n151# 0.02fF
-C6 a_n173_n125# a_15_n125# 0.13fF
-C7 a_111_n125# a_n81_n125# 0.13fF
-C8 a_111_n125# w_n311_n335# 0.17fF
-C9 a_15_n125# w_n311_n335# 0.12fF
-C10 a_n81_n125# w_n311_n335# 0.12fF
-C11 a_n173_n125# w_n311_n335# 0.17fF
-C12 a_81_n151# w_n311_n335# 0.05fF
-C13 a_n15_n151# w_n311_n335# 0.05fF
-C14 a_n111_n151# w_n311_n335# 0.05fF
-.ends
-
-.subckt trans_gate m1_187_n605# m1_45_n513# vss vdd
-Xsky130_fd_pr__pfet_01v8_4798MH_0 vss vss m1_187_n605# m1_45_n513# m1_45_n513# vdd
-+ vss vss m1_187_n605# sky130_fd_pr__pfet_01v8_4798MH
-Xsky130_fd_pr__nfet_01v8_BHR94T_0 vdd vss vdd m1_187_n605# m1_45_n513# m1_45_n513#
-+ vdd m1_187_n605# sky130_fd_pr__nfet_01v8_BHR94T
-C0 m1_45_n513# m1_187_n605# 0.36fF
-C1 m1_45_n513# vdd 0.69fF
-C2 vdd m1_187_n605# 0.55fF
-C3 m1_187_n605# vss 0.93fF
-C4 m1_45_n513# vss 1.31fF
-C5 vdd vss 3.36fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_7KT7MH VSUBS a_n111_n186# a_111_n125# a_15_n125# a_n173_n125#
-+ w_n311_n344# a_n81_n125#
-X0 a_n81_n125# a_n111_n186# a_n173_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_15_n125# a_n111_n186# a_n81_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_111_n125# a_n111_n186# a_15_n125# w_n311_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_111_n125# w_n311_n344# 0.14fF
-C1 a_n173_n125# a_n81_n125# 0.36fF
-C2 a_n173_n125# a_15_n125# 0.13fF
-C3 a_111_n125# a_n173_n125# 0.08fF
-C4 a_15_n125# a_n81_n125# 0.36fF
-C5 a_n173_n125# w_n311_n344# 0.14fF
-C6 a_111_n125# a_n81_n125# 0.13fF
-C7 a_n81_n125# w_n311_n344# 0.09fF
-C8 a_111_n125# a_15_n125# 0.36fF
-C9 a_15_n125# w_n311_n344# 0.09fF
-C10 a_111_n125# VSUBS 0.03fF
-C11 a_15_n125# VSUBS 0.03fF
-C12 a_n81_n125# VSUBS 0.03fF
-C13 a_n173_n125# VSUBS 0.03fF
-C14 a_n111_n186# VSUBS 0.26fF
-C15 w_n311_n344# VSUBS 2.21fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS6QM w_n311_n335# a_111_n125# a_15_n125# a_n173_n125#
-+ a_n111_n151# a_n81_n125#
-X0 a_111_n125# a_n111_n151# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n111_n151# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n111_n151# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n81_n125# a_15_n125# 0.36fF
-C1 a_n81_n125# a_111_n125# 0.13fF
-C2 a_n173_n125# a_n81_n125# 0.36fF
-C3 a_111_n125# a_15_n125# 0.36fF
-C4 a_n173_n125# a_15_n125# 0.13fF
-C5 a_n173_n125# a_111_n125# 0.08fF
-C6 a_111_n125# w_n311_n335# 0.17fF
-C7 a_15_n125# w_n311_n335# 0.12fF
-C8 a_n81_n125# w_n311_n335# 0.12fF
-C9 a_n173_n125# w_n311_n335# 0.17fF
-C10 a_n111_n151# w_n311_n335# 0.25fF
-.ends
-
-.subckt inverter_cp_x1 out in vss vdd
-Xsky130_fd_pr__pfet_01v8_7KT7MH_0 vss in out vdd vdd vdd out sky130_fd_pr__pfet_01v8_7KT7MH
-Xsky130_fd_pr__nfet_01v8_2BS6QM_0 vss out vss vss in out sky130_fd_pr__nfet_01v8_2BS6QM
-C0 out vdd 0.10fF
-C1 out in 0.32fF
-C2 out vss 0.77fF
-C3 in vss 0.95fF
-C4 vdd vss 3.13fF
-.ends
-
-.subckt clock_inverter vss inverter_cp_x1_2/in CLK vdd inverter_cp_x1_0/out CLK_d
-+ nCLK_d
-Xtrans_gate_0 nCLK_d inverter_cp_x1_0/out vss vdd trans_gate
-Xinverter_cp_x1_0 inverter_cp_x1_0/out CLK vss vdd inverter_cp_x1
-Xinverter_cp_x1_1 inverter_cp_x1_2/in CLK vss vdd inverter_cp_x1
-Xinverter_cp_x1_2 CLK_d inverter_cp_x1_2/in vss vdd inverter_cp_x1
-C0 nCLK_d vdd 0.03fF
-C1 inverter_cp_x1_2/in vdd 0.21fF
-C2 inverter_cp_x1_0/out CLK 0.31fF
-C3 inverter_cp_x1_0/out nCLK_d 0.11fF
-C4 inverter_cp_x1_2/in CLK_d 0.12fF
-C5 inverter_cp_x1_2/in CLK 0.31fF
-C6 inverter_cp_x1_0/out vdd 0.28fF
-C7 CLK_d vdd 0.03fF
-C8 CLK vdd 0.36fF
-C9 CLK_d vss 0.96fF
-C10 inverter_cp_x1_2/in vss 2.01fF
-C11 inverter_cp_x1_0/out vss 1.97fF
-C12 CLK vss 3.03fF
-C13 nCLK_d vss 1.44fF
-C14 vdd vss 16.51fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_MJG8BZ VSUBS a_n125_n95# a_63_n95# w_n263_n314# a_n33_n95#
-+ a_n63_n192#
-X0 a_63_n95# a_n63_n192# a_n33_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n33_n95# a_n63_n192# a_n125_n95# w_n263_n314# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_n125_n95# a_n33_n95# 0.28fF
-C1 a_n125_n95# w_n263_n314# 0.11fF
-C2 w_n263_n314# a_n33_n95# 0.08fF
-C3 a_n125_n95# a_63_n95# 0.10fF
-C4 a_63_n95# a_n33_n95# 0.28fF
-C5 a_63_n95# w_n263_n314# 0.11fF
-C6 a_63_n95# VSUBS 0.03fF
-C7 a_n33_n95# VSUBS 0.03fF
-C8 a_n125_n95# VSUBS 0.03fF
-C9 a_n63_n192# VSUBS 0.20fF
-C10 w_n263_n314# VSUBS 1.80fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_2BS854 w_n311_n335# a_n129_n213# a_111_n125# a_15_n125#
-+ a_n173_n125# a_n81_n125#
-X0 a_111_n125# a_n129_n213# a_15_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X1 a_n81_n125# a_n129_n213# a_n173_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-X2 a_15_n125# a_n129_n213# a_n81_n125# w_n311_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_n173_n125# a_n129_n213# 0.02fF
-C1 a_n81_n125# a_15_n125# 0.36fF
-C2 a_n81_n125# a_n129_n213# 0.10fF
-C3 a_n129_n213# a_15_n125# 0.10fF
-C4 a_n173_n125# a_111_n125# 0.08fF
-C5 a_n81_n125# a_111_n125# 0.13fF
-C6 a_n173_n125# a_n81_n125# 0.36fF
-C7 a_111_n125# a_15_n125# 0.36fF
-C8 a_111_n125# a_n129_n213# 0.01fF
-C9 a_n173_n125# a_15_n125# 0.13fF
-C10 a_111_n125# w_n311_n335# 0.05fF
-C11 a_15_n125# w_n311_n335# 0.05fF
-C12 a_n81_n125# w_n311_n335# 0.05fF
-C13 a_n173_n125# w_n311_n335# 0.05fF
-C14 a_n129_n213# w_n311_n335# 0.49fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_KU9PSX a_n125_n95# a_n33_n95# a_n81_n183# w_n263_n305#
-X0 a_n33_n95# a_n81_n183# a_n125_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-X1 a_n125_n95# a_n81_n183# a_n33_n95# w_n263_n305# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=950000u l=150000u
-C0 a_n125_n95# a_n81_n183# 0.16fF
-C1 a_n33_n95# a_n81_n183# 0.10fF
-C2 a_n125_n95# a_n33_n95# 0.88fF
-C3 a_n33_n95# w_n263_n305# 0.07fF
-C4 a_n125_n95# w_n263_n305# 0.13fF
-C5 a_n81_n183# w_n263_n305# 0.31fF
-.ends
-
-.subckt latch_diff m1_657_280# nQ Q vss CLK vdd nD D
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_0 vss vdd vdd vdd nQ Q sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__pfet_01v8_MJG8BZ_1 vss vdd vdd vdd Q nQ sky130_fd_pr__pfet_01v8_MJG8BZ
-Xsky130_fd_pr__nfet_01v8_2BS854_0 vss CLK vss m1_657_280# m1_657_280# vss sky130_fd_pr__nfet_01v8_2BS854
-Xsky130_fd_pr__nfet_01v8_KU9PSX_0 m1_657_280# Q nD vss sky130_fd_pr__nfet_01v8_KU9PSX
-Xsky130_fd_pr__nfet_01v8_KU9PSX_1 m1_657_280# nQ D vss sky130_fd_pr__nfet_01v8_KU9PSX
-C0 m1_657_280# CLK 0.24fF
-C1 m1_657_280# Q 0.94fF
-C2 nQ D 0.05fF
-C3 nQ m1_657_280# 1.41fF
-C4 nD Q 0.05fF
-C5 nQ Q 0.93fF
-C6 vdd Q 0.16fF
-C7 nQ nD 0.05fF
-C8 Q D 0.05fF
-C9 nQ vdd 0.16fF
-C10 nQ vss 1.16fF
-C11 D vss 0.53fF
-C12 Q vss -0.55fF
-C13 m1_657_280# vss 1.88fF
-C14 nD vss 0.16fF
-C15 CLK vss 0.87fF
-C16 vdd vss 5.98fF
-.ends
-
-.subckt DFlipFlop latch_diff_0/m1_657_280# vss latch_diff_1/D clock_inverter_0/inverter_cp_x1_2/in
-+ nQ Q latch_diff_1/nD D latch_diff_1/m1_657_280# latch_diff_0/D vdd CLK clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK latch_diff_0/nD
-Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in D vdd clock_inverter_0/inverter_cp_x1_0/out
-+ latch_diff_0/D latch_diff_0/nD clock_inverter
-Xlatch_diff_0 latch_diff_0/m1_657_280# latch_diff_1/nD latch_diff_1/D vss CLK vdd
-+ latch_diff_0/nD latch_diff_0/D latch_diff
-Xlatch_diff_1 latch_diff_1/m1_657_280# nQ Q vss nCLK vdd latch_diff_1/nD latch_diff_1/D
-+ latch_diff
-C0 latch_diff_1/D latch_diff_1/m1_657_280# 0.32fF
-C1 clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C2 latch_diff_1/D latch_diff_0/nD 0.41fF
-C3 latch_diff_1/D nQ 0.11fF
-C4 latch_diff_1/nD latch_diff_0/m1_657_280# 0.14fF
-C5 latch_diff_0/D latch_diff_0/m1_657_280# 0.37fF
-C6 latch_diff_1/nD vdd 0.02fF
-C7 latch_diff_1/nD latch_diff_0/D 0.04fF
-C8 latch_diff_1/m1_657_280# latch_diff_0/m1_657_280# 0.18fF
-C9 vdd latch_diff_0/D 0.09fF
-C10 latch_diff_1/nD latch_diff_1/m1_657_280# 0.42fF
-C11 latch_diff_0/m1_657_280# latch_diff_0/nD 0.38fF
-C12 Q latch_diff_1/nD 0.01fF
-C13 nQ latch_diff_1/nD 0.08fF
-C14 latch_diff_1/D latch_diff_0/m1_657_280# 0.43fF
-C15 vdd latch_diff_0/nD 0.14fF
-C16 latch_diff_1/D latch_diff_1/nD 0.33fF
-C17 latch_diff_1/D vdd 0.03fF
-C18 latch_diff_1/D latch_diff_0/D 0.11fF
-C19 nQ vss 0.57fF
-C20 Q vss -0.92fF
-C21 latch_diff_1/m1_657_280# vss 0.64fF
-C22 nCLK vss 0.83fF
-C23 latch_diff_1/nD vss 1.83fF
-C24 latch_diff_1/D vss -0.30fF
-C25 latch_diff_0/m1_657_280# vss 0.72fF
-C26 CLK vss 0.83fF
-C27 latch_diff_0/D vss 1.29fF
-C28 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C29 clock_inverter_0/inverter_cp_x1_0/out vss 1.84fF
-C30 D vss 3.27fF
-C31 latch_diff_0/nD vss 1.74fF
-C32 vdd vss 32.62fF
-.ends
-
-.subckt sky130_fd_pr__pfet_01v8_ZP3U9B VSUBS a_n221_n84# a_159_n84# w_n359_n303# a_n63_n110#
-+ a_n129_n84# a_33_n110# a_n159_n110# a_63_n84# a_129_n110# a_n33_n84#
-X0 a_n129_n84# a_n159_n110# a_n221_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X1 a_63_n84# a_33_n110# a_n33_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X2 a_n33_n84# a_n63_n110# a_n129_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-X3 a_159_n84# a_129_n110# a_63_n84# w_n359_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_33_n110# a_129_n110# 0.02fF
-C1 a_n221_n84# a_159_n84# 0.04fF
-C2 a_n221_n84# a_n33_n84# 0.09fF
-C3 a_n63_n110# a_n159_n110# 0.02fF
-C4 a_n221_n84# a_n129_n84# 0.24fF
-C5 w_n359_n303# a_n221_n84# 0.08fF
-C6 a_n33_n84# a_159_n84# 0.09fF
-C7 a_n129_n84# a_159_n84# 0.05fF
-C8 w_n359_n303# a_159_n84# 0.08fF
-C9 a_n33_n84# a_n129_n84# 0.24fF
-C10 w_n359_n303# a_n33_n84# 0.05fF
-C11 w_n359_n303# a_n129_n84# 0.06fF
-C12 a_n221_n84# a_63_n84# 0.05fF
-C13 a_63_n84# a_159_n84# 0.24fF
-C14 a_n63_n110# a_33_n110# 0.02fF
-C15 a_n33_n84# a_63_n84# 0.24fF
-C16 a_63_n84# a_n129_n84# 0.09fF
-C17 w_n359_n303# a_63_n84# 0.06fF
-C18 a_159_n84# VSUBS 0.03fF
-C19 a_63_n84# VSUBS 0.03fF
-C20 a_n33_n84# VSUBS 0.03fF
-C21 a_n129_n84# VSUBS 0.03fF
-C22 a_n221_n84# VSUBS 0.03fF
-C23 a_129_n110# VSUBS 0.05fF
-C24 a_33_n110# VSUBS 0.05fF
-C25 a_n63_n110# VSUBS 0.05fF
-C26 a_n159_n110# VSUBS 0.05fF
-C27 w_n359_n303# VSUBS 2.19fF
-.ends
-
-.subckt sky130_fd_pr__nfet_01v8_DXA56D w_n359_n252# a_n33_n42# a_129_n68# a_n159_n68#
-+ a_n221_n42# a_159_n42# a_n129_n42# a_33_n68# a_n63_n68# a_63_n42#
-X0 a_63_n42# a_33_n68# a_n33_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X1 a_n33_n42# a_n63_n68# a_n129_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X2 a_159_n42# a_129_n68# a_63_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-X3 a_n129_n42# a_n159_n68# a_n221_n42# w_n359_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
-C0 a_n221_n42# a_n33_n42# 0.05fF
-C1 a_159_n42# a_63_n42# 0.12fF
-C2 a_159_n42# a_n221_n42# 0.02fF
-C3 a_63_n42# a_n129_n42# 0.05fF
-C4 a_159_n42# a_n33_n42# 0.05fF
-C5 a_n221_n42# a_n129_n42# 0.12fF
-C6 a_33_n68# a_n63_n68# 0.02fF
-C7 a_n33_n42# a_n129_n42# 0.12fF
-C8 a_n159_n68# a_n63_n68# 0.02fF
-C9 a_n221_n42# a_63_n42# 0.03fF
-C10 a_129_n68# a_33_n68# 0.02fF
-C11 a_63_n42# a_n33_n42# 0.12fF
-C12 a_159_n42# a_n129_n42# 0.03fF
-C13 a_159_n42# w_n359_n252# 0.07fF
-C14 a_63_n42# w_n359_n252# 0.06fF
-C15 a_n33_n42# w_n359_n252# 0.06fF
-C16 a_n129_n42# w_n359_n252# 0.06fF
-C17 a_n221_n42# w_n359_n252# 0.07fF
-C18 a_129_n68# w_n359_n252# 0.05fF
-C19 a_33_n68# w_n359_n252# 0.05fF
-C20 a_n63_n68# w_n359_n252# 0.05fF
-C21 a_n159_n68# w_n359_n252# 0.05fF
-.ends
-
-.subckt inverter_min_x4 in vss out vdd
-Xsky130_fd_pr__pfet_01v8_ZP3U9B_0 vss out out vdd in vdd in in vdd in out sky130_fd_pr__pfet_01v8_ZP3U9B
-Xsky130_fd_pr__nfet_01v8_DXA56D_0 vss out in in out out vss in in vss sky130_fd_pr__nfet_01v8_DXA56D
-C0 vdd out 0.62fF
-C1 in out 0.67fF
-C2 in vdd 0.33fF
-C3 out vss 0.66fF
-C4 in vss 1.89fF
-C5 vdd vss 3.87fF
-.ends
-
 .subckt sky130_fd_pr__nfet_01v8_5RJ8EK a_n33_n42# a_33_n68# w_n263_n252# a_n63_n68#
 + a_n125_n42# a_63_n42#
 X0 a_63_n42# a_33_n68# a_n33_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
 X1 a_n33_n42# a_n63_n68# a_n125_n42# w_n263_n252# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
 C0 a_n33_n42# a_n125_n42# 0.12fF
-C1 a_n63_n68# a_33_n68# 0.02fF
-C2 a_n125_n42# a_63_n42# 0.05fF
+C1 a_63_n42# a_n125_n42# 0.05fF
+C2 a_33_n68# a_n63_n68# 0.02fF
 C3 a_n33_n42# a_63_n42# 0.12fF
 C4 a_63_n42# w_n263_n252# 0.09fF
 C5 a_n33_n42# w_n263_n252# 0.07fF
@@ -1247,13 +4990,13 @@
 + w_n263_n303# a_n33_n84#
 X0 a_63_n84# a_33_n110# a_n33_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
 X1 a_n33_n84# a_n63_n110# a_n125_n84# w_n263_n303# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
-C0 a_n125_n84# a_63_n84# 0.09fF
-C1 a_n125_n84# w_n263_n303# 0.10fF
-C2 a_33_n110# a_n63_n110# 0.02fF
-C3 a_63_n84# a_n33_n84# 0.24fF
-C4 w_n263_n303# a_n33_n84# 0.07fF
+C0 a_63_n84# a_n33_n84# 0.24fF
+C1 a_33_n110# a_n63_n110# 0.02fF
+C2 w_n263_n303# a_n125_n84# 0.10fF
+C3 w_n263_n303# a_n33_n84# 0.07fF
+C4 a_n33_n84# a_n125_n84# 0.24fF
 C5 a_63_n84# w_n263_n303# 0.10fF
-C6 a_n125_n84# a_n33_n84# 0.24fF
+C6 a_63_n84# a_n125_n84# 0.09fF
 C7 a_63_n84# VSUBS 0.03fF
 C8 a_n33_n84# VSUBS 0.03fF
 C9 a_n125_n84# VSUBS 0.03fF
@@ -1267,75 +5010,76 @@
 Xsky130_fd_pr__pfet_01v8_ZPB9BB_0 vss in in out out vdd vdd sky130_fd_pr__pfet_01v8_ZPB9BB
 C0 vdd out 0.15fF
 C1 vdd in 0.01fF
-C2 out in 0.30fF
+C2 in out 0.30fF
 C3 vdd vss 2.93fF
 C4 out vss 0.66fF
 C5 in vss 0.72fF
 .ends
 
 .subckt div_by_2 vss vdd clock_inverter_0/inverter_cp_x1_2/in CLK_2 nCLK_2 o1 CLK
-+ out_div o2 clock_inverter_0/inverter_cp_x1_0/out nout_div
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ nout_div out_div DFlipFlop_0/latch_diff_1/nD nout_div DFlipFlop_0/latch_diff_1/m1_657_280#
-+ DFlipFlop_0/latch_diff_0/D vdd DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
++ out_div o2 nout_div clock_inverter_0/inverter_cp_x1_0/out
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nout_div DFlipFlop_0/latch_diff_0/nD
++ out_div DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# nout_div
++ DFlipFlop_0/latch_diff_0/D DFlipFlop_0/CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/nCLK DFlipFlop
+Xinverter_min_x4_1 vdd o2 vss nCLK_2 inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss CLK_2 inverter_min_x4
 Xclock_inverter_0 vss clock_inverter_0/inverter_cp_x1_2/in CLK vdd clock_inverter_0/inverter_cp_x1_0/out
 + DFlipFlop_0/CLK DFlipFlop_0/nCLK clock_inverter
-Xinverter_min_x4_0 o1 vss CLK_2 vdd inverter_min_x4
-Xinverter_min_x4_1 o2 vss nCLK_2 vdd inverter_min_x4
 Xinverter_min_x2_0 nout_div o2 vss vdd inverter_min_x2
 Xinverter_min_x2_1 out_div o1 vss vdd inverter_min_x2
 C0 nout_div out_div 0.22fF
-C1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
-C2 o2 nCLK_2 0.11fF
-C3 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
-C4 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
-C5 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
-C6 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
-C7 vdd out_div 0.03fF
-C8 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
-C9 o2 vdd 0.14fF
-C10 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C11 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/nCLK -0.09fF
-C12 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
-C13 o1 vdd 0.14fF
-C14 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
-C15 DFlipFlop_0/latch_diff_0/D DFlipFlop_0/nCLK 0.13fF
-C16 nout_div vdd 0.16fF
-C17 DFlipFlop_0/latch_diff_1/D nout_div 0.64fF
-C18 o2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
-C19 nCLK_2 vdd 0.08fF
-C20 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
-C21 o1 CLK_2 0.11fF
-C22 o1 DFlipFlop_0/latch_diff_1/m1_657_280# 0.02fF
-C23 nout_div DFlipFlop_0/nCLK 0.43fF
-C24 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
-C25 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
-C26 nout_div DFlipFlop_0/CLK 0.42fF
-C27 DFlipFlop_0/nCLK vdd 0.30fF
-C28 nout_div DFlipFlop_0/latch_diff_1/m1_657_280# 0.21fF
-C29 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/nCLK 0.08fF
-C30 o1 out_div 0.01fF
-C31 CLK_2 vdd 0.08fF
-C32 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
-C33 DFlipFlop_0/CLK vdd 0.40fF
-C34 DFlipFlop_0/latch_diff_1/D DFlipFlop_0/CLK -0.48fF
-C35 nCLK_2 vss 1.08fF
-C36 o2 vss 2.21fF
-C37 CLK_2 vss 1.08fF
-C38 o1 vss 2.21fF
-C39 DFlipFlop_0/CLK vss 1.03fF
-C40 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C41 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C42 CLK vss 3.27fF
-C43 DFlipFlop_0/nCLK vss 1.76fF
+C1 nout_div DFlipFlop_0/latch_diff_0/D 0.09fF
+C2 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/nCLK 0.46fF
+C3 nout_div DFlipFlop_0/nCLK 0.43fF
+C4 nout_div DFlipFlop_0/latch_diff_0/nD 0.07fF
+C5 nout_div DFlipFlop_0/CLK 0.42fF
+C6 DFlipFlop_0/latch_diff_1/m1_657_280# o1 0.02fF
+C7 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C8 vdd out_div 0.03fF
+C9 DFlipFlop_0/nCLK vdd 0.30fF
+C10 o2 nCLK_2 0.11fF
+C11 o1 out_div 0.01fF
+C12 vdd DFlipFlop_0/CLK 0.40fF
+C13 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/nD -0.09fF
+C14 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_1/D 0.08fF
+C15 DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/CLK 0.11fF
+C16 DFlipFlop_0/CLK DFlipFlop_0/latch_diff_1/D -0.48fF
+C17 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C18 nCLK_2 vdd 0.08fF
+C19 nout_div vdd 0.16fF
+C20 DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/nCLK 0.26fF
+C21 o2 vdd 0.14fF
+C22 nout_div DFlipFlop_0/latch_diff_1/nD 1.18fF
+C23 DFlipFlop_0/latch_diff_0/m1_657_280# DFlipFlop_0/CLK 0.26fF
+C24 nout_div DFlipFlop_0/latch_diff_1/D 0.64fF
+C25 DFlipFlop_0/nCLK DFlipFlop_0/latch_diff_0/D 0.13fF
+C26 vdd CLK_2 0.08fF
+C27 clock_inverter_0/inverter_cp_x1_0/out vdd 0.10fF
+C28 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_0/CLK 0.29fF
+C29 DFlipFlop_0/latch_diff_1/m1_657_280# nout_div 0.21fF
+C30 o1 CLK_2 0.11fF
+C31 DFlipFlop_0/latch_diff_0/m1_657_280# nout_div 0.24fF
+C32 DFlipFlop_0/latch_diff_1/m1_657_280# o2 0.02fF
+C33 DFlipFlop_0/latch_diff_0/nD DFlipFlop_0/CLK 0.12fF
+C34 vdd o1 0.14fF
+C35 clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C36 DFlipFlop_0/CLK vss 1.03fF
+C37 clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
+C38 CLK vss 3.27fF
+C39 DFlipFlop_0/nCLK vss 1.76fF
+C40 o1 vss 2.21fF
+C41 CLK_2 vss 1.08fF
+C42 o2 vss 2.21fF
+C43 nCLK_2 vss 1.08fF
 C44 out_div vss -0.77fF
 C45 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.63fF
 C46 DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C47 DFlipFlop_0/latch_diff_1/D vss -1.72fF
 C48 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C49 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C50 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C49 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C50 DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C51 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.80fF
 C52 nout_div vss 4.41fF
 C53 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -1348,9 +5092,9 @@
 X1 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
 X2 a_n129_n600# a_n257_n777# a_n221_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
 X3 a_n221_n600# a_n257_n777# a_n129_n600# w_n257_n702# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=6e+06u l=150000u
-C0 a_n129_n600# a_n221_n600# 7.87fF
-C1 a_n129_n600# a_n257_n777# 0.29fF
-C2 a_n257_n777# a_n221_n600# 0.25fF
+C0 a_n129_n600# a_n257_n777# 0.29fF
+C1 a_n129_n600# a_n221_n600# 7.87fF
+C2 a_n221_n600# a_n257_n777# 0.25fF
 C3 a_n129_n600# VSUBS 0.10fF
 C4 a_n221_n600# VSUBS 0.25fF
 C5 a_n257_n777# VSUBS 1.05fF
@@ -1362,9 +5106,9 @@
 X1 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
 X2 a_n129_n300# a_n257_n404# a_n221_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
 X3 a_n221_n300# a_n257_n404# a_n129_n300# w_n257_n327# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=150000u
-C0 a_n257_n404# a_n129_n300# 0.30fF
-C1 a_n257_n404# a_n221_n300# 0.21fF
-C2 a_n221_n300# a_n129_n300# 4.05fF
+C0 a_n129_n300# a_n257_n404# 0.30fF
+C1 a_n129_n300# a_n221_n300# 4.05fF
+C2 a_n257_n404# a_n221_n300# 0.21fF
 C3 a_n129_n300# w_n257_n327# 0.11fF
 C4 a_n221_n300# w_n257_n327# 0.25fF
 C5 a_n257_n404# w_n257_n327# 1.11fF
@@ -1518,24 +5262,24 @@
 Xsky130_fd_pr__pfet_01v8_58ZKDE_19 vss a_3996_n100# out vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
 Xsky130_fd_pr__pfet_01v8_58ZKDE_0 vss in a_678_n100# vdd vdd sky130_fd_pr__pfet_01v8_58ZKDE
 C0 a_678_n100# vdd 0.08fF
-C1 in vdd 0.02fF
-C2 out vdd 47.17fF
-C3 in a_678_n100# 0.81fF
-C4 a_3996_n100# vdd 3.68fF
-C5 a_3996_n100# a_678_n100# 6.52fF
-C6 a_3996_n100# out 55.19fF
-C7 vdd vss 20.93fF
-C8 out vss 35.17fF
-C9 a_3996_n100# vss 49.53fF
+C1 out vdd 47.17fF
+C2 a_3996_n100# a_678_n100# 6.52fF
+C3 a_3996_n100# out 55.19fF
+C4 a_678_n100# in 0.81fF
+C5 a_3996_n100# vdd 3.68fF
+C6 vdd in 0.02fF
+C7 a_3996_n100# vss 49.53fF
+C8 vdd vss 20.93fF
+C9 out vss 35.17fF
 C10 a_678_n100# vss 13.08fF
 C11 in vss 0.87fF
 .ends
 
 .subckt sky130_fd_pr__nfet_01v8_CBAU6Y a_n73_n150# a_n33_n238# w_n211_n360# a_15_n150#
 X0 a_15_n150# a_n33_n238# a_n73_n150# w_n211_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_n33_n238# a_15_n150# 0.02fF
-C1 a_n73_n150# a_15_n150# 0.51fF
-C2 a_n33_n238# a_n73_n150# 0.02fF
+C0 a_15_n150# a_n33_n238# 0.02fF
+C1 a_n73_n150# a_n33_n238# 0.02fF
+C2 a_15_n150# a_n73_n150# 0.51fF
 C3 a_15_n150# w_n211_n360# 0.23fF
 C4 a_n73_n150# w_n211_n360# 0.23fF
 C5 a_n33_n238# w_n211_n360# 0.17fF
@@ -1544,11 +5288,11 @@
 .subckt sky130_fd_pr__pfet_01v8_4757AC VSUBS a_n73_n150# a_n33_181# w_n211_n369# a_15_n150#
 X0 a_15_n150# a_n33_181# a_n73_n150# w_n211_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 C0 w_n211_n369# a_n73_n150# 0.20fF
-C1 a_n33_181# a_n73_n150# 0.01fF
-C2 a_15_n150# w_n211_n369# 0.20fF
-C3 a_15_n150# a_n33_181# 0.01fF
-C4 w_n211_n369# a_n33_181# 0.05fF
-C5 a_15_n150# a_n73_n150# 0.51fF
+C1 a_15_n150# a_n73_n150# 0.51fF
+C2 w_n211_n369# a_n33_181# 0.05fF
+C3 a_n33_181# a_15_n150# 0.01fF
+C4 a_n33_181# a_n73_n150# 0.01fF
+C5 w_n211_n369# a_15_n150# 0.20fF
 C6 a_15_n150# VSUBS 0.03fF
 C7 a_n73_n150# VSUBS 0.03fF
 C8 a_n33_181# VSUBS 0.13fF
@@ -1568,51 +5312,51 @@
 X7 a_351_n150# a_n465_172# a_255_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X8 a_255_n150# a_n465_172# a_159_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X9 a_n321_n150# a_n465_172# a_n417_n150# w_n647_n360# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
-C0 a_63_n150# a_159_n150# 0.43fF
-C1 a_n465_172# a_n417_n150# 0.10fF
-C2 a_255_n150# a_63_n150# 0.16fF
-C3 a_n321_n150# a_63_n150# 0.07fF
-C4 a_n129_n150# a_63_n150# 0.16fF
-C5 a_n33_n150# a_351_n150# 0.07fF
-C6 a_n465_172# a_351_n150# 0.10fF
-C7 a_n33_n150# a_63_n150# 0.43fF
-C8 a_447_n150# a_159_n150# 0.10fF
-C9 a_255_n150# a_447_n150# 0.16fF
-C10 a_n465_172# a_63_n150# 0.10fF
-C11 a_n225_n150# a_n509_n150# 0.10fF
-C12 a_255_n150# a_159_n150# 0.43fF
-C13 a_n129_n150# a_159_n150# 0.10fF
-C14 a_n509_n150# a_n417_n150# 0.43fF
-C15 a_255_n150# a_n129_n150# 0.07fF
-C16 a_n321_n150# a_n129_n150# 0.16fF
-C17 a_n465_172# a_447_n150# 0.01fF
-C18 a_n33_n150# a_159_n150# 0.16fF
-C19 a_255_n150# a_n33_n150# 0.10fF
-C20 a_n321_n150# a_n33_n150# 0.10fF
-C21 a_n465_172# a_159_n150# 0.10fF
-C22 a_n33_n150# a_n129_n150# 0.43fF
-C23 a_255_n150# a_n465_172# 0.10fF
-C24 a_n321_n150# a_n465_172# 0.10fF
-C25 a_n465_172# a_n129_n150# 0.10fF
-C26 a_n465_172# a_n33_n150# 0.10fF
-C27 a_n225_n150# a_n417_n150# 0.16fF
-C28 a_n321_n150# a_n509_n150# 0.16fF
-C29 a_n225_n150# a_63_n150# 0.10fF
-C30 a_n129_n150# a_n509_n150# 0.07fF
-C31 a_n465_172# a_n509_n150# 0.01fF
-C32 a_351_n150# a_63_n150# 0.10fF
-C33 a_n225_n150# a_159_n150# 0.07fF
-C34 a_n321_n150# a_n225_n150# 0.43fF
-C35 a_n225_n150# a_n129_n150# 0.43fF
-C36 a_n321_n150# a_n417_n150# 0.43fF
-C37 a_351_n150# a_447_n150# 0.43fF
-C38 a_n129_n150# a_n417_n150# 0.10fF
-C39 a_447_n150# a_63_n150# 0.07fF
-C40 a_n33_n150# a_n225_n150# 0.16fF
-C41 a_351_n150# a_159_n150# 0.16fF
+C0 a_63_n150# a_255_n150# 0.16fF
+C1 a_63_n150# a_n129_n150# 0.16fF
+C2 a_n417_n150# a_n509_n150# 0.43fF
+C3 a_n509_n150# a_n225_n150# 0.10fF
+C4 a_255_n150# a_351_n150# 0.43fF
+C5 a_n417_n150# a_n129_n150# 0.10fF
+C6 a_n129_n150# a_n225_n150# 0.43fF
+C7 a_n33_n150# a_n321_n150# 0.10fF
+C8 a_63_n150# a_n225_n150# 0.10fF
+C9 a_63_n150# a_351_n150# 0.10fF
+C10 a_n417_n150# a_n225_n150# 0.16fF
+C11 a_159_n150# a_n465_172# 0.10fF
+C12 a_n33_n150# a_n465_172# 0.10fF
+C13 a_447_n150# a_n465_172# 0.01fF
+C14 a_159_n150# a_255_n150# 0.43fF
+C15 a_n33_n150# a_255_n150# 0.10fF
+C16 a_159_n150# a_n129_n150# 0.10fF
+C17 a_447_n150# a_255_n150# 0.16fF
+C18 a_n33_n150# a_n129_n150# 0.43fF
+C19 a_n465_172# a_n321_n150# 0.10fF
+C20 a_63_n150# a_159_n150# 0.43fF
+C21 a_159_n150# a_n225_n150# 0.07fF
+C22 a_63_n150# a_n33_n150# 0.43fF
+C23 a_159_n150# a_351_n150# 0.16fF
+C24 a_n33_n150# a_n417_n150# 0.07fF
+C25 a_63_n150# a_447_n150# 0.07fF
+C26 a_n33_n150# a_n225_n150# 0.16fF
+C27 a_n509_n150# a_n321_n150# 0.16fF
+C28 a_n33_n150# a_351_n150# 0.07fF
+C29 a_n129_n150# a_n321_n150# 0.16fF
+C30 a_447_n150# a_351_n150# 0.43fF
+C31 a_63_n150# a_n321_n150# 0.07fF
+C32 a_n417_n150# a_n321_n150# 0.43fF
+C33 a_n321_n150# a_n225_n150# 0.43fF
+C34 a_n465_172# a_255_n150# 0.10fF
+C35 a_n465_172# a_n509_n150# 0.01fF
+C36 a_n465_172# a_n129_n150# 0.10fF
+C37 a_255_n150# a_n129_n150# 0.07fF
+C38 a_63_n150# a_n465_172# 0.10fF
+C39 a_n509_n150# a_n129_n150# 0.07fF
+C40 a_159_n150# a_n33_n150# 0.16fF
+C41 a_n417_n150# a_n465_172# 0.10fF
 C42 a_n465_172# a_n225_n150# 0.10fF
-C43 a_n33_n150# a_n417_n150# 0.07fF
-C44 a_255_n150# a_351_n150# 0.43fF
+C43 a_159_n150# a_447_n150# 0.10fF
+C44 a_n465_172# a_351_n150# 0.10fF
 C45 a_447_n150# w_n647_n360# 0.17fF
 C46 a_351_n150# w_n647_n360# 0.10fF
 C47 a_255_n150# w_n647_n360# 0.08fF
@@ -1641,60 +5385,60 @@
 X8 a_n225_n150# a_n465_n247# a_n321_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 X9 a_447_n150# a_n465_n247# a_351_n150# w_n647_n369# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=150000u
 C0 a_n33_n150# a_63_n150# 0.43fF
-C1 a_n33_n150# a_n129_n150# 0.43fF
-C2 a_63_n150# a_n129_n150# 0.16fF
-C3 a_n509_n150# a_n225_n150# 0.10fF
-C4 a_n33_n150# a_159_n150# 0.16fF
-C5 a_63_n150# a_159_n150# 0.43fF
-C6 a_n321_n150# a_n417_n150# 0.43fF
-C7 a_n33_n150# a_351_n150# 0.07fF
-C8 a_159_n150# a_n129_n150# 0.10fF
-C9 a_351_n150# a_63_n150# 0.10fF
-C10 a_351_n150# a_159_n150# 0.16fF
-C11 a_255_n150# a_447_n150# 0.16fF
-C12 a_n321_n150# w_n647_n369# 0.05fF
-C13 a_n417_n150# w_n647_n369# 0.07fF
-C14 a_n465_n247# a_n321_n150# 0.08fF
-C15 a_n465_n247# a_n417_n150# 0.08fF
-C16 a_n321_n150# a_n225_n150# 0.43fF
-C17 a_n225_n150# a_n417_n150# 0.16fF
-C18 a_n465_n247# w_n647_n369# 0.47fF
-C19 a_63_n150# a_447_n150# 0.07fF
-C20 a_n225_n150# w_n647_n369# 0.04fF
-C21 a_159_n150# a_447_n150# 0.10fF
-C22 a_n465_n247# a_n225_n150# 0.08fF
-C23 a_351_n150# a_447_n150# 0.43fF
-C24 a_n509_n150# a_n129_n150# 0.07fF
-C25 a_255_n150# w_n647_n369# 0.05fF
-C26 a_n465_n247# a_255_n150# 0.08fF
-C27 a_n33_n150# a_n321_n150# 0.10fF
-C28 a_63_n150# a_n321_n150# 0.07fF
-C29 a_n33_n150# a_n417_n150# 0.07fF
-C30 a_n321_n150# a_n129_n150# 0.16fF
-C31 a_n417_n150# a_n129_n150# 0.10fF
-C32 a_n33_n150# w_n647_n369# 0.02fF
-C33 a_63_n150# w_n647_n369# 0.02fF
-C34 a_n129_n150# w_n647_n369# 0.02fF
-C35 a_n465_n247# a_n33_n150# 0.08fF
-C36 a_n465_n247# a_63_n150# 0.08fF
-C37 a_n465_n247# a_n129_n150# 0.08fF
-C38 a_159_n150# w_n647_n369# 0.04fF
-C39 a_351_n150# w_n647_n369# 0.07fF
-C40 a_n465_n247# a_159_n150# 0.08fF
-C41 a_n33_n150# a_n225_n150# 0.16fF
-C42 a_63_n150# a_n225_n150# 0.10fF
-C43 a_n465_n247# a_351_n150# 0.08fF
-C44 a_n225_n150# a_n129_n150# 0.43fF
-C45 a_n225_n150# a_159_n150# 0.07fF
-C46 a_447_n150# w_n647_n369# 0.14fF
-C47 a_n33_n150# a_255_n150# 0.10fF
-C48 a_63_n150# a_255_n150# 0.16fF
-C49 a_255_n150# a_n129_n150# 0.07fF
-C50 a_n509_n150# a_n321_n150# 0.16fF
-C51 a_n509_n150# a_n417_n150# 0.43fF
-C52 a_255_n150# a_159_n150# 0.43fF
-C53 a_351_n150# a_255_n150# 0.43fF
-C54 a_n509_n150# w_n647_n369# 0.14fF
+C1 a_n225_n150# a_n465_n247# 0.08fF
+C2 a_n225_n150# a_159_n150# 0.07fF
+C3 w_n647_n369# a_n509_n150# 0.14fF
+C4 w_n647_n369# a_447_n150# 0.14fF
+C5 a_n225_n150# a_63_n150# 0.10fF
+C6 a_n33_n150# a_n129_n150# 0.43fF
+C7 a_n225_n150# a_n129_n150# 0.43fF
+C8 w_n647_n369# a_n465_n247# 0.47fF
+C9 w_n647_n369# a_159_n150# 0.04fF
+C10 a_447_n150# a_255_n150# 0.16fF
+C11 a_n225_n150# a_n33_n150# 0.16fF
+C12 a_n417_n150# a_n321_n150# 0.43fF
+C13 w_n647_n369# a_63_n150# 0.02fF
+C14 a_n465_n247# a_255_n150# 0.08fF
+C15 a_255_n150# a_159_n150# 0.43fF
+C16 a_n509_n150# a_n321_n150# 0.16fF
+C17 w_n647_n369# a_n129_n150# 0.02fF
+C18 w_n647_n369# a_n33_n150# 0.02fF
+C19 a_255_n150# a_63_n150# 0.16fF
+C20 w_n647_n369# a_n225_n150# 0.04fF
+C21 a_255_n150# a_n129_n150# 0.07fF
+C22 a_n465_n247# a_n321_n150# 0.08fF
+C23 a_n33_n150# a_255_n150# 0.10fF
+C24 a_63_n150# a_n321_n150# 0.07fF
+C25 a_447_n150# a_351_n150# 0.43fF
+C26 a_n129_n150# a_n321_n150# 0.16fF
+C27 a_n509_n150# a_n417_n150# 0.43fF
+C28 a_n33_n150# a_n321_n150# 0.10fF
+C29 a_n465_n247# a_351_n150# 0.08fF
+C30 a_351_n150# a_159_n150# 0.16fF
+C31 a_351_n150# a_63_n150# 0.10fF
+C32 a_n225_n150# a_n321_n150# 0.43fF
+C33 w_n647_n369# a_255_n150# 0.05fF
+C34 a_n465_n247# a_n417_n150# 0.08fF
+C35 a_n33_n150# a_351_n150# 0.07fF
+C36 w_n647_n369# a_n321_n150# 0.05fF
+C37 a_447_n150# a_159_n150# 0.10fF
+C38 a_n417_n150# a_n129_n150# 0.10fF
+C39 a_n33_n150# a_n417_n150# 0.07fF
+C40 a_447_n150# a_63_n150# 0.07fF
+C41 a_n465_n247# a_159_n150# 0.08fF
+C42 a_n225_n150# a_n417_n150# 0.16fF
+C43 a_n509_n150# a_n129_n150# 0.07fF
+C44 a_n465_n247# a_63_n150# 0.08fF
+C45 a_63_n150# a_159_n150# 0.43fF
+C46 w_n647_n369# a_351_n150# 0.07fF
+C47 a_n225_n150# a_n509_n150# 0.10fF
+C48 a_n465_n247# a_n129_n150# 0.08fF
+C49 a_159_n150# a_n129_n150# 0.10fF
+C50 a_n33_n150# a_n465_n247# 0.08fF
+C51 a_n33_n150# a_159_n150# 0.16fF
+C52 w_n647_n369# a_n417_n150# 0.07fF
+C53 a_255_n150# a_351_n150# 0.43fF
+C54 a_63_n150# a_n129_n150# 0.16fF
 C55 a_447_n150# VSUBS 0.03fF
 C56 a_351_n150# VSUBS 0.03fF
 C57 a_255_n150# VSUBS 0.03fF
@@ -1713,8 +5457,8 @@
 .subckt sky130_fd_pr__nfet_01v8_EDT3AT a_15_n11# a_n33_n99# w_n211_n221# a_n73_n11#
 X0 a_15_n11# a_n33_n99# a_n73_n11# w_n211_n221# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u
 C0 a_n33_n99# a_n73_n11# 0.02fF
-C1 a_n33_n99# a_15_n11# 0.02fF
-C2 a_15_n11# a_n73_n11# 0.15fF
+C1 a_n73_n11# a_15_n11# 0.15fF
+C2 a_n33_n99# a_15_n11# 0.02fF
 C3 a_15_n11# w_n211_n221# 0.09fF
 C4 a_n73_n11# w_n211_n221# 0.09fF
 C5 a_n33_n99# w_n211_n221# 0.17fF
@@ -1731,8 +5475,8 @@
 .subckt sky130_fd_pr__pfet_01v8_HRYSXS VSUBS a_n33_n211# a_n78_n114# w_n216_n334#
 + a_20_n114#
 X0 a_20_n114# a_n33_n211# a_n78_n114# w_n216_n334# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=200000u
-C0 a_20_n114# w_n216_n334# 0.20fF
-C1 w_n216_n334# a_n78_n114# 0.20fF
+C0 w_n216_n334# a_n78_n114# 0.20fF
+C1 w_n216_n334# a_20_n114# 0.20fF
 C2 a_20_n114# a_n78_n114# 0.42fF
 C3 a_20_n114# VSUBS 0.03fF
 C4 a_n78_n114# VSUBS 0.03fF
@@ -1743,11 +5487,11 @@
 .subckt inverter_csvco in vbulkn out vbulkp vdd vss
 Xsky130_fd_pr__nfet_01v8_AQR2CW_0 in vss vbulkn out sky130_fd_pr__nfet_01v8_AQR2CW
 Xsky130_fd_pr__pfet_01v8_HRYSXS_0 vbulkn in vdd vbulkp out sky130_fd_pr__pfet_01v8_HRYSXS
-C0 in vss 0.01fF
-C1 in vdd 0.01fF
-C2 in out 0.11fF
-C3 vdd vbulkp 0.04fF
-C4 out vbulkp 0.08fF
+C0 in vdd 0.01fF
+C1 vss in 0.01fF
+C2 out vbulkp 0.08fF
+C3 out in 0.11fF
+C4 vbulkp vdd 0.04fF
 C5 vbulkp vbulkn 2.49fF
 C6 out vbulkn 0.60fF
 C7 vdd vbulkn 0.06fF
@@ -1765,20 +5509,20 @@
 + vdd vdd sky130_fd_pr__pfet_01v8_8DL6ZL
 Xsky130_fd_pr__nfet_01v8_EDT3AT_0 cap_vco_0/t D0 vss out sky130_fd_pr__nfet_01v8_EDT3AT
 Xinverter_csvco_0 in vss out vdd inverter_csvco_0/vdd inverter_csvco_0/vss inverter_csvco
-C0 out inverter_csvco_0/vss 0.03fF
-C1 D0 out 0.09fF
-C2 D0 inverter_csvco_0/vss 0.02fF
+C0 vbp inverter_csvco_0/vdd 0.75fF
+C1 in inverter_csvco_0/vdd 0.01fF
+C2 in inverter_csvco_0/vss 0.01fF
 C3 vdd cap_vco_0/t 0.04fF
-C4 inverter_csvco_0/vss vctrl 0.87fF
-C5 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
-C6 inverter_csvco_0/vdd in 0.01fF
+C4 vctrl inverter_csvco_0/vss 0.87fF
+C5 D0 out 0.09fF
+C6 cap_vco_0/t out 0.70fF
 C7 vdd vbp 1.21fF
-C8 inverter_csvco_0/vdd vdd 1.89fF
-C9 inverter_csvco_0/vdd vbp 0.75fF
-C10 cap_vco_0/t out 0.70fF
-C11 out in 0.06fF
-C12 inverter_csvco_0/vdd out 0.02fF
-C13 inverter_csvco_0/vss in 0.01fF
+C8 vdd inverter_csvco_0/vdd 1.89fF
+C9 D0 inverter_csvco_0/vss 0.02fF
+C10 inverter_csvco_0/vdd cap_vco_0/t 0.10fF
+C11 inverter_csvco_0/vdd out 0.02fF
+C12 inverter_csvco_0/vss out 0.03fF
+C13 in out 0.06fF
 C14 out vss 0.93fF
 C15 inverter_csvco_0/vdd vss 0.26fF
 C16 in vss 0.69fF
@@ -1805,21 +5549,21 @@
 Xcsvco_branch_1 vctrl csvco_branch_1/inverter_csvco_0/vdd csvco_branch_1/in csvco_branch_2/vbp
 + csvco_branch_1/cap_vco_0/t D0 csvco_branch_2/in csvco_branch_1/inverter_csvco_0/vss
 + vss vdd csvco_branch
-C0 D0 csvco_branch_0/inverter_csvco_0/vss 0.49fF
-C1 vdd csvco_branch_0/inverter_csvco_0/vdd 0.13fF
-C2 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vss 0.06fF
+C0 vctrl csvco_branch_2/vbp 0.06fF
+C1 csvco_branch_0/inverter_csvco_0/vdd vdd 0.13fF
+C2 out_vco csvco_branch_1/cap_vco_0/t 0.03fF
 C3 vdd csvco_branch_1/inverter_csvco_0/vdd 0.19fF
-C4 csvco_branch_0/cap_vco_0/t out_vco 0.03fF
-C5 csvco_branch_2/vbp vdd 1.49fF
-C6 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
-C7 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
-C8 vctrl D0 4.41fF
-C9 csvco_branch_2/vbp csvco_branch_0/inverter_csvco_0/vdd 0.06fF
-C10 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
-C11 vctrl csvco_branch_2/vbp 0.06fF
-C12 csvco_branch_2/in out_vco 0.58fF
-C13 csvco_branch_1/cap_vco_0/t out_vco 0.03fF
-C14 csvco_branch_1/in out_vco 0.76fF
+C4 D0 csvco_branch_2/inverter_csvco_0/vss 0.68fF
+C5 csvco_branch_0/inverter_csvco_0/vss D0 0.49fF
+C6 csvco_branch_0/inverter_csvco_0/vss csvco_branch_2/vbp 0.06fF
+C7 out_vco csvco_branch_2/in 0.58fF
+C8 D0 csvco_branch_1/inverter_csvco_0/vss 0.68fF
+C9 out_vco csvco_branch_0/cap_vco_0/t 0.03fF
+C10 out_vco csvco_branch_1/in 0.76fF
+C11 vdd csvco_branch_2/vbp 1.49fF
+C12 csvco_branch_0/inverter_csvco_0/vdd csvco_branch_2/vbp 0.06fF
+C13 csvco_branch_2/inverter_csvco_0/vdd vdd 0.10fF
+C14 D0 vctrl 4.41fF
 C15 csvco_branch_2/in vss 1.60fF
 C16 csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C17 csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -1839,19 +5583,19 @@
 .ends
 
 .subckt ring_osc_buffer vss in_vco vdd o1 out_div out_pad
-Xinverter_min_x4_0 o1 vss out_div vdd inverter_min_x4
-Xinverter_min_x4_1 out_div vss out_pad vdd inverter_min_x4
+Xinverter_min_x4_1 vdd out_div vss out_pad inverter_min_x4
+Xinverter_min_x4_0 vdd o1 vss out_div inverter_min_x4
 Xinverter_min_x2_0 in_vco o1 vss vdd inverter_min_x2
 C0 vdd o1 0.09fF
-C1 o1 out_div 0.11fF
-C2 vdd out_div 0.17fF
-C3 vdd out_pad 0.10fF
-C4 out_pad out_div 0.15fF
+C1 out_div vdd 0.17fF
+C2 vdd out_pad 0.10fF
+C3 out_div o1 0.11fF
+C4 out_div out_pad 0.15fF
 C5 in_vco vss 0.83fF
-C6 out_pad vss 0.70fF
-C7 out_div vss 3.00fF
-C8 vdd vss 14.54fF
-C9 o1 vss 2.72fF
+C6 o1 vss 2.72fF
+C7 vdd vss 14.54fF
+C8 out_div vss 3.00fF
+C9 out_pad vss 0.70fF
 .ends
 
 .subckt sky130_fd_sc_hs__xor2_1 A B VGND VNB VPB VPWR X a_194_125# a_355_368# a_455_87#
@@ -1866,27 +5610,27 @@
 X7 a_455_87# A VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
 X8 VGND B a_194_125# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
 X9 VGND a_194_125# X VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=740000u l=150000u
-C0 a_355_368# B 0.08fF
-C1 VPWR X 0.07fF
-C2 a_194_125# a_355_368# 0.51fF
-C3 A B 0.28fF
-C4 a_194_125# A 0.18fF
-C5 VGND B 0.10fF
-C6 a_194_125# VGND 0.25fF
-C7 A a_355_368# 0.02fF
-C8 X B 0.13fF
-C9 a_194_125# X 0.29fF
-C10 VGND A 0.31fF
-C11 X a_355_368# 0.17fF
-C12 VPWR B 0.09fF
-C13 VPWR a_194_125# 0.33fF
-C14 VPWR a_355_368# 0.37fF
-C15 VGND X 0.28fF
-C16 a_194_125# a_158_392# 0.06fF
-C17 VPWR VPB 0.06fF
-C18 VPWR A 0.15fF
-C19 VPWR VGND 0.01fF
-C20 a_194_125# B 0.57fF
+C0 X B 0.13fF
+C1 B a_355_368# 0.08fF
+C2 B VGND 0.10fF
+C3 VPWR B 0.09fF
+C4 B A 0.28fF
+C5 B a_194_125# 0.57fF
+C6 a_194_125# a_158_392# 0.06fF
+C7 X a_355_368# 0.17fF
+C8 X VGND 0.28fF
+C9 VPWR X 0.07fF
+C10 VPWR a_355_368# 0.37fF
+C11 VPWR VGND 0.01fF
+C12 a_355_368# A 0.02fF
+C13 X a_194_125# 0.29fF
+C14 a_355_368# a_194_125# 0.51fF
+C15 VPWR VPB 0.06fF
+C16 VGND A 0.31fF
+C17 VPWR A 0.15fF
+C18 VGND a_194_125# 0.25fF
+C19 VPWR a_194_125# 0.33fF
+C20 a_194_125# A 0.18fF
 C21 VGND VNB 0.78fF
 C22 X VNB 0.21fF
 C23 VPWR VNB 0.78fF
@@ -1904,20 +5648,20 @@
 X3 a_143_136# A a_56_136# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=640000u l=150000u
 X4 a_56_136# A VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
 X5 X a_56_136# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
-C0 a_56_136# VGND 0.06fF
-C1 VGND A 0.21fF
-C2 a_56_136# A 0.17fF
-C3 B VPWR 0.02fF
-C4 VPWR VPB 0.04fF
-C5 VPWR X 0.20fF
-C6 B X 0.02fF
-C7 B VGND 0.03fF
-C8 VGND X 0.15fF
-C9 a_56_136# VPWR 0.57fF
-C10 a_56_136# B 0.30fF
-C11 a_56_136# X 0.26fF
-C12 VPWR A 0.07fF
-C13 B A 0.08fF
+C0 a_56_136# VPWR 0.57fF
+C1 A VPWR 0.07fF
+C2 B VGND 0.03fF
+C3 VPB VPWR 0.04fF
+C4 a_56_136# B 0.30fF
+C5 a_56_136# VGND 0.06fF
+C6 B A 0.08fF
+C7 VGND A 0.21fF
+C8 VPWR X 0.20fF
+C9 a_56_136# A 0.17fF
+C10 B X 0.02fF
+C11 B VPWR 0.02fF
+C12 VGND X 0.15fF
+C13 a_56_136# X 0.26fF
 C14 VGND VNB 0.50fF
 C15 X VNB 0.23fF
 C16 VPWR VNB 0.50fF
@@ -1934,20 +5678,20 @@
 X3 X a_63_368# VPWR VPB sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.12e+06u l=150000u
 X4 a_63_368# B VGND VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
 X5 VGND A a_63_368# VNB sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=550000u l=150000u
-C0 VGND B 0.11fF
-C1 B a_63_368# 0.14fF
-C2 VGND X 0.16fF
-C3 VPWR B 0.01fF
-C4 a_63_368# X 0.33fF
-C5 a_63_368# A 0.28fF
-C6 VPWR X 0.18fF
-C7 VPWR A 0.05fF
-C8 a_152_368# a_63_368# 0.03fF
-C9 VGND a_63_368# 0.27fF
-C10 B A 0.10fF
-C11 VPWR VPB 0.04fF
+C0 A a_63_368# 0.28fF
+C1 VGND a_63_368# 0.27fF
+C2 X VPWR 0.18fF
+C3 X a_63_368# 0.33fF
+C4 X A 0.02fF
+C5 VGND X 0.16fF
+C6 VPWR VPB 0.04fF
+C7 B VPWR 0.01fF
+C8 B a_63_368# 0.14fF
+C9 B A 0.10fF
+C10 VGND B 0.11fF
+C11 a_152_368# a_63_368# 0.03fF
 C12 VPWR a_63_368# 0.29fF
-C13 X A 0.02fF
+C13 VPWR A 0.05fF
 C14 VGND VNB 0.53fF
 C15 X VNB 0.24fF
 C16 A VNB 0.21fF
@@ -1957,202 +5701,204 @@
 C20 a_63_368# VNB 0.37fF
 .ends
 
-.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_1/latch_diff_0/D
-+ nCLK DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd DFlipFlop_2/latch_diff_0/nD Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ CLK DFlipFlop_2/latch_diff_1/D vss DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ sky130_fd_sc_hs__and2_1_0/a_56_136# nQ0 DFlipFlop_1/latch_diff_1/nD CLK_5 DFlipFlop_3/latch_diff_0/nD
-+ nQ2 DFlipFlop_0/latch_diff_0/D DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_1/latch_diff_1/D Q1 DFlipFlop_2/D DFlipFlop_3/latch_diff_0/D DFlipFlop_1/D
-+ sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_0/latch_diff_0/nD
-+ DFlipFlop_2/nQ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_2/latch_diff_0/D
-+ sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ DFlipFlop_1/latch_diff_0/nD sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
-+ sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ sky130_fd_sc_hs__and2_1_0/a_143_136#
+.subckt div_by_5 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in nCLK DFlipFlop_0/latch_diff_1/nD
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vdd vss Q0 CLK DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out sky130_fd_sc_hs__and2_1_0/a_56_136#
++ DFlipFlop_3/latch_diff_0/D nQ0 DFlipFlop_1/latch_diff_0/nD DFlipFlop_1/latch_diff_1/nD
++ DFlipFlop_1/latch_diff_0/D CLK_5 nQ2 Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_1/latch_diff_1/D DFlipFlop_2/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ DFlipFlop_0/latch_diff_0/nD sky130_fd_sc_hs__xor2_1_0/a_355_368# DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/D DFlipFlop_3/latch_diff_1/nD DFlipFlop_0/latch_diff_1/D Q1_shift DFlipFlop_1/D
++ DFlipFlop_2/nQ DFlipFlop_3/latch_diff_0/nD DFlipFlop_2/latch_diff_0/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ DFlipFlop_0/latch_diff_0/D sky130_fd_sc_hs__xor2_1_0/a_158_392# DFlipFlop_3/latch_diff_1/D
++ sky130_fd_sc_hs__or2_1_0/a_63_368# DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
++ sky130_fd_sc_hs__and2_1_1/a_143_136# DFlipFlop_0/Q sky130_fd_sc_hs__and2_1_1/a_56_136#
++ sky130_fd_sc_hs__xor2_1_0/a_194_125# sky130_fd_sc_hs__and2_1_0/a_143_136# DFlipFlop_2/latch_diff_0/nD
 Xsky130_fd_sc_hs__xor2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_2/D sky130_fd_sc_hs__xor2_1_0/a_194_125#
 + sky130_fd_sc_hs__xor2_1_0/a_355_368# sky130_fd_sc_hs__xor2_1_0/a_455_87# sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + sky130_fd_sc_hs__xor2_1
-XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss DFlipFlop_0/latch_diff_1/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ nQ2 DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/D DFlipFlop_0/latch_diff_1/m1_657_280#
-+ DFlipFlop_0/latch_diff_0/D vdd CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_0/latch_diff_0/nD DFlipFlop
-XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss DFlipFlop_1/latch_diff_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ nQ0 Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/D DFlipFlop_1/latch_diff_1/m1_657_280#
-+ DFlipFlop_1/latch_diff_0/D vdd CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_1/latch_diff_0/nD DFlipFlop
-XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss DFlipFlop_2/latch_diff_1/D DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_2/nQ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/D DFlipFlop_2/latch_diff_1/m1_657_280#
-+ DFlipFlop_2/latch_diff_0/D vdd CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
-+ nCLK DFlipFlop_2/latch_diff_0/nD DFlipFlop
-XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss DFlipFlop_3/latch_diff_1/D DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
-+ DFlipFlop_3/nQ Q1_shift DFlipFlop_3/latch_diff_1/nD Q1 DFlipFlop_3/latch_diff_1/m1_657_280#
-+ DFlipFlop_3/latch_diff_0/D vdd nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ CLK DFlipFlop_3/latch_diff_0/nD DFlipFlop
+XDFlipFlop_0 DFlipFlop_0/latch_diff_0/m1_657_280# vss vdd DFlipFlop_0/latch_diff_1/D
++ DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in nQ2 DFlipFlop_0/latch_diff_0/nD
++ DFlipFlop_0/Q DFlipFlop_0/latch_diff_1/nD DFlipFlop_0/latch_diff_1/m1_657_280# DFlipFlop_0/D
++ DFlipFlop_0/latch_diff_0/D CLK DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_2 DFlipFlop_2/latch_diff_0/m1_657_280# vss vdd DFlipFlop_2/latch_diff_1/D
++ DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_2/nQ DFlipFlop_2/latch_diff_0/nD
++ Q1 DFlipFlop_2/latch_diff_1/nD DFlipFlop_2/latch_diff_1/m1_657_280# DFlipFlop_2/D
++ DFlipFlop_2/latch_diff_0/D CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_1 DFlipFlop_1/latch_diff_0/m1_657_280# vss vdd DFlipFlop_1/latch_diff_1/D
++ DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in nQ0 DFlipFlop_1/latch_diff_0/nD
++ Q0 DFlipFlop_1/latch_diff_1/nD DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_1/D
++ DFlipFlop_1/latch_diff_0/D CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
++ nCLK DFlipFlop
+XDFlipFlop_3 DFlipFlop_3/latch_diff_0/m1_657_280# vss vdd DFlipFlop_3/latch_diff_1/D
++ DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_3/nQ DFlipFlop_3/latch_diff_0/nD
++ Q1_shift DFlipFlop_3/latch_diff_1/nD DFlipFlop_3/latch_diff_1/m1_657_280# Q1 DFlipFlop_3/latch_diff_0/D
++ nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out CLK DFlipFlop
 Xsky130_fd_sc_hs__and2_1_0 Q1 Q0 vss vss vdd vdd DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_143_136#
 + sky130_fd_sc_hs__and2_1_0/a_56_136# sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__and2_1_1 nQ2 nQ0 vss vss vdd vdd DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_143_136#
 + sky130_fd_sc_hs__and2_1_1/a_56_136# sky130_fd_sc_hs__and2_1
 Xsky130_fd_sc_hs__or2_1_0 Q1 Q1_shift vss vss vdd vdd CLK_5 sky130_fd_sc_hs__or2_1_0/a_152_368#
 + sky130_fd_sc_hs__or2_1_0/a_63_368# sky130_fd_sc_hs__or2_1
-C0 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
-C1 DFlipFlop_1/latch_diff_1/m1_657_280# nQ0 0.21fF
-C2 CLK DFlipFlop_1/latch_diff_1/D 0.14fF
-C3 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
-C4 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
-C5 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C6 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
-C7 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
-C8 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
-C9 DFlipFlop_2/latch_diff_1/nD nCLK 0.16fF
-C10 vdd DFlipFlop_1/D 0.25fF
-C11 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
-C12 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
-C13 DFlipFlop_1/latch_diff_1/m1_657_280# Q0 0.01fF
-C14 DFlipFlop_2/nQ vdd 0.02fF
-C15 CLK_5 vdd 0.15fF
-C16 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
-C17 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
-C18 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
-C19 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
-C20 DFlipFlop_0/latch_diff_1/D Q0 0.23fF
-C21 CLK DFlipFlop_1/D 0.21fF
-C22 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
-C23 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
-C24 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
-C25 CLK DFlipFlop_2/nQ 0.13fF
-C26 Q1 DFlipFlop_1/D 0.03fF
-C27 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
-C28 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
-C29 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
-C30 DFlipFlop_2/nQ Q1 0.31fF
-C31 CLK vdd 0.41fF
-C32 Q1 vdd 9.49fF
-C33 CLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out -0.31fF
-C34 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
-C35 DFlipFlop_1/latch_diff_0/m1_657_280# nQ0 0.25fF
-C36 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
-C37 CLK Q1 -0.10fF
-C38 Q0 DFlipFlop_0/D 0.39fF
-C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
-C40 nCLK sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.11fF
-C41 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
-C42 CLK DFlipFlop_0/latch_diff_0/m1_657_280# 0.28fF
-C43 sky130_fd_sc_hs__xor2_1_0/a_194_125# Q0 0.26fF
-C44 Q1 DFlipFlop_0/latch_diff_0/D 0.15fF
-C45 CLK DFlipFlop_0/latch_diff_1/nD 0.02fF
-C46 DFlipFlop_1/latch_diff_0/D nQ0 0.09fF
-C47 Q1 DFlipFlop_0/latch_diff_1/nD 0.10fF
-C48 vdd DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C49 DFlipFlop_1/latch_diff_1/D nQ0 0.91fF
-C50 nCLK DFlipFlop_3/nQ 0.02fF
-C51 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
-C52 CLK DFlipFlop_2/latch_diff_0/m1_657_280# 0.28fF
-C53 CLK DFlipFlop_1/latch_diff_1/nD 0.09fF
-C54 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
-C55 Q1 DFlipFlop_1/latch_diff_1/nD 0.10fF
-C56 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
-C57 CLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C58 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
-C59 nCLK DFlipFlop_1/latch_diff_1/D 0.08fF
-C60 DFlipFlop_1/latch_diff_1/D Q0 0.06fF
-C61 Q1 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
-C62 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
-C63 DFlipFlop_1/latch_diff_0/nD nQ0 0.08fF
-C64 nCLK DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.05fF
-C65 sky130_fd_sc_hs__and2_1_1/a_56_136# nQ0 0.01fF
-C66 DFlipFlop_1/D nQ0 0.12fF
-C67 sky130_fd_sc_hs__and2_1_1/a_143_136# nQ0 0.04fF
-C68 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
-C69 vdd nQ0 0.11fF
-C70 nCLK DFlipFlop_3/latch_diff_1/D 0.14fF
-C71 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out DFlipFlop_1/D 0.03fF
-C72 nCLK DFlipFlop_1/D 0.14fF
-C73 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
-C74 nCLK DFlipFlop_2/nQ 0.09fF
-C75 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
-C76 DFlipFlop_2/D vdd 0.07fF
-C77 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
-C78 Q0 DFlipFlop_1/D 0.07fF
-C79 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
-C80 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vdd 0.02fF
-C81 CLK nQ0 0.19fF
-C82 nCLK vdd 0.34fF
-C83 Q1 nQ0 0.06fF
-C84 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
-C85 nQ2 vdd 0.04fF
-C86 Q0 vdd 5.33fF
-C87 nCLK DFlipFlop_2/latch_diff_1/m1_657_280# 0.28fF
-C88 nQ2 DFlipFlop_0/latch_diff_1/m1_657_280# 0.05fF
-C89 CLK DFlipFlop_2/D 0.14fF
-C90 sky130_fd_sc_hs__xor2_1_0/a_355_368# vdd 0.03fF
-C91 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
-C92 Q1 DFlipFlop_2/D 0.10fF
-C93 nCLK Q1 -0.01fF
-C94 CLK DFlipFlop_0/Q 0.08fF
-C95 Q1 DFlipFlop_0/Q 0.13fF
-C96 CLK nQ2 0.17fF
-C97 CLK Q0 0.08fF
-C98 nQ2 Q1 0.07fF
-C99 Q0 Q1 9.65fF
-C100 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
-C101 DFlipFlop_3/nQ Q1_shift 0.04fF
-C102 nCLK DFlipFlop_0/latch_diff_1/nD 0.05fF
-C103 DFlipFlop_1/latch_diff_1/nD nQ0 0.88fF
-C104 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
-C105 Q0 DFlipFlop_0/latch_diff_1/nD 0.21fF
-C106 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
-C107 nCLK DFlipFlop_1/latch_diff_1/nD 0.16fF
-C108 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
-C109 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
-C110 sky130_fd_sc_hs__or2_1_0/a_152_368# Q1_shift -0.04fF
-C111 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
-C112 DFlipFlop_2/latch_diff_1/nD CLK 0.09fF
-C113 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
-C114 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
-C115 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
-C116 DFlipFlop_2/latch_diff_1/nD Q1 0.21fF
-C117 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
-C118 Q1 DFlipFlop_3/latch_diff_1/m1_657_280# 0.28fF
-C119 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
-C120 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
-C121 DFlipFlop_0/latch_diff_1/D CLK 0.03fF
-C122 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
-C123 DFlipFlop_2/latch_diff_1/D Q1 0.23fF
-C124 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
-C125 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
-C126 vdd Q1_shift 0.10fF
-C127 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
-C128 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
-C129 DFlipFlop_0/D vdd 0.19fF
-C130 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
-C131 CLK DFlipFlop_2/latch_diff_0/nD 0.08fF
-C132 nCLK nQ0 0.09fF
-C133 Q1 Q1_shift 0.36fF
-C134 sky130_fd_sc_hs__xor2_1_0/a_194_125# vdd 0.03fF
-C135 nQ2 nQ0 0.03fF
-C136 Q0 nQ0 0.33fF
-C137 Q1 DFlipFlop_0/D 0.13fF
-C138 nCLK DFlipFlop_2/D 0.41fF
-C139 DFlipFlop_0/D DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
-C140 nCLK DFlipFlop_0/Q 0.11fF
-C141 CLK DFlipFlop_1/latch_diff_0/m1_657_280# 0.28fF
-C142 Q0 DFlipFlop_2/D 0.25fF
-C143 nCLK nQ2 0.10fF
-C144 nCLK Q0 0.20fF
-C145 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
-C146 nQ2 DFlipFlop_0/Q 0.09fF
-C147 nCLK sky130_fd_sc_hs__xor2_1_0/a_455_87# 0.02fF
-C148 Q0 DFlipFlop_0/Q 0.21fF
-C149 nQ2 Q0 0.23fF
-C150 DFlipFlop_3/nQ vdd 0.02fF
-C151 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C152 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
-C153 Q1 DFlipFlop_3/latch_diff_0/D 0.09fF
-C154 CLK DFlipFlop_3/nQ 0.01fF
-C155 Q1 DFlipFlop_3/nQ 0.10fF
-C156 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C0 vdd sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C1 DFlipFlop_0/Q Q1 0.13fF
+C2 nQ0 Q0 0.33fF
+C3 nQ0 DFlipFlop_1/latch_diff_0/D 0.09fF
+C4 DFlipFlop_1/latch_diff_0/m1_657_280# CLK 0.28fF
+C5 DFlipFlop_3/latch_diff_1/D nCLK 0.14fF
+C6 DFlipFlop_3/latch_diff_0/nD Q1 0.08fF
+C7 Q0 DFlipFlop_0/latch_diff_1/D 0.23fF
+C8 sky130_fd_sc_hs__xor2_1_0/a_455_87# DFlipFlop_2/D 0.08fF
+C9 Q0 nQ2 0.23fF
+C10 vdd sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C11 Q1 DFlipFlop_2/latch_diff_1/D 0.23fF
+C12 Q0 nCLK 0.20fF
+C13 nCLK DFlipFlop_1/latch_diff_0/D 0.11fF
+C14 DFlipFlop_0/latch_diff_0/D Q1 0.15fF
+C15 nQ0 DFlipFlop_1/latch_diff_0/m1_657_280# 0.25fF
+C16 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out CLK -0.31fF
+C17 CLK sky130_fd_sc_hs__and2_1_1/a_143_136# 0.03fF
+C18 Q0 vdd 5.33fF
+C19 DFlipFlop_3/latch_diff_1/D Q1 0.79fF
+C20 Q0 Q1 9.65fF
+C21 Q1 DFlipFlop_1/latch_diff_0/D 0.18fF
+C22 nQ0 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.04fF
+C23 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in CLK 0.03fF
+C24 sky130_fd_sc_hs__and2_1_0/a_143_136# Q1 0.02fF
+C25 nQ0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.21fF
+C26 DFlipFlop_0/latch_diff_1/nD Q0 0.21fF
+C27 Q0 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.33fF
+C28 DFlipFlop_2/latch_diff_0/nD CLK 0.08fF
+C29 nQ2 sky130_fd_sc_hs__and2_1_1/a_143_136# 0.01fF
+C30 CLK DFlipFlop_3/latch_diff_1/m1_657_280# 0.27fF
+C31 nCLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.14fF
+C32 CLK DFlipFlop_1/D 0.21fF
+C33 DFlipFlop_1/latch_diff_1/nD CLK 0.09fF
+C34 Q0 DFlipFlop_1/latch_diff_1/D 0.06fF
+C35 vdd sky130_fd_sc_hs__and2_1_0/a_56_136# 0.02fF
+C36 nCLK DFlipFlop_3/latch_diff_0/m1_657_280# 0.27fF
+C37 DFlipFlop_1/latch_diff_1/m1_657_280# nCLK 0.28fF
+C38 vdd DFlipFlop_0/D 0.19fF
+C39 sky130_fd_sc_hs__xor2_1_0/a_194_125# nCLK 0.11fF
+C40 nQ0 CLK 0.19fF
+C41 CLK_5 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.06fF
+C42 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out nCLK 0.05fF
+C43 Q0 DFlipFlop_2/D 0.25fF
+C44 Q1 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.14fF
+C45 Q1 DFlipFlop_0/D 0.13fF
+C46 nQ0 DFlipFlop_1/D 0.12fF
+C47 nQ0 DFlipFlop_1/latch_diff_1/nD 0.88fF
+C48 Q0 DFlipFlop_0/Q 0.21fF
+C49 CLK DFlipFlop_0/latch_diff_1/D 0.03fF
+C50 Q1 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.21fF
+C51 CLK nQ2 0.17fF
+C52 CLK_5 vdd 0.15fF
+C53 DFlipFlop_3/nQ CLK 0.01fF
+C54 vdd sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.03fF
+C55 DFlipFlop_2/latch_diff_0/m1_657_280# CLK 0.28fF
+C56 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.03fF
+C57 Q1 DFlipFlop_3/latch_diff_0/m1_657_280# 0.28fF
+C58 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in DFlipFlop_0/D 0.02fF
+C59 DFlipFlop_1/D nCLK 0.14fF
+C60 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vdd 0.03fF
+C61 DFlipFlop_1/latch_diff_1/nD nCLK 0.16fF
+C62 Q1_shift sky130_fd_sc_hs__or2_1_0/a_152_368# -0.04fF
+C63 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out Q1 0.15fF
+C64 Q0 DFlipFlop_0/latch_diff_0/D 0.42fF
+C65 DFlipFlop_2/latch_diff_1/m1_657_280# nCLK 0.28fF
+C66 CLK vdd 0.41fF
+C67 DFlipFlop_2/nQ CLK 0.13fF
+C68 nQ0 nQ2 0.03fF
+C69 Q0 sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C70 nCLK DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.33fF
+C71 nQ0 nCLK 0.09fF
+C72 vdd DFlipFlop_1/D 0.25fF
+C73 CLK Q1 -0.10fF
+C74 CLK DFlipFlop_2/latch_diff_1/nD 0.09fF
+C75 DFlipFlop_3/latch_diff_1/m1_657_280# Q1 0.28fF
+C76 DFlipFlop_3/nQ Q1_shift 0.04fF
+C77 nCLK nQ2 0.10fF
+C78 DFlipFlop_1/D Q1 0.03fF
+C79 DFlipFlop_1/latch_diff_1/nD Q1 0.10fF
+C80 DFlipFlop_3/nQ nCLK 0.02fF
+C81 Q1_shift sky130_fd_sc_hs__or2_1_0/a_63_368# -0.27fF
+C82 vdd DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.03fF
+C83 nQ0 vdd 0.11fF
+C84 Q0 DFlipFlop_1/latch_diff_0/D 0.42fF
+C85 DFlipFlop_0/latch_diff_1/nD CLK 0.02fF
+C86 nCLK DFlipFlop_2/latch_diff_0/D 0.11fF
+C87 DFlipFlop_1/latch_diff_1/m1_657_280# DFlipFlop_2/D 0.04fF
+C88 DFlipFlop_2/latch_diff_1/m1_657_280# Q1 0.03fF
+C89 CLK DFlipFlop_1/latch_diff_0/nD 0.08fF
+C90 sky130_fd_sc_hs__xor2_1_0/a_194_125# DFlipFlop_2/D 0.08fF
+C91 Q1 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in 0.20fF
+C92 Q0 sky130_fd_sc_hs__and2_1_0/a_143_136# 0.03fF
+C93 nQ0 Q1 0.06fF
+C94 DFlipFlop_0/latch_diff_1/m1_657_280# nQ2 0.05fF
+C95 vdd Q1_shift 0.10fF
+C96 vdd nQ2 0.04fF
+C97 DFlipFlop_1/latch_diff_1/D CLK 0.14fF
+C98 CLK DFlipFlop_3/latch_diff_0/D 0.11fF
+C99 DFlipFlop_3/nQ vdd 0.02fF
+C100 nCLK DFlipFlop_0/latch_diff_1/m1_657_280# 0.28fF
+C101 DFlipFlop_2/nQ nCLK 0.09fF
+C102 vdd nCLK 0.34fF
+C103 vdd sky130_fd_sc_hs__or2_1_0/a_63_368# 0.02fF
+C104 DFlipFlop_0/latch_diff_1/D Q1 0.06fF
+C105 CLK DFlipFlop_3/latch_diff_1/nD 0.16fF
+C106 Q1 Q1_shift 0.36fF
+C107 Q1 nQ2 0.07fF
+C108 CLK DFlipFlop_2/D 0.14fF
+C109 DFlipFlop_3/nQ Q1 0.10fF
+C110 CLK DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.15fF
+C111 nCLK Q1 -0.01fF
+C112 nQ0 DFlipFlop_1/latch_diff_0/nD 0.08fF
+C113 Q1 sky130_fd_sc_hs__or2_1_0/a_63_368# 0.10fF
+C114 Q1 DFlipFlop_2/latch_diff_0/D 0.42fF
+C115 nCLK DFlipFlop_2/latch_diff_1/nD 0.16fF
+C116 CLK DFlipFlop_0/Q 0.08fF
+C117 DFlipFlop_2/nQ vdd 0.02fF
+C118 DFlipFlop_1/D DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.03fF
+C119 nQ0 DFlipFlop_1/latch_diff_1/D 0.91fF
+C120 CLK sky130_fd_sc_hs__and2_1_1/a_56_136# 0.06fF
+C121 Q0 sky130_fd_sc_hs__and2_1_0/a_56_136# 0.17fF
+C122 DFlipFlop_0/latch_diff_1/nD nCLK 0.05fF
+C123 Q0 DFlipFlop_0/D 0.39fF
+C124 vdd Q1 9.49fF
+C125 DFlipFlop_2/nQ Q1 0.31fF
+C126 DFlipFlop_1/D sky130_fd_sc_hs__and2_1_1/a_56_136# 0.04fF
+C127 Q0 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in 0.42fF
+C128 sky130_fd_sc_hs__xor2_1_0/a_455_87# nCLK 0.02fF
+C129 CLK DFlipFlop_2/latch_diff_1/D 0.14fF
+C130 DFlipFlop_1/latch_diff_1/D nCLK 0.08fF
+C131 Q0 DFlipFlop_1/latch_diff_1/m1_657_280# 0.01fF
+C132 Q1 DFlipFlop_2/latch_diff_1/nD 0.21fF
+C133 nQ0 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C134 vdd DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.02fF
+C135 nCLK DFlipFlop_3/latch_diff_1/nD 0.09fF
+C136 Q0 sky130_fd_sc_hs__xor2_1_0/a_194_125# 0.26fF
+C137 nCLK DFlipFlop_2/D 0.41fF
+C138 DFlipFlop_0/latch_diff_1/nD Q1 0.10fF
+C139 DFlipFlop_0/Q nQ2 0.09fF
+C140 Q1 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.09fF
+C141 CLK DFlipFlop_3/latch_diff_1/D 0.08fF
+C142 DFlipFlop_0/Q nCLK 0.11fF
+C143 nQ2 sky130_fd_sc_hs__and2_1_1/a_56_136# 0.01fF
+C144 Q0 CLK 0.08fF
+C145 DFlipFlop_1/latch_diff_1/D Q1 -0.10fF
+C146 DFlipFlop_3/latch_diff_0/D Q1 0.09fF
+C147 vdd DFlipFlop_2/D 0.07fF
+C148 DFlipFlop_0/D sky130_fd_sc_hs__and2_1_0/a_56_136# 0.04fF
+C149 vdd DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out 0.02fF
+C150 DFlipFlop_3/latch_diff_0/nD nCLK 0.08fF
+C151 Q0 DFlipFlop_1/D 0.07fF
+C152 Q1 DFlipFlop_3/latch_diff_1/nD 1.24fF
+C153 Q0 DFlipFlop_1/latch_diff_1/nD 0.21fF
+C154 nCLK DFlipFlop_2/latch_diff_1/D 0.08fF
+C155 Q1 DFlipFlop_2/D 0.10fF
+C156 DFlipFlop_0/latch_diff_0/m1_657_280# CLK 0.28fF
 C157 CLK_5 vss -0.18fF
 C158 sky130_fd_sc_hs__or2_1_0/a_63_368# vss 0.38fF
 C159 sky130_fd_sc_hs__and2_1_1/a_56_136# vss 0.41fF
@@ -2163,32 +5909,32 @@
 C164 DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C165 DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C166 DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C167 DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C168 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C167 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.94fF
+C168 DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C169 DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.85fF
-C170 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C171 DFlipFlop_2/nQ vss 0.50fF
-C172 Q1 vss 8.55fF
-C173 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
-C174 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
-C175 DFlipFlop_2/latch_diff_1/D vss -1.72fF
-C176 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C177 DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C178 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
-C179 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C180 DFlipFlop_2/D vss 5.34fF
-C181 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C182 nQ0 vss 3.42fF
-C183 Q0 vss 0.53fF
-C184 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
-C185 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C186 DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C187 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C188 DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C189 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C190 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
-C191 DFlipFlop_1/D vss 3.72fF
-C192 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C170 Q1 vss 8.55fF
+C171 DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C172 nQ0 vss 3.42fF
+C173 Q0 vss 0.53fF
+C174 DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.62fF
+C175 DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C176 DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C177 DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C178 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C179 DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C180 DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.78fF
+C181 DFlipFlop_1/D vss 3.72fF
+C182 DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C183 DFlipFlop_2/nQ vss 0.50fF
+C184 DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.72fF
+C185 DFlipFlop_2/latch_diff_1/nD vss 0.58fF
+C186 DFlipFlop_2/latch_diff_1/D vss -1.72fF
+C187 DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C188 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.89fF
+C189 DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C190 DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C191 DFlipFlop_2/D vss 5.34fF
+C192 DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C193 nQ2 vss 2.05fF
 C194 DFlipFlop_0/Q vss -0.94fF
 C195 DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.61fF
@@ -2197,8 +5943,8 @@
 C198 DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C199 DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C200 CLK vss 0.20fF
-C201 DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C202 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C201 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.88fF
+C202 DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C203 DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C204 DFlipFlop_0/D vss 4.04fF
 C205 DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -2216,29 +5962,29 @@
 X3 a_n129_n125# a_n159_n151# a_n225_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X4 a_n33_n125# a_n63_n151# a_n129_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X5 a_255_n125# a_225_n151# a_159_n125# w_n455_n335# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 a_255_n125# a_63_n125# 0.13fF
-C1 a_63_n125# a_n317_n125# 0.06fF
-C2 a_n129_n125# a_159_n125# 0.08fF
-C3 a_n225_n125# a_n317_n125# 0.36fF
-C4 a_n255_n151# a_n159_n151# 0.02fF
-C5 a_n159_n151# a_n63_n151# 0.02fF
-C6 a_n33_n125# a_255_n125# 0.08fF
-C7 a_n33_n125# a_n317_n125# 0.08fF
-C8 a_n129_n125# a_63_n125# 0.13fF
-C9 a_33_n151# a_129_n151# 0.02fF
-C10 a_n129_n125# a_n225_n125# 0.36fF
-C11 a_33_n151# a_n63_n151# 0.02fF
-C12 a_159_n125# a_63_n125# 0.36fF
-C13 a_n129_n125# a_n33_n125# 0.36fF
-C14 a_n225_n125# a_159_n125# 0.06fF
-C15 a_129_n151# a_225_n151# 0.02fF
-C16 a_n129_n125# a_255_n125# 0.06fF
-C17 a_n129_n125# a_n317_n125# 0.13fF
-C18 a_n33_n125# a_159_n125# 0.13fF
-C19 a_n225_n125# a_63_n125# 0.08fF
-C20 a_255_n125# a_159_n125# 0.36fF
-C21 a_n33_n125# a_63_n125# 0.36fF
-C22 a_n225_n125# a_n33_n125# 0.13fF
+C0 a_63_n125# a_n33_n125# 0.36fF
+C1 a_n255_n151# a_n159_n151# 0.02fF
+C2 a_n225_n125# a_n129_n125# 0.36fF
+C3 a_129_n151# a_225_n151# 0.02fF
+C4 a_255_n125# a_63_n125# 0.13fF
+C5 a_n129_n125# a_n33_n125# 0.36fF
+C6 a_33_n151# a_n63_n151# 0.02fF
+C7 a_63_n125# a_n317_n125# 0.06fF
+C8 a_129_n151# a_33_n151# 0.02fF
+C9 a_255_n125# a_n129_n125# 0.06fF
+C10 a_n225_n125# a_159_n125# 0.06fF
+C11 a_n33_n125# a_159_n125# 0.13fF
+C12 a_n129_n125# a_n317_n125# 0.13fF
+C13 a_n129_n125# a_63_n125# 0.13fF
+C14 a_n225_n125# a_n33_n125# 0.13fF
+C15 a_255_n125# a_159_n125# 0.36fF
+C16 a_63_n125# a_159_n125# 0.36fF
+C17 a_255_n125# a_n33_n125# 0.08fF
+C18 a_n225_n125# a_n317_n125# 0.36fF
+C19 a_n159_n151# a_n63_n151# 0.02fF
+C20 a_n33_n125# a_n317_n125# 0.08fF
+C21 a_n225_n125# a_63_n125# 0.08fF
+C22 a_n129_n125# a_159_n125# 0.08fF
 C23 a_255_n125# w_n455_n335# 0.14fF
 C24 a_159_n125# w_n455_n335# 0.08fF
 C25 a_63_n125# w_n455_n335# 0.07fF
@@ -2263,36 +6009,36 @@
 X3 a_159_n125# a_129_n154# a_63_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X4 a_n225_n125# a_n255_n154# a_n317_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
 X5 a_63_n125# a_33_n154# a_n33_n125# w_n455_n344# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.25e+06u l=150000u
-C0 w_n455_n344# a_255_n125# 0.11fF
-C1 a_159_n125# a_n129_n125# 0.08fF
-C2 w_n455_n344# a_n33_n125# 0.05fF
-C3 a_n225_n125# a_n33_n125# 0.13fF
-C4 w_n455_n344# a_63_n125# 0.04fF
-C5 a_255_n125# a_n33_n125# 0.08fF
-C6 a_n129_n125# a_n317_n125# 0.13fF
-C7 a_n225_n125# a_63_n125# 0.08fF
-C8 a_159_n125# w_n455_n344# 0.06fF
-C9 a_255_n125# a_63_n125# 0.13fF
+C0 w_n455_n344# a_n33_n125# 0.05fF
+C1 a_159_n125# a_63_n125# 0.36fF
+C2 a_n225_n125# a_159_n125# 0.06fF
+C3 a_255_n125# a_159_n125# 0.36fF
+C4 a_n225_n125# a_63_n125# 0.08fF
+C5 a_255_n125# a_63_n125# 0.13fF
+C6 w_n455_n344# a_n317_n125# 0.11fF
+C7 a_n129_n125# a_n33_n125# 0.36fF
+C8 a_n33_n125# a_159_n125# 0.13fF
+C9 a_n129_n125# a_n317_n125# 0.13fF
 C10 a_n33_n125# a_63_n125# 0.36fF
-C11 a_159_n125# a_n225_n125# 0.06fF
-C12 a_n63_n154# a_n159_n154# 0.02fF
-C13 a_159_n125# a_255_n125# 0.36fF
-C14 w_n455_n344# a_n317_n125# 0.11fF
-C15 a_159_n125# a_n33_n125# 0.13fF
-C16 w_n455_n344# a_n129_n125# 0.04fF
-C17 a_n225_n125# a_n317_n125# 0.36fF
-C18 a_n225_n125# a_n129_n125# 0.36fF
-C19 a_33_n154# a_129_n154# 0.02fF
-C20 a_159_n125# a_63_n125# 0.36fF
-C21 a_n129_n125# a_255_n125# 0.06fF
-C22 a_n317_n125# a_n33_n125# 0.08fF
-C23 a_n129_n125# a_n33_n125# 0.36fF
-C24 a_33_n154# a_n63_n154# 0.02fF
-C25 a_n317_n125# a_63_n125# 0.06fF
-C26 a_n129_n125# a_63_n125# 0.13fF
-C27 a_n255_n154# a_n159_n154# 0.02fF
-C28 w_n455_n344# a_n225_n125# 0.06fF
-C29 a_225_n154# a_129_n154# 0.02fF
+C11 a_n225_n125# a_n33_n125# 0.13fF
+C12 w_n455_n344# a_n129_n125# 0.04fF
+C13 a_255_n125# a_n33_n125# 0.08fF
+C14 a_n317_n125# a_63_n125# 0.06fF
+C15 w_n455_n344# a_159_n125# 0.06fF
+C16 a_n225_n125# a_n317_n125# 0.36fF
+C17 a_n159_n154# a_n63_n154# 0.02fF
+C18 w_n455_n344# a_63_n125# 0.04fF
+C19 a_n225_n125# w_n455_n344# 0.06fF
+C20 w_n455_n344# a_255_n125# 0.11fF
+C21 a_129_n154# a_33_n154# 0.02fF
+C22 a_n159_n154# a_n255_n154# 0.02fF
+C23 a_n129_n125# a_159_n125# 0.08fF
+C24 a_n129_n125# a_63_n125# 0.13fF
+C25 a_33_n154# a_n63_n154# 0.02fF
+C26 a_n225_n125# a_n129_n125# 0.36fF
+C27 a_n317_n125# a_n33_n125# 0.08fF
+C28 a_225_n154# a_129_n154# 0.02fF
+C29 a_255_n125# a_n129_n125# 0.06fF
 C30 a_255_n125# VSUBS 0.03fF
 C31 a_159_n125# VSUBS 0.03fF
 C32 a_63_n125# VSUBS 0.03fF
@@ -2314,35 +6060,35 @@
 + sky130_fd_pr__nfet_01v8_AZESM8
 Xsky130_fd_pr__pfet_01v8_XJXT7S_0 vss vdd in in vdd in out out in in out vdd out vdd
 + in sky130_fd_pr__pfet_01v8_XJXT7S
-C0 out vdd 0.29fF
-C1 in out 0.85fF
-C2 in vdd 0.04fF
+C0 in vdd 0.04fF
+C1 out vdd 0.29fF
+C2 out in 0.85fF
 C3 vdd vss 5.90fF
 C4 out vss 1.30fF
 C5 in vss 1.82fF
 .ends
 
-.subckt pfd_cp_interface vss inverter_cp_x1_2/in vdd inverter_cp_x1_0/out Down QA
+.subckt pfd_cp_interface vss vdd inverter_cp_x1_0/out inverter_cp_x1_2/in Down QA
 + QB nDown Up nUp
 Xinverter_cp_x2_0 nDown Down vss vdd inverter_cp_x2
 Xinverter_cp_x2_1 Up nUp vss vdd inverter_cp_x2
 Xtrans_gate_0 nDown inverter_cp_x1_0/out vss vdd trans_gate
 Xinverter_cp_x1_0 inverter_cp_x1_0/out QB vss vdd inverter_cp_x1
-Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
 Xinverter_cp_x1_1 inverter_cp_x1_2/in QA vss vdd inverter_cp_x1
-C0 inverter_cp_x1_2/in Up 0.12fF
-C1 inverter_cp_x1_2/in vdd 0.42fF
-C2 inverter_cp_x1_0/out nDown 0.11fF
-C3 Up vdd 0.60fF
-C4 QB vdd 0.02fF
-C5 Down vdd 0.09fF
-C6 nUp Up 0.20fF
-C7 nDown Down 0.23fF
-C8 inverter_cp_x1_0/out Down 0.12fF
-C9 nDown vdd 0.80fF
-C10 inverter_cp_x1_0/out vdd 0.25fF
-C11 nUp vdd 0.14fF
-C12 QA vdd 0.02fF
+Xinverter_cp_x1_2 Up inverter_cp_x1_2/in vss vdd inverter_cp_x1
+C0 vdd Down 0.09fF
+C1 nDown inverter_cp_x1_0/out 0.11fF
+C2 nDown vdd 0.80fF
+C3 vdd inverter_cp_x1_0/out 0.25fF
+C4 vdd QB 0.02fF
+C5 vdd inverter_cp_x1_2/in 0.42fF
+C6 vdd Up 0.60fF
+C7 inverter_cp_x1_2/in Up 0.12fF
+C8 nUp vdd 0.14fF
+C9 nUp Up 0.20fF
+C10 vdd QA 0.02fF
+C11 nDown Down 0.23fF
+C12 Down inverter_cp_x1_0/out 0.12fF
 C13 inverter_cp_x1_2/in vss 2.01fF
 C14 QA vss 1.09fF
 C15 inverter_cp_x1_0/out vss 2.00fF
@@ -2360,22 +6106,22 @@
 X1 a_n129_n90# a_n159_n207# a_n221_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X2 a_63_n90# a_n159_n207# a_n33_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X3 a_n33_n90# a_n63_n116# a_n129_n90# w_n359_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 a_159_n90# a_63_n90# 0.26fF
-C1 w_n359_n309# a_n129_n90# 0.06fF
-C2 a_n129_n90# a_n33_n90# 0.26fF
-C3 a_159_n90# a_n221_n90# 0.04fF
-C4 a_n221_n90# a_63_n90# 0.06fF
-C5 w_n359_n309# a_n33_n90# 0.05fF
-C6 a_159_n90# a_n129_n90# 0.06fF
-C7 a_n129_n90# a_63_n90# 0.09fF
-C8 a_159_n90# w_n359_n309# 0.09fF
-C9 a_n221_n90# a_n129_n90# 0.26fF
-C10 a_159_n90# a_n33_n90# 0.09fF
-C11 w_n359_n309# a_63_n90# 0.06fF
-C12 a_n33_n90# a_63_n90# 0.26fF
-C13 a_n63_n116# a_n159_n207# 0.12fF
-C14 w_n359_n309# a_n221_n90# 0.09fF
-C15 a_n221_n90# a_n33_n90# 0.09fF
+C0 a_n129_n90# a_63_n90# 0.09fF
+C1 a_n221_n90# a_159_n90# 0.04fF
+C2 w_n359_n309# a_n221_n90# 0.09fF
+C3 a_n221_n90# a_n33_n90# 0.09fF
+C4 a_n221_n90# a_n129_n90# 0.26fF
+C5 a_n221_n90# a_63_n90# 0.06fF
+C6 a_n33_n90# a_159_n90# 0.09fF
+C7 w_n359_n309# a_159_n90# 0.09fF
+C8 a_n129_n90# a_159_n90# 0.06fF
+C9 a_63_n90# a_159_n90# 0.26fF
+C10 a_n63_n116# a_n159_n207# 0.12fF
+C11 w_n359_n309# a_n33_n90# 0.05fF
+C12 a_n129_n90# a_n33_n90# 0.26fF
+C13 w_n359_n309# a_n129_n90# 0.06fF
+C14 a_n33_n90# a_63_n90# 0.26fF
+C15 w_n359_n309# a_63_n90# 0.06fF
 C16 a_159_n90# VSUBS 0.03fF
 C17 a_63_n90# VSUBS 0.03fF
 C18 a_n33_n90# VSUBS 0.03fF
@@ -2390,10 +6136,10 @@
 + a_n125_n45# a_63_n45#
 X0 a_63_n45# a_33_n71# a_n33_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X1 a_n33_n45# a_n129_71# a_n125_n45# w_n263_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n125_n45# a_63_n45# 0.05fF
-C1 a_n33_n45# a_n125_n45# 0.13fF
-C2 a_n33_n45# a_63_n45# 0.13fF
-C3 a_n129_71# a_33_n71# 0.04fF
+C0 a_63_n45# a_n33_n45# 0.13fF
+C1 a_n129_71# a_33_n71# 0.04fF
+C2 a_n125_n45# a_n33_n45# 0.13fF
+C3 a_63_n45# a_n125_n45# 0.05fF
 C4 a_63_n45# w_n263_n255# 0.04fF
 C5 a_n33_n45# w_n263_n255# 0.04fF
 C6 a_n125_n45# w_n263_n255# 0.04fF
@@ -2406,14 +6152,14 @@
 Xsky130_fd_pr__pfet_01v8_4F35BC_0 vss sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
 + vdd B A sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out vdd vdd sky130_fd_pr__pfet_01v8_4F35BC
 Xsky130_fd_pr__nfet_01v8_C3YG4M_0 out B A vss vss vss sky130_fd_pr__nfet_01v8_C3YG4M
-C0 B A 0.24fF
-C1 vdd A 0.09fF
-C2 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.02fF
-C3 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# out 0.08fF
-C4 A out 0.06fF
-C5 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.02fF
-C6 B out 0.40fF
-C7 vdd out 0.11fF
+C0 out vdd 0.11fF
+C1 out A 0.06fF
+C2 out sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.08fF
+C3 A vdd 0.09fF
+C4 vdd sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.02fF
+C5 B out 0.40fF
+C6 B A 0.24fF
+C7 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.02fF
 C8 sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C9 out vss 0.45fF
 C10 sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2431,37 +6177,37 @@
 + vss vdd nor_pfd_2/A nor_pfd_2/B nor_pfd
 Xnor_pfd_3 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# nor_pfd_2/B nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90#
 + vss vdd nor_pfd_3/A Reset nor_pfd
-C0 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C1 nor_pfd_3/A nor_pfd_2/A 0.38fF
-C2 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# 0.06fF
-C3 vdd nor_pfd_2/A -0.01fF
-C4 Q Reset 0.14fF
-C5 nor_pfd_2/B Reset 0.43fF
-C6 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
-C7 nor_pfd_3/A vdd 0.09fF
-C8 vdd nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# 0.06fF
-C9 Q nor_pfd_2/A 1.38fF
-C10 nor_pfd_2/B nor_pfd_2/A 0.05fF
-C11 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C12 nor_pfd_3/A Q 0.98fF
-C13 nor_pfd_2/B nor_pfd_3/A 0.58fF
-C14 Q vdd 0.08fF
-C15 nor_pfd_2/B vdd 0.02fF
-C16 CLK Q 0.04fF
-C17 nor_pfd_3/A Reset 0.12fF
-C18 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
-C19 nor_pfd_2/B Q 2.22fF
+C0 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C1 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C2 nor_pfd_3/A vdd 0.09fF
+C3 Reset nor_pfd_2/B 0.43fF
+C4 nor_pfd_3/A nor_pfd_2/B 0.58fF
+C5 nor_pfd_2/A nor_pfd_3/A 0.38fF
+C6 vdd Q 0.08fF
+C7 nor_pfd_2/B Q 2.22fF
+C8 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C9 nor_pfd_2/A Q 1.38fF
+C10 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vdd 0.06fF
+C11 CLK Q 0.04fF
+C12 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
+C13 nor_pfd_3/A Reset 0.12fF
+C14 nor_pfd_2/B vdd 0.02fF
+C15 nor_pfd_2/A vdd -0.01fF
+C16 nor_pfd_2/A nor_pfd_2/B 0.05fF
+C17 Reset Q 0.14fF
+C18 nor_pfd_3/A Q 0.98fF
+C19 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vdd 0.06fF
 C20 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C21 nor_pfd_2/B vss 1.42fF
 C22 nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C23 nor_pfd_3/A vss 3.16fF
-C24 Reset vss 1.48fF
-C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C26 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C27 nor_pfd_2/A vss 2.56fF
-C28 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C29 Q vss 2.77fF
-C30 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C23 Reset vss 1.48fF
+C24 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C25 nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C26 nor_pfd_2/A vss 2.56fF
+C27 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C28 Q vss 2.77fF
+C29 nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C30 nor_pfd_3/A vss 3.16fF
 C31 vdd vss 16.42fF
 C32 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C33 nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2474,17 +6220,17 @@
 X1 a_n33_n45# a_n63_n71# a_n129_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X2 a_159_n45# a_n63_n71# a_63_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
 X3 a_n129_n45# a_n159_n173# a_n221_n45# w_n359_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n129_n45# a_n221_n45# 0.13fF
-C1 a_63_n45# a_n221_n45# 0.03fF
-C2 a_n33_n45# a_n129_n45# 0.13fF
-C3 a_63_n45# a_n33_n45# 0.13fF
-C4 a_63_n45# a_n129_n45# 0.05fF
-C5 a_n159_n173# a_n63_n71# 0.10fF
-C6 a_159_n45# a_n221_n45# 0.02fF
-C7 a_n33_n45# a_159_n45# 0.05fF
-C8 a_n33_n45# a_n221_n45# 0.05fF
+C0 a_159_n45# a_n221_n45# 0.02fF
+C1 a_63_n45# a_n33_n45# 0.13fF
+C2 a_n129_n45# a_63_n45# 0.05fF
+C3 a_n129_n45# a_n33_n45# 0.13fF
+C4 a_n221_n45# a_63_n45# 0.03fF
+C5 a_n221_n45# a_n33_n45# 0.05fF
+C6 a_n129_n45# a_n221_n45# 0.13fF
+C7 a_159_n45# a_63_n45# 0.13fF
+C8 a_159_n45# a_n33_n45# 0.05fF
 C9 a_159_n45# a_n129_n45# 0.03fF
-C10 a_63_n45# a_159_n45# 0.13fF
+C10 a_n63_n71# a_n159_n173# 0.10fF
 C11 a_159_n45# w_n359_n255# 0.04fF
 C12 a_63_n45# w_n359_n255# 0.05fF
 C13 a_n33_n45# w_n359_n255# 0.05fF
@@ -2499,7 +6245,7 @@
 X0 a_63_n90# a_33_n187# a_n33_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 X1 a_n33_n90# a_n99_n187# a_n125_n90# w_n263_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
 C0 a_n99_n187# a_33_n187# 0.04fF
-C1 a_63_n90# a_n125_n90# 0.09fF
+C1 a_n125_n90# a_63_n90# 0.09fF
 C2 a_n33_n90# a_63_n90# 0.26fF
 C3 a_n33_n90# a_n125_n90# 0.26fF
 C4 a_63_n90# VSUBS 0.03fF
@@ -2512,7 +6258,7 @@
 
 .subckt sky130_fd_pr__nfet_01v8_ZXAV3F a_n73_n45# a_n33_67# a_15_n45# w_n211_n255#
 X0 a_15_n45# a_n33_67# a_n73_n45# w_n211_n255# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=150000u
-C0 a_n73_n45# a_15_n45# 0.16fF
+C0 a_15_n45# a_n73_n45# 0.16fF
 C1 a_15_n45# w_n211_n255# 0.08fF
 C2 a_n73_n45# w_n211_n255# 0.06fF
 C3 a_n33_67# w_n211_n255# 0.10fF
@@ -2520,9 +6266,9 @@
 
 .subckt sky130_fd_pr__pfet_01v8_4F7GBC VSUBS a_n51_n187# a_n73_n90# a_15_n90# w_n211_n309#
 X0 a_15_n90# a_n51_n187# a_n73_n90# w_n211_n309# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=900000u l=150000u
-C0 w_n211_n309# a_n73_n90# 0.04fF
-C1 w_n211_n309# a_15_n90# 0.09fF
-C2 a_15_n90# a_n73_n90# 0.31fF
+C0 a_n73_n90# a_15_n90# 0.31fF
+C1 a_15_n90# w_n211_n309# 0.09fF
+C2 a_n73_n90# w_n211_n309# 0.04fF
 C3 a_15_n90# VSUBS 0.03fF
 C4 a_n73_n90# VSUBS 0.03fF
 C5 a_n51_n187# VSUBS 0.12fF
@@ -2535,16 +6281,16 @@
 Xsky130_fd_pr__pfet_01v8_7T83YG_0 vss vdd vdd B A a_656_410# vdd sky130_fd_pr__pfet_01v8_7T83YG
 Xsky130_fd_pr__nfet_01v8_ZXAV3F_0 vss a_656_410# out vss sky130_fd_pr__nfet_01v8_ZXAV3F
 Xsky130_fd_pr__pfet_01v8_4F7GBC_0 vss a_656_410# vdd out vdd sky130_fd_pr__pfet_01v8_4F7GBC
-C0 A a_656_410# 0.04fF
-C1 A vdd 0.05fF
-C2 B a_656_410# 0.30fF
-C3 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
-C4 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
-C5 out a_656_410# 0.20fF
-C6 out sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# 0.03fF
-C7 A B 0.33fF
-C8 vdd a_656_410# 0.20fF
-C9 out vdd 0.10fF
+C0 A vdd 0.05fF
+C1 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# out 0.03fF
+C2 sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# a_656_410# 0.07fF
+C3 out vdd 0.10fF
+C4 B A 0.33fF
+C5 A a_656_410# 0.04fF
+C6 vdd a_656_410# 0.20fF
+C7 out a_656_410# 0.20fF
+C8 B a_656_410# 0.30fF
+C9 B sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# 0.02fF
 C10 vdd vss 4.85fF
 C11 out vss 0.47fF
 C12 a_656_410# vss 1.00fF
@@ -2560,43 +6306,43 @@
 Xdff_pfd_1 vdd vss dff_pfd_1/nor_pfd_2/A Down B dff_pfd_1/nor_pfd_3/A dff_pfd_1/nor_pfd_2/B
 + Reset dff_pfd
 Xand_pfd_0 and_pfd_0/a_656_410# vss Reset vdd Up Down and_pfd
-C0 Up vdd 1.62fF
-C1 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
-C2 Down vdd 0.08fF
-C3 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
-C4 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
-C5 dff_pfd_0/nor_pfd_3/A vdd 0.08fF
-C6 dff_pfd_1/nor_pfd_2/B vdd 0.04fF
-C7 vdd Reset 0.02fF
-C8 dff_pfd_1/nor_pfd_3/A vdd 0.08fF
-C9 Down Up 0.06fF
+C0 vdd dff_pfd_0/nor_pfd_2/B 0.11fF
+C1 vdd dff_pfd_0/nor_pfd_3/A 0.08fF
+C2 vdd dff_pfd_1/nor_pfd_3/A 0.08fF
+C3 vdd Up 1.62fF
+C4 Down vdd 0.08fF
+C5 vdd dff_pfd_1/nor_pfd_2/B 0.04fF
+C6 vdd dff_pfd_0/nor_pfd_2/A 0.13fF
+C7 vdd dff_pfd_1/nor_pfd_2/A 0.13fF
+C8 Down Up 0.06fF
+C9 vdd Reset 0.02fF
 C10 and_pfd_0/a_656_410# vss 0.99fF
 C11 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C12 and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.05fF
 C13 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C14 dff_pfd_1/nor_pfd_2/B vss 1.51fF
 C15 dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C16 dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C18 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C19 dff_pfd_1/nor_pfd_2/A vss 2.56fF
-C20 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C21 Down vss 3.74fF
-C22 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C16 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C17 dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C18 dff_pfd_1/nor_pfd_2/A vss 2.56fF
+C19 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C20 Down vss 3.74fF
+C21 dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C22 dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C23 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C24 dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C25 B vss 1.07fF
 C26 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C27 dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C28 dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C29 dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C30 Reset vss 3.85fF
-C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C32 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C33 dff_pfd_0/nor_pfd_2/A vss 2.56fF
-C34 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C35 Up vss 3.18fF
-C36 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C29 Reset vss 3.85fF
+C30 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C31 dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C32 dff_pfd_0/nor_pfd_2/A vss 2.56fF
+C33 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C34 Up vss 3.18fF
+C35 dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C36 dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C37 vdd vss 44.73fF
 C38 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C39 dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
@@ -2612,8 +6358,8 @@
 Xcharge_pump_0 vss pswitch nswitch vco_vctrl vdd biasp nUp Down charge_pump_0/w_2544_775#
 + iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
 Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
-+ n_out_div_2 div_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
 Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
 + vss vdd buffer_salida
 Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
@@ -2621,161 +6367,163 @@
 + ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_D0 ring_osc_0/csvco_branch_2/cap_vco_0/t
 + vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
-+ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
 + div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
 + div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
 + div_by_5
-Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
 + Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 div_5_Q1_shift out_div_by_5 0.05fF
-C1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
-C2 Up pswitch 1.98fF
-C3 nswitch vco_vctrl -0.06fF
-C4 biasp Up 0.26fF
-C5 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
-C6 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
-C7 vdd buffer_salida_0/a_678_n100# 0.24fF
-C8 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
-C9 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
-C10 nUp vco_vctrl 0.02fF
-C11 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
-C12 vdd nDown 0.22fF
-C13 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
-C14 vdd iref_cp 0.15fF
-C15 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
-C16 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# n_out_by_2 0.12fF
-C17 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
-C18 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
-C19 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.23fF
-C20 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
-C21 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
-C22 vdd QA -0.04fF
-C23 vdd out_to_div 0.21fF
-C24 Down nswitch 0.54fF
-C25 n_out_by_2 div_5_nQ2 0.10fF
-C26 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
-C27 nswitch nDown 0.76fF
-C28 vdd vco_D0 0.03fF
-C29 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
-C30 n_out_by_2 vco_vctrl 0.52fF
-C31 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
-C32 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
-C33 nUp nDown -0.09fF
-C34 div_5_nQ2 out_by_2 0.16fF
-C35 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
-C36 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
-C37 div_5_Q1 out_div_by_5 0.01fF
-C38 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
-C39 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
-C40 vco_vctrl out_by_2 0.53fF
-C41 vdd lf_vc 0.02fF
-C42 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
-C43 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
-C44 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
-C45 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
-C46 Down biasp 1.24fF
-C47 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
-C48 nDown pswitch 0.53fF
-C49 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
-C50 biasp nDown 0.26fF
-C51 vdd out_div_by_5 0.28fF
-C52 vdd nUp 0.05fF
-C53 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
-C54 n_out_by_2 div_5_Q1 1.04fF
-C55 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C56 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
-C57 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
-C58 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
-C59 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
-C60 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
-C61 div_5_Q1 out_by_2 0.42fF
-C62 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C63 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
-C64 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
-C65 buffer_salida_0/a_678_n100# out_to_buffer 0.22fF
-C66 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
-C67 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
-C68 vdd Up 0.28fF
-C69 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
-C70 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
-C71 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C72 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C73 vdd ring_osc_0/csvco_branch_2/vbp 0.03fF
-C74 vdd n_out_by_2 1.03fF
-C75 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
-C76 div_5_nQ0 n_out_by_2 0.10fF
-C77 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
-C78 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
-C79 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
-C80 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
-C81 vco_vctrl div_5_Q1 0.14fF
-C82 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
-C83 n_out_by_2 div_5_Q0 -0.12fF
-C84 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C85 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
-C86 vdd out_by_2 0.97fF
-C87 out_to_buffer out_to_div 0.13fF
-C88 div_5_nQ0 out_by_2 0.32fF
-C89 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
-C90 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
-C91 Down nDown 2.55fF
-C92 iref_cp Down 0.09fF
-C93 div_5_Q0 out_by_2 0.09fF
-C94 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
-C95 nUp Up 2.72fF
-C96 nUp pswitch 0.85fF
-C97 nUp biasp -0.17fF
-C98 vdd vco_vctrl -1.02fF
-C99 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
-C100 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
-C101 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
-C102 vdd out_to_buffer 0.07fF
-C103 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
-C104 vco_vctrl div_5_Q0 0.48fF
-C105 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C0 vco_vctrl nswitch -0.06fF
+C1 vco_D0 vdd 0.03fF
+C2 Up vdd 0.28fF
+C3 iref_cp vdd 0.15fF
+C4 Down iref_cp 0.09fF
+C5 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
+C6 out_to_buffer vdd 0.07fF
+C7 out_div_by_5 div_5_Q1_shift 0.05fF
+C8 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C9 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
+C10 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.24fF
+C11 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C12 Up pswitch 1.98fF
+C13 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
+C14 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C15 vco_vctrl ring_osc_0/csvco_branch_2/vbp 0.26fF
+C16 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C17 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C18 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
+C19 vdd out_to_div 0.21fF
+C20 Up nUp 2.72fF
+C21 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
+C22 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# 0.02fF
+C23 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
+C24 n_out_by_2 div_5_nQ0 0.10fF
+C25 n_out_by_2 div_by_5_0/DFlipFlop_0/Q -0.23fF
+C26 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# -0.11fF
+C27 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
+C28 out_by_2 div_5_nQ0 0.32fF
+C29 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C30 Down biasp 1.24fF
+C31 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
+C32 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
+C33 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.10fF
+C34 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
+C35 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
+C36 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.17fF
+C37 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C38 n_out_by_2 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in -0.51fF
+C39 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C40 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD 0.33fF
+C41 biasp nUp -0.17fF
+C42 nDown biasp 0.26fF
+C43 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
+C44 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/nD 0.24fF
+C45 vdd lf_vc 0.02fF
+C46 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C47 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C48 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
+C49 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C50 n_out_by_2 div_5_nQ2 0.10fF
+C51 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C52 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C53 n_out_by_2 div_by_5_0/DFlipFlop_1/D 0.22fF
+C54 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C55 buffer_salida_0/a_678_n100# vdd 0.24fF
+C56 out_by_2 div_5_nQ2 0.16fF
+C57 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vco_vctrl 0.04fF
+C58 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C59 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C60 n_out_by_2 div_5_Q1 1.04fF
+C61 vco_vctrl div_5_Q1 0.14fF
+C62 n_out_by_2 vdd 1.03fF
+C63 nUp vdd 0.05fF
+C64 nDown vdd 0.22fF
+C65 vco_vctrl vdd -1.02fF
+C66 div_5_Q1 out_by_2 0.42fF
+C67 Down nDown 2.55fF
+C68 out_by_2 vdd 0.97fF
+C69 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
+C70 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.24fF
+C71 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
+C72 pswitch nUp 0.85fF
+C73 nDown pswitch 0.53fF
+C74 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C75 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C76 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
+C77 out_to_buffer out_to_div 0.13fF
+C78 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
+C79 n_out_by_2 vco_vctrl 0.52fF
+C80 nDown nUp -0.09fF
+C81 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
+C82 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
+C83 vco_vctrl nUp 0.02fF
+C84 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
+C85 n_out_by_2 div_5_Q0 -0.12fF
+C86 vco_vctrl div_5_Q0 0.48fF
+C87 vco_vctrl out_by_2 0.53fF
+C88 QA vdd -0.04fF
+C89 Up biasp 0.26fF
+C90 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C91 div_5_Q1 out_div_by_5 0.01fF
+C92 out_by_2 div_5_Q0 0.09fF
+C93 out_div_by_5 vdd 0.28fF
+C94 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C95 Down nswitch 0.54fF
+C96 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
+C97 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/nD 0.10fF
+C98 div_by_5_0/DFlipFlop_2/D out_by_2 0.22fF
+C99 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C100 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
+C101 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C102 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_to_div -0.16fF
+C103 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C104 n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/D 0.24fF
+C105 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
 C106 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
-C107 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C107 nDown nswitch 0.76fF
 C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
 C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
 C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
 C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C119 QB vss 4.46fF
-C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C123 out_div_by_5 vss -0.40fF
 C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C128 pfd_reset vss 2.17fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C133 QA vss 4.31fF
-C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C137 in_ref vss 1.19fF
@@ -2794,32 +6542,32 @@
 C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C158 div_5_Q1 vss 4.28fF
-C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C168 div_5_nQ0 vss 0.59fF
-C169 div_5_Q0 vss 0.01fF
-C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C179 div_5_nQ2 vss 1.24fF
 C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
 C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
@@ -2828,17 +6576,17 @@
 C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C186 out_by_2 vss -4.51fF
-C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
 C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
 C192 vdd vss 366.82fF
 C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
 C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
-C195 out_to_buffer vss 1.57fF
+C195 out_first_buffer vss 2.88fF
 C196 out_to_div vss 4.46fF
-C197 out_first_buffer vss 2.88fF
+C197 out_to_buffer vss 1.57fF
 C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
 C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -2853,22 +6601,22 @@
 C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
 C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
 C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 out_to_pad vss 7.50fF
-C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
 C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 n_out_buffer_div_2 vss 1.63fF
-C216 out_buffer_div_2 vss 1.60fF
-C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
 C221 out_div_2 vss -1.30fF
 C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
 C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C229 n_out_div_2 vss 1.95fF
 C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -2940,15 +6688,15 @@
 X48 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
 X49 a_n1731_n1219# a_n2017_n1317# a_n1879_n1219# w_n2018_n202# sky130_fd_pr__pfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=4.5e+06u l=450000u
 C0 w_n2018_n202# a_n2017_n61# 1.37fF
-C1 w_n2018_n202# a_n1731_n1219# 19.90fF
-C2 w_n2018_n202# a_n2017_n1317# 0.16fF
-C3 w_n2018_n202# a_n1879_n1219# 0.25fF
-C4 a_n1731_n1219# a_n2017_n61# 5.23fF
-C5 a_n2017_n1317# a_n2017_n61# 2.88fF
-C6 a_n1731_n1219# a_n2017_n1317# 4.73fF
-C7 a_n1879_n1219# a_n2017_n61# 0.16fF
-C8 a_n1879_n1219# a_n1731_n1219# 19.29fF
-C9 a_n1879_n1219# a_n2017_n1317# 2.66fF
+C1 w_n2018_n202# a_n1879_n1219# 0.25fF
+C2 a_n2017_n61# a_n1879_n1219# 0.16fF
+C3 a_n2017_n1317# a_n1731_n1219# 4.73fF
+C4 w_n2018_n202# a_n1731_n1219# 19.90fF
+C5 a_n2017_n61# a_n1731_n1219# 5.23fF
+C6 a_n1879_n1219# a_n1731_n1219# 19.29fF
+C7 w_n2018_n202# a_n2017_n1317# 0.16fF
+C8 a_n2017_n61# a_n2017_n1317# 2.88fF
+C9 a_n2017_n1317# a_n1879_n1219# 2.66fF
 C10 a_n1879_n1219# VSUBS 1.53fF
 C11 a_n2017_n1317# VSUBS 5.03fF
 C12 a_n1731_n1219# VSUBS 2.60fF
@@ -2956,7 +6704,7 @@
 C14 w_n2018_n202# VSUBS 37.43fF
 .ends
 
-.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref
+.subckt bias VSUBS vdd iref_0 iref_1 iref_2 iref_5 iref_6 iref_7 iref_8 iref_9 iref
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_5 VSUBS iref m1_20168_984# iref m1_20168_984#
 + vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_6 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219#
@@ -2979,57 +6727,57 @@
 + iref_3 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
 Xsky130_fd_pr__pfet_01v8_lvt_8P223X_4 VSUBS iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219#
 + iref_4 m1_20168_984# vdd sky130_fd_pr__pfet_01v8_lvt_8P223X
-C0 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
-C1 iref iref_2 -0.01fF
-C2 iref m1_20168_984# 0.07fF
-C3 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
-C4 vdd iref -0.07fF
-C5 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C6 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
-C7 iref iref_1 -0.02fF
-C8 iref iref_5 0.05fF
-C9 iref_2 iref_3 0.05fF
-C10 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# iref_3 0.24fF
-C11 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
-C12 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
-C13 iref iref_4 0.30fF
-C14 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
-C15 iref iref_8 -0.03fF
-C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# iref_5 0.24fF
-C17 iref_3 iref_4 0.05fF
-C18 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# iref_8 0.24fF
-C19 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# m1_20168_984# 0.01fF
-C20 vdd m1_20168_984# 0.25fF
-C21 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
-C22 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# 0.24fF
-C23 iref_0 iref_1 0.05fF
-C24 iref_2 iref_1 0.05fF
-C25 iref_9 iref_8 0.05fF
-C26 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
-C27 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
-C28 iref_7 iref_6 0.05fF
-C29 iref_5 iref_6 0.05fF
-C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# m1_20168_984# 0.54fF
-C31 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# -0.15fF
-C32 iref_7 iref_8 0.05fF
-C33 iref_9 iref -0.01fF
-C34 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C35 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
-C36 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
-C37 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
-C38 iref_4 VSUBS 1.17fF
-C39 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
-C40 iref_3 VSUBS 0.64fF
-C41 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
-C42 iref_2 VSUBS -1.26fF
-C43 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
-C44 iref_1 VSUBS -0.80fF
-C45 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
-C46 iref_0 VSUBS 1.88fF
-C47 iref VSUBS 32.42fF
-C48 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
-C49 m1_20168_984# VSUBS 56.92fF
-C50 vdd VSUBS 416.01fF
+C0 iref_4 iref_3 0.05fF
+C1 iref_5 iref_6 0.05fF
+C2 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# 0.24fF
+C3 iref_3 iref_2 0.05fF
+C4 iref_9 iref_8 0.05fF
+C5 iref_5 iref 0.05fF
+C6 iref_7 iref_6 0.05fF
+C7 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vdd 0.24fF
+C8 iref_7 sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C9 iref_2 iref_1 0.05fF
+C10 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# iref -0.15fF
+C11 iref_8 iref -0.03fF
+C12 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# iref_6 0.24fF
+C13 iref_3 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.24fF
+C14 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.01fF
+C15 iref_4 iref 0.30fF
+C16 sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vdd 0.24fF
+C17 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C18 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.01fF
+C19 m1_20168_984# iref 0.07fF
+C20 iref_2 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C21 m1_20168_984# vdd 0.25fF
+C22 iref iref_2 -0.01fF
+C23 iref_8 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# 0.24fF
+C24 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# 0.67fF
+C25 iref iref_1 -0.02fF
+C26 iref_8 iref_7 0.05fF
+C27 iref_0 iref_1 0.05fF
+C28 iref_5 sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# 0.24fF
+C29 iref sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# 0.02fF
+C30 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# iref_1 0.24fF
+C31 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vdd 0.24fF
+C32 iref_9 iref -0.01fF
+C33 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# m1_20168_984# -0.39fF
+C34 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# 0.24fF
+C35 m1_20168_984# sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# 0.54fF
+C36 vdd sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# 0.24fF
+C37 iref vdd -0.07fF
+C38 iref VSUBS 32.42fF
+C39 iref_4 VSUBS 1.17fF
+C40 sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# VSUBS 2.60fF
+C41 iref_3 VSUBS 0.64fF
+C42 sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# VSUBS 2.60fF
+C43 iref_2 VSUBS -1.26fF
+C44 sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# VSUBS 2.60fF
+C45 iref_1 VSUBS -0.80fF
+C46 sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# VSUBS 2.60fF
+C47 m1_20168_984# VSUBS 56.92fF
+C48 vdd VSUBS 416.01fF
+C49 iref_0 VSUBS 1.88fF
+C50 sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# VSUBS 2.60fF
 C51 iref_9 VSUBS -1.13fF
 C52 sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# VSUBS 2.60fF
 C53 iref_7 VSUBS -1.38fF
@@ -3057,13 +6805,13 @@
 X1 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X2 c1_n4209_n4150# m3_n4309_50# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
 X3 c1_110_n4150# m3_10_n4250# sky130_fd_pr__cap_mim_m3_1 l=2e+07u w=2e+07u
-C0 m3_10_n4250# c1_110_n4150# 81.11fF
-C1 m3_n4309_n4250# c1_n4209_n4150# 38.10fF
-C2 m3_10_n4250# m3_n4309_n4250# 1.75fF
-C3 m3_n4309_50# m3_n4309_n4250# 2.63fF
-C4 m3_n4309_50# c1_n4209_n4150# 38.10fF
-C5 m3_n4309_50# m3_10_n4250# 1.75fF
-C6 c1_110_n4150# c1_n4209_n4150# 1.32fF
+C0 c1_n4209_n4150# m3_n4309_n4250# 38.10fF
+C1 m3_n4309_50# m3_n4309_n4250# 2.63fF
+C2 c1_110_n4150# m3_10_n4250# 81.11fF
+C3 m3_n4309_50# m3_10_n4250# 1.75fF
+C4 m3_n4309_n4250# m3_10_n4250# 1.75fF
+C5 c1_n4209_n4150# c1_110_n4150# 1.32fF
+C6 c1_n4209_n4150# m3_n4309_50# 38.10fF
 C7 c1_110_n4150# VSUBS 0.12fF
 C8 c1_n4209_n4150# VSUBS 0.12fF
 C9 m3_n4309_n4250# VSUBS 8.68fF
@@ -3073,15 +6821,15 @@
 
 .subckt cap3_loop_filter VSUBS in out
 Xsky130_fd_pr__cap_mim_m3_1_WHJTNJ_0 VSUBS out out in in out sky130_fd_pr__cap_mim_m3_1_WHJTNJ
-C0 out in 3.21fF
+C0 in out 3.21fF
 C1 in VSUBS -8.91fF
 C2 out VSUBS 3.92fF
 .ends
 
 .subckt sky130_fd_pr__nfet_01v8_U2JGXT w_n226_n510# a_n118_n388# a_n88_n300# a_30_n300#
 X0 a_30_n300# a_n118_n388# a_n88_n300# w_n226_n510# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=3e+06u l=300000u
-C0 a_n118_n388# a_n88_n300# 0.11fF
-C1 a_n88_n300# a_30_n300# 0.61fF
+C0 a_30_n300# a_n88_n300# 0.61fF
+C1 a_n88_n300# a_n118_n388# 0.11fF
 C2 a_30_n300# w_n226_n510# 0.40fF
 C3 a_n88_n300# w_n226_n510# 0.40fF
 C4 a_n118_n388# w_n226_n510# 0.28fF
@@ -3095,9 +6843,9 @@
 Xres_loop_filter_0 vss res_loop_filter_2/out in res_loop_filter
 Xres_loop_filter_1 vss res_loop_filter_2/out vc_pex res_loop_filter
 Xres_loop_filter_2 vss res_loop_filter_2/out vc_pex res_loop_filter
-C0 vc_pex in 0.18fF
-C1 D0_cap in 0.07fF
-C2 cap3_loop_filter_0/in in 0.79fF
+C0 in cap3_loop_filter_0/in 0.79fF
+C1 in vc_pex 0.18fF
+C2 in D0_cap 0.07fF
 C3 vc_pex vss -38.13fF
 C4 res_loop_filter_2/out vss 8.49fF
 C5 D0_cap vss 0.04fF
@@ -3113,8 +6861,8 @@
 + iref_cp nDown Up charge_pump_0/w_1008_774# charge_pump
 Xloop_filter_v2_0 lf_vc DO_cap vco_vctrl vss loop_filter_v2
 Xdiv_by_2_0 vss vdd div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in out_by_2 n_out_by_2
-+ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
-+ n_out_div_2 div_by_2
++ out_buffer_div_2 out_to_div out_div_2 n_out_buffer_div_2 n_out_div_2 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_2
 Xbuffer_salida_0 buffer_salida_0/a_678_n100# out_to_pad out_to_buffer buffer_salida_0/a_3996_n100#
 + vss vdd buffer_salida
 Xring_osc_0 ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vco_vctrl ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd
@@ -3122,161 +6870,163 @@
 + ring_osc_0/csvco_branch_0/inverter_csvco_0/vss D0_vco ring_osc_0/csvco_branch_2/cap_vco_0/t
 + vco_out ring_osc
 Xring_osc_buffer_0 vss vco_out vdd out_first_buffer out_to_div out_to_buffer ring_osc_buffer
-Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/DFlipFlop_1/latch_diff_0/D
-+ n_out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_0/D div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
-+ vdd div_by_5_0/DFlipFlop_2/latch_diff_0/nD div_5_Q0 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in
-+ out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_1/nD
-+ out_div_by_5 div_by_5_0/DFlipFlop_3/latch_diff_0/nD div_5_nQ2 div_by_5_0/DFlipFlop_0/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_2/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_1/latch_diff_1/D div_5_Q1 div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/latch_diff_0/D
-+ div_by_5_0/DFlipFlop_1/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out
+Xdiv_by_5_0 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2
++ div_by_5_0/DFlipFlop_0/latch_diff_1/nD div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in
++ vdd vss div_5_Q0 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# div_by_5_0/DFlipFlop_3/latch_diff_0/D
++ div_5_nQ0 div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/DFlipFlop_1/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/latch_diff_0/D out_div_by_5 div_5_nQ2 div_5_Q1 div_by_5_0/DFlipFlop_2/latch_diff_1/nD
++ div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_1/latch_diff_1/D
++ div_by_5_0/DFlipFlop_2/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in
++ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368#
++ div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out div_by_5_0/DFlipFlop_0/D
 + div_by_5_0/DFlipFlop_3/latch_diff_1/nD div_by_5_0/DFlipFlop_0/latch_diff_1/D div_5_Q1_shift
-+ div_by_5_0/DFlipFlop_0/latch_diff_0/nD div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
-+ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
++ div_by_5_0/DFlipFlop_1/D div_by_5_0/DFlipFlop_2/nQ div_by_5_0/DFlipFlop_3/latch_diff_0/nD
++ div_by_5_0/DFlipFlop_2/latch_diff_0/D div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out
++ div_by_5_0/DFlipFlop_0/latch_diff_0/D div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392#
 + div_by_5_0/DFlipFlop_3/latch_diff_1/D div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368#
-+ div_by_5_0/DFlipFlop_1/latch_diff_0/nD div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
++ div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136#
 + div_by_5_0/DFlipFlop_0/Q div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125#
-+ div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136#
++ div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# div_by_5_0/DFlipFlop_2/latch_diff_0/nD
 + div_by_5
-Xpfd_cp_interface_0 vss pfd_cp_interface_0/inverter_cp_x1_2/in vdd pfd_cp_interface_0/inverter_cp_x1_0/out
+Xpfd_cp_interface_0 vss vdd pfd_cp_interface_0/inverter_cp_x1_0/out pfd_cp_interface_0/inverter_cp_x1_2/in
 + Down QA QB nDown Up nUp pfd_cp_interface
 XPFD_0 vss vdd QB QA in_ref out_div_by_5 pfd_reset PFD
-C0 n_out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out -0.11fF
-C1 out_to_buffer out_to_div 0.13fF
-C2 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# 0.03fF
-C3 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# out_by_2 -0.02fF
-C4 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vco_vctrl -0.36fF
-C5 nswitch vco_vctrl -0.06fF
-C6 div_by_5_0/DFlipFlop_3/latch_diff_0/nD n_out_by_2 0.11fF
-C7 Down iref_cp 0.09fF
-C8 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
-C9 D0_vco vdd 0.03fF
-C10 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
-C11 div_5_Q1 vco_vctrl 0.14fF
-C12 nDown biasp 0.26fF
-C13 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
-C14 Down nswitch 0.54fF
-C15 div_by_5_0/DFlipFlop_0/latch_diff_1/D out_by_2 0.33fF
-C16 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
-C17 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
-C18 div_5_Q1 out_by_2 0.42fF
-C19 n_out_by_2 div_5_Q1 1.04fF
-C20 Up biasp 0.26fF
-C21 div_by_5_0/DFlipFlop_0/D vco_vctrl -0.45fF
-C22 out_div_by_5 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# 0.18fF
-C23 n_out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/D 0.12fF
-C24 vco_vctrl vdd -1.02fF
-C25 pfd_cp_interface_0/inverter_cp_x1_2/in vdd 0.01fF
-C26 div_by_5_0/DFlipFlop_0/D out_by_2 0.35fF
-C27 n_out_by_2 div_by_5_0/DFlipFlop_0/D -1.48fF
-C28 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in out_by_2 -0.22fF
-C29 div_by_5_0/DFlipFlop_2/latch_diff_0/nD out_by_2 0.10fF
-C30 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
-C31 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
-C32 out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.23fF
-C33 n_out_by_2 div_by_5_0/DFlipFlop_2/nQ 0.10fF
-C34 out_by_2 vdd 0.97fF
-C35 vdd lf_vc 0.02fF
-C36 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
-C37 n_out_by_2 vdd 1.03fF
-C38 div_by_5_0/DFlipFlop_1/latch_diff_1/D out_by_2 0.23fF
-C39 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
-C40 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
-C41 nUp vdd 0.05fF
-C42 out_to_buffer vdd 0.07fF
-C43 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
-C44 nDown nswitch 0.76fF
-C45 div_by_5_0/DFlipFlop_3/latch_diff_0/D out_by_2 0.11fF
-C46 nUp pswitch 0.85fF
-C47 vco_vctrl out_by_2 0.53fF
-C48 div_5_nQ2 out_by_2 0.16fF
-C49 n_out_by_2 vco_vctrl 0.52fF
-C50 div_5_nQ2 n_out_by_2 0.10fF
-C51 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out out_to_div -0.12fF
-C52 div_by_5_0/DFlipFlop_1/latch_diff_1/nD out_by_2 0.09fF
-C53 out_div_by_5 div_5_Q1 0.01fF
-C54 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
-C55 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
-C56 nUp vco_vctrl 0.02fF
-C57 div_by_5_0/DFlipFlop_0/latch_diff_0/nD out_by_2 0.17fF
-C58 out_div_by_5 div_5_Q1_shift 0.05fF
-C59 div_by_5_0/DFlipFlop_3/latch_diff_1/D out_by_2 0.09fF
-C60 vco_vctrl div_5_Q0 0.48fF
-C61 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
-C62 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# out_by_2 0.10fF
-C63 div_by_5_0/DFlipFlop_2/latch_diff_0/D n_out_by_2 0.12fF
-C64 ring_osc_0/csvco_branch_2/cap_vco_0/t vdd 0.02fF
-C65 div_5_Q0 out_by_2 0.09fF
-C66 n_out_by_2 div_5_Q0 -0.12fF
-C67 out_div_by_5 vdd 0.28fF
-C68 nDown vdd 0.22fF
-C69 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
-C70 Up vdd 0.28fF
-C71 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
-C72 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
-C73 nDown pswitch 0.53fF
-C74 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
-C75 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
-C76 div_by_5_0/DFlipFlop_0/Q out_by_2 0.09fF
-C77 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C0 pswitch nDown 0.53fF
+C1 div_by_5_0/DFlipFlop_3/latch_diff_1/nD n_out_by_2 0.10fF
+C2 div_by_5_0/DFlipFlop_0/Q n_out_by_2 -0.23fF
+C3 div_5_nQ0 out_by_2 0.32fF
+C4 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.12fF
+C5 ring_osc_0/csvco_branch_2/vbp vdd 0.03fF
+C6 div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# out_div_by_5 0.18fF
+C7 n_out_by_2 div_by_5_0/DFlipFlop_2/D 0.19fF
+C8 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
+C9 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# vco_vctrl -0.11fF
+C10 div_by_5_0/DFlipFlop_0/latch_diff_1/nD n_out_by_2 0.33fF
+C11 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_1/D 0.33fF
+C12 vdd div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# 0.03fF
+C13 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.10fF
+C14 nDown nUp -0.09fF
+C15 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# n_out_by_2 0.01fF
+C16 vco_vctrl ring_osc_0/csvco_branch_0/inverter_csvco_0/vss 0.04fF
+C17 vdd nUp 0.05fF
+C18 Down nDown 2.55fF
+C19 div_by_5_0/DFlipFlop_0/latch_diff_0/D n_out_by_2 0.24fF
+C20 vdd Up 0.28fF
+C21 out_by_2 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in -0.22fF
+C22 pswitch nUp 0.85fF
+C23 nDown biasp 0.26fF
+C24 div_by_5_0/DFlipFlop_2/nQ n_out_by_2 0.10fF
+C25 vdd iref_cp 0.15fF
+C26 vdd ring_osc_0/csvco_branch_2/cap_vco_0/t 0.02fF
+C27 pswitch Up 1.98fF
+C28 div_5_Q1_shift out_div_by_5 0.05fF
+C29 nswitch nDown 0.76fF
+C30 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
+C31 out_by_2 vdd 0.97fF
+C32 div_by_5_0/DFlipFlop_0/D n_out_by_2 -1.48fF
+C33 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_1/D 0.09fF
+C34 div_5_Q1 n_out_by_2 1.04fF
+C35 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/nD 0.09fF
+C36 div_by_5_0/DFlipFlop_1/latch_diff_1/D n_out_by_2 0.10fF
+C37 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in -0.16fF
+C38 out_by_2 div_by_5_0/DFlipFlop_0/latch_diff_0/nD 0.17fF
+C39 Up nUp 2.72fF
+C40 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_143_136# -0.02fF
+C41 vco_vctrl n_out_by_2 0.52fF
+C42 vdd pfd_cp_interface_0/inverter_cp_x1_2/in 0.01fF
+C43 n_out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in -0.20fF
+C44 div_5_Q0 n_out_by_2 -0.12fF
+C45 vdd out_div_by_5 0.28fF
+C46 div_5_nQ2 n_out_by_2 0.10fF
+C47 div_by_5_0/DFlipFlop_1/latch_diff_0/D n_out_by_2 0.12fF
+C48 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
+C49 div_by_5_0/DFlipFlop_3/latch_diff_1/nD out_by_2 0.23fF
+C50 out_by_2 div_by_5_0/DFlipFlop_0/Q 0.09fF
+C51 vdd vco_vctrl -1.02fF
+C52 biasp nUp -0.17fF
+C53 out_by_2 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out -0.04fF
+C54 out_by_2 div_by_5_0/DFlipFlop_2/D 0.22fF
+C55 n_out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/D 0.12fF
+C56 Down iref_cp 0.09fF
+C57 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# n_out_by_2 0.03fF
+C58 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_143_136# n_out_by_2 0.02fF
+C59 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
+C60 out_to_buffer out_to_div 0.13fF
+C61 Up biasp 0.26fF
+C62 div_by_5_0/DFlipFlop_0/latch_diff_1/nD out_by_2 0.17fF
+C63 Down biasp 1.24fF
+C64 ring_osc_0/csvco_branch_2/vbp vco_vctrl 0.26fF
+C65 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_1/D 0.23fF
+C66 Down nswitch 0.54fF
+C67 div_5_nQ0 n_out_by_2 0.10fF
+C68 vco_vctrl div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# -0.36fF
+C69 out_to_div vdd 0.21fF
+C70 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
+C71 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
+C72 vco_vctrl nUp 0.02fF
+C73 div_by_5_0/DFlipFlop_0/latch_diff_1/D n_out_by_2 0.17fF
+C74 out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/D 0.11fF
+C75 out_by_2 div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# 0.10fF
+C76 div_by_5_0/DFlipFlop_2/nQ out_by_2 0.23fF
+C77 n_out_by_2 div_by_5_0/DFlipFlop_3/latch_diff_0/nD 0.11fF
 C78 vdd buffer_salida_0/a_678_n100# 0.24fF
-C79 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# n_out_by_2 -0.05fF
-C80 Up pswitch 1.98fF
-C81 div_by_5_0/DFlipFlop_2/latch_diff_1/nD out_by_2 0.09fF
-C82 div_by_5_0/DFlipFlop_2/latch_diff_1/nD n_out_by_2 0.24fF
-C83 out_by_2 div_5_nQ0 0.32fF
-C84 nUp nDown -0.09fF
-C85 n_out_by_2 div_5_nQ0 0.10fF
-C86 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_158_392# 0.01fF
-C87 nDown Down 2.55fF
-C88 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 0.27fF
-C89 nUp Up 2.72fF
-C90 out_to_div vdd 0.21fF
-C91 div_by_5_0/DFlipFlop_1/D out_by_2 0.38fF
-C92 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vdd 0.04fF
-C93 div_by_5_0/DFlipFlop_1/D n_out_by_2 0.22fF
-C94 div_by_5_0/DFlipFlop_2/latch_diff_1/D out_by_2 0.23fF
-C95 div_by_5_0/DFlipFlop_2/latch_diff_1/D n_out_by_2 0.10fF
-C96 vdd iref_cp 0.15fF
-C97 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.20fF
-C98 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in n_out_by_2 -0.51fF
-C99 QA vdd -0.04fF
-C100 out_to_buffer buffer_salida_0/a_678_n100# 0.22fF
-C101 nUp biasp -0.17fF
-C102 out_first_buffer ring_osc_0/csvco_branch_2/cap_vco_0/t 0.03fF
-C103 Down biasp 1.24fF
-C104 div_by_5_0/DFlipFlop_1/latch_diff_0/nD out_by_2 0.10fF
-C105 div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vdd 0.03fF
-C106 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.09fF
-C107 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out out_by_2 -0.04fF
+C79 vdd lf_vc 0.02fF
+C80 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out out_by_2 0.28fF
+C81 out_by_2 div_by_5_0/DFlipFlop_1/D 0.38fF
+C82 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out n_out_by_2 -0.11fF
+C83 out_by_2 div_by_5_0/DFlipFlop_0/D 0.35fF
+C84 out_by_2 div_5_Q1 0.42fF
+C85 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_1/D 0.23fF
+C86 out_by_2 div_by_5_0/DFlipFlop_2/latch_diff_0/nD 0.10fF
+C87 out_by_2 vco_vctrl 0.53fF
+C88 out_by_2 div_5_Q0 0.09fF
+C89 n_out_by_2 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in 0.27fF
+C90 vdd div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out 0.04fF
+C91 div_5_nQ2 out_by_2 0.16fF
+C92 n_out_by_2 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# -0.05fF
+C93 nswitch vco_vctrl -0.06fF
+C94 div_5_Q1 out_div_by_5 0.01fF
+C95 out_to_div div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out -0.12fF
+C96 out_to_buffer vdd 0.07fF
+C97 vdd n_out_by_2 1.03fF
+C98 div_by_5_0/DFlipFlop_3/latch_diff_1/D n_out_by_2 0.24fF
+C99 vco_vctrl div_by_5_0/DFlipFlop_0/D -0.45fF
+C100 div_by_5_0/DFlipFlop_1/latch_diff_1/nD n_out_by_2 0.24fF
+C101 vco_vctrl div_5_Q1 0.14fF
+C102 ring_osc_0/csvco_branch_2/cap_vco_0/t out_first_buffer 0.03fF
+C103 vdd nDown 0.22fF
+C104 out_by_2 div_by_5_0/DFlipFlop_1/latch_diff_0/nD 0.10fF
+C105 vdd QA -0.04fF
+C106 div_5_Q0 vco_vctrl 0.48fF
+C107 D0_vco vdd 0.03fF
 C108 PFD_0/and_pfd_0/a_656_410# vss 0.96fF
 C109 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vss 0.05fF
 C110 PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vss 0.07fF
 C111 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C112 PFD_0/dff_pfd_1/nor_pfd_2/B vss 1.40fF
 C113 PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C114 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
-C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C116 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C117 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
-C118 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C119 QB vss 4.46fF
-C120 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C114 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C115 PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C116 PFD_0/dff_pfd_1/nor_pfd_2/A vss 2.55fF
+C117 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C118 QB vss 4.46fF
+C119 PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C120 PFD_0/dff_pfd_1/nor_pfd_3/A vss 3.14fF
 C121 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C122 PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C123 out_div_by_5 vss -0.40fF
 C124 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C125 PFD_0/dff_pfd_0/nor_pfd_2/B vss 1.40fF
 C126 PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C127 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
-C128 pfd_reset vss 2.17fF
-C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C130 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
-C131 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
-C132 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
-C133 QA vss 4.31fF
-C134 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C127 pfd_reset vss 2.17fF
+C128 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C129 PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C130 PFD_0/dff_pfd_0/nor_pfd_2/A vss 2.55fF
+C131 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
+C132 QA vss 4.31fF
+C133 PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
+C134 PFD_0/dff_pfd_0/nor_pfd_3/A vss 3.14fF
 C135 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vss 0.03fF
 C136 PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vss 0.03fF
 C137 in_ref vss 1.19fF
@@ -3295,32 +7045,32 @@
 C150 div_by_5_0/DFlipFlop_3/latch_diff_1/nD vss 0.57fF
 C151 div_by_5_0/DFlipFlop_3/latch_diff_1/D vss -1.73fF
 C152 div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vss 0.57fF
-C153 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
-C154 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C153 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C154 div_by_5_0/DFlipFlop_3/latch_diff_0/D vss 0.96fF
 C155 div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C156 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
-C157 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
-C158 div_5_Q1 vss 4.28fF
-C159 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
-C160 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
-C161 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
-C162 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
-C163 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
-C164 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C165 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C166 div_by_5_0/DFlipFlop_2/D vss 3.13fF
-C167 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
-C168 div_5_nQ0 vss 0.59fF
-C169 div_5_Q0 vss 0.01fF
-C170 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
-C171 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
-C172 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
-C173 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
-C174 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
-C175 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C176 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
-C177 div_by_5_0/DFlipFlop_1/D vss 3.64fF
-C178 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C156 div_5_Q1 vss 4.28fF
+C157 div_by_5_0/DFlipFlop_3/latch_diff_0/nD vss 1.14fF
+C158 div_5_nQ0 vss 0.59fF
+C159 div_5_Q0 vss 0.01fF
+C160 div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vss 0.57fF
+C161 div_by_5_0/DFlipFlop_1/latch_diff_1/nD vss 0.57fF
+C162 div_by_5_0/DFlipFlop_1/latch_diff_1/D vss -1.73fF
+C163 div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vss 0.57fF
+C164 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C165 div_by_5_0/DFlipFlop_1/latch_diff_0/D vss 0.96fF
+C166 div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C167 div_by_5_0/DFlipFlop_1/D vss 3.64fF
+C168 div_by_5_0/DFlipFlop_1/latch_diff_0/nD vss 1.14fF
+C169 div_by_5_0/DFlipFlop_2/nQ vss 0.48fF
+C170 div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vss 0.57fF
+C171 div_by_5_0/DFlipFlop_2/latch_diff_1/nD vss 0.57fF
+C172 div_by_5_0/DFlipFlop_2/latch_diff_1/D vss -1.73fF
+C173 div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vss 0.57fF
+C174 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C175 div_by_5_0/DFlipFlop_2/latch_diff_0/D vss 0.96fF
+C176 div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
+C177 div_by_5_0/DFlipFlop_2/D vss 3.13fF
+C178 div_by_5_0/DFlipFlop_2/latch_diff_0/nD vss 1.14fF
 C179 div_5_nQ2 vss 1.24fF
 C180 div_by_5_0/DFlipFlop_0/Q vss -0.94fF
 C181 div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
@@ -3329,17 +7079,17 @@
 C184 div_by_5_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C185 div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
 C186 out_by_2 vss -4.51fF
-C187 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C188 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C187 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C188 div_by_5_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C189 div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C190 div_by_5_0/DFlipFlop_0/D vss 3.96fF
 C191 div_by_5_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
 C192 vdd vss 366.82fF
 C193 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vss 0.08fF
 C194 div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vss 0.40fF
-C195 out_to_buffer vss 1.57fF
+C195 out_first_buffer vss 2.88fF
 C196 out_to_div vss 4.46fF
-C197 out_first_buffer vss 2.88fF
+C197 out_to_buffer vss 1.57fF
 C198 ring_osc_0/csvco_branch_2/in vss 1.60fF
 C199 ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vss 0.16fF
 C200 ring_osc_0/csvco_branch_1/cap_vco_0/t vss 7.10fF
@@ -3354,22 +7104,22 @@
 C209 ring_osc_0/csvco_branch_0/cap_vco_0/t vss 7.10fF
 C210 ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vss 0.52fF
 C211 ring_osc_0/csvco_branch_2/vbp vss 0.38fF
-C212 out_to_pad vss 7.50fF
-C213 buffer_salida_0/a_3996_n100# vss 48.29fF
+C212 buffer_salida_0/a_3996_n100# vss 48.29fF
+C213 out_to_pad vss 7.50fF
 C214 buffer_salida_0/a_678_n100# vss 13.38fF
-C215 n_out_buffer_div_2 vss 1.63fF
-C216 out_buffer_div_2 vss 1.60fF
-C217 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
-C218 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
-C219 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
-C220 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C215 div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C216 div_by_2_0/DFlipFlop_0/CLK vss 0.31fF
+C217 div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.89fF
+C218 div_by_2_0/DFlipFlop_0/nCLK vss 1.03fF
+C219 out_buffer_div_2 vss 1.60fF
+C220 n_out_buffer_div_2 vss 1.63fF
 C221 out_div_2 vss -1.30fF
 C222 div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vss 0.57fF
 C223 div_by_2_0/DFlipFlop_0/latch_diff_1/nD vss 0.57fF
 C224 div_by_2_0/DFlipFlop_0/latch_diff_1/D vss -1.73fF
 C225 div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vss 0.57fF
-C226 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
-C227 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C226 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vss 1.86fF
+C227 div_by_2_0/DFlipFlop_0/latch_diff_0/D vss 0.96fF
 C228 div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vss 1.76fF
 C229 n_out_div_2 vss 1.95fF
 C230 div_by_2_0/DFlipFlop_0/latch_diff_0/nD vss 1.14fF
@@ -3391,8 +7141,8 @@
 + gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
 + gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
 + gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-+ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[7] io_analog[8] io_analog[9]
-+ io_analog[4] io_analog[6] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[4] io_analog[5] io_analog[6] io_analog[7]
++ io_analog[8] io_analog[9] io_clamp_high[0] io_clamp_high[2] io_clamp_low[0] io_clamp_low[2]
 + io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17]
 + io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25]
 + io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9]
@@ -3489,6 +7239,33 @@
 + wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30]
 + wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8]
 + wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xres_amp_top_0 vssa1 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in
++ vdda1 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# bias_0/iref_8
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out
++ bias_0/iref_6 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1
++ res_amp_top_0/res_amp_lin_prog_0/outn bias_0/iref_7 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828#
++ gpio_noesd[3] bias_0/iref_5 res_amp_top_0/res_amp_lin_prog_0/outp res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB io_analog[2]
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828#
++ io_analog[3] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1]
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out res_amp_top_0/res_amp_lin_prog_0/outp_cap
++ gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB
++ res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA io_analog[6]
++ gpio_noesd[5] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out gpio_noesd[6]
++ res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341#
++ res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in
++ gpio_noesd[2] io_analog[0] res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129#
++ io_analog[1] io_analog[4] res_amp_top_0/res_amp_sync_v2_0/rst res_amp_top
 Xtop_pll_v1_0 top_pll_v1_0/vco_vctrl vdda1 top_pll_v1_0/pswitch top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd
 + top_pll_v1_0/charge_pump_0/w_2544_775# top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp
 + top_pll_v1_0/biasp io_analog[10] top_pll_v1_0/Down vssa1 vssa1 gpio_noesd[7] top_pll_v1_0/buffer_salida_0/a_3996_n100#
@@ -3510,7 +7287,8 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_0[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 io_analog[5] bias
+Xbias_0 vssa1 vdda1 bias_0/iref_0 bias_0/iref_1 bias_0/iref_2 bias_0/iref_5 bias_0/iref_6
++ bias_0/iref_7 bias_0/iref_8 bias_0/iref_9 io_analog[5] bias
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[0] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[1] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_1[2] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
@@ -3533,8 +7311,6 @@
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[4] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[5] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[6] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[7] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
-Xsky130_fd_pr__cap_mim_m3_2_2Y8F6P_2[8] vssa1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2_2Y8F6P
 Xmimcap_decoup_1x5_2[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_2[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
@@ -3547,1099 +7323,1347 @@
 Xmimcap_decoup_1x5_5[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xmimcap_decoup_1x5_5[2] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[0] vssa1 vdda1 vssa1 mimcap_decoup_1x5
+Xmimcap_decoup_1x5_6[1] vssa1 vdda1 vssa1 mimcap_decoup_1x5
 Xtop_pll_v2_0 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd top_pll_v2_0/pswitch
 + vdda1 top_pll_v2_0/charge_pump_0/w_2544_775# top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp
 + top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd io_analog[10] top_pll_v2_0/vco_vctrl
 + top_pll_v2_0/Down vssa1 vssa1 gpio_noesd[7] bias_0/iref_1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd
 + top_pll_v2_0/out_to_div gpio_noesd[8] top_pll_v2_0/nDown top_pll_v2_0/biasp io_analog[8]
 + top_pll_v2_0/Up top_pll_v2_0/nUp top_pll_v2
-C0 io_clamp_high[2] io_analog[6] 0.53fF
-C1 vdda1 top_pll_v1_1/pswitch 0.48fF
-C2 top_pll_v2_0/biasp vdda1 0.03fF
-C3 vdda1 bias_0/iref_2 3.90fF
-C4 io_analog[10] gpio_noesd[7] 29.88fF
-C5 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
-C6 io_analog[7] bias_0/iref_2 13.22fF
-C7 vdda1 gpio_noesd[7] 120.83fF
-C8 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vdda1 0.17fF
-C9 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
-C10 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
-C11 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C12 bias_0/iref_1 vdda1 15.26fF
-C13 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
-C14 io_analog[10] vdda1 0.01fF
-C15 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
-C16 io_analog[7] bias_0/iref_1 13.22fF
-C17 io_clamp_high[0] io_analog[4] 0.53fF
-C18 top_pll_v2_0/nUp vdda1 0.01fF
-C19 gpio_noesd[7] top_pll_v1_0/vco_vctrl 0.05fF
-C20 top_pll_v1_1/charge_pump_0/w_1008_774# bias_0/iref_0 0.21fF
-C21 io_analog[7] vdda1 29.48fF
-C22 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
-C23 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
-C24 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
-C25 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
-C26 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
-C27 top_pll_v1_1/charge_pump_0/w_2544_775# bias_0/iref_0 0.21fF
-C28 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
-C29 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vdda1 1.01fF
-C30 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vdda1 0.12fF
-C31 gpio_noesd[8] gpio_noesd[7] 1.88fF
-C32 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
-C33 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vdda1 2.10fF
-C34 top_pll_v2_0/vco_vctrl gpio_noesd[7] 0.05fF
-C35 top_pll_v1_1/Up bias_0/iref_0 0.74fF
-C36 io_analog[10] gpio_noesd[8] 20.65fF
-C37 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
-C38 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdda1 0.17fF
-C39 io_clamp_low[2] io_analog[6] 0.53fF
-C40 top_pll_v1_1/nUp bias_0/iref_0 0.74fF
-C41 top_pll_v1_1/biasp bias_0/iref_0 3.13fF
-C42 gpio_noesd[8] vdda1 76.96fF
-C43 top_pll_v2_0/buffer_salida_0/a_3996_n100# vdda1 0.05fF
-C44 top_pll_v2_0/out_to_div gpio_noesd[7] 0.23fF
-C45 top_pll_v1_0/nUp bias_0/iref_2 0.70fF
-C46 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
-C47 top_pll_v2_0/vco_vctrl vdda1 0.59fF
-C48 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdda1 0.17fF
-C49 io_clamp_low[0] io_analog[4] 0.53fF
-C50 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vdda1 1.14fF
-C51 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
-C52 top_pll_v1_0/nUp vdda1 0.01fF
-C53 vdda1 bias_0/iref_0 15.18fF
-C54 top_pll_v2_0/pswitch vdda1 0.34fF
-C55 vdda1 top_pll_v1_0/pswitch 0.38fF
-C56 bias_0/iref_2 top_pll_v1_0/biasp 3.20fF
-C57 io_analog[10] top_pll_v1_0/QA 0.03fF
-C58 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vdda1 0.12fF
-C59 io_analog[5] m3_222594_702300# 0.53fF
-C60 io_analog[8] bias_0/iref_2 14.44fF
-C61 io_analog[9] bias_0/iref_2 14.44fF
-C62 top_pll_v1_1/out_to_div gpio_noesd[7] 0.15fF
-C63 top_pll_v1_1/nDown bias_0/iref_0 0.74fF
-C64 io_analog[5] m3_226242_702300# 0.53fF
-C65 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vdda1 0.12fF
-C66 top_pll_v1_1/Down bias_0/iref_0 1.08fF
-C67 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
-C68 vdda1 top_pll_v1_0/biasp 0.03fF
-C69 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
-C70 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C71 io_analog[8] vdda1 29.93fF
-C72 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
-C73 vdda1 io_analog[9] 30.05fF
-C74 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
-C75 io_in_3v3[0] vssa1 0.41fF
-C76 io_oeb[26] vssa1 0.61fF
-C77 io_in[0] vssa1 0.41fF
-C78 io_out[26] vssa1 0.61fF
-C79 io_out[0] vssa1 0.41fF
-C80 io_in[26] vssa1 0.61fF
-C81 io_oeb[0] vssa1 0.41fF
-C82 io_in_3v3[26] vssa1 0.61fF
-C83 io_in_3v3[1] vssa1 0.41fF
-C84 io_oeb[25] vssa1 0.61fF
-C85 io_in[1] vssa1 0.41fF
-C86 io_out[25] vssa1 0.61fF
-C87 io_out[1] vssa1 0.41fF
-C88 io_in[25] vssa1 0.61fF
-C89 io_oeb[1] vssa1 0.41fF
-C90 io_in_3v3[25] vssa1 0.61fF
-C91 io_in_3v3[2] vssa1 0.41fF
-C92 io_oeb[24] vssa1 0.61fF
-C93 io_in[2] vssa1 0.41fF
-C94 io_out[24] vssa1 0.61fF
-C95 io_out[2] vssa1 0.41fF
-C96 io_in[24] vssa1 0.61fF
-C97 io_oeb[2] vssa1 -0.20fF
-C98 io_in_3v3[3] vssa1 0.41fF
-C99 gpio_noesd[17] vssa1 0.61fF
-C100 io_in[3] vssa1 0.41fF
-C101 gpio_analog[17] vssa1 0.61fF
-C102 io_out[3] vssa1 0.41fF
-C103 io_oeb[3] vssa1 0.41fF
-C104 io_in_3v3[4] vssa1 0.41fF
-C105 io_in[4] vssa1 0.41fF
-C106 io_out[4] vssa1 0.41fF
-C107 io_oeb[4] vssa1 0.41fF
-C108 io_oeb[23] vssa1 0.61fF
-C109 io_out[23] vssa1 0.61fF
-C110 io_in[23] vssa1 0.61fF
-C111 io_in_3v3[23] vssa1 0.61fF
-C112 gpio_noesd[16] vssa1 0.61fF
-C113 io_in_3v3[5] vssa1 0.41fF
-C114 io_in[5] vssa1 -0.20fF
-C115 io_out[5] vssa1 0.41fF
-C116 io_oeb[5] vssa1 0.41fF
-C117 io_oeb[22] vssa1 0.61fF
-C118 io_out[22] vssa1 0.61fF
-C119 io_in[22] vssa1 0.61fF
-C120 io_in_3v3[22] vssa1 0.61fF
-C121 gpio_analog[15] vssa1 0.61fF
-C122 io_in_3v3[6] vssa1 -0.20fF
-C123 io_in[6] vssa1 0.41fF
-C124 io_out[6] vssa1 0.41fF
-C125 io_oeb[6] vssa1 0.41fF
-C126 io_oeb[21] vssa1 0.61fF
-C127 io_out[21] vssa1 0.61fF
-C128 io_in[21] vssa1 0.61fF
-C129 io_in_3v3[21] vssa1 0.61fF
-C130 gpio_noesd[14] vssa1 0.61fF
-C131 gpio_analog[14] vssa1 0.61fF
-C132 vssd2 vssa1 -5.19fF
-C133 vssd1 vssa1 1.13fF
-C134 vdda2 vssa1 -5.19fF
-C135 io_oeb[20] vssa1 0.61fF
-C136 io_out[20] vssa1 0.61fF
-C137 io_in[20] vssa1 0.61fF
-C138 io_in_3v3[20] vssa1 0.61fF
-C139 gpio_noesd[13] vssa1 0.61fF
-C140 gpio_analog[13] vssa1 0.61fF
-C141 gpio_analog[0] vssa1 0.41fF
-C142 gpio_noesd[0] vssa1 0.41fF
-C143 io_in_3v3[7] vssa1 0.41fF
-C144 io_in[7] vssa1 0.41fF
-C145 io_out[7] vssa1 0.41fF
-C146 io_oeb[7] vssa1 0.41fF
-C147 io_oeb[19] vssa1 0.61fF
-C148 io_out[19] vssa1 0.61fF
-C149 io_in[19] vssa1 0.61fF
-C150 io_in_3v3[19] vssa1 0.61fF
-C151 gpio_noesd[12] vssa1 0.61fF
-C152 gpio_analog[12] vssa1 0.61fF
-C153 gpio_analog[1] vssa1 0.41fF
-C154 gpio_noesd[1] vssa1 0.41fF
-C155 io_in_3v3[8] vssa1 0.41fF
-C156 io_in[8] vssa1 0.41fF
-C157 io_out[8] vssa1 -0.20fF
-C158 io_oeb[8] vssa1 0.41fF
-C159 io_oeb[18] vssa1 0.61fF
-C160 io_out[18] vssa1 0.61fF
-C161 io_in_3v3[18] vssa1 0.61fF
-C162 gpio_noesd[11] vssa1 0.61fF
-C163 gpio_analog[11] vssa1 0.61fF
-C164 gpio_analog[2] vssa1 0.41fF
-C165 gpio_noesd[2] vssa1 0.41fF
-C166 io_in_3v3[9] vssa1 0.41fF
-C167 io_in[9] vssa1 0.41fF
-C168 io_out[9] vssa1 0.41fF
-C169 io_oeb[9] vssa1 0.41fF
-C170 io_oeb[17] vssa1 0.61fF
-C171 io_in[17] vssa1 0.61fF
-C172 io_in_3v3[17] vssa1 0.61fF
-C173 gpio_noesd[10] vssa1 0.61fF
-C174 gpio_analog[10] vssa1 0.61fF
-C175 gpio_analog[3] vssa1 0.41fF
-C176 gpio_noesd[3] vssa1 0.41fF
-C177 io_in_3v3[10] vssa1 0.41fF
-C178 io_in[10] vssa1 0.41fF
-C179 io_out[10] vssa1 0.41fF
-C180 io_oeb[10] vssa1 0.41fF
-C181 io_out[16] vssa1 0.61fF
-C182 io_in[16] vssa1 0.61fF
-C183 io_in_3v3[16] vssa1 0.61fF
-C184 gpio_noesd[9] vssa1 0.61fF
-C185 gpio_analog[9] vssa1 0.61fF
-C186 gpio_analog[4] vssa1 0.41fF
-C187 gpio_noesd[4] vssa1 0.41fF
-C188 io_in_3v3[11] vssa1 0.41fF
-C189 io_in[11] vssa1 0.41fF
-C190 io_out[11] vssa1 0.41fF
-C191 io_oeb[11] vssa1 0.41fF
-C192 io_oeb[15] vssa1 0.61fF
-C193 io_out[15] vssa1 0.61fF
-C194 io_in[15] vssa1 0.61fF
-C195 io_in_3v3[15] vssa1 0.61fF
-C196 gpio_analog[5] vssa1 0.41fF
-C197 gpio_noesd[5] vssa1 0.41fF
-C198 io_in_3v3[12] vssa1 0.41fF
-C199 io_in[12] vssa1 0.41fF
-C200 io_out[12] vssa1 0.41fF
-C201 io_oeb[12] vssa1 0.41fF
-C202 gpio_analog[6] vssa1 0.60fF
-C203 gpio_noesd[6] vssa1 0.60fF
-C204 io_in_3v3[13] vssa1 0.60fF
-C205 io_in[13] vssa1 0.60fF
-C206 io_out[13] vssa1 0.60fF
-C207 io_oeb[13] vssa1 0.60fF
-C208 vccd1 vssa1 0.85fF
-C209 gpio_analog[8] vssa1 0.61fF
-C210 io_oeb[14] vssa1 0.61fF
-C211 io_out[14] vssa1 0.61fF
-C212 io_in[14] vssa1 0.61fF
-C213 io_in_3v3[14] vssa1 0.61fF
-C214 io_analog[0] vssa1 -6.01fF
-C215 io_analog[1] vssa1 0.76fF
-C216 vssa2 vssa1 1.66fF
-C217 vccd2 vssa1 0.91fF
-C218 io_analog[2] vssa1 -5.85fF
-C219 io_analog[3] vssa1 -5.74fF
-C220 io_analog[4] vssa1 -5.03fF
-C221 io_clamp_high[0] vssa1 -2.60fF
-C222 io_clamp_low[0] vssa1 0.82fF
-C223 io_analog[6] vssa1 -4.92fF
-C224 io_clamp_high[2] vssa1 0.66fF
-C225 io_clamp_low[2] vssa1 0.50fF
-C226 user_irq[2] vssa1 0.63fF
-C227 user_irq[1] vssa1 0.63fF
-C228 user_irq[0] vssa1 0.63fF
-C229 user_clock2 vssa1 0.63fF
-C230 la_oenb[127] vssa1 0.63fF
-C231 la_data_in[127] vssa1 0.63fF
-C232 la_oenb[126] vssa1 0.63fF
-C233 la_data_out[126] vssa1 0.63fF
-C234 la_data_in[126] vssa1 0.63fF
-C235 la_oenb[125] vssa1 0.63fF
-C236 la_data_out[125] vssa1 0.63fF
-C237 la_data_in[125] vssa1 0.63fF
-C238 la_oenb[124] vssa1 0.63fF
-C239 la_data_out[124] vssa1 0.63fF
-C240 la_data_in[124] vssa1 0.63fF
-C241 la_oenb[123] vssa1 0.63fF
-C242 la_data_out[123] vssa1 0.63fF
-C243 la_oenb[122] vssa1 0.63fF
-C244 la_data_out[122] vssa1 0.63fF
-C245 la_data_in[122] vssa1 0.63fF
-C246 la_oenb[121] vssa1 0.63fF
-C247 la_data_out[121] vssa1 0.63fF
-C248 la_data_in[121] vssa1 0.63fF
-C249 la_oenb[120] vssa1 0.63fF
-C250 la_data_out[120] vssa1 0.63fF
-C251 la_data_in[120] vssa1 0.63fF
-C252 la_oenb[119] vssa1 0.63fF
-C253 la_data_out[119] vssa1 0.63fF
-C254 la_data_in[119] vssa1 0.63fF
-C255 la_oenb[118] vssa1 0.63fF
-C256 la_data_out[118] vssa1 0.63fF
-C257 la_data_in[118] vssa1 0.63fF
-C258 la_oenb[117] vssa1 0.63fF
-C259 la_data_out[117] vssa1 0.63fF
-C260 la_data_in[117] vssa1 0.63fF
-C261 la_data_out[116] vssa1 0.63fF
-C262 la_data_in[116] vssa1 0.63fF
-C263 la_oenb[115] vssa1 0.63fF
-C264 la_data_out[115] vssa1 0.63fF
-C265 la_data_in[115] vssa1 0.63fF
-C266 la_oenb[114] vssa1 0.63fF
-C267 la_data_out[114] vssa1 0.63fF
-C268 la_data_in[114] vssa1 0.63fF
-C269 la_oenb[113] vssa1 0.63fF
-C270 la_data_out[113] vssa1 0.63fF
-C271 la_data_in[113] vssa1 0.63fF
-C272 la_oenb[112] vssa1 0.63fF
-C273 la_data_in[112] vssa1 0.63fF
-C274 la_oenb[111] vssa1 0.63fF
-C275 la_data_out[111] vssa1 0.63fF
-C276 la_data_in[111] vssa1 0.63fF
-C277 la_oenb[110] vssa1 0.63fF
-C278 la_data_out[110] vssa1 0.63fF
-C279 la_data_in[110] vssa1 0.63fF
-C280 la_oenb[109] vssa1 0.63fF
-C281 la_data_out[109] vssa1 0.63fF
-C282 la_data_in[109] vssa1 0.63fF
-C283 la_oenb[108] vssa1 0.63fF
-C284 la_data_out[108] vssa1 0.63fF
-C285 la_oenb[107] vssa1 0.63fF
-C286 la_data_out[107] vssa1 0.63fF
-C287 la_data_in[107] vssa1 0.63fF
-C288 la_oenb[106] vssa1 0.63fF
-C289 la_data_out[106] vssa1 0.63fF
-C290 la_oenb[105] vssa1 0.63fF
-C291 la_data_out[105] vssa1 0.63fF
-C292 la_data_in[105] vssa1 0.63fF
-C293 la_oenb[104] vssa1 0.63fF
-C294 la_data_out[104] vssa1 0.63fF
-C295 la_data_in[104] vssa1 0.63fF
-C296 la_oenb[103] vssa1 0.63fF
-C297 la_data_out[103] vssa1 0.63fF
-C298 la_data_in[103] vssa1 0.63fF
-C299 la_oenb[102] vssa1 0.63fF
-C300 la_data_out[102] vssa1 0.63fF
-C301 la_data_in[102] vssa1 0.63fF
-C302 la_data_out[101] vssa1 0.63fF
-C303 la_data_in[101] vssa1 0.63fF
-C304 la_oenb[100] vssa1 0.63fF
-C305 la_data_out[100] vssa1 0.63fF
-C306 la_data_in[100] vssa1 0.63fF
-C307 la_oenb[99] vssa1 0.63fF
-C308 la_data_out[99] vssa1 0.63fF
-C309 la_data_in[99] vssa1 0.63fF
-C310 la_oenb[98] vssa1 0.63fF
-C311 la_data_out[98] vssa1 0.63fF
-C312 la_data_in[98] vssa1 0.63fF
-C313 la_oenb[97] vssa1 0.63fF
-C314 la_data_in[97] vssa1 0.63fF
-C315 la_oenb[96] vssa1 0.63fF
-C316 la_data_out[96] vssa1 0.63fF
-C317 la_data_in[96] vssa1 0.63fF
-C318 la_oenb[95] vssa1 0.63fF
-C319 la_data_out[95] vssa1 0.63fF
-C320 la_data_in[95] vssa1 0.63fF
-C321 la_oenb[94] vssa1 0.63fF
-C322 la_data_out[94] vssa1 0.63fF
-C323 la_data_in[94] vssa1 0.63fF
-C324 la_oenb[93] vssa1 0.63fF
-C325 la_data_out[93] vssa1 0.63fF
-C326 la_oenb[92] vssa1 0.63fF
-C327 la_data_out[92] vssa1 0.63fF
-C328 la_data_in[92] vssa1 0.63fF
-C329 la_oenb[91] vssa1 0.63fF
-C330 la_data_out[91] vssa1 0.63fF
-C331 la_oenb[90] vssa1 0.63fF
-C332 la_data_out[90] vssa1 0.63fF
-C333 la_data_in[90] vssa1 0.63fF
-C334 la_oenb[89] vssa1 0.63fF
-C335 la_data_out[89] vssa1 0.63fF
-C336 la_data_in[89] vssa1 0.63fF
-C337 la_oenb[88] vssa1 0.63fF
-C338 la_data_out[88] vssa1 0.63fF
-C339 la_data_in[88] vssa1 0.63fF
-C340 la_oenb[87] vssa1 0.63fF
-C341 la_data_out[87] vssa1 0.63fF
-C342 la_data_in[87] vssa1 0.63fF
-C343 la_data_out[86] vssa1 0.63fF
-C344 la_data_in[86] vssa1 0.63fF
-C345 la_oenb[85] vssa1 0.63fF
-C346 la_data_out[85] vssa1 0.63fF
-C347 la_data_in[85] vssa1 0.63fF
-C348 la_oenb[84] vssa1 0.63fF
-C349 la_data_out[84] vssa1 0.63fF
-C350 la_data_in[84] vssa1 0.63fF
-C351 la_oenb[83] vssa1 0.63fF
-C352 la_data_out[83] vssa1 0.63fF
-C353 la_data_in[83] vssa1 0.63fF
-C354 la_oenb[82] vssa1 0.63fF
-C355 la_data_in[82] vssa1 0.63fF
-C356 la_oenb[81] vssa1 0.63fF
-C357 la_data_out[81] vssa1 0.63fF
-C358 la_data_in[81] vssa1 0.63fF
-C359 la_oenb[80] vssa1 0.63fF
-C360 la_data_out[80] vssa1 0.63fF
-C361 la_data_in[80] vssa1 0.63fF
-C362 la_oenb[79] vssa1 0.63fF
-C363 la_data_out[79] vssa1 0.63fF
-C364 la_data_in[79] vssa1 0.63fF
-C365 la_oenb[78] vssa1 0.63fF
-C366 la_data_out[78] vssa1 0.63fF
-C367 la_data_in[78] vssa1 0.63fF
-C368 la_oenb[77] vssa1 0.63fF
-C369 la_data_out[77] vssa1 0.63fF
-C370 la_data_in[77] vssa1 0.63fF
-C371 la_oenb[76] vssa1 0.63fF
-C372 la_data_out[76] vssa1 0.63fF
-C373 la_oenb[75] vssa1 0.63fF
-C374 la_data_out[75] vssa1 0.63fF
-C375 la_data_in[75] vssa1 0.63fF
-C376 la_oenb[74] vssa1 0.63fF
-C377 la_data_out[74] vssa1 0.63fF
-C378 la_data_in[74] vssa1 0.63fF
-C379 la_oenb[73] vssa1 0.63fF
-C380 la_data_out[73] vssa1 0.63fF
-C381 la_data_in[73] vssa1 0.63fF
-C382 la_oenb[72] vssa1 0.63fF
-C383 la_data_out[72] vssa1 0.63fF
-C384 la_data_in[72] vssa1 0.63fF
-C385 la_data_out[71] vssa1 0.63fF
-C386 la_data_in[71] vssa1 0.63fF
-C387 la_oenb[70] vssa1 0.63fF
-C388 la_data_out[70] vssa1 0.63fF
-C389 la_data_in[70] vssa1 0.63fF
-C390 la_oenb[69] vssa1 0.63fF
-C391 la_data_out[69] vssa1 0.63fF
-C392 la_data_in[69] vssa1 0.63fF
-C393 la_oenb[68] vssa1 0.63fF
-C394 la_data_out[68] vssa1 0.63fF
-C395 la_data_in[68] vssa1 0.63fF
-C396 la_oenb[67] vssa1 0.63fF
-C397 la_data_in[67] vssa1 0.63fF
-C398 la_oenb[66] vssa1 0.63fF
-C399 la_data_out[66] vssa1 0.63fF
-C400 la_data_in[66] vssa1 0.63fF
-C401 la_oenb[65] vssa1 0.63fF
-C402 la_data_out[65] vssa1 0.26fF
-C403 la_data_in[65] vssa1 0.63fF
-C404 la_oenb[64] vssa1 0.63fF
-C405 la_data_out[64] vssa1 0.63fF
-C406 la_data_in[64] vssa1 0.63fF
-C407 la_oenb[63] vssa1 0.63fF
-C408 la_data_out[63] vssa1 0.63fF
-C409 la_data_in[63] vssa1 0.63fF
-C410 la_oenb[62] vssa1 0.63fF
-C411 la_data_out[62] vssa1 0.63fF
-C412 la_data_in[62] vssa1 0.63fF
-C413 la_oenb[61] vssa1 0.63fF
-C414 la_data_out[61] vssa1 0.63fF
-C415 la_oenb[60] vssa1 0.63fF
-C416 la_data_out[60] vssa1 0.63fF
-C417 la_data_in[60] vssa1 0.63fF
-C418 la_oenb[59] vssa1 0.63fF
-C419 la_data_out[59] vssa1 0.63fF
-C420 la_data_in[59] vssa1 0.63fF
-C421 la_oenb[58] vssa1 0.63fF
-C422 la_data_out[58] vssa1 0.63fF
-C423 la_data_in[58] vssa1 0.63fF
-C424 la_oenb[57] vssa1 0.63fF
-C425 la_data_out[57] vssa1 0.63fF
-C426 la_data_in[57] vssa1 0.63fF
-C427 la_data_out[56] vssa1 0.63fF
-C428 la_data_in[56] vssa1 0.63fF
-C429 la_oenb[55] vssa1 0.63fF
-C430 la_data_out[55] vssa1 0.63fF
-C431 la_data_in[55] vssa1 0.63fF
-C432 la_oenb[54] vssa1 0.63fF
-C433 la_data_out[54] vssa1 0.63fF
-C434 la_data_in[54] vssa1 0.63fF
-C435 la_oenb[53] vssa1 0.63fF
-C436 la_data_out[53] vssa1 0.63fF
-C437 la_data_in[53] vssa1 0.63fF
-C438 la_oenb[52] vssa1 0.63fF
-C439 la_data_in[52] vssa1 0.63fF
-C440 la_oenb[51] vssa1 0.63fF
-C441 la_data_out[51] vssa1 0.63fF
-C442 la_data_in[51] vssa1 0.63fF
-C443 la_oenb[50] vssa1 0.63fF
-C444 la_data_in[50] vssa1 0.63fF
-C445 la_oenb[49] vssa1 0.63fF
-C446 la_data_out[49] vssa1 0.63fF
-C447 la_data_in[49] vssa1 0.63fF
-C448 la_oenb[48] vssa1 0.63fF
-C449 la_data_out[48] vssa1 0.63fF
-C450 la_data_in[48] vssa1 0.63fF
-C451 la_oenb[47] vssa1 0.63fF
-C452 la_data_out[47] vssa1 0.63fF
-C453 la_data_in[47] vssa1 0.63fF
-C454 la_oenb[46] vssa1 0.63fF
-C455 la_data_out[46] vssa1 0.63fF
-C456 la_oenb[45] vssa1 0.63fF
-C457 la_data_out[45] vssa1 0.63fF
-C458 la_data_in[45] vssa1 0.63fF
-C459 la_oenb[44] vssa1 0.63fF
-C460 la_data_out[44] vssa1 0.63fF
-C461 la_data_in[44] vssa1 0.63fF
-C462 la_oenb[43] vssa1 0.63fF
-C463 la_data_out[43] vssa1 0.63fF
-C464 la_data_in[43] vssa1 0.63fF
-C465 la_oenb[42] vssa1 0.63fF
-C466 la_data_out[42] vssa1 0.63fF
-C467 la_data_in[42] vssa1 0.63fF
-C468 la_data_out[41] vssa1 0.63fF
-C469 la_data_in[41] vssa1 0.63fF
-C470 la_oenb[40] vssa1 0.63fF
-C471 la_data_out[40] vssa1 0.63fF
-C472 la_data_in[40] vssa1 0.63fF
-C473 la_oenb[39] vssa1 0.63fF
-C474 la_data_out[39] vssa1 0.63fF
-C475 la_data_in[39] vssa1 0.63fF
-C476 la_oenb[38] vssa1 0.63fF
-C477 la_data_out[38] vssa1 0.63fF
-C478 la_data_in[38] vssa1 0.63fF
-C479 la_oenb[37] vssa1 0.63fF
-C480 la_data_out[37] vssa1 0.26fF
-C481 la_data_in[37] vssa1 0.63fF
-C482 la_oenb[36] vssa1 0.63fF
-C483 la_data_out[36] vssa1 0.63fF
-C484 la_data_in[36] vssa1 0.63fF
-C485 la_oenb[35] vssa1 0.63fF
-C486 la_data_in[35] vssa1 0.63fF
-C487 la_oenb[34] vssa1 0.63fF
-C488 la_data_out[34] vssa1 0.63fF
-C489 la_data_in[34] vssa1 0.63fF
-C490 la_oenb[33] vssa1 0.63fF
-C491 la_data_out[33] vssa1 0.63fF
-C492 la_data_in[33] vssa1 0.63fF
-C493 la_oenb[32] vssa1 0.63fF
-C494 la_data_out[32] vssa1 0.63fF
-C495 la_data_in[32] vssa1 0.63fF
-C496 la_oenb[31] vssa1 0.63fF
-C497 la_data_out[31] vssa1 0.63fF
-C498 la_oenb[30] vssa1 0.63fF
-C499 la_data_out[30] vssa1 0.63fF
-C500 la_data_in[30] vssa1 0.63fF
-C501 la_oenb[29] vssa1 0.63fF
-C502 la_data_out[29] vssa1 0.63fF
-C503 la_data_in[29] vssa1 0.63fF
-C504 la_oenb[28] vssa1 0.63fF
-C505 la_data_out[28] vssa1 0.63fF
-C506 la_data_in[28] vssa1 0.63fF
-C507 la_oenb[27] vssa1 0.63fF
-C508 la_data_out[27] vssa1 0.63fF
-C509 la_data_in[27] vssa1 0.63fF
-C510 la_data_out[26] vssa1 0.63fF
-C511 la_data_in[26] vssa1 0.63fF
-C512 la_oenb[25] vssa1 0.63fF
-C513 la_data_out[25] vssa1 0.63fF
-C514 la_data_in[25] vssa1 0.63fF
-C515 la_oenb[24] vssa1 0.63fF
-C516 la_data_out[24] vssa1 0.63fF
-C517 la_data_in[24] vssa1 0.63fF
-C518 la_oenb[23] vssa1 0.63fF
-C519 la_data_out[23] vssa1 0.63fF
-C520 la_data_in[23] vssa1 0.63fF
-C521 la_oenb[22] vssa1 0.63fF
-C522 la_data_out[22] vssa1 0.63fF
-C523 la_data_in[22] vssa1 0.63fF
-C524 la_oenb[21] vssa1 0.63fF
-C525 la_data_out[21] vssa1 0.63fF
-C526 la_data_in[21] vssa1 0.63fF
-C527 la_oenb[20] vssa1 0.63fF
-C528 la_data_in[20] vssa1 0.63fF
-C529 la_oenb[19] vssa1 0.63fF
-C530 la_data_out[19] vssa1 0.63fF
-C531 la_data_in[19] vssa1 0.63fF
-C532 la_oenb[18] vssa1 0.63fF
-C533 la_data_out[18] vssa1 0.63fF
-C534 la_data_in[18] vssa1 0.63fF
-C535 la_oenb[17] vssa1 0.63fF
-C536 la_data_out[17] vssa1 0.63fF
-C537 la_data_in[17] vssa1 0.63fF
-C538 la_oenb[16] vssa1 0.63fF
-C539 la_data_out[16] vssa1 0.63fF
-C540 la_oenb[15] vssa1 0.63fF
-C541 la_data_out[15] vssa1 0.63fF
-C542 la_data_in[15] vssa1 0.63fF
-C543 la_oenb[14] vssa1 0.63fF
-C544 la_data_out[14] vssa1 0.63fF
-C545 la_data_in[14] vssa1 0.63fF
-C546 la_oenb[13] vssa1 0.63fF
-C547 la_data_out[13] vssa1 0.63fF
-C548 la_data_in[13] vssa1 0.63fF
-C549 la_oenb[12] vssa1 0.63fF
-C550 la_data_out[12] vssa1 0.63fF
-C551 la_data_in[12] vssa1 0.63fF
-C552 la_data_out[11] vssa1 0.63fF
-C553 la_data_in[11] vssa1 0.63fF
-C554 la_oenb[10] vssa1 0.63fF
-C555 la_data_out[10] vssa1 0.63fF
-C556 la_data_in[10] vssa1 0.63fF
-C557 la_data_out[9] vssa1 0.63fF
-C558 la_data_in[9] vssa1 0.63fF
-C559 la_oenb[8] vssa1 0.63fF
-C560 la_data_out[8] vssa1 0.63fF
-C561 la_data_in[8] vssa1 0.63fF
-C562 la_oenb[7] vssa1 0.63fF
-C563 la_data_out[7] vssa1 0.63fF
-C564 la_data_in[7] vssa1 0.63fF
-C565 la_oenb[6] vssa1 0.63fF
-C566 la_data_out[6] vssa1 0.63fF
-C567 la_data_in[6] vssa1 0.63fF
-C568 la_oenb[5] vssa1 0.63fF
-C569 la_data_in[5] vssa1 0.63fF
-C570 la_oenb[4] vssa1 0.63fF
-C571 la_data_out[4] vssa1 0.63fF
-C572 la_data_in[4] vssa1 0.63fF
-C573 la_oenb[3] vssa1 0.63fF
-C574 la_data_out[3] vssa1 0.63fF
-C575 la_data_in[3] vssa1 0.63fF
-C576 la_oenb[2] vssa1 0.63fF
-C577 la_data_out[2] vssa1 0.63fF
-C578 la_data_in[2] vssa1 0.63fF
-C579 la_oenb[1] vssa1 0.63fF
-C580 la_data_out[1] vssa1 0.63fF
-C581 la_oenb[0] vssa1 0.63fF
-C582 la_data_out[0] vssa1 0.63fF
-C583 la_data_in[0] vssa1 0.63fF
-C584 wbs_dat_o[31] vssa1 0.63fF
-C585 wbs_dat_i[31] vssa1 0.63fF
-C586 wbs_adr_i[31] vssa1 0.63fF
-C587 wbs_dat_o[30] vssa1 0.63fF
-C588 wbs_dat_i[30] vssa1 0.63fF
-C589 wbs_adr_i[30] vssa1 0.63fF
-C590 wbs_dat_o[29] vssa1 0.63fF
-C591 wbs_dat_i[29] vssa1 0.63fF
-C592 wbs_adr_i[29] vssa1 0.63fF
-C593 wbs_dat_i[28] vssa1 0.63fF
-C594 wbs_adr_i[28] vssa1 0.63fF
-C595 wbs_dat_o[27] vssa1 0.63fF
-C596 wbs_dat_i[27] vssa1 0.63fF
-C597 wbs_adr_i[27] vssa1 0.63fF
-C598 wbs_dat_i[26] vssa1 0.63fF
-C599 wbs_adr_i[26] vssa1 0.63fF
-C600 wbs_dat_o[25] vssa1 0.63fF
-C601 wbs_dat_i[25] vssa1 0.63fF
-C602 wbs_adr_i[25] vssa1 0.63fF
-C603 wbs_dat_o[24] vssa1 0.63fF
-C604 wbs_dat_i[24] vssa1 0.63fF
-C605 wbs_adr_i[24] vssa1 0.63fF
-C606 wbs_dat_o[23] vssa1 0.63fF
-C607 wbs_dat_i[23] vssa1 0.63fF
-C608 wbs_adr_i[23] vssa1 0.63fF
-C609 wbs_dat_o[22] vssa1 0.63fF
-C610 wbs_adr_i[22] vssa1 0.63fF
-C611 wbs_dat_o[21] vssa1 0.63fF
-C612 wbs_dat_i[21] vssa1 0.63fF
-C613 wbs_adr_i[21] vssa1 0.63fF
-C614 wbs_dat_o[20] vssa1 0.63fF
-C615 wbs_dat_i[20] vssa1 0.63fF
-C616 wbs_adr_i[20] vssa1 0.63fF
-C617 wbs_dat_o[19] vssa1 0.63fF
-C618 wbs_dat_i[19] vssa1 0.63fF
-C619 wbs_adr_i[19] vssa1 0.63fF
-C620 wbs_dat_o[18] vssa1 0.63fF
-C621 wbs_dat_i[18] vssa1 0.63fF
-C622 wbs_dat_o[17] vssa1 0.63fF
-C623 wbs_dat_i[17] vssa1 0.63fF
-C624 wbs_adr_i[17] vssa1 0.63fF
-C625 wbs_dat_o[16] vssa1 0.63fF
-C626 wbs_dat_i[16] vssa1 0.63fF
-C627 wbs_adr_i[16] vssa1 0.63fF
-C628 wbs_dat_o[15] vssa1 0.63fF
-C629 wbs_dat_i[15] vssa1 0.63fF
-C630 wbs_adr_i[15] vssa1 0.63fF
-C631 wbs_dat_o[14] vssa1 0.63fF
-C632 wbs_dat_i[14] vssa1 0.63fF
-C633 wbs_adr_i[14] vssa1 0.63fF
-C634 wbs_dat_o[13] vssa1 0.63fF
-C635 wbs_dat_i[13] vssa1 0.63fF
-C636 wbs_adr_i[13] vssa1 0.63fF
-C637 wbs_dat_o[12] vssa1 0.63fF
-C638 wbs_dat_i[12] vssa1 0.63fF
-C639 wbs_adr_i[12] vssa1 0.63fF
-C640 wbs_dat_i[11] vssa1 0.63fF
-C641 wbs_adr_i[11] vssa1 0.63fF
-C642 wbs_dat_o[10] vssa1 0.63fF
-C643 wbs_dat_i[10] vssa1 0.63fF
-C644 wbs_adr_i[10] vssa1 0.63fF
-C645 wbs_dat_o[9] vssa1 0.63fF
-C646 wbs_dat_i[9] vssa1 0.63fF
-C647 wbs_adr_i[9] vssa1 0.63fF
-C648 wbs_dat_o[8] vssa1 0.63fF
-C649 wbs_dat_i[8] vssa1 0.63fF
-C650 wbs_adr_i[8] vssa1 0.63fF
-C651 wbs_dat_o[7] vssa1 0.63fF
-C652 wbs_adr_i[7] vssa1 0.63fF
-C653 wbs_dat_o[6] vssa1 0.63fF
-C654 wbs_dat_i[6] vssa1 0.63fF
-C655 wbs_adr_i[6] vssa1 0.63fF
-C656 wbs_dat_o[5] vssa1 0.63fF
-C657 wbs_dat_i[5] vssa1 0.63fF
-C658 wbs_adr_i[5] vssa1 0.63fF
-C659 wbs_dat_o[4] vssa1 0.63fF
-C660 wbs_dat_i[4] vssa1 0.63fF
-C661 wbs_adr_i[4] vssa1 0.63fF
-C662 wbs_sel_i[3] vssa1 0.63fF
-C663 wbs_dat_o[3] vssa1 0.63fF
-C664 wbs_adr_i[3] vssa1 0.63fF
-C665 wbs_sel_i[2] vssa1 0.63fF
-C666 wbs_dat_o[2] vssa1 0.63fF
-C667 wbs_dat_i[2] vssa1 0.63fF
-C668 wbs_adr_i[2] vssa1 0.63fF
-C669 wbs_dat_o[1] vssa1 0.63fF
-C670 wbs_dat_i[1] vssa1 0.63fF
-C671 wbs_adr_i[1] vssa1 0.63fF
-C672 wbs_sel_i[0] vssa1 0.63fF
-C673 wbs_dat_o[0] vssa1 0.63fF
-C674 wbs_dat_i[0] vssa1 0.63fF
-C675 wbs_adr_i[0] vssa1 0.63fF
-C676 wbs_we_i vssa1 0.63fF
-C677 wbs_stb_i vssa1 0.63fF
-C678 wbs_cyc_i vssa1 0.63fF
-C679 wbs_ack_o vssa1 0.63fF
-C680 wb_rst_i vssa1 0.63fF
-C681 m3_226242_702300# vssa1 -1.31fF $ **FLOATING
-C682 m3_222594_702300# vssa1 0.55fF $ **FLOATING
-C683 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C684 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C685 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C686 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C687 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C688 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C689 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C690 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C691 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C692 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C693 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C694 top_pll_v2_0/QB vssa1 4.35fF
-C695 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C696 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C697 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C698 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
-C699 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C700 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C701 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C702 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C703 top_pll_v2_0/pfd_reset vssa1 2.17fF
-C704 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C705 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C706 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C707 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C708 top_pll_v2_0/QA vssa1 4.22fF
-C709 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C710 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C711 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C712 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C713 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C714 top_pll_v2_0/nUp vssa1 5.39fF
-C715 top_pll_v2_0/Up vssa1 1.85fF
-C716 top_pll_v2_0/Down vssa1 6.19fF
-C717 top_pll_v2_0/nDown vssa1 -3.53fF
-C718 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C719 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C720 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C721 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C722 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
-C723 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C724 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C725 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C726 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C727 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C728 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C729 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C730 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C731 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C732 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
-C733 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C734 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C735 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C736 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C737 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C738 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C739 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C740 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C741 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C742 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
-C743 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
-C744 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C745 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C746 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C747 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C748 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C749 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C750 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C751 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C752 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C753 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
-C754 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C755 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C756 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
-C757 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C758 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C759 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C760 top_pll_v2_0/out_by_2 vssa1 -5.01fF
-C761 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C762 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C763 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C764 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C765 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C766 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C767 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C768 top_pll_v2_0/out_to_buffer vssa1 1.54fF
-C769 top_pll_v2_0/out_to_div vssa1 4.23fF
-C770 top_pll_v2_0/out_first_buffer vssa1 2.88fF
-C771 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C772 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C773 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C774 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C775 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C776 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C777 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C778 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C779 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C780 top_pll_v2_0/vco_out vssa1 1.01fF
-C781 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C782 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C783 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C784 io_analog[8] vssa1 13.78fF
-C785 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C786 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C787 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
-C788 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
-C789 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C790 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C791 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C792 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C793 top_pll_v2_0/out_div_2 vssa1 -1.30fF
-C794 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C795 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C796 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C797 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C798 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C799 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C800 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C801 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
-C802 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C803 top_pll_v2_0/lf_vc vssa1 -59.89fF
-C804 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
-C805 gpio_noesd[8] vssa1 210.79fF
-C806 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
-C807 top_pll_v2_0/nswitch vssa1 3.73fF
-C808 top_pll_v2_0/biasp vssa1 5.44fF
-C809 bias_0/iref_1 vssa1 -93.46fF
-C810 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
-C811 top_pll_v2_0/pswitch vssa1 3.57fF
-C812 bias_0/iref_4 vssa1 1.17fF
-C813 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
-C814 bias_0/iref_3 vssa1 0.64fF
-C815 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
-C816 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
-C817 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
-C818 io_analog[5] vssa1 33.29fF
-C819 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
-C820 bias_0/m1_20168_984# vssa1 56.92fF
-C821 bias_0/iref_9 vssa1 -1.13fF
-C822 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
-C823 bias_0/iref_7 vssa1 -1.38fF
-C824 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
-C825 bias_0/iref_8 vssa1 -1.19fF
-C826 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
-C827 bias_0/iref_6 vssa1 -1.00fF
-C828 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
-C829 bias_0/iref_5 vssa1 1.40fF
-C830 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
-C831 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C832 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C833 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C834 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C835 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C836 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C837 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C838 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C839 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C840 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C841 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C842 top_pll_v1_1/QB vssa1 4.35fF
-C843 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C844 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C845 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C846 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
-C847 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C848 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C849 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C850 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C851 top_pll_v1_1/pfd_reset vssa1 2.17fF
-C852 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C853 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C854 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C855 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C856 top_pll_v1_1/QA vssa1 4.22fF
-C857 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C858 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C859 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C860 io_analog[10] vssa1 503.33fF
-C861 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C862 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C863 top_pll_v1_1/nUp vssa1 5.39fF
-C864 top_pll_v1_1/Up vssa1 1.85fF
-C865 top_pll_v1_1/Down vssa1 6.19fF
-C866 top_pll_v1_1/nDown vssa1 -3.53fF
-C867 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C868 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C869 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C870 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C871 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
-C872 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C873 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C874 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C875 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C876 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C877 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C878 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C879 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C880 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C881 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
-C882 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C883 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C884 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C885 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C886 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C887 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C888 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C889 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C890 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C891 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
-C892 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
-C893 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C894 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C895 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C896 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C897 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C898 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C899 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C900 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C901 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C902 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
-C903 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C904 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C905 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
-C906 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C907 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C908 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C909 top_pll_v1_1/out_by_2 vssa1 -5.01fF
-C910 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C911 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C912 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C913 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C914 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C915 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C916 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C917 top_pll_v1_1/out_to_buffer vssa1 1.54fF
-C918 top_pll_v1_1/out_to_div vssa1 4.23fF
-C919 top_pll_v1_1/out_first_buffer vssa1 2.88fF
-C920 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C921 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C922 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C923 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C924 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C925 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C926 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C927 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C928 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C929 top_pll_v1_1/vco_out vssa1 1.01fF
-C930 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C931 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C932 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C933 io_analog[7] vssa1 24.61fF
-C934 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
-C935 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C936 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
-C937 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
-C938 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C939 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C940 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C941 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C942 top_pll_v1_1/out_div_2 vssa1 -1.30fF
-C943 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C944 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C945 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C946 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C947 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C948 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C949 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C950 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
-C951 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C952 top_pll_v1_1/nswitch vssa1 3.73fF
-C953 top_pll_v1_1/biasp vssa1 5.44fF
-C954 bias_0/iref_0 vssa1 -81.35fF
-C955 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
-C956 top_pll_v1_1/pswitch vssa1 3.57fF
-C957 top_pll_v1_1/lf_vc vssa1 -59.89fF
-C958 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
-C959 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
-C960 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
-C961 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
-C962 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C963 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
-C964 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C965 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
-C966 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C967 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C968 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
-C969 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C970 top_pll_v1_0/QB vssa1 4.35fF
-C971 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C972 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C973 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C974 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
-C975 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C976 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
-C977 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C978 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
-C979 top_pll_v1_0/pfd_reset vssa1 2.17fF
-C980 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C981 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C982 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
-C983 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C984 top_pll_v1_0/QA vssa1 4.22fF
-C985 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C986 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
-C987 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
-C988 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
-C989 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
-C990 top_pll_v1_0/nUp vssa1 5.39fF
-C991 top_pll_v1_0/Up vssa1 1.85fF
-C992 top_pll_v1_0/Down vssa1 6.19fF
-C993 top_pll_v1_0/nDown vssa1 -3.53fF
-C994 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
-C995 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
-C996 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
-C997 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
-C998 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
-C999 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1000 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
-C1001 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
-C1002 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1003 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
-C1004 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1005 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1006 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
-C1007 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
-C1008 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
-C1009 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1010 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
-C1011 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
-C1012 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1013 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
-C1014 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1015 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1016 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
-C1017 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
-C1018 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
-C1019 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
-C1020 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1021 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
-C1022 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
-C1023 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1024 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
-C1025 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1026 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1027 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
-C1028 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
-C1029 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
-C1030 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
-C1031 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1032 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
-C1033 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1034 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1035 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1036 top_pll_v1_0/out_by_2 vssa1 -5.01fF
-C1037 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1038 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1039 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1040 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
-C1041 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1042 vdda1 vssa1 6838.97fF
-C1043 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
-C1044 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
-C1045 top_pll_v1_0/out_to_buffer vssa1 1.54fF
-C1046 top_pll_v1_0/out_to_div vssa1 4.23fF
-C1047 top_pll_v1_0/out_first_buffer vssa1 2.88fF
-C1048 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
-C1049 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
-C1050 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
-C1051 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
-C1052 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
-C1053 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
-C1054 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
-C1055 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
-C1056 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
-C1057 top_pll_v1_0/vco_out vssa1 1.01fF
-C1058 gpio_noesd[7] vssa1 272.21fF
-C1059 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
-C1060 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
-C1061 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
-C1062 io_analog[9] vssa1 7.89fF
-C1063 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
-C1064 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
-C1065 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
-C1066 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
-C1067 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
-C1068 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1069 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1070 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
-C1071 top_pll_v1_0/out_div_2 vssa1 -1.30fF
-C1072 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
-C1073 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
-C1074 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
-C1075 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
-C1076 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
-C1077 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
-C1078 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
-C1079 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
-C1080 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
-C1081 top_pll_v1_0/nswitch vssa1 3.73fF
-C1082 top_pll_v1_0/biasp vssa1 5.44fF
-C1083 bias_0/iref_2 vssa1 -186.53fF
-C1084 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
-C1085 top_pll_v1_0/pswitch vssa1 3.57fF
-C1086 top_pll_v1_0/lf_vc vssa1 -59.89fF
-C1087 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C0 bias_0/iref_7 bias_0/iref_5 10.35fF
+C1 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out 0.21fF
+C2 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/clk 0.39fF
+C3 io_analog[4] bias_0/iref_9 15.97fF
+C4 bias_0/iref_8 bias_0/iref_7 13.23fF
+C5 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp 1.14fF
+C6 bias_0/iref_7 bias_0/iref_6 17.40fF
+C7 io_analog[10] gpio_noesd[8] 20.65fF
+C8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_7 0.40fF
+C9 bias_0/iref_1 top_pll_v2_0/nUp 0.22fF
+C10 vdda1 io_analog[1] 76.56fF
+C11 vdda1 gpio_noesd[5] 124.75fF
+C12 io_analog[5] m3_222594_702300# 0.53fF
+C13 io_analog[3] gpio_noesd[5] 0.12fF
+C14 vdda1 top_pll_v1_0/nUp 0.01fF
+C15 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.72fF
+C16 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in 0.18fF
+C17 vdda1 bias_0/iref_2 3.90fF
+C18 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# gpio_noesd[5] 0.16fF
+C19 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_8 0.37fF
+C20 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 gpio_noesd[5] 0.26fF
+C21 bias_0/iref_1 top_pll_v2_0/Up 0.54fF
+C22 vdda1 top_pll_v1_0/pswitch 0.38fF
+C23 vdda1 bias_0/iref_5 30.67fF
+C24 vdda1 gpio_noesd[3] 120.88fF
+C25 vdda1 bias_0/iref_8 31.37fF
+C26 gpio_noesd[6] gpio_noesd[5] 0.05fF
+C27 bias_0/iref_2 io_analog[7] 13.22fF
+C28 vdda1 bias_0/iref_6 29.75fF
+C29 io_analog[3] bias_0/iref_5 13.88fF
+C30 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b gpio_noesd[1] 0.23fF
+C31 bias_0/iref_8 io_analog[3] 13.88fF
+C32 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outp 0.61fF
+C33 io_analog[3] bias_0/iref_6 13.88fF
+C34 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.78fF
+C35 top_pll_v1_0/charge_pump_0/w_2544_775# bias_0/iref_2 0.02fF
+C36 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_7 0.45fF
+C37 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in -0.70fF
+C38 vdda1 top_pll_v1_0/vco_vctrl 0.43fF
+C39 gpio_noesd[4] vdda1 117.64fF
+C40 vdda1 top_pll_v2_0/pswitch 0.34fF
+C41 gpio_noesd[4] io_analog[3] -0.78fF
+C42 vdda1 io_analog[9] 30.05fF
+C43 gpio_noesd[2] gpio_noesd[1] 0.30fF
+C44 bias_0/iref_0 top_pll_v1_1/nDown 0.74fF
+C45 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.22fF
+C46 top_pll_v1_0/QA io_analog[10] 0.03fF
+C47 io_analog[6] bias_0/iref_1 13.22fF
+C48 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out gpio_noesd[1] 0.21fF
+C49 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 -0.05fF
+C50 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA 0.49fF
+C51 io_analog[4] io_clamp_low[0] 0.53fF
+C52 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.17fF
+C53 io_analog[6] bias_0/iref_0 6.93fF
+C54 res_amp_top_0/res_amp_lin_prog_0/outp gpio_noesd[5] 0.44fF
+C55 vdda1 top_pll_v2_0/biasp 0.03fF
+C56 vdda1 top_pll_v1_0/biasp 0.03fF
+C57 io_analog[2] bias_0/iref_7 13.88fF
+C58 io_analog[6] io_clamp_high[2] 0.53fF
+C59 vdda1 bias_0/iref_9 30.24fF
+C60 io_analog[7] top_pll_v1_1/buffer_salida_0/a_3996_n100# -0.08fF
+C61 io_analog[6] io_analog[4] 0.59fF
+C62 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB 0.19fF
+C63 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl gpio_noesd[5] 0.33fF
+C64 bias_0/iref_9 io_analog[3] 13.88fF
+C65 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in 0.20fF
+C66 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in 0.94fF
+C67 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp 1.01fF
+C68 bias_0/iref_2 top_pll_v1_0/nUp 0.70fF
+C69 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# -0.11fF
+C70 bias_0/iref_7 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.46fF
+C71 io_analog[4] bias_0/iref_7 15.97fF
+C72 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.12fF
+C73 gpio_noesd[4] gpio_noesd[5] 4.67fF
+C74 bias_0/iref_0 top_pll_v1_1/Up 0.74fF
+C75 vdda1 bias_0/iref_1 15.26fF
+C76 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outp -0.31fF
+C77 vdda1 top_pll_v2_0/nUp 0.01fF
+C78 vdda1 io_analog[2] 25.90fF
+C79 bias_0/iref_8 bias_0/iref_5 10.19fF
+C80 vdda1 bias_0/iref_0 15.18fF
+C81 bias_0/iref_5 bias_0/iref_6 29.11fF
+C82 io_analog[2] io_analog[3] 0.14fF
+C83 io_analog[7] bias_0/iref_1 13.22fF
+C84 gpio_noesd[2] vdda1 214.16fF
+C85 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# bias_0/iref_8 0.11fF
+C86 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.07fF
+C87 bias_0/iref_1 top_pll_v2_0/nDown 0.54fF
+C88 res_amp_top_0/res_amp_lin_prog_0/clk gpio_noesd[5] 0.68fF
+C89 vdda1 gpio_noesd[7] 120.83fF
+C90 bias_0/iref_2 io_analog[9] 14.44fF
+C91 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.17fF
+C92 gpio_noesd[7] top_pll_v2_0/vco_vctrl 0.05fF
+C93 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.33fF
+C94 io_analog[4] vdda1 182.26fF
+C95 gpio_noesd[7] top_pll_v1_0/out_to_div 0.23fF
+C96 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA gpio_noesd[1] 0.29fF
+C97 io_analog[5] m3_226242_702300# 0.53fF
+C98 gpio_noesd[7] top_pll_v1_1/vco_vctrl 0.04fF
+C99 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_1008_774# 0.21fF
+C100 bias_0/iref_9 gpio_noesd[5] 1.30fF
+C101 vdda1 io_analog[8] 29.93fF
+C102 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out 0.19fF
+C103 gpio_noesd[7] gpio_noesd[8] 1.88fF
+C104 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.12fF
+C105 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.17fF
+C106 gpio_noesd[1] vdda1 214.54fF
+C107 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[6] 2.12fF
+C108 gpio_noesd[6] res_amp_top_0/res_amp_lin_prog_0/outn 0.45fF
+C109 vdda1 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.12fF
+C110 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/clk 0.21fF
+C111 top_pll_v1_0/biasp bias_0/iref_2 3.20fF
+C112 top_pll_v1_1/pswitch vdda1 0.48fF
+C113 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_5 0.45fF
+C114 bias_0/iref_1 top_pll_v2_0/charge_pump_0/w_2544_775# 0.09fF
+C115 gpio_noesd[7] top_pll_v1_1/out_to_div 0.15fF
+C116 gpio_noesd[7] top_pll_v2_0/out_to_div 0.23fF
+C117 gpio_noesd[7] io_analog[10] 29.88fF
+C118 bias_0/iref_9 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl 0.42fF
+C119 res_amp_top_0/res_amp_sync_v2_0/rst bias_0/iref_9 0.39fF
+C120 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# bias_0/iref_6 0.15fF
+C121 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/clk -0.01fF
+C122 vdda1 top_pll_v1_0/buffer_salida_0/a_3996_n100# 0.06fF
+C123 io_analog[6] vdda1 124.15fF
+C124 bias_0/iref_9 bias_0/iref_8 9.89fF
+C125 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# 0.18fF
+C126 io_analog[2] gpio_noesd[5] 0.09fF
+C127 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C128 res_amp_top_0/res_amp_lin_prog_0/outp_cap bias_0/iref_7 0.37fF
+C129 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in gpio_noesd[5] 0.47fF
+C130 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out gpio_noesd[3] 0.03fF
+C131 bias_0/iref_0 top_pll_v1_1/charge_pump_0/w_2544_775# 0.21fF
+C132 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk gpio_noesd[5] 0.44fF
+C133 res_amp_top_0/res_amp_lin_prog_0/outn gpio_noesd[5] 1.42fF
+C134 gpio_noesd[4] bias_0/iref_9 -0.25fF
+C135 vdda1 bias_0/iref_7 33.08fF
+C136 bias_0/iref_5 io_analog[5] 0.09fF
+C137 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB gpio_noesd[5] 0.14fF
+C138 bias_0/iref_0 top_pll_v1_1/nUp 0.74fF
+C139 vdda1 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp 2.10fF
+C140 io_analog[3] bias_0/iref_7 13.88fF
+C141 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in gpio_noesd[5] 0.05fF
+C142 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd 0.04fF
+C143 io_analog[2] bias_0/iref_5 13.88fF
+C144 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp gpio_noesd[5] 0.54fF
+C145 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out 0.57fF
+C146 io_analog[2] bias_0/iref_8 13.88fF
+C147 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[5] 0.14fF
+C148 io_analog[2] bias_0/iref_6 13.88fF
+C149 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.01fF
+C150 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out 0.21fF
+C151 io_analog[6] io_clamp_low[2] 0.53fF
+C152 gpio_noesd[3] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.01fF
+C153 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in bias_0/iref_5 0.46fF
+C154 io_analog[4] io_clamp_high[0] 0.53fF
+C155 gpio_noesd[4] io_analog[2] -0.21fF
+C156 bias_0/iref_5 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 0.46fF
+C157 io_analog[4] bias_0/iref_5 15.97fF
+C158 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA 0.42fF
+C159 bias_0/iref_8 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in 1.34fF
+C160 io_analog[4] bias_0/iref_8 15.97fF
+C161 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk -0.13fF
+C162 bias_0/iref_2 io_analog[8] 14.44fF
+C163 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/outn -1.06fF
+C164 vdda1 top_pll_v2_0/vco_vctrl 0.59fF
+C165 io_analog[4] bias_0/iref_6 15.97fF
+C166 vdda1 io_analog[0] 76.77fF
+C167 vdda1 io_analog[3] 25.90fF
+C168 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB 0.08fF
+C169 top_pll_v1_0/vco_vctrl gpio_noesd[7] 0.05fF
+C170 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# bias_0/iref_7 0.09fF
+C171 vdda1 io_analog[7] 29.48fF
+C172 bias_0/iref_2 top_pll_v1_0/Up 0.70fF
+C173 vdda1 top_pll_v1_1/vco_vctrl 0.54fF
+C174 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C175 bias_0/iref_0 top_pll_v1_1/Down 1.08fF
+C176 gpio_noesd[5] res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# 0.32fF
+C177 vdda1 gpio_noesd[8] 76.96fF
+C178 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp 0.17fF
+C179 bias_0/iref_1 top_pll_v2_0/biasp 2.20fF
+C180 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b 0.31fF
+C181 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# gpio_noesd[4] -0.08fF
+C182 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd 0.04fF
+C183 gpio_noesd[1] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in 0.23fF
+C184 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/clk 0.37fF
+C185 bias_0/iref_2 top_pll_v1_0/nDown 0.70fF
+C186 vdda1 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd 0.04fF
+C187 io_analog[6] bias_0/iref_2 54.67fF
+C188 vdda1 gpio_noesd[6] 53.94fF
+C189 bias_0/iref_1 top_pll_v2_0/Down 0.91fF
+C190 bias_0/iref_9 io_analog[2] 13.88fF
+C191 gpio_noesd[4] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in 0.12fF
+C192 vdda1 io_analog[10] 0.01fF
+C193 bias_0/iref_0 top_pll_v1_1/biasp 3.13fF
+C194 gpio_noesd[2] res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out 0.38fF
+C195 vdda1 top_pll_v2_0/buffer_salida_0/a_3996_n100# 0.05fF
+C196 bias_0/iref_2 top_pll_v1_0/Down 1.11fF
+C197 io_in_3v3[0] vssa1 0.41fF
+C198 io_oeb[26] vssa1 0.61fF
+C199 io_in[0] vssa1 0.41fF
+C200 io_out[26] vssa1 0.61fF
+C201 io_out[0] vssa1 0.41fF
+C202 io_in[26] vssa1 0.61fF
+C203 io_oeb[0] vssa1 0.41fF
+C204 io_in_3v3[26] vssa1 0.61fF
+C205 io_in_3v3[1] vssa1 0.41fF
+C206 io_oeb[25] vssa1 0.61fF
+C207 io_in[1] vssa1 0.41fF
+C208 io_out[25] vssa1 0.61fF
+C209 io_out[1] vssa1 0.41fF
+C210 io_in[25] vssa1 0.61fF
+C211 io_oeb[1] vssa1 0.41fF
+C212 io_in_3v3[25] vssa1 0.61fF
+C213 io_in_3v3[2] vssa1 0.41fF
+C214 io_oeb[24] vssa1 0.61fF
+C215 io_in[2] vssa1 0.41fF
+C216 io_out[24] vssa1 0.61fF
+C217 io_out[2] vssa1 0.41fF
+C218 io_in[24] vssa1 0.61fF
+C219 io_oeb[2] vssa1 -0.20fF
+C220 io_in_3v3[3] vssa1 0.41fF
+C221 gpio_noesd[17] vssa1 0.61fF
+C222 io_in[3] vssa1 0.41fF
+C223 gpio_analog[17] vssa1 0.61fF
+C224 io_out[3] vssa1 0.41fF
+C225 io_oeb[3] vssa1 0.41fF
+C226 io_in_3v3[4] vssa1 0.41fF
+C227 io_in[4] vssa1 0.41fF
+C228 io_out[4] vssa1 0.41fF
+C229 io_oeb[4] vssa1 0.41fF
+C230 io_oeb[23] vssa1 0.61fF
+C231 io_out[23] vssa1 0.61fF
+C232 io_in[23] vssa1 0.61fF
+C233 io_in_3v3[23] vssa1 0.61fF
+C234 gpio_noesd[16] vssa1 0.61fF
+C235 io_in_3v3[5] vssa1 0.41fF
+C236 io_in[5] vssa1 -0.20fF
+C237 io_out[5] vssa1 0.41fF
+C238 io_oeb[5] vssa1 0.41fF
+C239 io_oeb[22] vssa1 0.61fF
+C240 io_out[22] vssa1 0.61fF
+C241 io_in[22] vssa1 0.61fF
+C242 io_in_3v3[22] vssa1 0.61fF
+C243 gpio_analog[15] vssa1 0.61fF
+C244 io_in_3v3[6] vssa1 -0.20fF
+C245 io_in[6] vssa1 0.41fF
+C246 io_out[6] vssa1 0.41fF
+C247 io_oeb[6] vssa1 0.41fF
+C248 io_oeb[21] vssa1 0.61fF
+C249 io_out[21] vssa1 0.61fF
+C250 io_in[21] vssa1 0.61fF
+C251 io_in_3v3[21] vssa1 0.61fF
+C252 gpio_noesd[14] vssa1 0.61fF
+C253 gpio_analog[14] vssa1 0.61fF
+C254 vssd2 vssa1 -5.19fF
+C255 vssd1 vssa1 1.13fF
+C256 vdda2 vssa1 -5.19fF
+C257 io_oeb[20] vssa1 0.61fF
+C258 io_out[20] vssa1 0.61fF
+C259 io_in[20] vssa1 0.61fF
+C260 io_in_3v3[20] vssa1 0.61fF
+C261 gpio_noesd[13] vssa1 0.61fF
+C262 gpio_analog[13] vssa1 0.61fF
+C263 gpio_analog[0] vssa1 0.41fF
+C264 gpio_noesd[0] vssa1 0.41fF
+C265 io_in_3v3[7] vssa1 0.41fF
+C266 io_in[7] vssa1 0.41fF
+C267 io_out[7] vssa1 0.41fF
+C268 io_oeb[7] vssa1 0.41fF
+C269 io_oeb[19] vssa1 0.61fF
+C270 io_out[19] vssa1 0.61fF
+C271 io_in[19] vssa1 0.61fF
+C272 io_in_3v3[19] vssa1 0.61fF
+C273 gpio_noesd[12] vssa1 0.61fF
+C274 gpio_analog[12] vssa1 0.61fF
+C275 gpio_analog[1] vssa1 0.41fF
+C276 io_in_3v3[8] vssa1 0.41fF
+C277 io_in[8] vssa1 0.41fF
+C278 io_out[8] vssa1 -0.20fF
+C279 io_oeb[8] vssa1 0.41fF
+C280 gpio_analog[2] vssa1 0.41fF
+C281 io_in_3v3[9] vssa1 0.41fF
+C282 io_in[9] vssa1 0.41fF
+C283 io_out[9] vssa1 0.41fF
+C284 io_oeb[9] vssa1 0.41fF
+C285 gpio_analog[3] vssa1 0.41fF
+C286 io_in_3v3[10] vssa1 0.41fF
+C287 io_in[10] vssa1 0.41fF
+C288 io_out[10] vssa1 0.41fF
+C289 io_oeb[10] vssa1 0.41fF
+C290 gpio_analog[4] vssa1 0.41fF
+C291 io_in_3v3[11] vssa1 0.41fF
+C292 io_in[11] vssa1 0.41fF
+C293 io_out[11] vssa1 0.41fF
+C294 io_oeb[11] vssa1 0.41fF
+C295 gpio_analog[5] vssa1 0.41fF
+C296 io_in_3v3[12] vssa1 0.41fF
+C297 io_in[12] vssa1 0.41fF
+C298 io_out[12] vssa1 0.41fF
+C299 io_oeb[12] vssa1 0.41fF
+C300 gpio_analog[6] vssa1 0.60fF
+C301 io_in_3v3[13] vssa1 0.60fF
+C302 io_in[13] vssa1 0.60fF
+C303 io_out[13] vssa1 0.60fF
+C304 io_oeb[13] vssa1 0.60fF
+C305 io_oeb[18] vssa1 0.61fF
+C306 io_out[18] vssa1 0.61fF
+C307 io_in_3v3[18] vssa1 0.61fF
+C308 gpio_noesd[11] vssa1 0.61fF
+C309 gpio_analog[11] vssa1 0.61fF
+C310 io_oeb[17] vssa1 0.61fF
+C311 io_in[17] vssa1 0.61fF
+C312 io_in_3v3[17] vssa1 0.61fF
+C313 gpio_noesd[10] vssa1 0.61fF
+C314 gpio_analog[10] vssa1 0.61fF
+C315 io_out[16] vssa1 0.61fF
+C316 io_in[16] vssa1 0.61fF
+C317 io_in_3v3[16] vssa1 0.61fF
+C318 gpio_noesd[9] vssa1 0.61fF
+C319 gpio_analog[9] vssa1 0.61fF
+C320 io_oeb[15] vssa1 0.61fF
+C321 io_out[15] vssa1 0.61fF
+C322 io_in[15] vssa1 0.61fF
+C323 io_in_3v3[15] vssa1 0.61fF
+C324 vccd1 vssa1 0.85fF
+C325 gpio_analog[8] vssa1 0.61fF
+C326 io_oeb[14] vssa1 0.61fF
+C327 io_out[14] vssa1 0.61fF
+C328 io_in[14] vssa1 0.61fF
+C329 io_in_3v3[14] vssa1 0.61fF
+C330 vssa2 vssa1 1.66fF
+C331 vccd2 vssa1 0.91fF
+C332 io_clamp_high[0] vssa1 -2.60fF
+C333 io_clamp_low[0] vssa1 0.82fF
+C334 io_clamp_high[2] vssa1 0.66fF
+C335 io_clamp_low[2] vssa1 0.50fF
+C336 user_irq[2] vssa1 0.63fF
+C337 user_irq[1] vssa1 0.63fF
+C338 user_irq[0] vssa1 0.63fF
+C339 user_clock2 vssa1 0.63fF
+C340 la_oenb[127] vssa1 0.63fF
+C341 la_data_in[127] vssa1 0.63fF
+C342 la_oenb[126] vssa1 0.63fF
+C343 la_data_out[126] vssa1 0.63fF
+C344 la_data_in[126] vssa1 0.63fF
+C345 la_oenb[125] vssa1 0.63fF
+C346 la_data_out[125] vssa1 0.63fF
+C347 la_data_in[125] vssa1 0.63fF
+C348 la_oenb[124] vssa1 0.63fF
+C349 la_data_out[124] vssa1 0.63fF
+C350 la_data_in[124] vssa1 0.63fF
+C351 la_oenb[123] vssa1 0.63fF
+C352 la_data_out[123] vssa1 0.63fF
+C353 la_oenb[122] vssa1 0.63fF
+C354 la_data_out[122] vssa1 0.63fF
+C355 la_data_in[122] vssa1 0.63fF
+C356 la_oenb[121] vssa1 0.63fF
+C357 la_data_out[121] vssa1 0.63fF
+C358 la_data_in[121] vssa1 0.63fF
+C359 la_oenb[120] vssa1 0.63fF
+C360 la_data_out[120] vssa1 0.63fF
+C361 la_data_in[120] vssa1 0.63fF
+C362 la_oenb[119] vssa1 0.63fF
+C363 la_data_out[119] vssa1 0.63fF
+C364 la_data_in[119] vssa1 0.63fF
+C365 la_oenb[118] vssa1 0.63fF
+C366 la_data_out[118] vssa1 0.63fF
+C367 la_data_in[118] vssa1 0.63fF
+C368 la_oenb[117] vssa1 0.63fF
+C369 la_data_out[117] vssa1 0.63fF
+C370 la_data_in[117] vssa1 0.63fF
+C371 la_data_out[116] vssa1 0.63fF
+C372 la_data_in[116] vssa1 0.63fF
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+C738 wbs_dat_o[15] vssa1 0.63fF
+C739 wbs_dat_i[15] vssa1 0.63fF
+C740 wbs_adr_i[15] vssa1 0.63fF
+C741 wbs_dat_o[14] vssa1 0.63fF
+C742 wbs_dat_i[14] vssa1 0.63fF
+C743 wbs_adr_i[14] vssa1 0.63fF
+C744 wbs_dat_o[13] vssa1 0.63fF
+C745 wbs_dat_i[13] vssa1 0.63fF
+C746 wbs_adr_i[13] vssa1 0.63fF
+C747 wbs_dat_o[12] vssa1 0.63fF
+C748 wbs_dat_i[12] vssa1 0.63fF
+C749 wbs_adr_i[12] vssa1 0.63fF
+C750 wbs_dat_i[11] vssa1 0.63fF
+C751 wbs_adr_i[11] vssa1 0.63fF
+C752 wbs_dat_o[10] vssa1 0.63fF
+C753 wbs_dat_i[10] vssa1 0.63fF
+C754 wbs_adr_i[10] vssa1 0.63fF
+C755 wbs_dat_o[9] vssa1 0.63fF
+C756 wbs_dat_i[9] vssa1 0.63fF
+C757 wbs_adr_i[9] vssa1 0.63fF
+C758 wbs_dat_o[8] vssa1 0.63fF
+C759 wbs_dat_i[8] vssa1 0.63fF
+C760 wbs_adr_i[8] vssa1 0.63fF
+C761 wbs_dat_o[7] vssa1 0.63fF
+C762 wbs_adr_i[7] vssa1 0.63fF
+C763 wbs_dat_o[6] vssa1 0.63fF
+C764 wbs_dat_i[6] vssa1 0.63fF
+C765 wbs_adr_i[6] vssa1 0.63fF
+C766 wbs_dat_o[5] vssa1 0.63fF
+C767 wbs_dat_i[5] vssa1 0.63fF
+C768 wbs_adr_i[5] vssa1 0.63fF
+C769 wbs_dat_o[4] vssa1 0.63fF
+C770 wbs_dat_i[4] vssa1 0.63fF
+C771 wbs_adr_i[4] vssa1 0.63fF
+C772 wbs_sel_i[3] vssa1 0.63fF
+C773 wbs_dat_o[3] vssa1 0.63fF
+C774 wbs_adr_i[3] vssa1 0.63fF
+C775 wbs_sel_i[2] vssa1 0.63fF
+C776 wbs_dat_o[2] vssa1 0.63fF
+C777 wbs_dat_i[2] vssa1 0.63fF
+C778 wbs_adr_i[2] vssa1 0.63fF
+C779 wbs_dat_o[1] vssa1 0.63fF
+C780 wbs_dat_i[1] vssa1 0.63fF
+C781 wbs_adr_i[1] vssa1 0.63fF
+C782 wbs_sel_i[0] vssa1 0.63fF
+C783 wbs_dat_o[0] vssa1 0.63fF
+C784 wbs_dat_i[0] vssa1 0.63fF
+C785 wbs_adr_i[0] vssa1 0.63fF
+C786 wbs_we_i vssa1 0.63fF
+C787 wbs_stb_i vssa1 0.63fF
+C788 wbs_cyc_i vssa1 0.63fF
+C789 wbs_ack_o vssa1 0.63fF
+C790 wb_rst_i vssa1 0.63fF
+C791 m3_226242_702300# vssa1 -1.31fF
+C792 m3_222594_702300# vssa1 0.55fF
+C793 top_pll_v2_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C794 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C795 top_pll_v2_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C796 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C797 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C798 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C799 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C800 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C801 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C802 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C803 top_pll_v2_0/QB vssa1 4.35fF
+C804 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C805 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C806 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C807 top_pll_v2_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C808 top_pll_v2_0/out_div_by_5 vssa1 -0.40fF
+C809 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C810 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C811 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C812 top_pll_v2_0/pfd_reset vssa1 2.17fF
+C813 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C814 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C815 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C816 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C817 top_pll_v2_0/QA vssa1 4.22fF
+C818 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C819 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C820 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C821 top_pll_v2_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C822 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C823 top_pll_v2_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C824 top_pll_v2_0/nUp vssa1 5.39fF
+C825 top_pll_v2_0/Up vssa1 1.85fF
+C826 top_pll_v2_0/Down vssa1 6.19fF
+C827 top_pll_v2_0/nDown vssa1 -3.53fF
+C828 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C829 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C830 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C831 top_pll_v2_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C832 top_pll_v2_0/div_5_Q1_shift vssa1 -0.14fF
+C833 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C834 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C835 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C836 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C837 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C838 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C839 top_pll_v2_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C840 top_pll_v2_0/div_5_Q1 vssa1 4.25fF
+C841 top_pll_v2_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C842 top_pll_v2_0/div_5_nQ0 vssa1 0.59fF
+C843 top_pll_v2_0/div_5_Q0 vssa1 0.01fF
+C844 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C845 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C846 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C847 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C848 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C849 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C850 top_pll_v2_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C851 top_pll_v2_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C852 top_pll_v2_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C853 top_pll_v2_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C854 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C855 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C856 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C857 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C858 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C859 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C860 top_pll_v2_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C861 top_pll_v2_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C862 top_pll_v2_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C863 top_pll_v2_0/div_5_nQ2 vssa1 1.24fF
+C864 top_pll_v2_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C865 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C866 top_pll_v2_0/n_out_by_2 vssa1 -2.75fF
+C867 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C868 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C869 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C870 top_pll_v2_0/out_by_2 vssa1 -5.01fF
+C871 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C872 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C873 top_pll_v2_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C874 top_pll_v2_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C875 top_pll_v2_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C876 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C877 top_pll_v2_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C878 top_pll_v2_0/out_first_buffer vssa1 2.88fF
+C879 top_pll_v2_0/out_to_div vssa1 4.23fF
+C880 top_pll_v2_0/out_to_buffer vssa1 1.54fF
+C881 top_pll_v2_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C882 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C883 top_pll_v2_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C884 top_pll_v2_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C885 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C886 top_pll_v2_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C887 top_pll_v2_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C888 top_pll_v2_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C889 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C890 top_pll_v2_0/vco_out vssa1 1.01fF
+C891 top_pll_v2_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C892 top_pll_v2_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C893 top_pll_v2_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C894 top_pll_v2_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C895 io_analog[8] vssa1 13.78fF
+C896 top_pll_v2_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C897 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C898 top_pll_v2_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C899 top_pll_v2_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C900 top_pll_v2_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C901 top_pll_v2_0/out_buffer_div_2 vssa1 1.60fF
+C902 top_pll_v2_0/n_out_buffer_div_2 vssa1 1.63fF
+C903 top_pll_v2_0/out_div_2 vssa1 -1.30fF
+C904 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C905 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C906 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C907 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C908 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C909 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C910 top_pll_v2_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C911 top_pll_v2_0/n_out_div_2 vssa1 1.95fF
+C912 top_pll_v2_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C913 top_pll_v2_0/lf_vc vssa1 -59.89fF
+C914 top_pll_v2_0/loop_filter_v2_0/res_loop_filter_2/out vssa1 7.90fF
+C915 gpio_noesd[8] vssa1 210.79fF
+C916 top_pll_v2_0/loop_filter_v2_0/cap3_loop_filter_0/in vssa1 -12.03fF
+C917 top_pll_v2_0/nswitch vssa1 3.73fF
+C918 top_pll_v2_0/biasp vssa1 5.44fF
+C919 bias_0/iref_1 vssa1 -91.53fF
+C920 top_pll_v2_0/vco_vctrl vssa1 -20.08fF
+C921 top_pll_v2_0/pswitch vssa1 3.57fF
+C922 io_analog[5] vssa1 33.29fF
+C923 bias_0/iref_4 vssa1 1.17fF
+C924 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_4/a_n1731_n1219# vssa1 2.60fF
+C925 bias_0/iref_3 vssa1 0.64fF
+C926 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_3/a_n1731_n1219# vssa1 2.60fF
+C927 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_2/a_n1731_n1219# vssa1 2.60fF
+C928 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_1/a_n1731_n1219# vssa1 2.60fF
+C929 bias_0/m1_20168_984# vssa1 56.92fF
+C930 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_0/a_n1731_n1219# vssa1 2.60fF
+C931 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_10/a_n1731_n1219# vssa1 2.60fF
+C932 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_8/a_n1731_n1219# vssa1 2.60fF
+C933 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_9/a_n1731_n1219# vssa1 2.60fF
+C934 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_7/a_n1731_n1219# vssa1 2.60fF
+C935 bias_0/sky130_fd_pr__pfet_01v8_lvt_8P223X_6/a_n1731_n1219# vssa1 2.60fF
+C936 top_pll_v1_1/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C937 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C938 top_pll_v1_1/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C939 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C940 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C941 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C942 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C943 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C944 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C945 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C946 top_pll_v1_1/QB vssa1 4.35fF
+C947 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C948 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C949 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C950 top_pll_v1_1/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C951 top_pll_v1_1/out_div_by_5 vssa1 -0.40fF
+C952 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C953 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C954 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C955 top_pll_v1_1/pfd_reset vssa1 2.17fF
+C956 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C957 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C958 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C959 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C960 top_pll_v1_1/QA vssa1 4.22fF
+C961 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C962 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C963 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C964 top_pll_v1_1/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C965 io_analog[10] vssa1 503.33fF
+C966 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C967 top_pll_v1_1/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C968 top_pll_v1_1/nUp vssa1 5.39fF
+C969 top_pll_v1_1/Up vssa1 1.85fF
+C970 top_pll_v1_1/Down vssa1 6.19fF
+C971 top_pll_v1_1/nDown vssa1 -3.53fF
+C972 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C973 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C974 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C975 top_pll_v1_1/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C976 top_pll_v1_1/div_5_Q1_shift vssa1 -0.14fF
+C977 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C978 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C979 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C980 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C981 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C982 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C983 top_pll_v1_1/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C984 top_pll_v1_1/div_5_Q1 vssa1 4.25fF
+C985 top_pll_v1_1/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C986 top_pll_v1_1/div_5_nQ0 vssa1 0.59fF
+C987 top_pll_v1_1/div_5_Q0 vssa1 0.01fF
+C988 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C989 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C990 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C991 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C992 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C993 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C994 top_pll_v1_1/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C995 top_pll_v1_1/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C996 top_pll_v1_1/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C997 top_pll_v1_1/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C998 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C999 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1000 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1001 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1002 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1003 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1004 top_pll_v1_1/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1005 top_pll_v1_1/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1006 top_pll_v1_1/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1007 top_pll_v1_1/div_5_nQ2 vssa1 1.24fF
+C1008 top_pll_v1_1/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1009 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1010 top_pll_v1_1/n_out_by_2 vssa1 -2.75fF
+C1011 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1012 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1013 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1014 top_pll_v1_1/out_by_2 vssa1 -5.01fF
+C1015 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1016 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1017 top_pll_v1_1/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1018 top_pll_v1_1/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1019 top_pll_v1_1/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1020 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1021 top_pll_v1_1/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1022 top_pll_v1_1/out_first_buffer vssa1 2.88fF
+C1023 top_pll_v1_1/out_to_div vssa1 4.23fF
+C1024 top_pll_v1_1/out_to_buffer vssa1 1.54fF
+C1025 top_pll_v1_1/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1026 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1027 top_pll_v1_1/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1028 top_pll_v1_1/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1029 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1030 top_pll_v1_1/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1031 top_pll_v1_1/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1032 top_pll_v1_1/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1033 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1034 top_pll_v1_1/vco_out vssa1 1.01fF
+C1035 top_pll_v1_1/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1036 top_pll_v1_1/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1037 top_pll_v1_1/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1038 top_pll_v1_1/buffer_salida_0/a_3996_n100# vssa1 48.11fF
+C1039 io_analog[7] vssa1 24.61fF
+C1040 top_pll_v1_1/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1041 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1042 top_pll_v1_1/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1043 top_pll_v1_1/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1044 top_pll_v1_1/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1045 top_pll_v1_1/out_buffer_div_2 vssa1 1.60fF
+C1046 top_pll_v1_1/n_out_buffer_div_2 vssa1 1.63fF
+C1047 top_pll_v1_1/out_div_2 vssa1 -1.30fF
+C1048 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1049 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1050 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1051 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1052 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1053 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1054 top_pll_v1_1/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1055 top_pll_v1_1/n_out_div_2 vssa1 1.95fF
+C1056 top_pll_v1_1/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1057 top_pll_v1_1/nswitch vssa1 3.73fF
+C1058 top_pll_v1_1/biasp vssa1 5.44fF
+C1059 bias_0/iref_0 vssa1 -81.35fF
+C1060 top_pll_v1_1/vco_vctrl vssa1 -18.17fF
+C1061 top_pll_v1_1/pswitch vssa1 3.57fF
+C1062 top_pll_v1_1/lf_vc vssa1 -59.89fF
+C1063 top_pll_v1_1/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1064 top_pll_v1_0/PFD_0/and_pfd_0/a_656_410# vssa1 0.96fF
+C1065 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_63_n45# vssa1 0.05fF
+C1066 top_pll_v1_0/PFD_0/and_pfd_0/sky130_fd_pr__nfet_01v8_ZCYAJJ_0/a_n129_n45# vssa1 0.05fF
+C1067 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1068 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/B vssa1 1.40fF
+C1069 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1070 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1071 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1072 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_2/A vssa1 2.55fF
+C1073 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1074 top_pll_v1_0/QB vssa1 4.35fF
+C1075 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1076 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_3/A vssa1 3.14fF
+C1077 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1078 top_pll_v1_0/PFD_0/dff_pfd_1/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1079 top_pll_v1_0/out_div_by_5 vssa1 -0.40fF
+C1080 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1081 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/B vssa1 1.40fF
+C1082 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1083 top_pll_v1_0/pfd_reset vssa1 2.17fF
+C1084 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1085 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1086 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_2/A vssa1 2.55fF
+C1087 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1088 top_pll_v1_0/QA vssa1 4.22fF
+C1089 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_1/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1090 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_3/A vssa1 3.14fF
+C1091 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_63_n90# vssa1 0.03fF
+C1092 top_pll_v1_0/PFD_0/dff_pfd_0/nor_pfd_0/sky130_fd_pr__pfet_01v8_4F35BC_0/a_n129_n90# vssa1 0.03fF
+C1093 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_2/in vssa1 1.85fF
+C1094 top_pll_v1_0/pfd_cp_interface_0/inverter_cp_x1_0/out vssa1 1.77fF
+C1095 top_pll_v1_0/nUp vssa1 5.39fF
+C1096 top_pll_v1_0/Up vssa1 1.85fF
+C1097 top_pll_v1_0/Down vssa1 6.19fF
+C1098 top_pll_v1_0/nDown vssa1 -3.53fF
+C1099 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__or2_1_0/a_63_368# vssa1 0.37fF
+C1100 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_1/a_56_136# vssa1 0.38fF
+C1101 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__and2_1_0/a_56_136# vssa1 0.38fF
+C1102 top_pll_v1_0/div_by_5_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1103 top_pll_v1_0/div_5_Q1_shift vssa1 -0.14fF
+C1104 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1105 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1106 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1107 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1108 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1109 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1110 top_pll_v1_0/div_by_5_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1111 top_pll_v1_0/div_5_Q1 vssa1 4.25fF
+C1112 top_pll_v1_0/div_by_5_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1113 top_pll_v1_0/div_5_nQ0 vssa1 0.59fF
+C1114 top_pll_v1_0/div_5_Q0 vssa1 0.01fF
+C1115 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1116 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1117 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1118 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1119 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1120 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1121 top_pll_v1_0/div_by_5_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1122 top_pll_v1_0/div_by_5_0/DFlipFlop_1/D vssa1 3.64fF
+C1123 top_pll_v1_0/div_by_5_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1124 top_pll_v1_0/div_by_5_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1125 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1126 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1127 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1128 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1129 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1130 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1131 top_pll_v1_0/div_by_5_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1132 top_pll_v1_0/div_by_5_0/DFlipFlop_2/D vssa1 3.13fF
+C1133 top_pll_v1_0/div_by_5_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1134 top_pll_v1_0/div_5_nQ2 vssa1 1.24fF
+C1135 top_pll_v1_0/div_by_5_0/DFlipFlop_0/Q vssa1 -0.94fF
+C1136 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1137 top_pll_v1_0/n_out_by_2 vssa1 -2.75fF
+C1138 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1139 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1140 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1141 top_pll_v1_0/out_by_2 vssa1 -5.01fF
+C1142 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1143 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1144 top_pll_v1_0/div_by_5_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1145 top_pll_v1_0/div_by_5_0/DFlipFlop_0/D vssa1 3.96fF
+C1146 top_pll_v1_0/div_by_5_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1147 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_355_368# vssa1 0.08fF
+C1148 top_pll_v1_0/div_by_5_0/sky130_fd_sc_hs__xor2_1_0/a_194_125# vssa1 0.40fF
+C1149 top_pll_v1_0/out_first_buffer vssa1 2.88fF
+C1150 top_pll_v1_0/out_to_div vssa1 4.23fF
+C1151 top_pll_v1_0/out_to_buffer vssa1 1.54fF
+C1152 top_pll_v1_0/ring_osc_0/csvco_branch_2/in vssa1 1.60fF
+C1153 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vdd vssa1 0.16fF
+C1154 top_pll_v1_0/ring_osc_0/csvco_branch_1/cap_vco_0/t vssa1 7.10fF
+C1155 top_pll_v1_0/ring_osc_0/csvco_branch_1/inverter_csvco_0/vss vssa1 0.52fF
+C1156 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vdd vssa1 0.16fF
+C1157 top_pll_v1_0/ring_osc_0/csvco_branch_2/cap_vco_0/t vssa1 7.10fF
+C1158 top_pll_v1_0/ring_osc_0/csvco_branch_2/inverter_csvco_0/vss vssa1 0.52fF
+C1159 top_pll_v1_0/ring_osc_0/csvco_branch_1/in vssa1 1.58fF
+C1160 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vdd vssa1 0.16fF
+C1161 top_pll_v1_0/vco_out vssa1 1.01fF
+C1162 gpio_noesd[7] vssa1 272.21fF
+C1163 top_pll_v1_0/ring_osc_0/csvco_branch_0/cap_vco_0/t vssa1 7.10fF
+C1164 top_pll_v1_0/ring_osc_0/csvco_branch_0/inverter_csvco_0/vss vssa1 0.52fF
+C1165 top_pll_v1_0/ring_osc_0/csvco_branch_2/vbp vssa1 0.36fF
+C1166 top_pll_v1_0/buffer_salida_0/a_3996_n100# vssa1 48.23fF
+C1167 io_analog[9] vssa1 7.89fF
+C1168 top_pll_v1_0/buffer_salida_0/a_678_n100# vssa1 13.21fF
+C1169 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1170 top_pll_v1_0/div_by_2_0/DFlipFlop_0/CLK vssa1 0.31fF
+C1171 top_pll_v1_0/div_by_2_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1172 top_pll_v1_0/div_by_2_0/DFlipFlop_0/nCLK vssa1 1.03fF
+C1173 top_pll_v1_0/out_buffer_div_2 vssa1 1.60fF
+C1174 top_pll_v1_0/n_out_buffer_div_2 vssa1 1.63fF
+C1175 top_pll_v1_0/out_div_2 vssa1 -1.30fF
+C1176 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1177 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1178 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1179 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1180 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1181 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1182 top_pll_v1_0/div_by_2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1183 top_pll_v1_0/n_out_div_2 vssa1 1.95fF
+C1184 top_pll_v1_0/div_by_2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
+C1185 top_pll_v1_0/nswitch vssa1 3.73fF
+C1186 top_pll_v1_0/biasp vssa1 5.44fF
+C1187 bias_0/iref_2 vssa1 -178.91fF
+C1188 top_pll_v1_0/vco_vctrl vssa1 -18.17fF
+C1189 top_pll_v1_0/pswitch vssa1 3.57fF
+C1190 top_pll_v1_0/lf_vc vssa1 -59.89fF
+C1191 top_pll_v1_0/loop_filter_0/res_loop_filter_2/out vssa1 7.90fF
+C1192 bias_0/iref_6 vssa1 -645.65fF
+C1193 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/in vssa1 -32.98fF
+C1194 io_analog[1] vssa1 74.58fF
+C1195 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_1/m1_460_n1129# vssa1 1.29fF
+C1196 bias_0/iref_5 vssa1 -623.45fF
+C1197 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/in vssa1 -32.98fF
+C1198 io_analog[0] vssa1 -154.61fF
+C1199 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_nmos_0/m1_460_n1129# vssa1 1.29fF
+C1200 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_1/m1_957_828# vssa1 -35.44fF
+C1201 bias_0/iref_8 vssa1 -189.06fF
+C1202 res_amp_top_0/source_follower_buff_diff_0/source_follower_buff_pmos_0/m1_957_828# vssa1 -35.44fF
+C1203 bias_0/iref_7 vssa1 -205.18fF
+C1204 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_511_801# vssa1 -1.87fF
+C1205 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1384_n363# vssa1 0.47fF
+C1206 gpio_noesd[5] vssa1 122.09fF
+C1207 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_448_n363# vssa1 -1.10fF
+C1208 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vctrl vssa1 -2.03fF
+C1209 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_1996_n363# vssa1 -2.23fF
+C1210 gpio_noesd[6] vssa1 325.91fF
+C1211 gpio_noesd[4] vssa1 116.78fF
+C1212 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_964_n363# vssa1 -1.03fF
+C1213 res_amp_top_0/res_amp_lin_prog_0/iref_ctrl_res_amp_0/m1_n356_n363# vssa1 0.51fF
+C1214 bias_0/iref_9 vssa1 -181.57fF
+C1215 res_amp_top_0/res_amp_lin_prog_0/outn vssa1 1.55fF
+C1216 io_analog[3] vssa1 -119.52fF
+C1217 res_amp_top_0/res_amp_lin_prog_0/outp vssa1 -4.89fF
+C1218 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/vp vssa1 -4.89fF
+C1219 io_analog[2] vssa1 -131.04fF
+C1220 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/a_3747_261# vssa1 -0.95fF
+C1221 res_amp_top_0/res_amp_lin_prog_0/outn_cap vssa1 -0.01fF
+C1222 res_amp_top_0/res_amp_lin_prog_0/res_amp_lin_0/clk vssa1 4.27fF
+C1223 res_amp_top_0/res_amp_lin_prog_0/inverter_min_x4_0/out vssa1 4.60fF
+C1224 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/in vssa1 1.07fF
+C1225 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_7/inverter_min_1/in vssa1 1.03fF
+C1226 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_6/inverter_min_1/in vssa1 1.03fF
+C1227 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/in vssa1 1.07fF
+C1228 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_5/inverter_min_1/in vssa1 1.03fF
+C1229 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_4/inverter_min_1/in vssa1 1.03fF
+C1230 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/in vssa1 1.07fF
+C1231 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_3/inverter_min_1/in vssa1 1.03fF
+C1232 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/in vssa1 1.07fF
+C1233 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_1/inverter_min_1/in vssa1 1.03fF
+C1234 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_2/inverter_min_1/in vssa1 1.03fF
+C1235 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_0/inverter_min_1/in vssa1 1.03fF
+C1236 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/in vssa1 1.07fF
+C1237 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinB vssa1 -7.88fF
+C1238 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_13/inverter_min_1/in vssa1 1.03fF
+C1239 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_12/inverter_min_1/in vssa1 1.03fF
+C1240 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/in vssa1 1.07fF
+C1241 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_11/inverter_min_1/in vssa1 1.03fF
+C1242 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1243 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_10/inverter_min_1/in vssa1 1.03fF
+C1244 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_6/sel_b vssa1 2.03fF
+C1245 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/nand_logic_0/in1 vssa1 1.54fF
+C1246 gpio_noesd[3] vssa1 213.06fF
+C1247 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/sel_b vssa1 2.03fF
+C1248 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_5/out vssa1 -1.67fF
+C1249 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/DinA vssa1 -2.58fF
+C1250 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/sel_b vssa1 2.03fF
+C1251 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_4/out vssa1 -2.25fF
+C1252 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinA vssa1 -0.04fF
+C1253 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/sel_b vssa1 2.03fF
+C1254 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/out vssa1 -2.69fF
+C1255 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_3/DinB vssa1 -4.96fF
+C1256 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/sel_b vssa1 2.03fF
+C1257 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_2/out vssa1 -4.71fF
+C1258 gpio_noesd[2] vssa1 216.13fF
+C1259 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinA vssa1 0.63fF
+C1260 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/sel_b vssa1 2.03fF
+C1261 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/out vssa1 -2.49fF
+C1262 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_1/DinB vssa1 -3.92fF
+C1263 gpio_noesd[1] vssa1 230.09fF
+C1264 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/sel_b vssa1 2.03fF
+C1265 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/out vssa1 -0.27fF
+C1266 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/mux_2to1_logic_0/DinB vssa1 -0.97fF
+C1267 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/in vssa1 1.07fF
+C1268 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_9/inverter_min_1/in vssa1 1.03fF
+C1269 res_amp_top_0/res_amp_lin_prog_0/delay_cell_buff_0/buffer_no_inv_x05_8/inverter_min_1/in vssa1 1.03fF
+C1270 res_amp_top_0/res_amp_lin_prog_0/outp_cap vssa1 -7.66fF
+C1271 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/m1_21_n341# vssa1 0.72fF
+C1272 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/m1_21_n341# vssa1 0.72fF
+C1273 res_amp_top_0/res_amp_lin_prog_0/clk vssa1 -8.26fF
+C1274 res_amp_top_0/res_amp_sync_v2_0/inverter_min_x4_4/out vssa1 5.85fF
+C1275 res_amp_top_0/res_amp_sync_v2_0/nand_logic_1/out vssa1 1.70fF
+C1276 res_amp_top_0/res_amp_sync_v2_0/rst vssa1 -7.88fF
+C1277 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/nQ vssa1 0.48fF
+C1278 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/Q vssa1 -2.08fF
+C1279 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1280 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/nD vssa1 0.57fF
+C1281 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_1/D vssa1 -1.73fF
+C1282 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1283 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1284 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/D vssa1 0.96fF
+C1285 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1286 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/D vssa1 1.83fF
+C1287 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_4/latch_diff_0/nD vssa1 1.14fF
+C1288 res_amp_top_0/res_amp_sync_v2_0/nand_logic_0/out vssa1 1.20fF
+C1289 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/Q vssa1 -4.73fF
+C1290 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/nQ vssa1 0.48fF
+C1291 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/Q vssa1 -2.94fF
+C1292 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1293 io_analog[4] vssa1 -253.69fF
+C1294 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/nD vssa1 0.57fF
+C1295 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_1/D vssa1 -1.73fF
+C1296 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1297 io_analog[6] vssa1 -26.69fF
+C1298 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1299 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/D vssa1 0.96fF
+C1300 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1301 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/D vssa1 0.79fF
+C1302 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_3/latch_diff_0/nD vssa1 1.14fF
+C1303 vdda1 vssa1 7275.97fF
+C1304 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/nQ vssa1 0.48fF
+C1305 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/Q vssa1 -1.08fF
+C1306 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1307 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/nD vssa1 0.57fF
+C1308 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_1/D vssa1 -1.73fF
+C1309 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1310 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1311 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/D vssa1 0.96fF
+C1312 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1313 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/D vssa1 -0.38fF
+C1314 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_2/latch_diff_0/nD vssa1 1.14fF
+C1315 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/nQ vssa1 0.48fF
+C1316 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1317 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/nD vssa1 0.57fF
+C1318 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_1/D vssa1 -1.73fF
+C1319 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1320 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1321 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/D vssa1 0.96fF
+C1322 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1323 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/D vssa1 -1.04fF
+C1324 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_1/latch_diff_0/nD vssa1 1.14fF
+C1325 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/nQ vssa1 0.48fF
+C1326 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/m1_657_280# vssa1 0.57fF
+C1327 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/nD vssa1 0.57fF
+C1328 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_1/D vssa1 -1.73fF
+C1329 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/m1_657_280# vssa1 0.57fF
+C1330 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_2/in vssa1 1.86fF
+C1331 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/D vssa1 0.96fF
+C1332 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/clock_inverter_0/inverter_cp_x1_0/out vssa1 1.76fF
+C1333 res_amp_top_0/res_amp_sync_v2_0/DFlipFlop_0/latch_diff_0/nD vssa1 1.14fF
 .ends
 
diff --git a/xschem/afernandez_residue_amplifier/DFlipFlop.sch b/xschem/afernandez_residue_amplifier/DFlipFlop.sch
deleted file mode 100644
index f8435cd..0000000
--- a/xschem/afernandez_residue_amplifier/DFlipFlop.sch
+++ /dev/null
@@ -1,50 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 150 -210 210 -210 { lab=D_d}
-N 280 -290 280 -250 { lab=vdd}
-N 300 -90 300 -60 { lab=vss}
-N 570 -210 640 -210 { lab=Q}
-N 640 -210 650 -210 { lab=Q}
-N 150 -130 210 -130 { lab=nD_d}
-N 350 -130 390 -130 { lab=nA}
-N 350 -210 390 -210 { lab=A}
-N 390 -210 430 -210 { lab=A}
-N 390 -130 430 -130 { lab=nA}
-N 520 -90 520 -60 { lab=vss}
-N 500 -90 500 -60 { lab=nCLK}
-N 500 -280 500 -250 { lab=vdd}
-N 280 -90 280 -60 { lab=CLK}
-N 570 -130 640 -130 { lab=nQ}
-N 640 -130 650 -130 { lab=nQ}
-N -130 -170 -100 -170 { lab=D}
-N -100 -170 -60 -170 { lab=D}
-N 0 -260 0 -230 { lab=vdd}
-N 0 -110 0 -80 { lab=vss}
-N 60 -150 90 -150 { lab=nD_d}
-N 90 -150 90 -130 { lab=nD_d}
-N 90 -130 150 -130 { lab=nD_d}
-N 60 -190 90 -190 { lab=D_d}
-N 90 -210 90 -190 { lab=D_d}
-N 90 -210 150 -210 { lab=D_d}
-C {iopin.sym} 280 -290 3 0 {name=p1 lab=vdd}
-C {iopin.sym} 300 -60 1 0 {name=p3 lab=vss}
-C {opin.sym} 650 -210 0 0 {name=p7 lab=Q}
-C {lab_pin.sym} 520 -60 3 0 {name=l7 lab=vss}
-C {lab_pin.sym} 500 -280 1 0 {name=l8 lab=vdd}
-C {lab_wire.sym} 380 -130 0 1 {name=l19 lab=nA}
-C {opin.sym} 650 -130 0 0 {name=p2 lab=nQ}
-C {lab_wire.sym} 380 -210 0 1 {name=l1 lab=A}
-C {ipin.sym} -130 -170 0 0 {name=p6 lab=D}
-C {lab_wire.sym} 150 -210 0 0 {name=l27 lab=D_d}
-C {lab_wire.sym} 150 -130 0 0 {name=l28 lab=nD_d}
-C {ipin.sym} 280 -60 3 0 {name=p4 lab=CLK}
-C {ipin.sym} 500 -60 3 0 {name=p5 lab=nCLK}
-C {lab_pin.sym} 0 -260 1 0 {name=l2 lab=vdd}
-C {lab_pin.sym} 0 -80 3 0 {name=l3 lab=vss}
-C {clock_inverter.sym} 0 -170 0 0 {name=x1}
-C {latch_diff.sym} 280 -170 0 0 {name=x2}
-C {latch_diff.sym} 500 -170 0 0 {name=x3}
diff --git a/xschem/afernandez_residue_amplifier/DFlipFlop.sym b/xschem/afernandez_residue_amplifier/DFlipFlop.sym
deleted file mode 100644
index 3498bba..0000000
--- a/xschem/afernandez_residue_amplifier/DFlipFlop.sym
+++ /dev/null
@@ -1,40 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 50 -40 70 -40 {}
-L 4 50 40 70 40 {}
-L 4 -70 -40 -50 -40 {}
-L 4 -70 0 -50 0 {}
-L 4 -50 -60 50 -60 {}
-L 4 -50 60 50 60 {}
-L 4 -50 -10 -40 -0 {}
-L 4 -50 10 -40 -0 {}
-L 4 -50 -60 -50 60 {}
-L 4 50 -60 50 60 {}
-L 4 -70 40 -50 40 {}
-L 4 -50 30 -40 40 {}
-L 4 -50 50 -40 40 {}
-L 7 0 -80 0 -60 {}
-L 7 0 60 0 80 {}
-B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
-B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
-B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
-B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
-B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
-B 5 -72.5 -2.5 -67.5 2.5 {name=CLK dir=in }
-B 5 -72.5 37.5 -67.5 42.5 {name=nCLK dir=in }
-T {@symname} 7 64 0 0 0.3 0.3 {}
-T {@name} -15 -52 0 0 0.2 0.2 {}
-T {vdd} -14 -85 3 1 0.2 0.2 {}
-T {Q} 45 -44 0 1 0.2 0.2 {}
-T {nQ} 45 36 0 1 0.2 0.2 {}
-T {vss} -6 85 1 1 0.2 0.2 {}
-T {D} -45 -44 0 0 0.2 0.2 {}
-T {CLK} -35 -4 0 0 0.2 0.2 {}
-T {nCLK} -35 36 0 0 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/clock_inverter.sch b/xschem/afernandez_residue_amplifier/clock_inverter.sch
deleted file mode 100644
index 7d62fc3..0000000
--- a/xschem/afernandez_residue_amplifier/clock_inverter.sch
+++ /dev/null
@@ -1,41 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N -430 0 -400 0 { lab=CLK}
-N -280 -200 -280 -170 { lab=vdd}
-N -280 -70 -280 -40 { lab=vss}
-N -280 180 -280 210 { lab=vss}
-N -280 50 -280 80 { lab=vdd}
-N -360 -120 -320 -120 { lab=CLK}
-N -400 0 -360 0 { lab=CLK}
-N -70 -200 -70 -170 { lab=vdd}
-N -70 -70 -70 -40 { lab=vss}
-N -360 130 -320 130 { lab=CLK}
-N -360 10 -360 130 { lab=CLK}
-N -360 -110 -360 10 { lab=CLK}
-N -360 -120 -360 -110 { lab=CLK}
-N -40 20 -40 50 { lab=vdd}
-N -40 230 -40 260 { lab=vss}
-N -190 130 -130 130 { lab=#net1}
-N 50 -120 140 -120 { lab=CLK_d}
-N 50 130 140 130 { lab=nCLK_d}
-N 20 -120 50 -120 { lab=CLK_d}
-N -190 -120 -110 -120 { lab=#net2}
-C {ipin.sym} -430 0 0 0 {name=p4 lab=CLK}
-C {iopin.sym} -280 -200 3 0 {name=p1 lab=vdd}
-C {lab_pin.sym} -280 -40 3 0 {name=l5 lab=vss}
-C {trans_gate.sym} -40 130 0 0 {name=x5}
-C {iopin.sym} -280 210 1 0 {name=p11 lab=vss}
-C {lab_pin.sym} -280 50 1 0 {name=l12 lab=vdd}
-C {lab_pin.sym} -70 -200 1 0 {name=l9 lab=vdd}
-C {lab_pin.sym} -70 -40 3 0 {name=l10 lab=vss}
-C {lab_pin.sym} -40 20 1 0 {name=l13 lab=vdd}
-C {lab_pin.sym} -40 260 3 0 {name=l14 lab=vss}
-C {opin.sym} 140 130 0 0 {name=p16 lab=nCLK_d}
-C {opin.sym} 140 -120 0 0 {name=p17 lab=CLK_d}
-C {inverter_cp_x1.sym} -50 -120 0 0 {name=x1}
-C {inverter_cp_x1.sym} -260 -120 0 0 {name=x2}
-C {inverter_cp_x1.sym} -260 130 0 0 {name=x3}
diff --git a/xschem/afernandez_residue_amplifier/clock_inverter.sym b/xschem/afernandez_residue_amplifier/clock_inverter.sym
deleted file mode 100644
index 971d7ed..0000000
--- a/xschem/afernandez_residue_amplifier/clock_inverter.sym
+++ /dev/null
@@ -1,30 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 -40 -40 -40 40 {}
-L 4 40 -40 40 40 {}
-L 4 40 -20 60 -20 {}
-L 4 -60 0 -40 0 {}
-L 4 40 20 60 20 {}
-L 4 -40 -40 40 -40 {}
-L 4 -40 40 40 40 {}
-L 7 0 -60 0 -40 {}
-L 7 0 40 0 60 {}
-B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout }
-B 5 57.5 -22.5 62.5 -17.5 {name=CLK_d dir=out }
-B 5 -62.5 -2.5 -57.5 2.5 {name=CLK dir=in }
-B 5 57.5 17.5 62.5 22.5 {name=nCLK_d dir=out }
-B 5 -2.5 57.5 2.5 62.5 {name=vss dir=inout }
-T {@symname} 9 44 0 0 0.3 0.3 {}
-T {@name} 15 -52 0 0 0.2 0.2 {}
-T {vdd} -14 -65 3 1 0.2 0.2 {}
-T {CLK_d} 35 -24 0 1 0.2 0.2 {}
-T {CLK} -35 -4 0 0 0.2 0.2 {}
-T {nCLK_d} 35 16 0 1 0.2 0.2 {}
-T {vss} -6 65 1 1 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/inverter_cp_x1.sch b/xschem/afernandez_residue_amplifier/inverter_cp_x1.sch
deleted file mode 100644
index c9fe522..0000000
--- a/xschem/afernandez_residue_amplifier/inverter_cp_x1.sch
+++ /dev/null
@@ -1,50 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 250 -60 250 60 { lab=out}
-N 250 0 340 -0 { lab=out}
-N 160 90 210 90 { lab=in}
-N 160 -90 160 90 { lab=in}
-N 160 -90 210 -90 { lab=in}
-N 100 -0 160 -0 { lab=in}
-N 250 -180 250 -120 { lab=vdd}
-N 250 120 250 180 { lab=vss}
-N 250 -90 350 -90 { lab=vdd}
-N 250 90 350 90 { lab=vss}
-C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
-L=0.15
-W=1.25
-nf=1
-mult=3
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_01v8
-spiceprefix=X
-}
-C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
-C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
-C {opin.sym} 340 0 0 0 {name=p3 lab=out}
-C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
-L=0.15
-W=1.25
-nf=1 
-mult=3
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
-C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
-C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
-C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/afernandez_residue_amplifier/inverter_cp_x1.sym b/xschem/afernandez_residue_amplifier/inverter_cp_x1.sym
deleted file mode 100644
index cdda9c9..0000000
--- a/xschem/afernandez_residue_amplifier/inverter_cp_x1.sym
+++ /dev/null
@@ -1,27 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 50 0 70 0 {}
-L 4 -60 0 -40 0 {}
-L 4 -40 40 40 0 {}
-L 4 -40 -40 40 0 {}
-L 4 -40 -40 -40 40 {}
-L 7 -20 -50 -20 -30 {}
-L 7 -20 30 -20 50 {}
-B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
-B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
-B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
-B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
-A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
-T {@symname} -16 30 0 0 0.3 0.3 {}
-T {@name} -23 -6 0 0 0.2 0.2 {}
-T {vdd} -34 -55 3 1 0.2 0.2 {}
-T {out} 67 -13 0 1 0.2 0.2 {}
-T {in} -56 -14 0 0 0.2 0.2 {}
-T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/inverter_min_x4.sch b/xschem/afernandez_residue_amplifier/inverter_min_x4.sch
deleted file mode 100644
index 6f8dda8..0000000
--- a/xschem/afernandez_residue_amplifier/inverter_min_x4.sch
+++ /dev/null
@@ -1,50 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 250 -60 250 60 { lab=out}
-N 250 0 340 -0 { lab=out}
-N 160 90 210 90 { lab=in}
-N 160 -90 160 90 { lab=in}
-N 160 -90 210 -90 { lab=in}
-N 100 -0 160 -0 { lab=in}
-N 250 -180 250 -120 { lab=vdd}
-N 250 120 250 180 { lab=vss}
-N 250 -90 350 -90 { lab=vdd}
-N 250 90 350 90 { lab=vss}
-C {sky130_fd_pr/pfet_01v8.sym} 230 -90 0 0 {name=M2
-L=0.15
-W=0.84
-nf=1
-mult=4
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_01v8
-spiceprefix=X
-}
-C {iopin.sym} 250 180 1 0 {name=p1 lab=vss}
-C {ipin.sym} 100 0 0 0 {name=p2 lab=in}
-C {opin.sym} 340 0 0 0 {name=p3 lab=out}
-C {sky130_fd_pr/nfet_01v8.sym} 230 90 0 0 {name=M1
-L=0.15
-W=0.42
-nf=1 
-mult=4
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
-C {lab_pin.sym} 350 90 2 0 {name=l1 sig_type=std_logic lab=vss}
-C {lab_pin.sym} 350 -90 2 0 {name=l2 sig_type=std_logic lab=vdd}
-C {iopin.sym} 250 -180 3 0 {name=p4 lab=vdd}
diff --git a/xschem/afernandez_residue_amplifier/inverter_min_x4.sym b/xschem/afernandez_residue_amplifier/inverter_min_x4.sym
deleted file mode 100644
index cdda9c9..0000000
--- a/xschem/afernandez_residue_amplifier/inverter_min_x4.sym
+++ /dev/null
@@ -1,27 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 50 0 70 0 {}
-L 4 -60 0 -40 0 {}
-L 4 -40 40 40 0 {}
-L 4 -40 -40 40 0 {}
-L 4 -40 -40 -40 40 {}
-L 7 -20 -50 -20 -30 {}
-L 7 -20 30 -20 50 {}
-B 5 -22.5 -52.5 -17.5 -47.5 {name=vdd dir=inout }
-B 5 67.5 -2.5 72.5 2.5 {name=out dir=out }
-B 5 -62.5 -2.5 -57.5 2.5 {name=in dir=in }
-B 5 -22.5 47.5 -17.5 52.5 {name=vss dir=inout }
-A 4 45 -0.5 5.024937810560445 354.2894068625004 360 {}
-T {@symname} -16 30 0 0 0.3 0.3 {}
-T {@name} -23 -6 0 0 0.2 0.2 {}
-T {vdd} -34 -55 3 1 0.2 0.2 {}
-T {out} 67 -13 0 1 0.2 0.2 {}
-T {in} -56 -14 0 0 0.2 0.2 {}
-T {vss} -22 54 1 1 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/latch_diff.sch b/xschem/afernandez_residue_amplifier/latch_diff.sch
deleted file mode 100644
index 3458830..0000000
--- a/xschem/afernandez_residue_amplifier/latch_diff.sch
+++ /dev/null
@@ -1,120 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 60 80 60 100 { lab=#net1}
-N 60 100 180 100 { lab=#net1}
-N 180 100 180 120 { lab=#net1}
-N 180 100 300 100 { lab=#net1}
-N 300 80 300 100 { lab=#net1}
-N 60 -40 60 20 { lab=nQ}
-N 60 -140 60 -100 { lab=vdd}
-N 60 -140 300 -140 { lab=vdd}
-N 300 -140 300 -100 { lab=vdd}
-N 300 -40 300 20 { lab=Q}
-N 60 50 300 50 { lab=vss}
-N 60 -10 130 -10 { lab=nQ}
-N 130 -10 220 -70 { lab=nQ}
-N 220 -70 260 -70 { lab=nQ}
-N 100 -70 130 -70 { lab=Q}
-N 130 -70 230 -10 { lab=Q}
-N 230 -10 300 -10 { lab=Q}
-N -10 -70 60 -70 { lab=vdd}
-N -10 -140 -10 -70 { lab=vdd}
-N -10 -140 60 -140 { lab=vdd}
-N 300 -70 370 -70 { lab=vdd}
-N 370 -140 370 -70 { lab=vdd}
-N 300 -140 370 -140 { lab=vdd}
-N -10 -10 60 -10 { lab=nQ}
-N 300 -10 370 -10 { lab=Q}
-N -10 50 20 50 { lab=D}
-N 340 50 370 50 { lab=nD}
-N -10 150 140 150 { lab=CLK}
-N 180 180 180 210 { lab=vss}
-N 180 150 220 150 { lab=vss}
-N -30 210 180 210 { lab=vss}
-N -30 -140 -10 -140 { lab=vdd}
-N -30 -10 -10 -10 { lab=nQ}
-N -30 50 -10 50 { lab=D}
-N -30 150 -10 150 { lab=CLK}
-C {sky130_fd_pr/nfet_01v8.sym} 160 150 0 0 {name=M3
-L=0.15
-W=1.25
-nf=1 
-mult=3
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
-C {iopin.sym} -30 -140 2 0 {name=p1 lab=vdd}
-C {iopin.sym} -30 210 2 0 {name=p2 lab=vss}
-C {ipin.sym} -30 50 0 0 {name=p4 lab=D}
-C {opin.sym} -30 -10 2 0 {name=p5 lab=nQ}
-C {ipin.sym} -30 150 0 0 {name=p3 lab=CLK}
-C {lab_pin.sym} 220 150 2 0 {name=l6 lab=vss}
-C {ipin.sym} 370 50 2 0 {name=p6 lab=nD}
-C {opin.sym} 370 -10 0 0 {name=p7 lab=Q}
-C {lab_wire.sym} 160 50 0 1 {name=l1 lab=vss}
-C {sky130_fd_pr/pfet_01v8.sym} 80 -70 0 1 {name=M4
-L=0.15
-W=0.95
-nf=1
-mult=2
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_01v8
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_01v8.sym} 280 -70 0 0 {name=M5
-L=0.15
-W=0.95
-nf=1
-mult=2
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_01v8
-spiceprefix=X
-}
-C {sky130_fd_pr/nfet_01v8.sym} 40 50 0 0 {name=M1
-L=0.15
-W=0.95
-nf=1 
-mult=2
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
-C {sky130_fd_pr/nfet_01v8.sym} 320 50 0 1 {name=M2
-L=0.15
-W=0.95
-nf=1 
-mult=2
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
diff --git a/xschem/afernandez_residue_amplifier/latch_diff.sym b/xschem/afernandez_residue_amplifier/latch_diff.sym
deleted file mode 100644
index 34bb3fc..0000000
--- a/xschem/afernandez_residue_amplifier/latch_diff.sym
+++ /dev/null
@@ -1,36 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 50 40 70 40 {}
-L 4 50 -40 70 -40 {}
-L 4 -70 -40 -50 -40 {}
-L 4 -70 40 -50 40 {}
-L 4 0 60 0 80 {}
-L 4 -50 -60 -50 60 {}
-L 4 50 -60 50 60 {}
-L 4 -50 60 50 60 {}
-L 4 -50 -60 50 -60 {}
-L 7 0 -80 0 -60 {}
-L 7 20 60 20 80 {}
-B 5 -2.5 -82.5 2.5 -77.5 {name=vdd dir=inout }
-B 5 67.5 37.5 72.5 42.5 {name=nQ dir=out }
-B 5 67.5 -42.5 72.5 -37.5 {name=Q dir=out }
-B 5 -72.5 -42.5 -67.5 -37.5 {name=D dir=in }
-B 5 -72.5 37.5 -67.5 42.5 {name=nD dir=in }
-B 5 -2.5 77.5 2.5 82.5 {name=CLK dir=in }
-B 5 17.5 77.5 22.5 82.5 {name=vss dir=inout }
-T {@symname} 7 -76 0 0 0.3 0.3 {}
-T {@name} -15 -2 0 0 0.2 0.2 {}
-T {vdd} -14 -85 3 1 0.2 0.2 {}
-T {nQ} 45 36 0 1 0.2 0.2 {}
-T {Q} 45 -44 0 1 0.2 0.2 {}
-T {D} -45 -44 0 0 0.2 0.2 {}
-T {nD} -45 36 0 0 0.2 0.2 {}
-T {CLK} -14 45 0 0 0.2 0.2 {}
-T {vss} 34 85 1 1 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/trans_gate.sch b/xschem/afernandez_residue_amplifier/trans_gate.sch
deleted file mode 100644
index 138ab52..0000000
--- a/xschem/afernandez_residue_amplifier/trans_gate.sch
+++ /dev/null
@@ -1,62 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 380 -100 380 -70 { lab=vss}
-N 380 70 380 100 { lab=vdd}
-N 310 -100 350 -100 { lab=in}
-N 310 -100 310 -40 { lab=in}
-N 280 -40 310 -40 { lab=in}
-N 280 -40 280 0 { lab=in}
-N 310 100 350 100 { lab=in}
-N 310 40 310 100 { lab=in}
-N 280 40 310 40 { lab=in}
-N 280 0 280 40 { lab=in}
-N 410 100 450 100 { lab=out}
-N 450 40 450 100 { lab=out}
-N 450 40 480 40 { lab=out}
-N 480 0 480 40 { lab=out}
-N 410 -100 450 -100 { lab=out}
-N 450 -100 450 -40 { lab=out}
-N 450 -40 480 -40 { lab=out}
-N 480 -40 480 0 { lab=out}
-N 480 -0 540 0 { lab=out}
-N 220 -0 280 0 { lab=in}
-N 380 140 380 170 { lab=vss}
-N 380 -170 380 -140 { lab=vdd}
-C {sky130_fd_pr/pfet_01v8.sym} 380 120 3 0 {name=M2
-L=0.15
-W=1.25
-nf=1
-mult=3
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_01v8
-spiceprefix=X
-}
-C {iopin.sym} 380 170 1 0 {name=p1 lab=vss}
-C {ipin.sym} 220 0 0 0 {name=p2 lab=in}
-C {opin.sym} 540 0 0 0 {name=p3 lab=out}
-C {sky130_fd_pr/nfet_01v8.sym} 380 -120 1 0 {name=M1
-L=0.15
-W=1.25
-nf=1 
-mult=3
-ad="'int((nf+1)/2) * W/nf * 0.29'" 
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'" 
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_01v8
-spiceprefix=X
-}
-C {lab_pin.sym} 380 -70 3 0 {name=l1 sig_type=std_logic lab=vss}
-C {lab_pin.sym} 380 70 1 0 {name=l2 sig_type=std_logic lab=vdd}
-C {iopin.sym} 380 -170 3 0 {name=p4 lab=vdd}
diff --git a/xschem/afernandez_residue_amplifier/trans_gate.sym b/xschem/afernandez_residue_amplifier/trans_gate.sym
deleted file mode 100644
index 54b0866..0000000
--- a/xschem/afernandez_residue_amplifier/trans_gate.sym
+++ /dev/null
@@ -1,49 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 70 0 90 0 {}
-L 4 -90 0 -70 0 {}
-L 4 -20 -50 20 -50 {}
-L 4 -20 -40 20 -40 {}
-L 4 20 -40 20 -20 {}
-L 4 20 -20 40 -20 {}
-L 4 40 -20 40 0 {}
-L 4 40 0 60 0 {}
-L 4 -20 -40 -20 -20 {}
-L 4 -40 -20 -20 -20 {}
-L 4 -40 -20 -40 0 {}
-L 4 -60 0 -40 0 {}
-L 4 -20 50 20 50 {}
-L 4 -20 40 20 40 {}
-L 4 -20 20 -20 40 {}
-L 4 -40 20 -20 20 {}
-L 4 -40 0 -40 20 {}
-L 4 20 20 20 40 {}
-L 4 20 20 40 20 {}
-L 4 40 0 40 20 {}
-L 4 0 -60 -0 -50 {}
-L 4 0 60 0 70 {}
-L 4 -70 80 -0 80 {}
-L 4 -70 -70 -70 80 {}
-L 4 -70 -70 70 -70 {}
-L 4 70 -70 70 80 {}
-L 4 0 80 70 80 {}
-L 7 0 -90 0 -70 {}
-L 7 0 80 0 100 {}
-B 5 -2.5 -92.5 2.5 -87.5 {name=vdd dir=inout }
-B 5 87.5 -2.5 92.5 2.5 {name=out dir=out }
-B 5 -92.5 -2.5 -87.5 2.5 {name=in dir=in }
-B 5 -2.5 97.5 2.5 102.5 {name=vss dir=inout }
-A 4 0 55.5 5.024937810560445 354.2894068625004 360 {}
-T {@symname} 14 90 0 0 0.3 0.3 {}
-T {@name} -23 -6 0 0 0.2 0.2 {}
-T {vdd} -14 -95 3 1 0.2 0.2 {}
-T {out} 87 -13 0 1 0.2 0.2 {}
-T {in} -86 -14 0 0 0.2 0.2 {}
-T {vss} -2 104 1 1 0.2 0.2 {}
diff --git a/xschem/afernandez_residue_amplifier/buffer_no_inv_x05.sch b/xschem/buffer_no_inv_x05.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/buffer_no_inv_x05.sch
rename to xschem/buffer_no_inv_x05.sch
diff --git a/xschem/afernandez_residue_amplifier/buffer_no_inv_x05.sym b/xschem/buffer_no_inv_x05.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/buffer_no_inv_x05.sym
rename to xschem/buffer_no_inv_x05.sym
diff --git a/xschem/afernandez_residue_amplifier/delay_cell_buff.sch b/xschem/delay_cell_buff.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/delay_cell_buff.sch
rename to xschem/delay_cell_buff.sch
diff --git a/xschem/afernandez_residue_amplifier/delay_cell_buff.sym b/xschem/delay_cell_buff.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/delay_cell_buff.sym
rename to xschem/delay_cell_buff.sym
diff --git a/xschem/afernandez_residue_amplifier/inverter_min.sch b/xschem/inverter_min.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/inverter_min.sch
rename to xschem/inverter_min.sch
diff --git a/xschem/afernandez_residue_amplifier/inverter_min.sym b/xschem/inverter_min.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/inverter_min.sym
rename to xschem/inverter_min.sym
diff --git a/xschem/afernandez_residue_amplifier/inverter_min_x16.sch b/xschem/inverter_min_x16.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/inverter_min_x16.sch
rename to xschem/inverter_min_x16.sch
diff --git a/xschem/afernandez_residue_amplifier/inverter_min_x16.sym b/xschem/inverter_min_x16.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/inverter_min_x16.sym
rename to xschem/inverter_min_x16.sym
diff --git a/xschem/afernandez_residue_amplifier/iref_ctrl_res_amp.sch b/xschem/iref_ctrl_res_amp.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/iref_ctrl_res_amp.sch
rename to xschem/iref_ctrl_res_amp.sch
diff --git a/xschem/afernandez_residue_amplifier/iref_ctrl_res_amp.sym b/xschem/iref_ctrl_res_amp.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/iref_ctrl_res_amp.sym
rename to xschem/iref_ctrl_res_amp.sym
diff --git a/xschem/afernandez_residue_amplifier/mux_2to1_logic.sch b/xschem/mux_2to1_logic.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/mux_2to1_logic.sch
rename to xschem/mux_2to1_logic.sch
diff --git a/xschem/afernandez_residue_amplifier/mux_2to1_logic.sym b/xschem/mux_2to1_logic.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/mux_2to1_logic.sym
rename to xschem/mux_2to1_logic.sym
diff --git a/xschem/afernandez_residue_amplifier/nand_logic.sch b/xschem/nand_logic.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/nand_logic.sch
rename to xschem/nand_logic.sch
diff --git a/xschem/afernandez_residue_amplifier/nand_logic.sym b/xschem/nand_logic.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/nand_logic.sym
rename to xschem/nand_logic.sym
diff --git a/xschem/afernandez_residue_amplifier/res_amp_lin.sch b/xschem/res_amp_lin.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_lin.sch
rename to xschem/res_amp_lin.sch
diff --git a/xschem/afernandez_residue_amplifier/res_amp_lin.sym b/xschem/res_amp_lin.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_lin.sym
rename to xschem/res_amp_lin.sym
diff --git a/xschem/afernandez_residue_amplifier/res_amp_lin_prog.sch b/xschem/res_amp_lin_prog.sch
similarity index 95%
rename from xschem/afernandez_residue_amplifier/res_amp_lin_prog.sch
rename to xschem/res_amp_lin_prog.sch
index 76975e6..84a4843 100644
--- a/xschem/afernandez_residue_amplifier/res_amp_lin_prog.sch
+++ b/xschem/res_amp_lin_prog.sch
@@ -91,9 +91,6 @@
 N 3730 -810 3780 -810 { lab=outn_cap}
 N 3730 -790 3780 -790 { lab=outp_cap}
 N 3970 -550 3970 -500 { lab=rst}
-N 3370 -530 3370 -490 { lab=avss1p8}
-N 3370 -490 3640 -490 { lab=avss1p8}
-N 3640 -520 3640 -490 { lab=avss1p8}
 C {ipin.sym} 2550 -430 0 0 {name=p4 lab=clk}
 C {opin.sym} 3780 -830 0 0 {name=p7 lab=outp}
 C {opin.sym} 3780 -850 0 0 {name=p8 lab=outn}
@@ -231,14 +228,3 @@
 C {ipin.sym} 2780 -320 3 0 {name=p13 lab=delay_reg1}
 C {ipin.sym} 2790 -320 3 0 {name=p14 lab=delay_reg2}
 C {ipin.sym} 3970 -500 3 0 {name=p17 lab=rst}
-C {capa.sym} 3370 -560 0 0 {name=C1
-m=1
-value=\{C\}
-footprint=1206
-device="ceramic capacitor"}
-C {capa.sym} 3640 -550 0 0 {name=C2
-m=1
-value=\{C\}
-footprint=1206
-device="ceramic capacitor"}
-C {lab_wire.sym} 3540 -490 0 0 {name=l3 sig_type=std_logic lab=avss1p8}
diff --git a/xschem/afernandez_residue_amplifier/res_amp_lin_prog.sym b/xschem/res_amp_lin_prog.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_lin_prog.sym
rename to xschem/res_amp_lin_prog.sym
diff --git a/xschem/afernandez_residue_amplifier/res_amp_sync_v2.sch b/xschem/res_amp_sync_v2.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_sync_v2.sch
rename to xschem/res_amp_sync_v2.sch
diff --git a/xschem/afernandez_residue_amplifier/res_amp_sync_v2.sym b/xschem/res_amp_sync_v2.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_sync_v2.sym
rename to xschem/res_amp_sync_v2.sym
diff --git a/xschem/afernandez_residue_amplifier/res_amp_top.sch b/xschem/res_amp_top.sch
similarity index 84%
rename from xschem/afernandez_residue_amplifier/res_amp_top.sch
rename to xschem/res_amp_top.sch
index 3b98c1a..afc412a 100644
--- a/xschem/afernandez_residue_amplifier/res_amp_top.sch
+++ b/xschem/res_amp_top.sch
@@ -37,6 +37,11 @@
 N 1220 180 1220 250 { lab=iref2}
 N 1240 180 1240 250 { lab=iref3}
 N 1260 180 1260 250 { lab=iref4}
+N 890 220 890 250 { lab=avss1p8}
+N 890 250 1000 250 { lab=avss1p8}
+N 1000 220 1000 250 { lab=avss1p8}
+N 890 110 890 160 { lab=outp_cap}
+N 1000 110 1000 160 { lab=outn_cap}
 C {res_amp_lin_prog.sym} 740 140 0 0 {name=x2}
 C {lab_wire.sym} 530 -80 0 0 {name=l31 sig_type=std_logic lab=rst}
 C {lab_wire.sym} 930 -60 0 0 {name=l32 sig_type=std_logic lab=outn_amp}
@@ -75,3 +80,8 @@
 C {ipin.sym} 630 150 3 0 {name=p17 lab=delay_reg0}
 C {ipin.sym} 640 150 3 0 {name=p18 lab=delay_reg1}
 C {ipin.sym} 650 150 3 0 {name=p19 lab=delay_reg2}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 890 190 0 0 {name=C1 model=cap_mim_m3_1 W=5.5 L=7.5 MF=1 spiceprefix=X}
+C {lab_wire.sym} 920 250 2 0 {name=l12 sig_type=std_logic lab=avss1p8}
+C {lab_wire.sym} 890 120 0 0 {name=l13 sig_type=std_logic lab=outp_cap}
+C {lab_wire.sym} 1000 130 0 0 {name=l14 sig_type=std_logic lab=outn_cap}
+C {sky130_fd_pr/cap_mim_m3_1.sym} 1000 190 0 0 {name=C2 model=cap_mim_m3_1 W=5.5 L=7.5 MF=1 spiceprefix=X}
diff --git a/xschem/afernandez_residue_amplifier/res_amp_top.sym b/xschem/res_amp_top.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/res_amp_top.sym
rename to xschem/res_amp_top.sym
diff --git a/xschem/simulations/res_amp_lin_prog.spice b/xschem/simulations/res_amp_lin_prog.spice
new file mode 100644
index 0000000..011077d
--- /dev/null
+++ b/xschem/simulations/res_amp_lin_prog.spice
@@ -0,0 +1,260 @@
+**.subckt res_amp_lin_prog clk outp outn avdd1p8 avss1p8 iref inp inn iref_reg0 iref_reg1 iref_reg2
+*+ outp_cap outn_cap delay_reg0 delay_reg1 delay_reg2 rst
+*.ipin clk
+*.opin outp
+*.opin outn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref
+*.ipin inp
+*.ipin inn
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.opin outp_cap
+*.opin outn_cap
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+*.ipin rst
+x3 avdd1p8 clk avss1p8 clk_out delay_reg0 delay_reg1 delay_reg2 delay_cell_buff
+XM3 outn_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+x4 avdd1p8 clk_out inp inn outp outn avss1p8 vctrl res_amp_lin
+XM1 outp clk_out_b outp_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5 
+XM2 outn clk_out_b outn_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5 
+XM5 outp_cap clk_out outp avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM6 outn_cap clk_out outn avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+x5 avdd1p8 clk_out_b clk_out avss1p8 inverter_min_x4
+XM4 outp_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+x7 avdd1p8 iref avss1p8 vctrl iref_reg0 iref_reg1 iref_reg2 iref_ctrl_res_amp
+**.ends
+
+* expanding   symbol:  delay_cell_buff.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sch
+.subckt delay_cell_buff  avdd1p8 clk avss1p8 clk_out reg0 reg1 reg2
+*.ipin clk
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin clk_out
+*.ipin reg2
+*.ipin reg1
+*.ipin reg0
+x1 avdd1p8 reg2 avss1p8 clk3 net1 clk2 mux_2to1_logic
+x2 avdd1p8 reg2 avss1p8 clk1 net2 clk mux_2to1_logic
+x3 avdd1p8 reg1 avss1p8 net1 net3 net2 mux_2to1_logic
+x4 avdd1p8 out_mux clk_out clk avss1p8 nand_logic
+x513 avdd1p8 clk avss1p8 clk1_int buffer_no_inv_x05
+x512 avdd1p8 clk1_int avss1p8 clk1 buffer_no_inv_x05
+x511 avdd1p8 clk1 avss1p8 clk2_int buffer_no_inv_x05
+x510 avdd1p8 clk2_int avss1p8 clk2 buffer_no_inv_x05
+x59 avdd1p8 clk2 avss1p8 clk3_int buffer_no_inv_x05
+x58 avdd1p8 clk3_int avss1p8 clk3 buffer_no_inv_x05
+x57 avdd1p8 clk3 avss1p8 clk4_int buffer_no_inv_x05
+x56 avdd1p8 clk4_int avss1p8 clk4 buffer_no_inv_x05
+x55 avdd1p8 clk4 avss1p8 clk5_int buffer_no_inv_x05
+x54 avdd1p8 clk5_int avss1p8 clk5 buffer_no_inv_x05
+x53 avdd1p8 clk5 avss1p8 clk6_int buffer_no_inv_x05
+x52 avdd1p8 clk6_int avss1p8 clk6 buffer_no_inv_x05
+x51 avdd1p8 clk6 avss1p8 clk7_int buffer_no_inv_x05
+x50 avdd1p8 clk7_int avss1p8 clk7 buffer_no_inv_x05
+x5 avdd1p8 reg2 avss1p8 clk7 net4 clk6 mux_2to1_logic
+x6 avdd1p8 reg2 avss1p8 clk5 net5 clk4 mux_2to1_logic
+x7 avdd1p8 reg1 avss1p8 net4 net6 net5 mux_2to1_logic
+x8 avdd1p8 reg0 avss1p8 net6 out_mux net3 mux_2to1_logic
+.ends
+
+
+* expanding   symbol:  res_amp_lin.sym # of pins=8
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sch
+.subckt res_amp_lin  avdd1p8 clk inp inn outp outn avss1p8 vctrl
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inn
+*.ipin inp
+*.ipin clk
+*.ipin vctrl
+XM6 int clk avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM8 outn clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM9 outp clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 vp vctrl int avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=5 m=5 
+XM1 outn inp vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20 
+XM2 outp inn vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20 
+.ends
+
+
+* expanding   symbol:  inverter_min_x4.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+.subckt inverter_min_x4  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=4 m=4 
+.ends
+
+
+* expanding   symbol:  iref_ctrl_res_amp.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
+.subckt iref_ctrl_res_amp  avdd1p8 iref avss1p8 vctrl reg0 reg1 reg2
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin reg0
+*.ipin reg1
+*.ipin reg2
+*.opin vctrl
+*.ipin iref
+XM7 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM8 vctrl iref net2 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM9 vctrl vctrl net3 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM10 net3 avss1p8 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 vctrl iref net4 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 vctrl iref net5 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4 
+XM3 net4 reg0 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM4 net5 reg1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4 
+XM5 net2 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM6 net1 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM11 vctrl iref net6 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8 
+XM12 net6 reg2 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8 
+.ends
+
+
+* expanding   symbol:  mux_2to1_logic.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
+.subckt mux_2to1_logic  avdd1p8 sel avss1p8 DinB out DinA
+*.ipin DinB
+*.ipin DinA
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin sel
+*.opin out
+XM5 out sel_b DinB avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 DinB sel out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out sel DinA avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 DinA sel_b out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+x1 avdd1p8 sel_b sel avss1p8 inverter_min
+.ends
+
+
+* expanding   symbol:  nand_logic.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sch
+.subckt nand_logic  avdd1p8 in1 out in2 avss1p8
+*.ipin in1
+*.ipin in2
+*.opin out
+*.iopin avdd1p8
+*.iopin avss1p8
+XM4 out in2 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 n1 in1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in2 n1 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 out in1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  buffer_no_inv_x05.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
+.subckt buffer_no_inv_x05  avdd1p8 in avss1p8 out
+*.ipin in
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+x1 avdd1p8 net1 in avss1p8 inverter_min
+x2 avdd1p8 out net1 avss1p8 inverter_min
+.ends
+
+
+* expanding   symbol:  inverter_min.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sch
+.subckt inverter_min  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
+** flattened .save nodes
+.end
diff --git a/xschem/simulations/user_analog_project_wrapper.spice b/xschem/simulations/user_analog_project_wrapper.spice
index 60eacf8..464abdb 100644
--- a/xschem/simulations/user_analog_project_wrapper.spice
+++ b/xschem/simulations/user_analog_project_wrapper.spice
@@ -62,27 +62,31 @@
 x1 iref_cp2 vssa1 vdda1 net13 net12 net6 net1 net5 io_analog[10] io_analog[9] net4 net7 net2
 + gpio_noesd[7] net11 net14 net8 net9 net3 net10 net20 net15 net27 net21 net23 net25 net24 net18 net19 net22 net17
 + net26 net16 net28 top_pll_v1
-x2 vdda1 io_analog[5] iref_cp0 iref_cp1 iref_cp2 net29 net30 net31 net32 net33 net34 net35 bias
-x3 iref_cp1 vssa1 vdda1 net48 net47 net41 net36 net40 io_analog[10] io_analog[8] net39 net42 net37
-+ gpio_noesd[7] net46 net49 net43 net44 net38 net45 net55 net50 net62 net56 net58 net60 net59 net53 net54 net57
-+ net52 net61 net51 net63 gpio_noesd[8] top_pll_v2
-x4 iref_cp0 vssa1 vdda1 net76 net75 net69 net64 net68 io_analog[10] io_analog[7] net67 net70 net65
-+ gpio_noesd[7] net74 net77 net71 net72 net66 net73 net83 net78 net90 net84 net86 net88 net87 net81 net82 net85
-+ net80 net89 net79 net91 top_pll_v1
+x2 vdda1 io_analog[5] iref_cp0 iref_cp1 iref_cp2 net29 net30 iref4 iref2 iref3 iref1 iref0 bias
+x3 iref_cp1 vssa1 vdda1 net43 net42 net36 net31 net35 io_analog[10] io_analog[8] net34 net37 net32
++ gpio_noesd[7] net41 net44 net38 net39 net33 net40 net50 net45 net57 net51 net53 net55 net54 net48 net49 net52
++ net47 net56 net46 net58 gpio_noesd[8] top_pll_v2
+x4 iref_cp0 vssa1 vdda1 net71 net70 net64 net59 net63 io_analog[10] io_analog[7] net62 net65 net60
++ gpio_noesd[7] net69 net72 net66 net67 net61 net68 net78 net73 net85 net79 net81 net83 net82 net76 net77 net80
++ net75 net84 net74 net86 top_pll_v1
 XC1 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
 XC2 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
-XC3 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=9 m=9
+XC3 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=7 m=7
 XC4 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
 XC5 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
 XC6 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
 XC7 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
 XC8 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
 XC9 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=15 m=15
+x5 vdda1 io_analog[3] io_analog[2] io_analog[0] io_analog[1] vssa1 io_analog[6] gpio_noesd[4]
++ gpio_noesd[5] gpio_noesd[6] gpio_noesd[3] gpio_noesd[1] gpio_noesd[2] iref0 io_analog[4] iref1 iref2 iref3 iref4
++ res_amp_top
+XC10 vdda1 vssa1 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=10 m=10
 **.ends
 
 * expanding   symbol:  top_pll_v1.sym # of pins=34
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v1.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v1.sch
 .subckt top_pll_v1  iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
 + pfd_QB vco_D0 lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
 + out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
@@ -136,8 +140,8 @@
 
 
 * expanding   symbol:  bias.sym # of pins=12
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/bias.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/bias.sch
 .subckt bias  vdd iref iref_0 iref_1 iref_2 iref_3 iref_4 iref_5 iref_6 iref_7 iref_8 iref_9
 *.iopin iref
 *.iopin vdd
@@ -221,8 +225,8 @@
 
 
 * expanding   symbol:  top_pll_v2.sym # of pins=35
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v2.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/top_pll_v2.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/top_pll_v2.sch
 .subckt top_pll_v2  iref_cp vss vdd vco_out vco_vctrl Up pfd_QA nUp in_ref out_to_pad Down nDown
 + pfd_QB D0_vco lf_vc out_first_buffer cp_biasp cp_pswitch pfd_reset cp_nswitch out_by_2 out_to_div
 + out_div_by_5 n_out_by_2 div_5_nQ0 div_5_Q1_shift div_5_Q1 n_out_buffer_div_2 out_buffer_div_2 div_5_Q0
@@ -276,9 +280,42 @@
 .ends
 
 
+* expanding   symbol:  res_amp_top.sym # of pins=19
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_top.sch
+.subckt res_amp_top  avdd1p8 inp inn outp outn avss1p8 clkp iref_reg0 iref_reg1 iref_reg2 delay_reg0
++ delay_reg2 delay_reg1 iref0 clkn iref1 iref2 iref3 iref4
+*.ipin inp
+*.ipin inn
+*.ipin clkp
+*.ipin clkn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref0
+*.ipin iref1
+*.ipin iref2
+*.ipin iref3
+*.ipin iref4
+*.opin outn
+*.opin outp
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+x2 avdd1p8 rst inp inn outp_amp outn_amp avss1p8 outp_cap outn_cap clk_amp iref_reg0 iref_reg1
++ iref_reg2 delay_reg0 delay_reg2 delay_reg1 iref0 res_amp_lin_prog
+x1 avdd1p8 clkp clkn avss1p8 clk_amp rst res_amp_sync_v2
+x3 avdd1p8 iref1 outp_cap outp avss1p8 outn_cap outn iref2 iref3 iref4 source_follower_buff_diff
+XC1 outp_cap avss1p8 sky130_fd_pr__cap_mim_m3_1 W=5.5 L=7.5 MF=1 m=1
+XC2 outn_cap avss1p8 sky130_fd_pr__cap_mim_m3_1 W=5.5 L=7.5 MF=1 m=1
+.ends
+
+
 * expanding   symbol:  PFD.sym # of pins=7
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/PFD.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/PFD.sch
 .subckt PFD  vss vdd Up A B Down Reset
 *.iopin vdd
 *.iopin vss
@@ -294,8 +331,8 @@
 
 
 * expanding   symbol:  charge_pump.sym # of pins=11
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/charge_pump.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/charge_pump.sch
 .subckt charge_pump  vdd Up nUp out Down nDown vss iref nswitch pswitch biasp
 *.iopin vss
 *.iopin vdd
@@ -345,8 +382,8 @@
 
 
 * expanding   symbol:  pfd_cp_interface.sym # of pins=8
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/pfd_cp_interface.sch
 .subckt pfd_cp_interface  Up vdd QA nUp Down QB vss nDown
 *.iopin vdd
 *.iopin vss
@@ -366,8 +403,8 @@
 
 
 * expanding   symbol:  loop_filter.sym # of pins=3
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter.sch
 .subckt loop_filter  vss in vc_pex
 *.iopin in
 *.iopin vss
@@ -381,8 +418,8 @@
 
 
 * expanding   symbol:  csvco.sym # of pins=5
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco.sch
 .subckt csvco  vdd out D0 vctrl vss
 *.ipin vctrl
 *.iopin vss
@@ -402,8 +439,8 @@
 
 
 * expanding   symbol:  ring_osc_buffer.sym # of pins=6
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/ring_osc_buffer.sch
 .subckt ring_osc_buffer  vdd in_vco out_pad out_div vss o1
 *.iopin vdd
 *.iopin vss
@@ -418,8 +455,8 @@
 
 
 * expanding   symbol:  div_by_5.sym # of pins=10
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_5.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_5.sch
 .subckt div_by_5  vdd CLK_5 CLK vss nCLK nQ2 Q1 nQ0 Q0 Q1_shift
 *.iopin vdd
 *.iopin vss
@@ -443,8 +480,8 @@
 
 
 * expanding   symbol:  div_by_2.sym # of pins=9
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/div_by_2.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/div_by_2.sch
 .subckt div_by_2  nCLK_2 vss CLK vdd CLK_2 out_div nout_div o1 o2
 *.ipin CLK
 *.opin CLK_2
@@ -465,8 +502,8 @@
 
 
 * expanding   symbol:  buffer_salida.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/buffer_salida.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_salida.sch
 .subckt buffer_salida  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -494,8 +531,8 @@
 
 
 * expanding   symbol:  loop_filter_v2.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/loop_filter_v2.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/loop_filter_v2.sch
 .subckt loop_filter_v2  vss in vc_pex D0_cap
 *.iopin in
 *.iopin vss
@@ -513,9 +550,103 @@
 .ends
 
 
+* expanding   symbol:  res_amp_lin_prog.sym # of pins=17
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin_prog.sch
+.subckt res_amp_lin_prog  avdd1p8 rst inp inn outp outn avss1p8 outp_cap outn_cap clk iref_reg0
++ iref_reg1 iref_reg2 delay_reg0 delay_reg2 delay_reg1 iref
+*.ipin clk
+*.opin outp
+*.opin outn
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin iref
+*.ipin inp
+*.ipin inn
+*.ipin iref_reg0
+*.ipin iref_reg1
+*.ipin iref_reg2
+*.opin outp_cap
+*.opin outn_cap
+*.ipin delay_reg0
+*.ipin delay_reg1
+*.ipin delay_reg2
+*.ipin rst
+x3 avdd1p8 clk avss1p8 clk_out delay_reg0 delay_reg1 delay_reg2 delay_cell_buff
+XM3 outn_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+x4 avdd1p8 clk_out inp inn outp outn avss1p8 vctrl res_amp_lin
+XM1 outp clk_out_b outp_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5 
+XM2 outn clk_out_b outn_cap avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=5 m=5 
+XM5 outp_cap clk_out outp avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+XM6 outn_cap clk_out outn avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=10 m=10 
+x5 avdd1p8 clk_out_b clk_out avss1p8 inverter_min_x4
+XM4 outp_cap rst avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+x7 avdd1p8 iref avss1p8 vctrl iref_reg0 iref_reg1 iref_reg2 iref_ctrl_res_amp
+.ends
+
+
+* expanding   symbol:  res_amp_sync_v2.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_sync_v2.sch
+.subckt res_amp_sync_v2  avdd1p8 clkp clkn avss1p8 clk_amp rst
+*.ipin clkn
+*.ipin clkp
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin rst
+*.opin clk_amp
+x4 avdd1p8 net1 net3 net2 avss1p8 nand_logic
+x1 avdd1p8 d1 q1 avss1p8 inverter_min_x4
+x5 avdd1p8 pulse net3 avss1p8 inverter_min_x4
+x21 avdd1p8 pulse net6 clkp avss1p8 nand_logic
+x3 avdd1p8 net2 net7 avss1p8 d1 clkp clkn DFlipFlop
+x6 avdd1p8 net1 net8 avss1p8 q2 clkp clkn DFlipFlop
+x7 avdd1p8 q1 net9 avss1p8 d1 clkp clkn DFlipFlop
+x8 avdd1p8 q2 net10 avss1p8 d2 d1 q1 DFlipFlop
+x9 avdd1p8 net4 net11 avss1p8 pulse clkp clkn DFlipFlop
+x2 avdd1p8 d2 q2 avss1p8 inverter_min_x4
+x10 avdd1p8 rst net6 avss1p8 inverter_min_x4
+x11 avdd1p8 net5 net4 avss1p8 inverter_min_x4
+x12 avdd1p8 clk_amp net5 avss1p8 inverter_min_x16
+.ends
+
+
+* expanding   symbol:  source_follower_buff_diff.sym # of pins=10
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_diff.sch
+.subckt source_follower_buff_diff  avdd1p8 iref1 inp outp avss1p8 inn outn iref2 iref3 iref4
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inp
+*.ipin inn
+*.ipin iref1
+*.ipin iref2
+*.ipin iref3
+*.ipin iref4
+x1 avdd1p8 iref1 inp outp_int avss1p8 source_follower_buff_pmos
+x2 avdd1p8 iref2 outp_int outp avss1p8 source_follower_buff_nmos
+x3 avdd1p8 iref3 inn outn_int avss1p8 source_follower_buff_pmos
+x4 avdd1p8 iref4 outn_int outn avss1p8 source_follower_buff_nmos
+.ends
+
+
 * expanding   symbol:  DFF.sym # of pins=5
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFF.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFF.sch
 .subckt DFF  D CLK Q Reset vss
 *.ipin D
 *.ipin CLK
@@ -530,8 +661,8 @@
 
 
 * expanding   symbol:  and_pfd.sym # of pins=5
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/and_pfd.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/and_pfd.sch
 .subckt and_pfd  vdd out A B vss
 *.iopin vdd
 *.iopin vss
@@ -566,8 +697,8 @@
 
 
 * expanding   symbol:  trans_gate.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/trans_gate.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/trans_gate.sch
 .subckt trans_gate  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -583,8 +714,8 @@
 
 
 * expanding   symbol:  inverter_cp_x1.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x1.sch
 .subckt inverter_cp_x1  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -600,8 +731,8 @@
 
 
 * expanding   symbol:  inverter_cp_x2.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_cp_x2.sch
 .subckt inverter_cp_x2  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -617,19 +748,19 @@
 
 
 * expanding   symbol:  res_loop_filter.sym # of pins=3
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/res_loop_filter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_loop_filter.sch
 .subckt res_loop_filter  in out vss
 *.iopin in
 *.iopin vss
 *.iopin out
-XR3 out in vss sky130_fd_pr__res_high_po_5p73 L=22.92 mult=1 m=1
+XR3 out in vss sky130_fd_pr__res_high_po_5p73 W=5.73 L=22.92 mult=1 m=1
 .ends
 
 
 * expanding   symbol:  cap1_loop_filter.sym # of pins=2
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap1_loop_filter.sch
 .subckt cap1_loop_filter  in out
 *.iopin in
 *.iopin out
@@ -638,8 +769,8 @@
 
 
 * expanding   symbol:  cap2_loop_filter.sym # of pins=2
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap2_loop_filter.sch
 .subckt cap2_loop_filter  in out
 *.iopin in
 *.iopin out
@@ -648,8 +779,8 @@
 
 
 * expanding   symbol:  csvco_branch.sym # of pins=7
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/csvco_branch.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/csvco_branch.sch
 .subckt csvco_branch  vdd vbp in out vctrl vss D0
 *.ipin vctrl
 *.ipin vbp
@@ -673,8 +804,8 @@
 
 
 * expanding   symbol:  inverter_min_x2.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x2.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x2.sch
 .subckt inverter_min_x2  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -690,8 +821,8 @@
 
 
 * expanding   symbol:  inverter_min_x4.sym # of pins=4
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_min_x4.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x4.sch
 .subckt inverter_min_x4  vdd out in vss
 *.iopin vss
 *.ipin in
@@ -707,8 +838,8 @@
 
 
 * expanding   symbol:  DFlipFlop.sym # of pins=7
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/DFlipFlop.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/DFlipFlop.sch
 .subckt DFlipFlop  vdd Q nQ vss D CLK nCLK
 *.iopin vdd
 *.iopin vss
@@ -724,8 +855,8 @@
 
 
 * expanding   symbol:  clock_inverter.sym # of pins=5
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/clock_inverter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/clock_inverter.sch
 .subckt clock_inverter  vdd CLK_d CLK nCLK_d vss
 *.ipin CLK
 *.iopin vdd
@@ -740,8 +871,8 @@
 
 
 * expanding   symbol:  cap3_loop_filter.sym # of pins=2
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/cap3_loop_filter.sch
 .subckt cap3_loop_filter  in out
 *.iopin in
 *.iopin out
@@ -749,9 +880,220 @@
 .ends
 
 
+* expanding   symbol:  delay_cell_buff.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/delay_cell_buff.sch
+.subckt delay_cell_buff  avdd1p8 clk avss1p8 clk_out reg0 reg1 reg2
+*.ipin clk
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin clk_out
+*.ipin reg2
+*.ipin reg1
+*.ipin reg0
+x1 avdd1p8 reg2 avss1p8 clk3 net1 clk2 mux_2to1_logic
+x2 avdd1p8 reg2 avss1p8 clk1 net2 clk mux_2to1_logic
+x3 avdd1p8 reg1 avss1p8 net1 net3 net2 mux_2to1_logic
+x4 avdd1p8 out_mux clk_out clk avss1p8 nand_logic
+x513 avdd1p8 clk avss1p8 clk1_int buffer_no_inv_x05
+x512 avdd1p8 clk1_int avss1p8 clk1 buffer_no_inv_x05
+x511 avdd1p8 clk1 avss1p8 clk2_int buffer_no_inv_x05
+x510 avdd1p8 clk2_int avss1p8 clk2 buffer_no_inv_x05
+x59 avdd1p8 clk2 avss1p8 clk3_int buffer_no_inv_x05
+x58 avdd1p8 clk3_int avss1p8 clk3 buffer_no_inv_x05
+x57 avdd1p8 clk3 avss1p8 clk4_int buffer_no_inv_x05
+x56 avdd1p8 clk4_int avss1p8 clk4 buffer_no_inv_x05
+x55 avdd1p8 clk4 avss1p8 clk5_int buffer_no_inv_x05
+x54 avdd1p8 clk5_int avss1p8 clk5 buffer_no_inv_x05
+x53 avdd1p8 clk5 avss1p8 clk6_int buffer_no_inv_x05
+x52 avdd1p8 clk6_int avss1p8 clk6 buffer_no_inv_x05
+x51 avdd1p8 clk6 avss1p8 clk7_int buffer_no_inv_x05
+x50 avdd1p8 clk7_int avss1p8 clk7 buffer_no_inv_x05
+x5 avdd1p8 reg2 avss1p8 clk7 net4 clk6 mux_2to1_logic
+x6 avdd1p8 reg2 avss1p8 clk5 net5 clk4 mux_2to1_logic
+x7 avdd1p8 reg1 avss1p8 net4 net6 net5 mux_2to1_logic
+x8 avdd1p8 reg0 avss1p8 net6 out_mux net3 mux_2to1_logic
+.ends
+
+
+* expanding   symbol:  res_amp_lin.sym # of pins=8
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/res_amp_lin.sch
+.subckt res_amp_lin  avdd1p8 clk inp inn outp outn avss1p8 vctrl
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin outp
+*.opin outn
+*.ipin inn
+*.ipin inp
+*.ipin clk
+*.ipin vctrl
+XM6 int clk avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM8 outn clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM9 outp clk avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM3 vp vctrl int avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=5 m=5 
+XM1 outn inp vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20 
+XM2 outp inn vp avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=20 m=20 
+.ends
+
+
+* expanding   symbol:  iref_ctrl_res_amp.sym # of pins=7
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/iref_ctrl_res_amp.sch
+.subckt iref_ctrl_res_amp  avdd1p8 iref avss1p8 vctrl reg0 reg1 reg2
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin reg0
+*.ipin reg1
+*.ipin reg2
+*.opin vctrl
+*.ipin iref
+XM7 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM8 vctrl iref net2 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM9 vctrl vctrl net3 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM10 net3 avss1p8 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM1 vctrl iref net4 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 vctrl iref net5 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4 
+XM3 net4 reg0 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM4 net5 reg1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=4 m=4 
+XM5 net2 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=3 m=3 
+XM6 net1 avdd1p8 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM11 vctrl iref net6 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8 
+XM12 net6 reg2 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=8 m=8 
+.ends
+
+
+* expanding   symbol:  nand_logic.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nand_logic.sch
+.subckt nand_logic  avdd1p8 in1 out in2 avss1p8
+*.ipin in1
+*.ipin in2
+*.opin out
+*.iopin avdd1p8
+*.iopin avss1p8
+XM4 out in2 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM5 n1 in1 avss1p8 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+XM1 out in2 n1 avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=2 m=2 
+XM2 out in1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1.02 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=2 m=2 
+.ends
+
+
+* expanding   symbol:  inverter_min_x16.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min_x16.sch
+.subckt inverter_min_x16  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=16 m=16 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=16 m=16 
+.ends
+
+
+* expanding   symbol:  source_follower_buff_pmos.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_pmos.sch
+.subckt source_follower_buff_pmos  avdd1p8 iref in out avss1p8
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+*.ipin in
+*.ipin iref
+XM5 net1 net1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15 
+XM6 out net1 avdd1p8 avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=15 m=15 
+XM1 avss1p8 in out avdd1p8 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=20 m=20 
+XM2 iref iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM3 net1 iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+
+* expanding   symbol:  source_follower_buff_nmos.sym # of pins=5
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/source_follower_buff_nmos.sch
+.subckt source_follower_buff_nmos  avdd1p8 iref in out avss1p8
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+*.ipin in
+*.ipin iref
+XM2 net1 iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+XM1 out iref avss1p8 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=160 m=160 
+XM3 avdd1p8 in out avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=80 m=80 
+XM4 iref iref net1 avss1p8 sky130_fd_pr__nfet_01v8_lvt L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=6 m=6 
+.ends
+
+
 * expanding   symbol:  nor.sym # of pins=5
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/nor.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/nor.sch
 .subckt nor  vdd A B out vss
 *.ipin A
 *.ipin B
@@ -780,8 +1122,8 @@
 
 
 * expanding   symbol:  inverter_csvco.sym # of pins=6
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/inverter_csvco.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_csvco.sch
 .subckt inverter_csvco  vdd out in vss vbulkp vbulkn
 *.iopin vss
 *.ipin in
@@ -799,8 +1141,8 @@
 
 
 * expanding   symbol:  latch_diff.sym # of pins=7
-* sym_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sym
-* sch_path: /home/dhernando/caravel_analog_fulgor/xschem/latch_diff.sch
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/latch_diff.sch
 .subckt latch_diff  vdd nQ Q D nD CLK vss
 *.iopin vdd
 *.iopin vss
@@ -826,5 +1168,61 @@
 + sa=0 sb=0 sd=0 mult=2 m=2 
 .ends
 
+
+* expanding   symbol:  mux_2to1_logic.sym # of pins=6
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/mux_2to1_logic.sch
+.subckt mux_2to1_logic  avdd1p8 sel avss1p8 DinB out DinA
+*.ipin DinB
+*.ipin DinA
+*.iopin avdd1p8
+*.iopin avss1p8
+*.ipin sel
+*.opin out
+XM5 out sel_b DinB avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM6 DinB sel out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM2 out sel DinA avdd1p8 sky130_fd_pr__pfet_01v8 L=0.15 W=2.22 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+XM7 DinA sel_b out avss1p8 sky130_fd_pr__nfet_01v8 L=0.15 W=1.11 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 
+x1 avdd1p8 sel_b sel avss1p8 inverter_min
+.ends
+
+
+* expanding   symbol:  buffer_no_inv_x05.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/buffer_no_inv_x05.sch
+.subckt buffer_no_inv_x05  avdd1p8 in avss1p8 out
+*.ipin in
+*.iopin avdd1p8
+*.iopin avss1p8
+*.opin out
+x1 avdd1p8 net1 in avss1p8 inverter_min
+x2 avdd1p8 out net1 avss1p8 inverter_min
+.ends
+
+
+* expanding   symbol:  inverter_min.sym # of pins=4
+* sym_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sym
+* sch_path: /home/afernandez/caravel_analog_fulgor/xschem/inverter_min.sch
+.subckt inverter_min  vdd out in vss
+*.iopin vss
+*.ipin in
+*.opin out
+*.iopin vdd
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+XM1 out in vss vss sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1 
+.ends
+
 ** flattened .save nodes
 .end
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_diff.sch b/xschem/source_follower_buff_diff.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_diff.sch
rename to xschem/source_follower_buff_diff.sch
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_diff.sym b/xschem/source_follower_buff_diff.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_diff.sym
rename to xschem/source_follower_buff_diff.sym
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_nmos.sch b/xschem/source_follower_buff_nmos.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_nmos.sch
rename to xschem/source_follower_buff_nmos.sch
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_nmos.sym b/xschem/source_follower_buff_nmos.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_nmos.sym
rename to xschem/source_follower_buff_nmos.sym
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_pmos.sch b/xschem/source_follower_buff_pmos.sch
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_pmos.sch
rename to xschem/source_follower_buff_pmos.sch
diff --git a/xschem/afernandez_residue_amplifier/source_follower_buff_pmos.sym b/xschem/source_follower_buff_pmos.sym
similarity index 100%
rename from xschem/afernandez_residue_amplifier/source_follower_buff_pmos.sym
rename to xschem/source_follower_buff_pmos.sym
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index 1d46956..62d50fa 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch
@@ -75,74 +75,74 @@
 N 3950 -270 4000 -270 { lab=#net29}
 N 4000 -250 4050 -250 { lab=#net30}
 N 3950 -250 4000 -250 { lab=#net30}
-N 4000 -230 4050 -230 { lab=#net31}
-N 3950 -230 4000 -230 { lab=#net31}
-N 4000 -210 4050 -210 { lab=#net32}
-N 3950 -210 4000 -210 { lab=#net32}
-N 4000 -190 4050 -190 { lab=#net33}
-N 3950 -190 4000 -190 { lab=#net33}
-N 4000 -170 4050 -170 { lab=#net34}
-N 3950 -170 4000 -170 { lab=#net34}
-N 4000 -150 4050 -150 { lab=#net35}
-N 3950 -150 4000 -150 { lab=#net35}
+N 4000 -230 4050 -230 { lab=iref4}
+N 3950 -230 4000 -230 { lab=iref4}
+N 4000 -210 4050 -210 { lab=iref2}
+N 3950 -210 4000 -210 { lab=iref2}
+N 4000 -190 4050 -190 { lab=iref3}
+N 3950 -190 4000 -190 { lab=iref3}
+N 4000 -170 4050 -170 { lab=iref1}
+N 3950 -170 4000 -170 { lab=iref1}
+N 4000 -150 4050 -150 { lab=iref0}
+N 3950 -150 4000 -150 { lab=iref0}
 N 5660 160 5660 220 { lab=vdda1}
 N 5720 160 5720 220 { lab=vssa1}
-N 5240 530 5240 580 { lab=#net36}
-N 5240 480 5240 530 { lab=#net36}
-N 5220 530 5220 580 { lab=#net37}
-N 5220 480 5220 530 { lab=#net37}
-N 5200 530 5200 580 { lab=#net38}
-N 5200 480 5200 530 { lab=#net38}
-N 5310 530 5310 580 { lab=#net39}
-N 5310 480 5310 530 { lab=#net39}
-N 5290 530 5290 580 { lab=#net40}
-N 5290 480 5290 530 { lab=#net40}
-N 5270 530 5270 580 { lab=#net41}
-N 5270 480 5270 530 { lab=#net41}
-N 5330 530 5330 580 { lab=#net42}
-N 5330 480 5330 530 { lab=#net42}
-N 5400 530 5400 580 { lab=#net43}
-N 5400 480 5400 530 { lab=#net43}
-N 5380 530 5380 580 { lab=#net44}
-N 5380 480 5380 530 { lab=#net44}
-N 5360 530 5360 580 { lab=#net45}
-N 5360 480 5360 530 { lab=#net45}
-N 5430 530 5430 580 { lab=#net46}
-N 5430 480 5430 530 { lab=#net46}
-N 5460 530 5460 580 { lab=#net47}
-N 5460 480 5460 530 { lab=#net47}
-N 5480 530 5480 580 { lab=#net48}
-N 5480 480 5480 530 { lab=#net48}
-N 5500 530 5500 580 { lab=#net49}
-N 5500 480 5500 530 { lab=#net49}
-N 5520 530 5520 580 { lab=#net50}
-N 5520 480 5520 530 { lab=#net50}
-N 5550 530 5550 580 { lab=#net51}
-N 5550 480 5550 530 { lab=#net51}
-N 5570 530 5570 580 { lab=#net52}
-N 5570 480 5570 530 { lab=#net52}
-N 5590 530 5590 580 { lab=#net53}
-N 5590 480 5590 530 { lab=#net53}
-N 5610 530 5610 580 { lab=#net54}
-N 5610 480 5610 530 { lab=#net54}
-N 5630 530 5630 580 { lab=#net55}
-N 5630 480 5630 530 { lab=#net55}
-N 5650 530 5650 580 { lab=#net56}
-N 5650 480 5650 530 { lab=#net56}
-N 5680 530 5680 580 { lab=#net57}
-N 5680 480 5680 530 { lab=#net57}
-N 5700 530 5700 580 { lab=#net58}
-N 5700 480 5700 530 { lab=#net58}
-N 5720 530 5720 580 { lab=#net59}
-N 5720 480 5720 530 { lab=#net59}
-N 5740 530 5740 580 { lab=#net60}
-N 5740 480 5740 530 { lab=#net60}
-N 5760 530 5760 580 { lab=#net61}
-N 5760 480 5760 530 { lab=#net61}
-N 5780 530 5780 580 { lab=#net62}
-N 5780 480 5780 530 { lab=#net62}
-N 5830 530 5830 580 { lab=#net63}
-N 5830 480 5830 530 { lab=#net63}
+N 5240 530 5240 580 { lab=#net31}
+N 5240 480 5240 530 { lab=#net31}
+N 5220 530 5220 580 { lab=#net32}
+N 5220 480 5220 530 { lab=#net32}
+N 5200 530 5200 580 { lab=#net33}
+N 5200 480 5200 530 { lab=#net33}
+N 5310 530 5310 580 { lab=#net34}
+N 5310 480 5310 530 { lab=#net34}
+N 5290 530 5290 580 { lab=#net35}
+N 5290 480 5290 530 { lab=#net35}
+N 5270 530 5270 580 { lab=#net36}
+N 5270 480 5270 530 { lab=#net36}
+N 5330 530 5330 580 { lab=#net37}
+N 5330 480 5330 530 { lab=#net37}
+N 5400 530 5400 580 { lab=#net38}
+N 5400 480 5400 530 { lab=#net38}
+N 5380 530 5380 580 { lab=#net39}
+N 5380 480 5380 530 { lab=#net39}
+N 5360 530 5360 580 { lab=#net40}
+N 5360 480 5360 530 { lab=#net40}
+N 5430 530 5430 580 { lab=#net41}
+N 5430 480 5430 530 { lab=#net41}
+N 5460 530 5460 580 { lab=#net42}
+N 5460 480 5460 530 { lab=#net42}
+N 5480 530 5480 580 { lab=#net43}
+N 5480 480 5480 530 { lab=#net43}
+N 5500 530 5500 580 { lab=#net44}
+N 5500 480 5500 530 { lab=#net44}
+N 5520 530 5520 580 { lab=#net45}
+N 5520 480 5520 530 { lab=#net45}
+N 5550 530 5550 580 { lab=#net46}
+N 5550 480 5550 530 { lab=#net46}
+N 5570 530 5570 580 { lab=#net47}
+N 5570 480 5570 530 { lab=#net47}
+N 5590 530 5590 580 { lab=#net48}
+N 5590 480 5590 530 { lab=#net48}
+N 5610 530 5610 580 { lab=#net49}
+N 5610 480 5610 530 { lab=#net49}
+N 5630 530 5630 580 { lab=#net50}
+N 5630 480 5630 530 { lab=#net50}
+N 5650 530 5650 580 { lab=#net51}
+N 5650 480 5650 530 { lab=#net51}
+N 5680 530 5680 580 { lab=#net52}
+N 5680 480 5680 530 { lab=#net52}
+N 5700 530 5700 580 { lab=#net53}
+N 5700 480 5700 530 { lab=#net53}
+N 5720 530 5720 580 { lab=#net54}
+N 5720 480 5720 530 { lab=#net54}
+N 5740 530 5740 580 { lab=#net55}
+N 5740 480 5740 530 { lab=#net55}
+N 5760 530 5760 580 { lab=#net56}
+N 5760 480 5760 530 { lab=#net56}
+N 5780 530 5780 580 { lab=#net57}
+N 5780 480 5780 530 { lab=#net57}
+N 5830 530 5830 580 { lab=#net58}
+N 5830 480 5830 530 { lab=#net58}
 N 5950 350 6000 350 { lab=io_analog[8]}
 N 5900 350 5950 350 { lab=io_analog[8]}
 N 5070 350 5140 350 { lab=io_analog[10]}
@@ -153,62 +153,62 @@
 N 5340 150 5340 220 { lab=gpio_noesd[8]}
 N 6880 160 6880 220 { lab=vdda1}
 N 6940 160 6940 220 { lab=vssa1}
-N 6460 530 6460 580 { lab=#net64}
-N 6460 480 6460 530 { lab=#net64}
-N 6440 530 6440 580 { lab=#net65}
-N 6440 480 6440 530 { lab=#net65}
-N 6420 530 6420 580 { lab=#net66}
-N 6420 480 6420 530 { lab=#net66}
-N 6530 530 6530 580 { lab=#net67}
-N 6530 480 6530 530 { lab=#net67}
-N 6510 530 6510 580 { lab=#net68}
-N 6510 480 6510 530 { lab=#net68}
-N 6490 530 6490 580 { lab=#net69}
-N 6490 480 6490 530 { lab=#net69}
-N 6550 530 6550 580 { lab=#net70}
-N 6550 480 6550 530 { lab=#net70}
-N 6620 530 6620 580 { lab=#net71}
-N 6620 480 6620 530 { lab=#net71}
-N 6600 530 6600 580 { lab=#net72}
-N 6600 480 6600 530 { lab=#net72}
-N 6580 530 6580 580 { lab=#net73}
-N 6580 480 6580 530 { lab=#net73}
-N 6650 530 6650 580 { lab=#net74}
-N 6650 480 6650 530 { lab=#net74}
-N 6680 530 6680 580 { lab=#net75}
-N 6680 480 6680 530 { lab=#net75}
-N 6700 530 6700 580 { lab=#net76}
-N 6700 480 6700 530 { lab=#net76}
-N 6720 530 6720 580 { lab=#net77}
-N 6720 480 6720 530 { lab=#net77}
-N 6740 530 6740 580 { lab=#net78}
-N 6740 480 6740 530 { lab=#net78}
-N 6770 530 6770 580 { lab=#net79}
-N 6770 480 6770 530 { lab=#net79}
-N 6790 530 6790 580 { lab=#net80}
-N 6790 480 6790 530 { lab=#net80}
-N 6810 530 6810 580 { lab=#net81}
-N 6810 480 6810 530 { lab=#net81}
-N 6830 530 6830 580 { lab=#net82}
-N 6830 480 6830 530 { lab=#net82}
-N 6850 530 6850 580 { lab=#net83}
-N 6850 480 6850 530 { lab=#net83}
-N 6870 530 6870 580 { lab=#net84}
-N 6870 480 6870 530 { lab=#net84}
-N 6900 530 6900 580 { lab=#net85}
-N 6900 480 6900 530 { lab=#net85}
-N 6920 530 6920 580 { lab=#net86}
-N 6920 480 6920 530 { lab=#net86}
-N 6940 530 6940 580 { lab=#net87}
-N 6940 480 6940 530 { lab=#net87}
-N 6960 530 6960 580 { lab=#net88}
-N 6960 480 6960 530 { lab=#net88}
-N 6980 530 6980 580 { lab=#net89}
-N 6980 480 6980 530 { lab=#net89}
-N 7000 530 7000 580 { lab=#net90}
-N 7000 480 7000 530 { lab=#net90}
-N 7050 530 7050 580 { lab=#net91}
-N 7050 480 7050 530 { lab=#net91}
+N 6460 530 6460 580 { lab=#net59}
+N 6460 480 6460 530 { lab=#net59}
+N 6440 530 6440 580 { lab=#net60}
+N 6440 480 6440 530 { lab=#net60}
+N 6420 530 6420 580 { lab=#net61}
+N 6420 480 6420 530 { lab=#net61}
+N 6530 530 6530 580 { lab=#net62}
+N 6530 480 6530 530 { lab=#net62}
+N 6510 530 6510 580 { lab=#net63}
+N 6510 480 6510 530 { lab=#net63}
+N 6490 530 6490 580 { lab=#net64}
+N 6490 480 6490 530 { lab=#net64}
+N 6550 530 6550 580 { lab=#net65}
+N 6550 480 6550 530 { lab=#net65}
+N 6620 530 6620 580 { lab=#net66}
+N 6620 480 6620 530 { lab=#net66}
+N 6600 530 6600 580 { lab=#net67}
+N 6600 480 6600 530 { lab=#net67}
+N 6580 530 6580 580 { lab=#net68}
+N 6580 480 6580 530 { lab=#net68}
+N 6650 530 6650 580 { lab=#net69}
+N 6650 480 6650 530 { lab=#net69}
+N 6680 530 6680 580 { lab=#net70}
+N 6680 480 6680 530 { lab=#net70}
+N 6700 530 6700 580 { lab=#net71}
+N 6700 480 6700 530 { lab=#net71}
+N 6720 530 6720 580 { lab=#net72}
+N 6720 480 6720 530 { lab=#net72}
+N 6740 530 6740 580 { lab=#net73}
+N 6740 480 6740 530 { lab=#net73}
+N 6770 530 6770 580 { lab=#net74}
+N 6770 480 6770 530 { lab=#net74}
+N 6790 530 6790 580 { lab=#net75}
+N 6790 480 6790 530 { lab=#net75}
+N 6810 530 6810 580 { lab=#net76}
+N 6810 480 6810 530 { lab=#net76}
+N 6830 530 6830 580 { lab=#net77}
+N 6830 480 6830 530 { lab=#net77}
+N 6850 530 6850 580 { lab=#net78}
+N 6850 480 6850 530 { lab=#net78}
+N 6870 530 6870 580 { lab=#net79}
+N 6870 480 6870 530 { lab=#net79}
+N 6900 530 6900 580 { lab=#net80}
+N 6900 480 6900 530 { lab=#net80}
+N 6920 530 6920 580 { lab=#net81}
+N 6920 480 6920 530 { lab=#net81}
+N 6940 530 6940 580 { lab=#net82}
+N 6940 480 6940 530 { lab=#net82}
+N 6960 530 6960 580 { lab=#net83}
+N 6960 480 6960 530 { lab=#net83}
+N 6980 530 6980 580 { lab=#net84}
+N 6980 480 6980 530 { lab=#net84}
+N 7000 530 7000 580 { lab=#net85}
+N 7000 480 7000 530 { lab=#net85}
+N 7050 530 7050 580 { lab=#net86}
+N 7050 480 7050 530 { lab=#net86}
 N 7170 350 7220 350 { lab=io_analog[7]}
 N 7120 350 7170 350 { lab=io_analog[7]}
 N 6290 350 6360 350 { lab=io_analog[10]}
@@ -234,6 +234,27 @@
 N 5600 -240 5600 -180 { lab=vssa1}
 N 5750 -360 5750 -300 { lab=vdda1}
 N 5750 -240 5750 -180 { lab=vssa1}
+N 6680 -510 6680 -460 { lab=vdda1}
+N 6720 -230 6720 -180 { lab=vssa1}
+N 6850 -350 6960 -350 { lab=io_analog[0]}
+N 6850 -370 6960 -370 { lab=io_analog[1]}
+N 6450 -410 6560 -410 { lab=io_analog[4]}
+N 6450 -430 6560 -430 { lab=io_analog[6]}
+N 6450 -350 6560 -350 { lab=io_analog[2]}
+N 6450 -370 6560 -370 { lab=io_analog[3]}
+N 6450 -280 6560 -280 { lab=iref2}
+N 6450 -300 6560 -300 { lab=iref0}
+N 6450 -270 6560 -270 { lab=iref3}
+N 6450 -290 6560 -290 { lab=iref1}
+N 6450 -260 6560 -260 { lab=iref4}
+N 6610 -230 6610 -120 { lab=gpio_noesd[6]}
+N 6630 -230 6630 -120 { lab=gpio_noesd[2]}
+N 6600 -230 6600 -120 { lab=gpio_noesd[5]}
+N 6620 -230 6620 -120 { lab=gpio_noesd[3]}
+N 6590 -230 6590 -120 { lab=gpio_noesd[4]}
+N 6640 -230 6640 -120 { lab=gpio_noesd[1]}
+N 5880 -360 5880 -300 { lab=vdda1}
+N 5880 -240 5880 -180 { lab=vssa1}
 C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
 C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
 C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
@@ -303,11 +324,6 @@
 C {lab_pin.sym} 3950 150 1 0 {name=l44 sig_type=std_logic lab=iref_cp2}
 C {noconn.sym} 4050 -270 2 0 {name=l48}
 C {noconn.sym} 4050 -250 2 0 {name=l49}
-C {noconn.sym} 4050 -230 2 0 {name=l50}
-C {noconn.sym} 4050 -210 2 0 {name=l51}
-C {noconn.sym} 4050 -190 2 0 {name=l52}
-C {noconn.sym} 4050 -170 2 0 {name=l53}
-C {noconn.sym} 4050 -150 2 0 {name=l54}
 C {lab_pin.sym} 3780 350 0 0 {name=l45 sig_type=std_logic lab=io_analog[10]}
 C {lab_pin.sym} 4750 350 2 0 {name=l55 sig_type=std_logic lab=io_analog[9]}
 C {lab_pin.sym} 4030 150 3 1 {name=l56 sig_type=std_logic lab=gpio_noesd[7]}
@@ -391,7 +407,7 @@
 C {sky130_fd_pr/cap_mim_m3_2.sym} 4680 -270 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
 C {lab_pin.sym} 4680 -360 1 0 {name=l118 sig_type=std_logic lab=vdda1}
 C {lab_pin.sym} 4680 -180 3 0 {name=l119 sig_type=std_logic lab=vssa1}
-C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=7 spiceprefix=X}
 C {lab_pin.sym} 4820 -360 1 0 {name=l120 sig_type=std_logic lab=vdda1}
 C {lab_pin.sym} 4820 -180 3 0 {name=l121 sig_type=std_logic lab=vssa1}
 C {sky130_fd_pr/cap_mim_m3_2.sym} 5050 -270 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
@@ -412,3 +428,31 @@
 C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
 C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1}
 C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1}
+C {lab_pin.sym} 6680 -490 2 0 {name=l134 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6720 -190 2 0 {name=l135 sig_type=std_logic lab=vssa1}
+C {res_amp_top.sym} 6730 -190 0 0 {name=x5}
+C {lab_pin.sym} 6960 -370 2 0 {name=l136 sig_type=std_logic lab=io_analog[1]}
+C {lab_pin.sym} 6960 -350 2 0 {name=l137 sig_type=std_logic lab=io_analog[0]}
+C {lab_pin.sym} 6450 -410 0 0 {name=l138 sig_type=std_logic lab=io_analog[4]}
+C {lab_pin.sym} 6450 -430 0 0 {name=l139 sig_type=std_logic lab=io_analog[6]}
+C {lab_pin.sym} 6450 -350 0 0 {name=l140 sig_type=std_logic lab=io_analog[2]}
+C {lab_pin.sym} 6450 -370 0 0 {name=l141 sig_type=std_logic lab=io_analog[3]}
+C {lab_pin.sym} 4050 -150 2 0 {name=l50 sig_type=std_logic lab=iref0}
+C {lab_pin.sym} 4050 -170 2 0 {name=l51 sig_type=std_logic lab=iref1}
+C {lab_pin.sym} 4050 -190 2 0 {name=l52 sig_type=std_logic lab=iref3}
+C {lab_pin.sym} 4050 -210 2 0 {name=l53 sig_type=std_logic lab=iref2}
+C {lab_pin.sym} 4050 -230 2 0 {name=l54 sig_type=std_logic lab=iref4}
+C {lab_pin.sym} 6450 -280 0 0 {name=l142 sig_type=std_logic lab=iref2}
+C {lab_pin.sym} 6450 -300 0 0 {name=l143 sig_type=std_logic lab=iref0}
+C {lab_pin.sym} 6450 -270 0 0 {name=l144 sig_type=std_logic lab=iref3}
+C {lab_pin.sym} 6450 -290 0 0 {name=l145 sig_type=std_logic lab=iref1}
+C {lab_pin.sym} 6450 -260 0 0 {name=l146 sig_type=std_logic lab=iref4}
+C {lab_pin.sym} 6610 -120 3 0 {name=l147 sig_type=std_logic lab=gpio_noesd[6]}
+C {lab_pin.sym} 6600 -120 3 0 {name=l148 sig_type=std_logic lab=gpio_noesd[5]}
+C {lab_pin.sym} 6590 -120 3 0 {name=l149 sig_type=std_logic lab=gpio_noesd[4]}
+C {lab_pin.sym} 6640 -120 3 0 {name=l150 sig_type=std_logic lab=gpio_noesd[1]}
+C {lab_pin.sym} 6630 -120 3 0 {name=l151 sig_type=std_logic lab=gpio_noesd[2]}
+C {lab_pin.sym} 6620 -120 3 0 {name=l152 sig_type=std_logic lab=gpio_noesd[3]}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5880 -270 0 0 {name=C10 model=cap_mim_m3_2 W=30 L=30 MF=10 spiceprefix=X}
+C {lab_pin.sym} 5880 -360 1 0 {name=l153 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5880 -180 3 0 {name=l154 sig_type=std_logic lab=vssa1}
diff --git a/xschem/user_analog_project_wrapper_backup.sch b/xschem/user_analog_project_wrapper_backup.sch
new file mode 100644
index 0000000..1d46956
--- /dev/null
+++ b/xschem/user_analog_project_wrapper_backup.sch
@@ -0,0 +1,414 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 4410 160 4410 220 { lab=vdda1}
+N 4470 160 4470 220 { lab=vssa1}
+N 3990 530 3990 580 { lab=#net1}
+N 3990 480 3990 530 { lab=#net1}
+N 3970 530 3970 580 { lab=#net2}
+N 3970 480 3970 530 { lab=#net2}
+N 3950 530 3950 580 { lab=#net3}
+N 3950 480 3950 530 { lab=#net3}
+N 4060 530 4060 580 { lab=#net4}
+N 4060 480 4060 530 { lab=#net4}
+N 4040 530 4040 580 { lab=#net5}
+N 4040 480 4040 530 { lab=#net5}
+N 4020 530 4020 580 { lab=#net6}
+N 4020 480 4020 530 { lab=#net6}
+N 4080 530 4080 580 { lab=#net7}
+N 4080 480 4080 530 { lab=#net7}
+N 4150 530 4150 580 { lab=#net8}
+N 4150 480 4150 530 { lab=#net8}
+N 4130 530 4130 580 { lab=#net9}
+N 4130 480 4130 530 { lab=#net9}
+N 4110 530 4110 580 { lab=#net10}
+N 4110 480 4110 530 { lab=#net10}
+N 4180 530 4180 580 { lab=#net11}
+N 4180 480 4180 530 { lab=#net11}
+N 4210 530 4210 580 { lab=#net12}
+N 4210 480 4210 530 { lab=#net12}
+N 4230 530 4230 580 { lab=#net13}
+N 4230 480 4230 530 { lab=#net13}
+N 4250 530 4250 580 { lab=#net14}
+N 4250 480 4250 530 { lab=#net14}
+N 4270 530 4270 580 { lab=#net15}
+N 4270 480 4270 530 { lab=#net15}
+N 4300 530 4300 580 { lab=#net16}
+N 4300 480 4300 530 { lab=#net16}
+N 4320 530 4320 580 { lab=#net17}
+N 4320 480 4320 530 { lab=#net17}
+N 4340 530 4340 580 { lab=#net18}
+N 4340 480 4340 530 { lab=#net18}
+N 4360 530 4360 580 { lab=#net19}
+N 4360 480 4360 530 { lab=#net19}
+N 4380 530 4380 580 { lab=#net20}
+N 4380 480 4380 530 { lab=#net20}
+N 4400 530 4400 580 { lab=#net21}
+N 4400 480 4400 530 { lab=#net21}
+N 4430 530 4430 580 { lab=#net22}
+N 4430 480 4430 530 { lab=#net22}
+N 4450 530 4450 580 { lab=#net23}
+N 4450 480 4450 530 { lab=#net23}
+N 4470 530 4470 580 { lab=#net24}
+N 4470 480 4470 530 { lab=#net24}
+N 4490 530 4490 580 { lab=#net25}
+N 4490 480 4490 530 { lab=#net25}
+N 4510 530 4510 580 { lab=#net26}
+N 4510 480 4510 530 { lab=#net26}
+N 4530 530 4530 580 { lab=#net27}
+N 4530 480 4530 530 { lab=#net27}
+N 4580 530 4580 580 { lab=#net28}
+N 4580 480 4580 530 { lab=#net28}
+N 4700 350 4750 350 { lab=io_analog[9]}
+N 4650 350 4700 350 { lab=io_analog[9]}
+N 3820 350 3890 350 { lab=io_analog[10]}
+N 3950 150 3950 220 { lab=iref_cp2}
+N 4030 150 4030 220 { lab=gpio_noesd[7]}
+N 3890 -430 3890 -370 { lab=vdda1}
+N 3950 -290 3990 -290 { lab=iref_cp2}
+N 3780 350 3820 350 { lab=io_analog[10]}
+N 3890 -110 3890 -50 { lab=io_analog[5]}
+N 4000 -270 4050 -270 { lab=#net29}
+N 3950 -270 4000 -270 { lab=#net29}
+N 4000 -250 4050 -250 { lab=#net30}
+N 3950 -250 4000 -250 { lab=#net30}
+N 4000 -230 4050 -230 { lab=#net31}
+N 3950 -230 4000 -230 { lab=#net31}
+N 4000 -210 4050 -210 { lab=#net32}
+N 3950 -210 4000 -210 { lab=#net32}
+N 4000 -190 4050 -190 { lab=#net33}
+N 3950 -190 4000 -190 { lab=#net33}
+N 4000 -170 4050 -170 { lab=#net34}
+N 3950 -170 4000 -170 { lab=#net34}
+N 4000 -150 4050 -150 { lab=#net35}
+N 3950 -150 4000 -150 { lab=#net35}
+N 5660 160 5660 220 { lab=vdda1}
+N 5720 160 5720 220 { lab=vssa1}
+N 5240 530 5240 580 { lab=#net36}
+N 5240 480 5240 530 { lab=#net36}
+N 5220 530 5220 580 { lab=#net37}
+N 5220 480 5220 530 { lab=#net37}
+N 5200 530 5200 580 { lab=#net38}
+N 5200 480 5200 530 { lab=#net38}
+N 5310 530 5310 580 { lab=#net39}
+N 5310 480 5310 530 { lab=#net39}
+N 5290 530 5290 580 { lab=#net40}
+N 5290 480 5290 530 { lab=#net40}
+N 5270 530 5270 580 { lab=#net41}
+N 5270 480 5270 530 { lab=#net41}
+N 5330 530 5330 580 { lab=#net42}
+N 5330 480 5330 530 { lab=#net42}
+N 5400 530 5400 580 { lab=#net43}
+N 5400 480 5400 530 { lab=#net43}
+N 5380 530 5380 580 { lab=#net44}
+N 5380 480 5380 530 { lab=#net44}
+N 5360 530 5360 580 { lab=#net45}
+N 5360 480 5360 530 { lab=#net45}
+N 5430 530 5430 580 { lab=#net46}
+N 5430 480 5430 530 { lab=#net46}
+N 5460 530 5460 580 { lab=#net47}
+N 5460 480 5460 530 { lab=#net47}
+N 5480 530 5480 580 { lab=#net48}
+N 5480 480 5480 530 { lab=#net48}
+N 5500 530 5500 580 { lab=#net49}
+N 5500 480 5500 530 { lab=#net49}
+N 5520 530 5520 580 { lab=#net50}
+N 5520 480 5520 530 { lab=#net50}
+N 5550 530 5550 580 { lab=#net51}
+N 5550 480 5550 530 { lab=#net51}
+N 5570 530 5570 580 { lab=#net52}
+N 5570 480 5570 530 { lab=#net52}
+N 5590 530 5590 580 { lab=#net53}
+N 5590 480 5590 530 { lab=#net53}
+N 5610 530 5610 580 { lab=#net54}
+N 5610 480 5610 530 { lab=#net54}
+N 5630 530 5630 580 { lab=#net55}
+N 5630 480 5630 530 { lab=#net55}
+N 5650 530 5650 580 { lab=#net56}
+N 5650 480 5650 530 { lab=#net56}
+N 5680 530 5680 580 { lab=#net57}
+N 5680 480 5680 530 { lab=#net57}
+N 5700 530 5700 580 { lab=#net58}
+N 5700 480 5700 530 { lab=#net58}
+N 5720 530 5720 580 { lab=#net59}
+N 5720 480 5720 530 { lab=#net59}
+N 5740 530 5740 580 { lab=#net60}
+N 5740 480 5740 530 { lab=#net60}
+N 5760 530 5760 580 { lab=#net61}
+N 5760 480 5760 530 { lab=#net61}
+N 5780 530 5780 580 { lab=#net62}
+N 5780 480 5780 530 { lab=#net62}
+N 5830 530 5830 580 { lab=#net63}
+N 5830 480 5830 530 { lab=#net63}
+N 5950 350 6000 350 { lab=io_analog[8]}
+N 5900 350 5950 350 { lab=io_analog[8]}
+N 5070 350 5140 350 { lab=io_analog[10]}
+N 5200 150 5200 220 { lab=iref_cp1}
+N 5280 150 5280 220 { lab=gpio_noesd[7]}
+N 5030 350 5070 350 { lab=io_analog[10]}
+N 3950 -310 3990 -310 { lab=iref_cp1}
+N 5340 150 5340 220 { lab=gpio_noesd[8]}
+N 6880 160 6880 220 { lab=vdda1}
+N 6940 160 6940 220 { lab=vssa1}
+N 6460 530 6460 580 { lab=#net64}
+N 6460 480 6460 530 { lab=#net64}
+N 6440 530 6440 580 { lab=#net65}
+N 6440 480 6440 530 { lab=#net65}
+N 6420 530 6420 580 { lab=#net66}
+N 6420 480 6420 530 { lab=#net66}
+N 6530 530 6530 580 { lab=#net67}
+N 6530 480 6530 530 { lab=#net67}
+N 6510 530 6510 580 { lab=#net68}
+N 6510 480 6510 530 { lab=#net68}
+N 6490 530 6490 580 { lab=#net69}
+N 6490 480 6490 530 { lab=#net69}
+N 6550 530 6550 580 { lab=#net70}
+N 6550 480 6550 530 { lab=#net70}
+N 6620 530 6620 580 { lab=#net71}
+N 6620 480 6620 530 { lab=#net71}
+N 6600 530 6600 580 { lab=#net72}
+N 6600 480 6600 530 { lab=#net72}
+N 6580 530 6580 580 { lab=#net73}
+N 6580 480 6580 530 { lab=#net73}
+N 6650 530 6650 580 { lab=#net74}
+N 6650 480 6650 530 { lab=#net74}
+N 6680 530 6680 580 { lab=#net75}
+N 6680 480 6680 530 { lab=#net75}
+N 6700 530 6700 580 { lab=#net76}
+N 6700 480 6700 530 { lab=#net76}
+N 6720 530 6720 580 { lab=#net77}
+N 6720 480 6720 530 { lab=#net77}
+N 6740 530 6740 580 { lab=#net78}
+N 6740 480 6740 530 { lab=#net78}
+N 6770 530 6770 580 { lab=#net79}
+N 6770 480 6770 530 { lab=#net79}
+N 6790 530 6790 580 { lab=#net80}
+N 6790 480 6790 530 { lab=#net80}
+N 6810 530 6810 580 { lab=#net81}
+N 6810 480 6810 530 { lab=#net81}
+N 6830 530 6830 580 { lab=#net82}
+N 6830 480 6830 530 { lab=#net82}
+N 6850 530 6850 580 { lab=#net83}
+N 6850 480 6850 530 { lab=#net83}
+N 6870 530 6870 580 { lab=#net84}
+N 6870 480 6870 530 { lab=#net84}
+N 6900 530 6900 580 { lab=#net85}
+N 6900 480 6900 530 { lab=#net85}
+N 6920 530 6920 580 { lab=#net86}
+N 6920 480 6920 530 { lab=#net86}
+N 6940 530 6940 580 { lab=#net87}
+N 6940 480 6940 530 { lab=#net87}
+N 6960 530 6960 580 { lab=#net88}
+N 6960 480 6960 530 { lab=#net88}
+N 6980 530 6980 580 { lab=#net89}
+N 6980 480 6980 530 { lab=#net89}
+N 7000 530 7000 580 { lab=#net90}
+N 7000 480 7000 530 { lab=#net90}
+N 7050 530 7050 580 { lab=#net91}
+N 7050 480 7050 530 { lab=#net91}
+N 7170 350 7220 350 { lab=io_analog[7]}
+N 7120 350 7170 350 { lab=io_analog[7]}
+N 6290 350 6360 350 { lab=io_analog[10]}
+N 6420 150 6420 220 { lab=iref_cp0}
+N 6500 150 6500 220 { lab=gpio_noesd[7]}
+N 6250 350 6290 350 { lab=io_analog[10]}
+N 3950 -330 3990 -330 { lab=iref_cp0}
+N 4540 -360 4540 -300 { lab=vdda1}
+N 4540 -240 4540 -180 { lab=vssa1}
+N 4680 -360 4680 -300 { lab=vdda1}
+N 4680 -240 4680 -180 { lab=vssa1}
+N 4820 -360 4820 -300 { lab=vdda1}
+N 4820 -240 4820 -180 { lab=vssa1}
+N 5050 -360 5050 -300 { lab=vdda1}
+N 5050 -240 5050 -180 { lab=vssa1}
+N 5190 -360 5190 -300 { lab=vdda1}
+N 5190 -240 5190 -180 { lab=vssa1}
+N 5330 -360 5330 -300 { lab=vdda1}
+N 5330 -240 5330 -180 { lab=vssa1}
+N 5470 -360 5470 -300 { lab=vdda1}
+N 5470 -240 5470 -180 { lab=vssa1}
+N 5600 -360 5600 -300 { lab=vdda1}
+N 5600 -240 5600 -180 { lab=vssa1}
+N 5750 -360 5750 -300 { lab=vdda1}
+N 5750 -240 5750 -180 { lab=vssa1}
+C {iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {top_pll_v1.sym} 4240 350 0 0 {name=x1}
+C {lab_pin.sym} 4410 160 1 0 {name=l13 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4470 160 1 0 {name=l14 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 3990 580 3 0 {name=l15}
+C {noconn.sym} 3970 580 3 0 {name=l6}
+C {noconn.sym} 3950 580 3 0 {name=l16}
+C {noconn.sym} 4060 580 3 0 {name=l17}
+C {noconn.sym} 4040 580 3 0 {name=l18}
+C {noconn.sym} 4020 580 3 0 {name=l19}
+C {noconn.sym} 4080 580 3 0 {name=l20}
+C {noconn.sym} 4150 580 3 0 {name=l21}
+C {noconn.sym} 4130 580 3 0 {name=l22}
+C {noconn.sym} 4110 580 3 0 {name=l23}
+C {noconn.sym} 4180 580 3 0 {name=l24}
+C {noconn.sym} 4210 580 3 0 {name=l25}
+C {noconn.sym} 4230 580 3 0 {name=l26}
+C {noconn.sym} 4250 580 3 0 {name=l27}
+C {noconn.sym} 4270 580 3 0 {name=l28}
+C {noconn.sym} 4300 580 3 0 {name=l29}
+C {noconn.sym} 4320 580 3 0 {name=l30}
+C {noconn.sym} 4340 580 3 0 {name=l31}
+C {noconn.sym} 4360 580 3 0 {name=l32}
+C {noconn.sym} 4380 580 3 0 {name=l33}
+C {noconn.sym} 4400 580 3 0 {name=l34}
+C {noconn.sym} 4430 580 3 0 {name=l35}
+C {noconn.sym} 4450 580 3 0 {name=l36}
+C {noconn.sym} 4470 580 3 0 {name=l37}
+C {noconn.sym} 4490 580 3 0 {name=l38}
+C {noconn.sym} 4510 580 3 0 {name=l39}
+C {noconn.sym} 4530 580 3 0 {name=l40}
+C {noconn.sym} 4580 580 3 0 {name=l41}
+C {bias.sym} 3890 -240 0 0 {name=x2}
+C {lab_pin.sym} 3890 -430 1 0 {name=l42 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 3990 -290 2 0 {name=l43 sig_type=std_logic lab=iref_cp2}
+C {lab_pin.sym} 3950 150 1 0 {name=l44 sig_type=std_logic lab=iref_cp2}
+C {noconn.sym} 4050 -270 2 0 {name=l48}
+C {noconn.sym} 4050 -250 2 0 {name=l49}
+C {noconn.sym} 4050 -230 2 0 {name=l50}
+C {noconn.sym} 4050 -210 2 0 {name=l51}
+C {noconn.sym} 4050 -190 2 0 {name=l52}
+C {noconn.sym} 4050 -170 2 0 {name=l53}
+C {noconn.sym} 4050 -150 2 0 {name=l54}
+C {lab_pin.sym} 3780 350 0 0 {name=l45 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 4750 350 2 0 {name=l55 sig_type=std_logic lab=io_analog[9]}
+C {lab_pin.sym} 4030 150 3 1 {name=l56 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3890 -50 3 0 {name=l1 sig_type=std_logic lab=io_analog[5]}
+C {lab_pin.sym} 5660 160 1 0 {name=l2 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5720 160 1 0 {name=l3 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 5240 580 3 0 {name=l4}
+C {noconn.sym} 5220 580 3 0 {name=l5}
+C {noconn.sym} 5200 580 3 0 {name=l7}
+C {noconn.sym} 5310 580 3 0 {name=l8}
+C {noconn.sym} 5290 580 3 0 {name=l9}
+C {noconn.sym} 5270 580 3 0 {name=l10}
+C {noconn.sym} 5330 580 3 0 {name=l11}
+C {noconn.sym} 5400 580 3 0 {name=l12}
+C {noconn.sym} 5380 580 3 0 {name=l57}
+C {noconn.sym} 5360 580 3 0 {name=l58}
+C {noconn.sym} 5430 580 3 0 {name=l59}
+C {noconn.sym} 5460 580 3 0 {name=l60}
+C {noconn.sym} 5480 580 3 0 {name=l61}
+C {noconn.sym} 5500 580 3 0 {name=l62}
+C {noconn.sym} 5520 580 3 0 {name=l63}
+C {noconn.sym} 5550 580 3 0 {name=l64}
+C {noconn.sym} 5570 580 3 0 {name=l65}
+C {noconn.sym} 5590 580 3 0 {name=l66}
+C {noconn.sym} 5610 580 3 0 {name=l67}
+C {noconn.sym} 5630 580 3 0 {name=l68}
+C {noconn.sym} 5650 580 3 0 {name=l69}
+C {noconn.sym} 5680 580 3 0 {name=l70}
+C {noconn.sym} 5700 580 3 0 {name=l71}
+C {noconn.sym} 5720 580 3 0 {name=l72}
+C {noconn.sym} 5740 580 3 0 {name=l73}
+C {noconn.sym} 5760 580 3 0 {name=l74}
+C {noconn.sym} 5780 580 3 0 {name=l75}
+C {noconn.sym} 5830 580 3 0 {name=l76}
+C {lab_pin.sym} 5200 150 1 0 {name=l77 sig_type=std_logic lab=iref_cp1}
+C {lab_pin.sym} 5030 350 0 0 {name=l78 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 6000 350 2 0 {name=l79 sig_type=std_logic lab=io_analog[8]}
+C {lab_pin.sym} 5280 150 3 1 {name=l80 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -310 2 0 {name=l81 sig_type=std_logic lab=iref_cp1}
+C {top_pll_v2.sym} 5490 350 0 0 {name=x3}
+C {lab_pin.sym} 5340 150 3 1 {name=l47 sig_type=std_logic lab=gpio_noesd[8]}
+C {top_pll_v1.sym} 6710 350 0 0 {name=x4}
+C {lab_pin.sym} 6880 160 1 0 {name=l82 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 6940 160 1 0 {name=l83 sig_type=std_logic lab=vssa1}
+C {noconn.sym} 6460 580 3 0 {name=l84}
+C {noconn.sym} 6440 580 3 0 {name=l85}
+C {noconn.sym} 6420 580 3 0 {name=l86}
+C {noconn.sym} 6530 580 3 0 {name=l87}
+C {noconn.sym} 6510 580 3 0 {name=l88}
+C {noconn.sym} 6490 580 3 0 {name=l89}
+C {noconn.sym} 6550 580 3 0 {name=l90}
+C {noconn.sym} 6620 580 3 0 {name=l91}
+C {noconn.sym} 6600 580 3 0 {name=l92}
+C {noconn.sym} 6580 580 3 0 {name=l93}
+C {noconn.sym} 6650 580 3 0 {name=l94}
+C {noconn.sym} 6680 580 3 0 {name=l95}
+C {noconn.sym} 6700 580 3 0 {name=l96}
+C {noconn.sym} 6720 580 3 0 {name=l97}
+C {noconn.sym} 6740 580 3 0 {name=l98}
+C {noconn.sym} 6770 580 3 0 {name=l99}
+C {noconn.sym} 6790 580 3 0 {name=l100}
+C {noconn.sym} 6810 580 3 0 {name=l101}
+C {noconn.sym} 6830 580 3 0 {name=l102}
+C {noconn.sym} 6850 580 3 0 {name=l103}
+C {noconn.sym} 6870 580 3 0 {name=l104}
+C {noconn.sym} 6900 580 3 0 {name=l105}
+C {noconn.sym} 6920 580 3 0 {name=l106}
+C {noconn.sym} 6940 580 3 0 {name=l107}
+C {noconn.sym} 6960 580 3 0 {name=l108}
+C {noconn.sym} 6980 580 3 0 {name=l109}
+C {noconn.sym} 7000 580 3 0 {name=l110}
+C {noconn.sym} 7050 580 3 0 {name=l111}
+C {lab_pin.sym} 6420 150 1 0 {name=l112 sig_type=std_logic lab=iref_cp0}
+C {lab_pin.sym} 6250 350 0 0 {name=l113 sig_type=std_logic lab=io_analog[10]}
+C {lab_pin.sym} 7220 350 2 0 {name=l114 sig_type=std_logic lab=io_analog[7]}
+C {lab_pin.sym} 6500 150 3 1 {name=l115 sig_type=std_logic lab=gpio_noesd[7]}
+C {lab_pin.sym} 3990 -330 2 0 {name=l46 sig_type=std_logic lab=iref_cp0}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4540 -270 0 0 {name=C1 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4540 -360 1 0 {name=l116 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4540 -180 3 0 {name=l117 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4680 -270 0 0 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4680 -360 1 0 {name=l118 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4680 -180 3 0 {name=l119 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 4820 -270 0 0 {name=C3 model=cap_mim_m3_2 W=30 L=30 MF=9 spiceprefix=X}
+C {lab_pin.sym} 4820 -360 1 0 {name=l120 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 4820 -180 3 0 {name=l121 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5050 -270 0 0 {name=C4 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5050 -360 1 0 {name=l122 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5050 -180 3 0 {name=l123 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5190 -270 0 0 {name=C5 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5190 -360 1 0 {name=l124 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5190 -180 3 0 {name=l125 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5330 -270 0 0 {name=C6 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5330 -360 1 0 {name=l126 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5330 -180 3 0 {name=l127 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5470 -270 0 0 {name=C7 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5470 -360 1 0 {name=l128 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5470 -180 3 0 {name=l129 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5600 -270 0 0 {name=C8 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5600 -360 1 0 {name=l130 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5600 -180 3 0 {name=l131 sig_type=std_logic lab=vssa1}
+C {sky130_fd_pr/cap_mim_m3_2.sym} 5750 -270 0 0 {name=C9 model=cap_mim_m3_2 W=30 L=30 MF=15 spiceprefix=X}
+C {lab_pin.sym} 5750 -360 1 0 {name=l132 sig_type=std_logic lab=vdda1}
+C {lab_pin.sym} 5750 -180 3 0 {name=l133 sig_type=std_logic lab=vssa1}