diff --git a/run_test.sh b/run_test.sh
index 1cdf933..211f5bf 100755
--- a/run_test.sh
+++ b/run_test.sh
@@ -66,4 +66,12 @@
 echo "###############################################" >>  test.log
 echo "Start WB test 5" >>  test.log
 make verify-wb_test5 >>  ./test.log
+echo "Start WB test 6"
+echo "###############################################" >>  test.log
+echo "Start WB test 6" >>  test.log
+make verify-wb_test6 >>  ./test.log
+echo "Start WB test 7"
+echo "###############################################" >>  test.log
+echo "Start WB test 7" >>  test.log
+make verify-wb_test7 >>  ./test.log
 echo "End Test"
\ No newline at end of file
diff --git a/verilog/dv/la_test4/la_test4.c b/verilog/dv/la_test4/la_test4.c
index 863ddbb..9049427 100644
--- a/verilog/dv/la_test4/la_test4.c
+++ b/verilog/dv/la_test4/la_test4.c
@@ -156,6 +156,7 @@
 	add_value_to_register(25432,1);
 	clock();
 	add_value_to_register(38,2);
+	clock();
 
 	read_value_from_triplet_register(0);
 	clock();
diff --git a/verilog/dv/la_test4/la_test4.gtkw b/verilog/dv/la_test4/la_test4.gtkw
index 47eb23e..06497c7 100644
--- a/verilog/dv/la_test4/la_test4.gtkw
+++ b/verilog/dv/la_test4/la_test4.gtkw
@@ -1,19 +1,20 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Fri May 28 12:06:49 2021
+[*] Tue Jun 15 07:19:05 2021
 [*]
 [dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test4/la_test4.vcd"
-[dumpfile_mtime] "Fri May 28 12:01:29 2021"
-[dumpfile_size] 2291794024
+[dumpfile_mtime] "Tue Jun 15 07:15:06 2021"
+[dumpfile_size] 2292201270
 [savefile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test4/la_test4.gtkw"
-[timestart] 153100000
+[timestart] 437300000
 [size] 1848 1016
 [pos] -1 -1
-*-27.000000 523712500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-25.000000 540300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] la_test4_tb.
 [treeopen] la_test4_tb.uut.
 [treeopen] la_test4_tb.uut.mprj.
 [treeopen] la_test4_tb.uut.mprj.mprj.
+[treeopen] la_test4_tb.uut.mprj.mprj.register_file.
 [sst_width] 253
 [signals_width] 310
 [sst_expanded] 1
@@ -28,13 +29,23 @@
 @28
 la_test4_tb.uut.mprj.mprj.register_file.rregister_i
 la_test4_tb.uut.mprj.mprj.register_file.wregister_i
-la_test4_tb.uut.mprj.mprj.register_file.operation_type_i
 la_test4_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
 @22
 la_test4_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
 @200
 -GPIO
-@23
+@22
 la_test4_tb.mprj_io[37:0]
+@200
+-
+-REGISTER DATA
+@22
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_1[31:0]
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_2[31:0]
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_3[31:0]
+@28
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_1
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_2
+la_test4_tb.uut.mprj.mprj.register_file.inst_RD.xor_reduce_3
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/verilog/dv/wb_test1/wb_test1.c b/verilog/dv/wb_test1/wb_test1.c
index 71b9d90..957c931 100644
--- a/verilog/dv/wb_test1/wb_test1.c
+++ b/verilog/dv/wb_test1/wb_test1.c
@@ -155,7 +155,7 @@
     //apply modification to the register
     reg_wb_register = 0x00000003;
     clock();
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
     read_value_from_register(0);
     clock();
diff --git a/verilog/dv/wb_test2/wb_test2.c b/verilog/dv/wb_test2/wb_test2.c
index 9f2b868..c70b894 100644
--- a/verilog/dv/wb_test2/wb_test2.c
+++ b/verilog/dv/wb_test2/wb_test2.c
@@ -161,7 +161,7 @@
     reg_wb_register = 0x00000003;
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
     read_value_from_register(4);
     clock();
@@ -188,7 +188,7 @@
 
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
     read_value_from_register(0);
     clock();
     
diff --git a/verilog/dv/wb_test2/wb_test2.gtkw b/verilog/dv/wb_test2/wb_test2.gtkw
index 4d8966a..c92b33d 100644
--- a/verilog/dv/wb_test2/wb_test2.gtkw
+++ b/verilog/dv/wb_test2/wb_test2.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sun Jun 13 09:45:33 2021
+[*] Tue Jun 15 07:47:47 2021
 [*]
 [dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.vcd"
-[dumpfile_mtime] "Sat Jun 12 22:44:29 2021"
-[dumpfile_size] 1649511525
+[dumpfile_mtime] "Tue Jun 15 05:30:21 2021"
+[dumpfile_size] 1641689878
 [savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.gtkw"
-[timestart] 1227360000
+[timestart] 493800000
 [size] 1848 1016
 [pos] -1 -1
-*-23.000000 746087500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-25.000000 676000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] wb_test2_tb.
 [treeopen] wb_test2_tb.uut.
 [treeopen] wb_test2_tb.uut.mprj.
diff --git a/verilog/dv/wb_test3/wb_test3.c b/verilog/dv/wb_test3/wb_test3.c
index e7fa865..a26ba0f 100644
--- a/verilog/dv/wb_test3/wb_test3.c
+++ b/verilog/dv/wb_test3/wb_test3.c
@@ -167,7 +167,7 @@
     //apply modification to the register
     reg_wb_register = 0x00032053;
     clock();
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
     read_value_from_triplet_register(12);
     clock();
diff --git a/verilog/dv/wb_test4/wb_test4.c b/verilog/dv/wb_test4/wb_test4.c
index 279b046..bad9919 100644
--- a/verilog/dv/wb_test4/wb_test4.c
+++ b/verilog/dv/wb_test4/wb_test4.c
@@ -169,7 +169,7 @@
         reg_wb_register = reg_wb_register + 1;
 	}
     clock();
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
 	for (uint32_t i = 0; i < 32; ++i ){
 		read_value_from_register_no_proteccion(i);
diff --git a/verilog/dv/wb_test5/wb_test5.c b/verilog/dv/wb_test5/wb_test5.c
index 1866fa4..719a638 100644
--- a/verilog/dv/wb_test5/wb_test5.c
+++ b/verilog/dv/wb_test5/wb_test5.c
@@ -163,7 +163,7 @@
     reg_wb_register = 0x00000003;
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
     read_value_from_register(4);
     clock();
@@ -190,7 +190,7 @@
 
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
     read_value_from_register(0);
     clock();
     
diff --git a/verilog/dv/wb_test6/wb_test6.c b/verilog/dv/wb_test6/wb_test6.c
index 6330b5a..58528c4 100644
--- a/verilog/dv/wb_test6/wb_test6.c
+++ b/verilog/dv/wb_test6/wb_test6.c
@@ -163,7 +163,7 @@
     reg_wb_invalid_register = 0x0000000F;
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
 
     read_value_from_register(4);
     clock();
@@ -189,7 +189,7 @@
 
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
     read_value_from_register(0);
     clock();
     
diff --git a/verilog/dv/wb_test7/wb_test7.c b/verilog/dv/wb_test7/wb_test7.c
index 1238eb1..c5e7e81 100644
--- a/verilog/dv/wb_test7/wb_test7.c
+++ b/verilog/dv/wb_test7/wb_test7.c
@@ -230,7 +230,7 @@
     }
     clock();
     // re enable clock
-    reg_la2_oenb = 0xFFFFFFFC;
+    reg_la2_oenb = 0xFFFFFFF8;
     add_value_to_register(50, 0);
     clock();
     read_value_from_register(0);
diff --git a/verilog/rtl/ecc_registers/register_data.v b/verilog/rtl/ecc_registers/register_data.v
index 8fbadc1..1f61dc6 100755
--- a/verilog/rtl/ecc_registers/register_data.v
+++ b/verilog/rtl/ecc_registers/register_data.v
@@ -219,7 +219,7 @@
             end 
             // triple redundaccy value
             else if (operation_type_i == 3'b001) begin
-                r[register_i[REGDIRSIZE - 1: 2]][116:0] <= {7'b0000000,data_to_register_i[31:0],7'b0000000,data_to_register_i[31:0],7'b0000000,data_to_register_i[31:0]};
+                r[register_i[REGDIRSIZE - 1: 2]][116:0] <= {data_to_register_i,data_to_register_i,data_to_register_i};
                 store_data_o <= {WORD_SIZE + ECCBITS{1'b0}};
                 redundat_validation_o <= 2'b00;
                 operational_o <= 1'b1;
diff --git a/verilog/rtl/user_proj.v b/verilog/rtl/user_proj.v
index 3a0fbfb..a8b8e01 100644
--- a/verilog/rtl/user_proj.v
+++ b/verilog/rtl/user_proj.v
@@ -108,7 +108,7 @@
     assign wdata = wbs_dat_i;
 
     // IO
-    assign io_out = {output_verification,output_data[15:0],operational, 19'b0};//{6'b000000,output_data};
+    assign io_out = {output_verification,output_data[15:0],operational, 19'b0};//{6'b000000,output_data};b
     assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
 
     // IRQ