diff --git a/info.yaml b/info.yaml
index 8ba8660..1a54163 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,18 +1,18 @@
 ---
 project:
-  description: "An analog project for Google sponsored Open MPW shuttles for SKY130."
+  description: "An analog test chip for IP blocks under development for a larger project"
   foundry: "SkyWater"
-  git_url: "https://github.com/efabless/caravel_analog_user.git"
-  organization: "Efabless"
-  organization_url: "http://efabless.com"
-  owner: "Tim Edwards"
+  git_url: "https://gitlab.com/skywater130/mpw2-columbus-a0.git"
+  organization: "Home Project"
+  organization_url: "https://gitlab.com/skywater130/mpw2-columbus-a0.git"
+  owner: "Tom Stanway-Mayers"
   process: "SKY130"
-  project_name: "Caravel Analog User"
+  project_name: "Columbus A0"
   project_id: "00000000"
   tags:
     - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
+    - "Test Chip"
+  category: "Test Chip"
   top_level_netlist: "caravel/verilog/gl/caravan.v"
   user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
   version: "1.00"
diff --git a/verilog/rtl/bgr.v b/verilog/rtl/bgr.v
new file mode 100644
index 0000000..1956234
--- /dev/null
+++ b/verilog/rtl/bgr.v
@@ -0,0 +1,42 @@
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * Bandgap Refrence
+ *
+ *-------------------------------------------------------------
+ */
+
+module bgr
+    (
+    `ifdef USE_POWER_PINS
+        inout vdda1,
+        inout vssa1,
+    `endif
+        inout vref,
+        inout ir20u
+    );
+
+    `ifdef USE_POWER_PINS
+    assign vref  = vdda1 & ~vssa1;
+    assign ir20u = vdda1 & ~vssa1;
+    `else
+    assign vref  = 1'b1;
+    assign ir20u = 1'b1;
+    `endif
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index a4a8c1a..cbf04bc 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -122,60 +122,15 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-user_analog_proj_example mprj (
-    `ifdef USE_POWER_PINS
-        .vdda1(vdda1),  // User area 1 3.3V power
-        .vdda2(vdda2),  // User area 2 3.3V power
-        .vssa1(vssa1),  // User area 1 analog ground
-        .vssa2(vssa2),  // User area 2 analog ground
-        .vccd1(vccd1),  // User area 1 1.8V power
-        .vccd2(vccd2),  // User area 2 1.8V power
-        .vssd1(vssd1),  // User area 1 digital ground
-        .vssd2(vssd2),  // User area 2 digital ground
-    `endif
-
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
-
-    // MGMT SoC Wishbone Slave
-
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
-
-    // Logic Analyzer
-
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
-
-    // IO Pads
-    .io_in (io_in),
-    .io_in_3v3 (io_in_3v3),
-    .io_out(io_out),
-    .io_oeb(io_oeb),
-
-    // GPIO-analog
-    .gpio_analog(gpio_analog),
-    .gpio_noesd(gpio_noesd),
-
-    // Dedicated analog
-    .io_analog(io_analog),
-    .io_clamp_high(io_clamp_high),
-    .io_clamp_low(io_clamp_low),
-
-    // Clock
-    .user_clock2(user_clock2),
-
-    // IRQ
-    .irq(user_irq)
-);
-
+    bgr i_bgr
+        (
+        `ifdef USE_POWER_PINS
+            .vdd   (vdda1),
+            .vss   (vssa1),
+        `endif
+            .vref  (gpio_noesd[5]),
+            .ir20u (gpio_noesd[4])
+        );
 endmodule	// user_analog_project_wrapper
 
 `default_nettype wire