)]}'
{
  "commit": "6229cd014b1219b6199deed9dff62a8370e1e663",
  "tree": "78a17cd03a1b0e7bbd8788b86d6c8609be38b5b6",
  "parents": [
    "637bee4ede17295f212a8a38e89f5ac101b40204"
  ],
  "author": {
    "name": "Kavya Sreedhar",
    "email": "skavya@stanford.edu",
    "time": "Tue Jun 22 21:56:02 2021 -0700"
  },
  "committer": {
    "name": "Kavya Sreedhar",
    "email": "skavya@stanford.edu",
    "time": "Tue Jun 22 21:56:02 2021 -0700"
  },
  "message": "clk -\u003e analog_io[23], routing blocks to avoid shorts with pins in caravel wrapper\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "db464c46d0a86edb525ddbabf5d32451412c156b",
      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds.gz",
      "new_id": "2eaac42b3fe792c03a49dc6533c6affbfde472ae",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds.gz"
    },
    {
      "type": "modify",
      "old_id": "fe2448adfeaaf3ea8bfeab653ce14b5e8eaab5a9",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v.gz",
      "new_id": "6283eb9483611f3d86a5a2fef8f60cf24dc6634a",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v.gz"
    }
  ]
}