diff --git a/caravel/mag/BGR.ext b/caravel/mag/BGR.ext
deleted file mode 100644
index 88df886..0000000
--- a/caravel/mag/BGR.ext
+++ /dev/null
@@ -1,384 +0,0 @@
-timestamp 1619695245
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_0 1 0 2182 0 1 2266
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_1 1 0 3226 0 1 2296
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_2 1 0 4230 0 1 2284
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_3 1 0 5200 0 1 2284
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_4 1 0 6218 0 1 2296
-use resistor30K resistor30K_0 1 0 10016 0 1 2900
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_5 1 0 2206 0 1 3292
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_6 1 0 3180 0 1 3292
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_7 1 0 4224 0 1 3270
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_8 1 0 5198 0 1 3270
-use sky130_fd_pr__pnp_05v5_W3p40L3p40 sky130_fd_pr__pnp_05v5_W3p40L3p40_9 1 0 6218 0 1 3270
-use resistor273K resistor273K_0 1 0 3522 0 1 8642
-use nmos2metal nmos2metal_9 1 0 14708 0 1 2456
-use NMOS120 NMOS120_0 1 0 14302 0 1 2380
-use NMOS520 NMOS520_0 1 0 14910 0 1 2360
-use nmos_substrate nmos_substrate_0 1 0 14470 0 1 0
-use nmos_substrate nmos_substrate_1 1 0 13920 0 1 0
-use nmos_substrate nmos_substrate_2 1 0 15070 0 1 0
-use nmos_substrate nmos_substrate_3 1 0 15620 0 1 0
-use nmos2metal nmos2metal_14 1 0 16260 0 1 2454
-use NMOS520 NMOS520_1 1 0 16458 0 1 2350
-use nmos_substrate nmos_substrate_4 1 0 16220 0 1 0
-use nmos_substrate nmos_substrate_5 1 0 16820 0 1 0
-use nmos_substrate nmos_substrate_6 1 0 17420 0 1 0
-use nmos_substrate nmos_substrate_9 1 0 19220 0 1 0
-use nmos_substrate nmos_substrate_8 1 0 18620 0 1 0
-use NMOS520 NMOS520_3 1 0 19758 0 1 2350
-use NMOS520 NMOS520_2 1 0 18150 0 1 2350
-use nmos_substrate nmos_substrate_7 1 0 18020 0 1 0
-use nmos_substrate nmos_substrate_12 1 0 21020 0 1 0
-use nmos_substrate nmos_substrate_11 1 0 20420 0 1 0
-use nmos_substrate nmos_substrate_10 1 0 19820 0 1 0
-use NMOS520 NMOS520_4 1 0 21446 0 1 2360
-use nmos2metal nmos2metal_3 1 0 17462 0 1 6056
-use nmos2metal nmos2metal_8 1 0 15906 0 1 6062
-use PMOS520 PMOS520_0 1 0 17220 0 1 7896
-use PMOS520 PMOS520_1 1 0 19218 0 1 7886
-use nmos2metal nmos2metal_0 1 0 19148 0 1 6054
-use nmos2metal nmos2metal_1 1 0 19558 0 1 6054
-use nmos2metal nmos2metal_2 1 0 17948 0 1 6054
-use pmos2metal pmos2metal_3 1 0 18224 0 1 8002
-use PMOS520 PMOS520_2 1 0 21214 0 1 7884
-use nmos2metal nmos2metal_4 1 0 20760 0 1 6046
-use nmos2metal nmos2metal_5 1 0 21248 0 1 6054
-use pmos2metal pmos2metal_4 1 0 20216 0 1 7982
-use pmos2metal pmos2metal_0 1 0 17014 0 1 11590
-use pmos2metal pmos2metal_1 1 0 19014 0 1 11582
-use pmos2metal pmos2metal_2 1 0 21014 0 1 11580
-use pmos2metal pmos2metal_5 1 0 22206 0 1 7980
-use nmos2metal nmos2metal_11 1 0 22454 0 1 2462
-use nmos_substrate nmos_substrate_14 1 0 22218 0 1 0
-use nmos_substrate nmos_substrate_13 1 0 21620 0 1 0
-use nmos2metal nmos2metal_13 1 0 24092 0 1 6026
-use nmos2metal nmos2metal_6 1 0 22882 0 1 6034
-use NMOS520 NMOS520_5 1 0 23088 0 1 2350
-use nmos_substrate nmos_substrate_15 1 0 22820 0 1 0
-use nmos_substrate nmos_substrate_16 1 0 23420 0 1 0
-use nmos_substrate nmos_substrate_17 1 0 24020 0 1 0
-use nmos2metal nmos2metal_10 1 0 24592 0 1 2460
-use nmos_substrate nmos_substrate_19 1 0 25220 0 1 0
-use NMOS520 NMOS520_6 1 0 24788 0 1 2360
-use nmos_substrate nmos_substrate_18 1 0 24620 0 1 0
-use resistor200K resistor200K_0 0 1 26910 -1 0 10506
-use nmos2metal nmos2metal_7 1 0 25790 0 1 2458
-use nmos_substrate nmos_substrate_20 1 0 25820 0 1 0
-use nmos_substrate nmos_substrate_21 1 0 26420 0 1 0
-use pmos_substrate pmos_substrate_5 1 0 22062 0 1 13056
-use pmos_substrate pmos_substrate_4 1 0 21496 0 1 13056
-use pmos_substrate pmos_substrate_3 1 0 20226 0 1 13056
-use pmos_substrate pmos_substrate_2 1 0 19656 0 1 13056
-use pmos_substrate pmos_substrate_1 1 0 18290 0 1 13056
-use pmos_substrate pmos_substrate_0 1 0 17606 0 1 13056
-port "Vref" 2 13292 8670 13292 8670 li
-port "En" 3 19130 1888 19294 2044 pc
-port "GND" 1 11202 36 11202 36 m1
-node "li_16316_30#" 3425 5914.63 16316 30 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 363816 20284 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_15714_30#" 171 314.95 15714 30 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18216 1084 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_15166_30#" 171 314.95 15166 30 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18216 1084 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_16144_1712#" 93 3544.45 16144 1712 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 130128 2200 65888 1032 985768 13028 0 0 0 0 0 0 0 0
-node "K" 167 1524.49 25854 2476 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 317392 4476 0 0 0 0 0 0 0 0 0 0 0 0
-node "I" 23 3458.41 11152 1282 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14560 488 881860 13400 0 0 0 0 0 0 0 0 0 0
-node "J" 771 12491.3 11040 2874 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3209416 28868 502232 5488 902984 8376 0 0 0 0 0 0 0 0
-node "E" 62 5568.32 9610 2880 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49728 1112 1211440 22820 0 0 0 0 0 0 0 0 0 0
-equiv "E" "E"
-node "li_5566_2864#" 16 141.095 5566 2864 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_4590_2852#" 16 141.095 4590 2852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_2536_2852#" 16 141.095 2536 2852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_6578_3362#" 16 132.011 6578 3362 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11904 440 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_5544_3358#" 16 141.095 5544 3358 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_4582_3350#" 16 141.095 4582 3350 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_3524_3378#" 16 141.095 3524 3378 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_2550_3378#" 16 141.095 2550 3378 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13400 468 0 0 0 0 0 0 0 0 0 0 0 0
-node "D" 39 471.905 20836 6064 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90384 1412 0 0 0 0 0 0 0 0 0 0 0 0
-node "B" 34 438.378 17532 6070 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83868 1312 0 0 0 0 0 0 0 0 0 0 0 0
-node "H" 205 2032.36 22240 7998 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 454980 5860 0 0 0 0 0 0 0 0 0 0 0 0
-node "Vref" 629 8739.55 13292 8670 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 956020 14212 323504 3288 1375984 19220 0 0 0 0 0 0 0 0
-node "F" 639 3952.23 2532 4192 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 572744 11156 76632 1660 0 0 0 0 0 0 0 0 0 0
-node "li_16858_13086#" 758 18463 16858 13086 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1202832 17572 2739840 57272 0 0 0 0 0 0 0 0 0 0
-node "En" 1349 15813.1 19130 1888 pc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3770120 21172 0 0 54696 940 0 0 0 0 0 0 0 0 0 0 0 0
-node "G" 1249 10350.6 14524 2442 mvndc 0 0 0 0 0 0 0 0 0 0 0 0 1296 144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 361884 2620 0 0 1841828 25136 57888 1392 128080 2228 0 0 0 0 0 0 0 0
-node "GND" 965 25238.3 11202 36 m1 0 0 0 0 0 0 0 0 0 0 0 0 1156 136 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3584344 32076 2739840 57272 0 0 0 0 0 0 0 0 0 0
-node "A" 1031 8512.51 14302 6432 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 701252 6492 0 0 760948 10272 77364 1528 259284 8132 0 0 0 0 0 0 0 0
-equiv "A" "A"
-node "C" 1752 9493.63 17212 7642 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 916880 10292 0 0 1179740 13668 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "C" "C"
-node "w_16722_12162#" 9014 20382.8 16722 12162 nw 0 0 0 0 6794264 14268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "li_15714_30#" "li_16316_30#" 12.375
-cap "GND" "J" 430.08
-cap "GND" "li_6578_3362#" 113.143
-cap "Vref" "H" 123.127
-cap "G" "GND" 497.446
-cap "li_5566_2864#" "GND" 1657.98
-cap "En" "J" 466.513
-cap "li_15166_30#" "GND" 253.991
-cap "li_16144_1712#" "J" 1019.67
-cap "G" "En" 331.766
-cap "G" "li_16144_1712#" 377.281
-cap "GND" "li_4590_2852#" 235.714
-cap "GND" "li_3524_3378#" 66
-cap "GND" "li_2536_2852#" 235.714
-cap "li_5544_3358#" "li_5566_2864#" 7.15
-cap "li_2550_3378#" "GND" 66
-cap "li_4590_2852#" "li_4582_3350#" 8.34066
-cap "I" "li_16144_1712#" 722.708
-cap "GND" "li_4582_3350#" 150
-cap "li_15166_30#" "li_15714_30#" 28.2857
-cap "li_2550_3378#" "li_2536_2852#" 7.2398
-cap "Vref" "A" 806.291
-cap "GND" "li_16144_1712#" 202.734
-cap "GND" "li_16316_30#" 4586.58
-cap "A" "C" 687.209
-cap "li_5544_3358#" "GND" 110
-cap "li_15714_30#" "GND" 241.616
-cap "E" "GND" 382.861
-cap "G" "J" 826.287
-cap "E" "li_3524_3378#" 103.966
-cap "Vref" "C" 911.987
-cap "li_16858_13086#" "w_16722_12162#" 809.155
-subcap "li_16316_30#" -4482.1
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_0_0#" 115.595
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#" 722.658
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/a_330_330#" 843.924
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/a_330_330#" -5.67187
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/a_330_330#" 310.302
-subcap "E" -5700.7
-subcap "J" -12535
-subcap "E" -5734.71
-subcap "J" -12520
-subcap "G" -10021.7
-cap "NMOS520_1/a_0_n100#" "nmos2metal_14/a_20_20#" 53.98
-cap "NMOS520_1/a_0_n100#" "NMOS520_2/a_0_n100#" 10.4545
-subcap "En" -13967.1
-cap "En" "NMOS520_2/a_0_n100#" 198.636
-cap "NMOS520_3/a_0_n100#" "En" 209.091
-cap "nmos2metal_10/a_20_20#" "NMOS520_6/a_0_n100#" 55.96
-subcap "K" -1126.52
-subcap "F" -3581.79
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/a_330_330#" 339.071
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_0_0#" -8.59375
-subcap "F" -4088.38
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/a_330_330#" 3.55271e-15
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_0_0#" 518.151
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_0_0#" -11.5156
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/a_330_330#" 828.628
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/a_330_330#" -5.67188
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" 871.941
-cap "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/a_330_330#" -8.25
-subcap "E" -4381
-subcap "J" -12273.5
-subcap "E" -4890.49
-subcap "J" -11740.5
-subcap "G" -10399.9
-subcap "K" -2513.38
-subcap "F" -3645.46
-cap "F" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_0_0#" 20.087
-cap "F" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_153_153#" 9.2093
-subcap "F" -4013.77
-subcap "A" -8629.36
-subcap "A" -7485.97
-cap "nmos2metal_8/a_20_20#" "NMOS520_0/a_0_n100#" 55.96
-subcap "B" -216.677
-cap "NMOS520_3/a_0_n100#" "nmos2metal_1/a_20_20#" -22.5812
-subcap "D" -481.894
-cap "NMOS520_3/a_0_n100#" "nmos2metal_1/a_20_20#" -5.925
-cap "nmos2metal_1/a_20_20#" "NMOS520_2/a_1000_0#" -2.42946
-subcap "D" -341.001
-cap "NMOS520_4/a_0_n100#" "nmos2metal_4/a_20_20#" 53.98
-subcap "Vref" -9686.94
-subcap "C" -7910.71
-cap "PMOS520_0/a_0_n60#" "PMOS520_0/w_n502_n372#" 24.4496
-cap "PMOS520_1/w_n502_n372#" "PMOS520_0/a_1000_0#" 25.5152
-cap "PMOS520_1/a_0_n60#" "PMOS520_2/w_n502_n372#" 47.7818
-subcap "H" -2029.06
-cap "PMOS520_2/a_1000_0#" "PMOS520_2/a_0_n60#" 59.92
-subcap "H" -680.178
-cap "PMOS520_2/a_1000_0#" "PMOS520_2/w_n502_n372#" 47.4118
-subcap "w_16722_12162#" -20048.8
-subcap "w_16722_12162#" -14502.8
-cap "PMOS520_0/w_n502_n372#" "pmos2metal_0/a_20_20#" 42.4464
-cap "pmos2metal_1/a_20_20#" "PMOS520_1/w_n502_n372#" 43.6304
-cap "PMOS520_2/a_0_n60#" "pmos2metal_2/a_20_20#" 52
-cap "PMOS520_2/w_n502_n372#" "pmos2metal_2/a_20_20#" 43.2012
-subcap "li_16858_13086#" -18402.4
-subcap "li_16858_13086#" -15817.7
-merge "pmos2metal_3/a_20_20#" "PMOS520_0/a_1000_0#" 1462.63 0 0 0 0 0 0 0 0 0 0 0 0 -25600 -640 -86168 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1947084 -4784 0 0 214742 -2164 11190 -968 493014 -5886 0 0 0 0 0 0 0 0
-merge "PMOS520_0/a_1000_0#" "nmos2metal_0/a_20_20#"
-merge "nmos2metal_0/a_20_20#" "NMOS520_2/a_1000_0#"
-merge "NMOS520_2/a_1000_0#" "NMOS520_3/a_0_n100#"
-merge "NMOS520_3/a_0_n100#" "NMOS520_2/a_0_n100#"
-merge "NMOS520_2/a_0_n100#" "NMOS120_0/a_0_n60#"
-merge "NMOS120_0/a_0_n60#" "A"
-merge "pmos_substrate_4/SUB" "pmos_substrate_5/SUB" -1817.71 0 0 0 0 0 0 0 0 0 0 0 0 -140312 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -486040 -6178 0 0 0 0 0 0 0 0 0 0 0 0
-merge "pmos_substrate_5/SUB" "pmos_substrate_3/SUB"
-merge "pmos_substrate_3/SUB" "pmos_substrate_2/SUB"
-merge "pmos_substrate_2/SUB" "pmos_substrate_0/SUB"
-merge "pmos_substrate_0/SUB" "pmos_substrate_1/SUB"
-merge "pmos_substrate_1/SUB" "pmos2metal_2/SUB"
-merge "pmos2metal_2/SUB" "pmos2metal_1/SUB"
-merge "pmos2metal_1/SUB" "pmos2metal_0/SUB"
-merge "pmos2metal_0/SUB" "pmos2metal_5/SUB"
-merge "pmos2metal_5/SUB" "pmos2metal_4/SUB"
-merge "pmos2metal_4/SUB" "PMOS520_2/SUB"
-merge "PMOS520_2/SUB" "PMOS520_1/SUB"
-merge "PMOS520_1/SUB" "pmos2metal_3/SUB"
-merge "pmos2metal_3/SUB" "PMOS520_0/SUB"
-merge "PMOS520_0/SUB" "resistor273K_0/SUB"
-merge "resistor273K_0/SUB" "nmos2metal_6/SUB"
-merge "nmos2metal_6/SUB" "nmos2metal_13/SUB"
-merge "nmos2metal_13/SUB" "nmos2metal_5/SUB"
-merge "nmos2metal_5/SUB" "nmos2metal_4/SUB"
-merge "nmos2metal_4/SUB" "nmos2metal_1/SUB"
-merge "nmos2metal_1/SUB" "nmos2metal_0/SUB"
-merge "nmos2metal_0/SUB" "nmos2metal_2/SUB"
-merge "nmos2metal_2/SUB" "nmos2metal_3/SUB"
-merge "nmos2metal_3/SUB" "nmos2metal_8/SUB"
-merge "nmos2metal_8/SUB" "sky130_fd_pr__pnp_05v5_W3p40L3p40_9/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_9/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/w_153_153#" "li_4582_3350#"
-merge "li_4582_3350#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/w_153_153#" "li_2550_3378#"
-merge "li_2550_3378#" "nmos2metal_7/SUB"
-merge "nmos2metal_7/SUB" "resistor200K_0/SUB"
-merge "resistor200K_0/SUB" "NMOS520_6/SUB"
-merge "NMOS520_6/SUB" "nmos2metal_10/SUB"
-merge "nmos2metal_10/SUB" "NMOS520_5/SUB"
-merge "NMOS520_5/SUB" "nmos2metal_11/SUB"
-merge "nmos2metal_11/SUB" "NMOS520_4/SUB"
-merge "NMOS520_4/SUB" "NMOS520_3/SUB"
-merge "NMOS520_3/SUB" "NMOS520_2/SUB"
-merge "NMOS520_2/SUB" "NMOS520_1/SUB"
-merge "NMOS520_1/SUB" "nmos2metal_14/SUB"
-merge "nmos2metal_14/SUB" "NMOS520_0/SUB"
-merge "NMOS520_0/SUB" "NMOS520_0/a_n202_0#"
-merge "NMOS520_0/a_n202_0#" "nmos2metal_9/SUB"
-merge "nmos2metal_9/SUB" "nmos2metal_9/a_20_20#"
-merge "nmos2metal_9/a_20_20#" "NMOS120_0/SUB"
-merge "NMOS120_0/SUB" "NMOS120_0/a_n80_0#"
-merge "NMOS120_0/a_n80_0#" "resistor30K_0/SUB"
-merge "resistor30K_0/SUB" "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/w_153_153#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_153_153#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_153_153#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_153_153#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/w_0_0#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_153_153#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_0_0#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/w_0_0#" "nmos_substrate_21/a_0_0#"
-merge "nmos_substrate_21/a_0_0#" "nmos_substrate_20/a_0_0#"
-merge "nmos_substrate_20/a_0_0#" "nmos_substrate_18/a_0_0#"
-merge "nmos_substrate_18/a_0_0#" "nmos_substrate_19/a_0_0#"
-merge "nmos_substrate_19/a_0_0#" "nmos_substrate_17/a_0_0#"
-merge "nmos_substrate_17/a_0_0#" "nmos_substrate_16/a_0_0#"
-merge "nmos_substrate_16/a_0_0#" "nmos_substrate_15/a_0_0#"
-merge "nmos_substrate_15/a_0_0#" "nmos_substrate_13/a_0_0#"
-merge "nmos_substrate_13/a_0_0#" "nmos_substrate_14/a_0_0#"
-merge "nmos_substrate_14/a_0_0#" "nmos_substrate_11/a_0_0#"
-merge "nmos_substrate_11/a_0_0#" "nmos_substrate_12/a_0_0#"
-merge "nmos_substrate_12/a_0_0#" "nmos_substrate_10/a_0_0#"
-merge "nmos_substrate_10/a_0_0#" "nmos_substrate_8/a_0_0#"
-merge "nmos_substrate_8/a_0_0#" "nmos_substrate_9/a_0_0#"
-merge "nmos_substrate_9/a_0_0#" "nmos_substrate_7/a_0_0#"
-merge "nmos_substrate_7/a_0_0#" "nmos_substrate_6/a_0_0#"
-merge "nmos_substrate_6/a_0_0#" "nmos_substrate_5/a_0_0#"
-merge "nmos_substrate_5/a_0_0#" "nmos_substrate_4/a_0_0#"
-merge "nmos_substrate_4/a_0_0#" "nmos_substrate_3/a_0_0#"
-merge "nmos_substrate_3/a_0_0#" "nmos_substrate_2/a_0_0#"
-merge "nmos_substrate_2/a_0_0#" "nmos_substrate_0/a_0_0#"
-merge "nmos_substrate_0/a_0_0#" "nmos_substrate_1/a_0_0#"
-merge "nmos_substrate_1/a_0_0#" "GND"
-merge "GND" "SUB"
-merge "SUB" "li_15166_30#"
-merge "li_15166_30#" "li_15714_30#"
-merge "li_15714_30#" "li_16316_30#"
-merge "li_16316_30#" "li_2536_2852#"
-merge "li_2536_2852#" "li_4590_2852#"
-merge "li_4590_2852#" "li_5566_2864#"
-merge "li_5566_2864#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/w_153_153#" "li_3524_3378#"
-merge "li_3524_3378#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/w_153_153#" "li_5544_3358#"
-merge "li_5544_3358#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_9/w_153_153#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_9/w_153_153#" "li_6578_3362#"
-merge "pmos2metal_4/a_20_20#" "PMOS520_1/a_1000_0#" -3449.1 0 0 0 0 0 0 0 0 0 0 0 0 -76800 -1280 -114720 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 133104 -5924 0 0 -272780 -3676 0 0 0 0 0 0 0 0 0 0 0 0
-merge "PMOS520_1/a_1000_0#" "PMOS520_2/a_0_n60#"
-merge "PMOS520_2/a_0_n60#" "PMOS520_1/a_0_n60#"
-merge "PMOS520_1/a_0_n60#" "PMOS520_0/a_0_n60#"
-merge "PMOS520_0/a_0_n60#" "nmos2metal_1/a_20_20#"
-merge "nmos2metal_1/a_20_20#" "NMOS520_3/a_n202_0#"
-merge "NMOS520_3/a_n202_0#" "nmos2metal_8/a_20_20#"
-merge "nmos2metal_8/a_20_20#" "NMOS520_0/a_1000_0#"
-merge "NMOS520_0/a_1000_0#" "C"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_4/a_330_330#" "I" -428.993 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -252222 -534 0 0 0 0 0 0 0 0 0 0
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_9/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/a_330_330#" -3532.46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19476 -1104 -994836 -4070 0 0 0 0 0 0 0 0 0 0
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_8/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_7/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_6/a_330_330#" "resistor30K_0/a_n402_n22#"
-merge "resistor30K_0/a_n402_n22#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_3/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_2/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_1/a_330_330#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#"
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_0/a_330_330#" "E"
-merge "pmos_substrate_4/w_n66_n68#" "pmos_substrate_5/w_n66_n68#" 756.155 0 0 0 0 946224 -6514 0 0 0 0 0 0 49912 0 -170880 -1920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 362052 -3304 -60008 -3830 0 0 0 0 0 0 0 0 0 0
-merge "pmos_substrate_5/w_n66_n68#" "pmos_substrate_3/w_n66_n68#"
-merge "pmos_substrate_3/w_n66_n68#" "pmos_substrate_2/w_n66_n68#"
-merge "pmos_substrate_2/w_n66_n68#" "pmos_substrate_0/w_n66_n68#"
-merge "pmos_substrate_0/w_n66_n68#" "pmos_substrate_1/w_n66_n68#"
-merge "pmos_substrate_1/w_n66_n68#" "PMOS520_2/w_n502_n372#"
-merge "PMOS520_2/w_n502_n372#" "PMOS520_1/w_n502_n372#"
-merge "PMOS520_1/w_n502_n372#" "PMOS520_0/w_n502_n372#"
-merge "PMOS520_0/w_n502_n372#" "w_16722_12162#"
-merge "w_16722_12162#" "pmos2metal_2/a_20_20#"
-merge "pmos2metal_2/a_20_20#" "PMOS520_2/a_n200_0#"
-merge "PMOS520_2/a_n200_0#" "pmos2metal_1/a_20_20#"
-merge "pmos2metal_1/a_20_20#" "PMOS520_1/a_n200_0#"
-merge "PMOS520_1/a_n200_0#" "pmos2metal_0/a_20_20#"
-merge "pmos2metal_0/a_20_20#" "PMOS520_0/a_n200_0#"
-merge "PMOS520_0/a_n200_0#" "resistor200K_0/a_n700_n40#"
-merge "resistor200K_0/a_n700_n40#" "li_16858_13086#"
-merge "nmos2metal_11/a_20_20#" "NMOS520_4/a_1000_0#" -857.202 0 0 0 0 0 0 0 0 0 0 0 0 -75044 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -264816 -1456 -7608 -482 -7608 -482 0 0 0 0 0 0 0 0
-merge "NMOS520_4/a_1000_0#" "resistor30K_0/a_1020_n20#"
-merge "resistor30K_0/a_1020_n20#" "J"
-merge "NMOS520_1/a_n202_0#" "nmos2metal_14/a_20_20#" -468.98 0 0 0 0 0 0 0 0 0 0 0 0 -97440 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 141364 -368 8360 -758 8360 -758 0 0 0 0 0 0 0 0
-merge "nmos2metal_14/a_20_20#" "li_16144_1712#"
-merge "nmos2metal_7/a_20_20#" "NMOS520_6/a_1000_0#" -1573.13 0 0 0 0 0 0 0 0 0 0 0 0 -97448 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -452492 -3550 0 0 0 0 0 0 0 0 0 0 0 0
-merge "NMOS520_6/a_1000_0#" "resistor200K_0/a_6964_n40#"
-merge "resistor200K_0/a_6964_n40#" "K"
-merge "NMOS520_6/a_0_n100#" "NMOS520_5/a_0_n100#" -6224.62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3843272 -21465 0 0 49432 -940 0 0 0 0 0 0 0 0 0 0 0 0
-merge "NMOS520_5/a_0_n100#" "NMOS520_4/a_0_n100#"
-merge "NMOS520_4/a_0_n100#" "NMOS520_1/a_0_n100#"
-merge "NMOS520_1/a_0_n100#" "En"
-merge "resistor273K_0/a_8730_n10#" "NMOS520_5/a_1000_0#" -5457.73 0 0 0 0 0 0 0 0 0 0 0 0 -25600 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -849028 -4354 46796 -1508 -1005684 -17038 0 0 0 0 0 0 0 0
-merge "NMOS520_5/a_1000_0#" "nmos2metal_13/a_20_20#"
-merge "nmos2metal_13/a_20_20#" "Vref"
-merge "nmos2metal_2/a_20_20#" "NMOS520_2/a_n202_0#" -653.38 0 0 0 0 0 0 0 0 0 0 0 0 -88320 -1280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1740 -1088 0 0 0 0 0 0 0 0 0 0 0 0
-merge "NMOS520_2/a_n202_0#" "nmos2metal_3/a_20_20#"
-merge "nmos2metal_3/a_20_20#" "NMOS520_1/a_1000_0#"
-merge "NMOS520_1/a_1000_0#" "B"
-merge "nmos2metal_5/a_20_20#" "NMOS520_4/a_n202_0#" -683.246 0 0 0 0 0 0 0 0 0 0 0 0 -86400 -1280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6384 -1172 0 0 0 0 0 0 0 0 0 0 0 0
-merge "NMOS520_4/a_n202_0#" "nmos2metal_4/a_20_20#"
-merge "nmos2metal_4/a_20_20#" "NMOS520_3/a_1000_0#"
-merge "NMOS520_3/a_1000_0#" "D"
-merge "pmos2metal_5/a_20_20#" "PMOS520_2/a_1000_0#" -996.967 0 0 0 0 0 0 0 0 0 0 0 0 -25600 -640 -101280 -640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -484076 -1344 0 0 0 0 0 0 0 0 0 0 0 0
-merge "PMOS520_2/a_1000_0#" "NMOS520_5/a_n202_0#"
-merge "NMOS520_5/a_n202_0#" "nmos2metal_6/a_20_20#"
-merge "nmos2metal_6/a_20_20#" "H"
-merge "NMOS520_6/a_n202_0#" "nmos2metal_10/a_20_20#" -3347.98 0 0 0 0 0 0 0 0 0 0 0 0 -85704 -784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -513792 -3400 0 0 -212956 -4986 890 -290 890 -290 0 0 0 0 0 0 0 0
-merge "nmos2metal_10/a_20_20#" "NMOS520_0/a_0_n100#"
-merge "NMOS520_0/a_0_n100#" "NMOS120_0/a_200_0#"
-merge "NMOS120_0/a_200_0#" "G"
-merge "resistor273K_0/a_n430_n10#" "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/a_330_330#" -1141.51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -391838 -1798 10206 -842 0 0 0 0 0 0 0 0 0 0
-merge "sky130_fd_pr__pnp_05v5_W3p40L3p40_5/a_330_330#" "F"
diff --git a/caravel/mag/BGR.mag b/caravel/mag/BGR.mag
deleted file mode 100644
index 91862f6..0000000
--- a/caravel/mag/BGR.mag
+++ /dev/null
@@ -1,953 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1620723023
-<< nwell >>
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-rect 18704 6398 18896 6443
-rect 17532 6070 18014 6244
-rect 19170 6170 19332 7040
-rect 19568 6788 19760 7148
-rect 19570 6172 19752 6788
-rect 20836 6064 21374 6232
-rect 22900 6062 23062 7998
-rect 24066 7292 24388 7554
-rect 24066 7258 24189 7292
-rect 24223 7258 24388 7292
-rect 24066 7220 24388 7258
-rect 24066 7186 24189 7220
-rect 24223 7186 24388 7220
-rect 24066 6986 24388 7186
-rect 24118 6154 24262 6986
-rect 2532 4272 2700 4330
-rect 2532 4238 2586 4272
-rect 2620 4238 2700 4272
-rect 2532 4192 2700 4238
-rect 2550 3378 2650 3512
-rect 3524 3378 3624 3512
-rect 4582 3350 4682 3484
-rect 5544 3358 5644 3492
-rect 6578 3362 6674 3486
-rect 5790 3328 6972 3334
-rect 2214 3304 6972 3328
-rect 1082 3298 6972 3304
-rect 868 3290 6972 3298
-rect 810 3004 6972 3290
-rect 810 2984 1184 3004
-rect 2214 3000 6972 3004
-rect 810 568 1114 2984
-rect 2536 2852 2636 2986
-rect 3574 2868 3674 3000
-rect 4590 2852 4690 2986
-rect 5566 2864 5666 2998
-rect 5790 2968 6972 3000
-rect 6578 2870 6674 2968
-rect 9610 2956 10054 2992
-rect 9610 2922 9753 2956
-rect 9787 2922 9825 2956
-rect 9859 2922 9897 2956
-rect 9931 2922 10054 2956
-rect 9610 2880 10054 2922
-rect 11040 2874 12092 3002
-rect 11836 2810 12086 2874
-rect 11152 1405 11256 1422
-rect 11152 1371 11187 1405
-rect 11221 1371 11256 1405
-rect 11152 1333 11256 1371
-rect 11152 1299 11187 1333
-rect 11221 1299 11256 1333
-rect 11152 1282 11256 1299
-rect 11836 1072 12092 2810
-rect 26866 2798 27014 3542
-rect 26870 2754 27002 2798
-rect 26874 2638 27002 2754
-rect 13294 1072 13756 1206
-rect 14222 1188 14280 2398
-rect 14514 1838 14570 2404
-rect 14452 1769 14606 1838
-rect 14452 1735 14511 1769
-rect 14545 1735 14606 1769
-rect 14452 1656 14606 1735
-rect 11824 1007 13756 1072
-rect 11824 829 13431 1007
-rect 13537 829 13756 1007
-rect 11824 800 13756 829
-rect 13294 690 13756 800
-rect 14224 718 14280 1188
-rect 14708 1492 14884 2576
-rect 15494 2209 15700 2268
-rect 15494 2107 15542 2209
-rect 15644 2107 15700 2209
-rect 15158 1802 15292 1864
-rect 15494 1802 15700 2107
-rect 16298 1944 16408 2528
-rect 19076 2017 19334 2070
-rect 15158 1765 15700 1802
-rect 15158 1731 15197 1765
-rect 15231 1731 15700 1765
-rect 15158 1704 15700 1731
-rect 16144 1831 16428 1944
-rect 19076 1915 19161 2017
-rect 19263 1915 19334 2017
-rect 19076 1858 19334 1915
-rect 22510 1890 22606 2540
-rect 16144 1797 16262 1831
-rect 16296 1797 16428 1831
-rect 16144 1712 16428 1797
-rect 22458 1802 22656 1890
-rect 22458 1768 22550 1802
-rect 22584 1768 22656 1802
-rect 15158 1654 15292 1704
-rect 15494 1612 15700 1704
-rect 22458 1692 22656 1768
-rect 24618 1626 24764 2636
-rect 25854 2476 27006 2638
-rect 21954 1612 24764 1626
-rect 14224 670 14286 718
-rect 804 66 1116 568
-rect 14230 66 14286 670
-rect 14708 612 14888 1492
-rect 15494 1466 24764 1612
-rect 15494 1464 16404 1466
-rect 16492 1464 24764 1466
-rect 15494 1454 15700 1464
-rect 15840 1456 16404 1464
-rect 21858 1454 24764 1464
-rect 15002 1072 15288 1176
-rect 19566 1076 19754 1082
-rect 22352 1076 22706 1116
-rect 19476 1074 22706 1076
-rect 16918 1072 22706 1074
-rect 15002 1011 22706 1072
-rect 15002 976 22468 1011
-rect 15002 942 15131 976
-rect 15165 942 22468 976
-rect 15002 905 22468 942
-rect 22574 905 22706 1011
-rect 15002 904 22706 905
-rect 15002 870 15131 904
-rect 15165 870 22706 904
-rect 15002 844 22706 870
-rect 15002 842 22390 844
-rect 15002 728 15288 842
-rect 16918 840 19796 842
-rect 19476 836 19796 840
-rect 14710 66 14882 612
-rect 670 65 1246 66
-rect 670 31 671 65
-rect 705 31 761 65
-rect 795 31 851 65
-rect 885 31 941 65
-rect 975 31 1031 65
-rect 1065 31 1121 65
-rect 1155 31 1211 65
-rect 1245 31 1246 65
-rect 670 30 1246 31
-rect 14016 65 14532 66
-rect 14016 31 14141 65
-rect 14175 31 14231 65
-rect 14265 31 14321 65
-rect 14355 31 14532 65
-rect 14016 30 14532 31
-rect 14566 65 15070 66
-rect 14566 31 14682 65
-rect 14716 31 14771 65
-rect 14805 31 14860 65
-rect 14894 31 15070 65
-rect 14566 30 15070 31
-rect 15166 30 15672 66
-rect 15714 30 16220 66
-rect 16316 30 26422 66
-<< viali >>
-rect 16861 13087 16895 13121
-rect 16993 13087 17027 13121
-rect 17149 13087 17183 13121
-rect 17289 13087 17323 13121
-rect 18921 13087 18955 13121
-rect 19069 13087 19103 13121
-rect 19221 13087 19255 13121
-rect 19337 13087 19371 13121
-rect 20943 13087 20977 13121
-rect 21063 13087 21097 13121
-rect 21189 13087 21223 13121
-rect 21295 13087 21329 13121
-rect 26733 13087 26767 13121
-rect 26903 13087 26937 13121
-rect 27049 13087 27083 13121
-rect 27211 13087 27245 13121
-rect 15734 7313 15840 7419
-rect 14442 6809 14476 6843
-rect 17963 6824 17997 6858
-rect 17963 6752 17997 6786
-rect 24189 7258 24223 7292
-rect 24189 7186 24223 7220
-rect 2586 4238 2620 4272
-rect 9753 2922 9787 2956
-rect 9825 2922 9859 2956
-rect 9897 2922 9931 2956
-rect 11187 1371 11221 1405
-rect 11187 1299 11221 1333
-rect 14511 1735 14545 1769
-rect 13431 829 13537 1007
-rect 15197 1731 15231 1765
-rect 16262 1797 16296 1831
-rect 22550 1768 22584 1802
-rect 15131 942 15165 976
-rect 22468 905 22574 1011
-rect 15131 870 15165 904
-rect 671 31 705 65
-rect 761 31 795 65
-rect 851 31 885 65
-rect 941 31 975 65
-rect 1031 31 1065 65
-rect 1121 31 1155 65
-rect 1211 31 1245 65
-rect 14141 31 14175 65
-rect 14231 31 14265 65
-rect 14321 31 14355 65
-rect 14682 31 14716 65
-rect 14771 31 14805 65
-rect 14860 31 14894 65
-<< metal1 >>
-rect 0 13121 28540 13152
-rect 0 13087 16861 13121
-rect 16895 13087 16993 13121
-rect 17027 13087 17149 13121
-rect 17183 13087 17289 13121
-rect 17323 13087 18921 13121
-rect 18955 13087 19069 13121
-rect 19103 13087 19221 13121
-rect 19255 13087 19337 13121
-rect 19371 13087 20943 13121
-rect 20977 13087 21063 13121
-rect 21097 13087 21189 13121
-rect 21223 13087 21295 13121
-rect 21329 13087 26733 13121
-rect 26767 13087 26903 13121
-rect 26937 13087 27049 13121
-rect 27083 13087 27211 13121
-rect 27245 13087 28540 13121
-rect 0 13056 28540 13087
-rect 15632 7424 15970 7574
-rect 15632 7419 15761 7424
-rect 15813 7419 15970 7424
-rect 15632 7313 15734 7419
-rect 15840 7313 15970 7419
-rect 15632 7308 15761 7313
-rect 15813 7308 15970 7313
-rect 15632 7158 15970 7308
-rect 24066 7292 24388 7554
-rect 24066 7265 24189 7292
-rect 24223 7265 24388 7292
-rect 24066 7213 24180 7265
-rect 24232 7213 24388 7265
-rect 24066 7186 24189 7213
-rect 24223 7186 24388 7213
-rect 24066 6986 24388 7186
-rect 14386 6852 14530 6892
-rect 14386 6800 14433 6852
-rect 14485 6800 14530 6852
-rect 14386 6756 14530 6800
-rect 17882 6863 18096 6946
-rect 17882 6811 17954 6863
-rect 18006 6811 18096 6863
-rect 17882 6799 18096 6811
-rect 17882 6747 17954 6799
-rect 18006 6747 18096 6799
-rect 17882 6676 18096 6747
-rect 2532 4272 2700 4330
-rect 2532 4238 2586 4272
-rect 2620 4238 2700 4272
-rect 2532 4192 2700 4238
-rect 2554 3668 2656 4192
-rect 6564 3732 9810 3736
-rect 3516 3638 9810 3732
-rect 3568 2732 3646 3638
-rect 6564 3608 9810 3638
-rect 9388 3600 9810 3608
-rect 9654 3012 9810 3600
-rect 9654 2992 10016 3012
-rect 9610 2956 10054 2992
-rect 9610 2922 9753 2956
-rect 9787 2922 9825 2956
-rect 9859 2922 9897 2956
-rect 9931 2922 10054 2956
-rect 9610 2880 10054 2922
-rect 2518 2638 5568 2732
-rect 6554 2636 9142 2758
-rect 9046 1396 9136 2636
-rect 14454 1836 14514 1840
-rect 14570 1836 14606 1840
-rect 14454 1774 14606 1836
-rect 14454 1722 14504 1774
-rect 14556 1722 14606 1774
-rect 14454 1656 14606 1722
-rect 15154 1824 15294 1864
-rect 16144 1840 16428 1944
-rect 15154 1773 15298 1824
-rect 15154 1721 15197 1773
-rect 15249 1721 15298 1773
-rect 15154 1708 15298 1721
-rect 16144 1788 16253 1840
-rect 16305 1788 16428 1840
-rect 16144 1712 16428 1788
-rect 22458 1886 22510 1888
-rect 22606 1886 22658 1888
-rect 22458 1812 22658 1886
-rect 22458 1760 22542 1812
-rect 22594 1760 22658 1812
-rect 15154 1652 15294 1708
-rect 22458 1688 22658 1760
-rect 11038 1405 11398 1608
-rect 11038 1396 11187 1405
-rect 9046 1371 11187 1396
-rect 11221 1371 11398 1405
-rect 9046 1333 11398 1371
-rect 9046 1299 11187 1333
-rect 11221 1299 11398 1333
-rect 9046 1262 11398 1299
-rect 9052 1256 11398 1262
-rect 11038 1120 11398 1256
-rect 13300 1036 13758 1206
-rect 13292 1007 13758 1036
-rect 13292 832 13429 1007
-rect 13300 827 13429 832
-rect 13545 827 13758 1007
-rect 13300 690 13758 827
-rect 15004 1068 15292 1170
-rect 22352 1068 22706 1116
-rect 15004 982 15294 1068
-rect 15004 930 15130 982
-rect 15182 930 15294 982
-rect 15004 918 15294 930
-rect 15004 866 15130 918
-rect 15182 866 15294 918
-rect 15004 848 15294 866
-rect 22350 1011 22706 1068
-rect 22350 905 22468 1011
-rect 22574 905 22706 1011
-rect 22350 848 22706 905
-rect 15004 728 15292 848
-rect 22352 844 22706 848
-rect 0 65 28540 96
-rect 0 31 671 65
-rect 705 31 761 65
-rect 795 31 851 65
-rect 885 31 941 65
-rect 975 31 1031 65
-rect 1065 31 1121 65
-rect 1155 31 1211 65
-rect 1245 31 14141 65
-rect 14175 31 14231 65
-rect 14265 31 14321 65
-rect 14355 31 14682 65
-rect 14716 31 14771 65
-rect 14805 31 14860 65
-rect 14894 31 28540 65
-rect 0 0 28540 31
-<< via1 >>
-rect 15761 7419 15813 7424
-rect 15761 7372 15813 7419
-rect 15761 7313 15813 7360
-rect 15761 7308 15813 7313
-rect 24180 7258 24189 7265
-rect 24189 7258 24223 7265
-rect 24223 7258 24232 7265
-rect 24180 7220 24232 7258
-rect 24180 7213 24189 7220
-rect 24189 7213 24223 7220
-rect 24223 7213 24232 7220
-rect 14433 6843 14485 6852
-rect 14433 6809 14442 6843
-rect 14442 6809 14476 6843
-rect 14476 6809 14485 6843
-rect 14433 6800 14485 6809
-rect 17954 6858 18006 6863
-rect 17954 6824 17963 6858
-rect 17963 6824 17997 6858
-rect 17997 6824 18006 6858
-rect 17954 6811 18006 6824
-rect 17954 6786 18006 6799
-rect 17954 6752 17963 6786
-rect 17963 6752 17997 6786
-rect 17997 6752 18006 6786
-rect 17954 6747 18006 6752
-rect 14504 1769 14556 1774
-rect 14504 1735 14511 1769
-rect 14511 1735 14545 1769
-rect 14545 1735 14556 1769
-rect 14504 1722 14556 1735
-rect 15197 1765 15249 1773
-rect 15197 1731 15231 1765
-rect 15231 1731 15249 1765
-rect 15197 1721 15249 1731
-rect 16253 1831 16305 1840
-rect 16253 1797 16262 1831
-rect 16262 1797 16296 1831
-rect 16296 1797 16305 1831
-rect 16253 1788 16305 1797
-rect 22542 1802 22594 1812
-rect 22542 1768 22550 1802
-rect 22550 1768 22584 1802
-rect 22584 1768 22594 1802
-rect 22542 1760 22594 1768
-rect 13429 829 13431 1007
-rect 13431 829 13537 1007
-rect 13537 829 13545 1007
-rect 13429 827 13545 829
-rect 15130 976 15182 982
-rect 15130 942 15131 976
-rect 15131 942 15165 976
-rect 15165 942 15182 976
-rect 15130 930 15182 942
-rect 15130 904 15182 918
-rect 15130 870 15131 904
-rect 15131 870 15165 904
-rect 15165 870 15182 904
-rect 15130 866 15182 870
-rect 22495 931 22547 983
-<< metal2 >>
-rect 15632 7424 15970 7574
-rect 15632 7372 15761 7424
-rect 15813 7372 15970 7424
-rect 15632 7360 15970 7372
-rect 15632 7308 15761 7360
-rect 15813 7334 15970 7360
-rect 24066 7334 24388 7554
-rect 15813 7308 24388 7334
-rect 15632 7265 24388 7308
-rect 15632 7213 24180 7265
-rect 24232 7213 24388 7265
-rect 15632 7204 24388 7213
-rect 15632 7158 15970 7204
-rect 24066 6986 24388 7204
-rect 14386 6852 14530 6892
-rect 14386 6800 14433 6852
-rect 14485 6844 14530 6852
-rect 17882 6863 18096 6946
-rect 17882 6844 17954 6863
-rect 14485 6811 17954 6844
-rect 18006 6811 18096 6863
-rect 14485 6800 18096 6811
-rect 14386 6799 18096 6800
-rect 14386 6790 17954 6799
-rect 14386 6756 14530 6790
-rect 15902 6786 16130 6790
-rect 17882 6747 17954 6790
-rect 18006 6747 18096 6799
-rect 17882 6676 18096 6747
-rect 14454 1836 14514 1840
-rect 14570 1836 14606 1840
-rect 14454 1820 14606 1836
-rect 15154 1820 15294 1864
-rect 14454 1774 15294 1820
-rect 14454 1722 14504 1774
-rect 14556 1773 15294 1774
-rect 14556 1722 15197 1773
-rect 14454 1721 15197 1722
-rect 15249 1721 15294 1773
-rect 14454 1692 15294 1721
-rect 16144 1840 16428 1944
-rect 16144 1788 16253 1840
-rect 16305 1788 16428 1840
-rect 16144 1712 16428 1788
-rect 22458 1886 22510 1888
-rect 22606 1886 22658 1888
-rect 22458 1812 22658 1886
-rect 22458 1760 22542 1812
-rect 22594 1760 22658 1812
-rect 14454 1656 14606 1692
-rect 14692 1690 14948 1692
-rect 15154 1652 15294 1692
-rect 11038 1410 11398 1608
-rect 16234 1410 16382 1712
-rect 22458 1688 22658 1760
-rect 11038 1270 16386 1410
-rect 22494 1320 22572 1688
-rect 11038 1120 11398 1270
-rect 16234 1262 16382 1270
-rect 13300 1084 13758 1206
-rect 14214 1084 14318 1086
-rect 15004 1084 15292 1170
-rect 22496 1116 22572 1320
-rect 13300 1007 15292 1084
-rect 13300 827 13429 1007
-rect 13545 982 15292 1007
-rect 13545 930 15130 982
-rect 15182 930 15292 982
-rect 13545 918 15292 930
-rect 13545 866 15130 918
-rect 15182 866 15292 918
-rect 13545 827 15292 866
-rect 22352 983 22706 1116
-rect 22352 931 22495 983
-rect 22547 931 22706 983
-rect 22352 844 22706 931
-rect 13300 796 15292 827
-rect 13300 690 13758 796
-rect 15004 728 15292 796
-use resistor30K  resistor30K_0
-timestamp 1620719712
-transform 1 0 10016 0 1 2900
-box -402 -22 1462 96
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_5
-timestamp 1615375237
-transform 1 0 6218 0 1 2296
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_6
-timestamp 1615375237
-transform 1 0 5200 0 1 2284
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_7
-timestamp 1615375237
-transform 1 0 4230 0 1 2284
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_8
-timestamp 1615375237
-transform 1 0 3226 0 1 2296
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_9
-timestamp 1615375237
-transform 1 0 2182 0 1 2266
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_3
-timestamp 1615375237
-transform 1 0 3180 0 1 3292
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_4
-timestamp 1615375237
-transform 1 0 2206 0 1 3292
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_0
-timestamp 1615375237
-transform 1 0 6218 0 1 3270
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_1
-timestamp 1615375237
-transform 1 0 5198 0 1 3270
-box 26 26 770 795
-use sky130_fd_pr__pnp_05v5_W3p40L3p40  sky130_fd_pr__pnp_05v5_W3p40L3p40_2
-timestamp 1615375237
-transform 1 0 4224 0 1 3270
-box 26 26 770 795
-use resistor273K  resistor273K_0
-timestamp 1620719712
-transform 1 0 3522 0 1 8642
-box -430 -10 9170 80
-use nmos2metal120  nmos2metal120_1
-timestamp 1620722909
-transform 1 0 14524 0 1 2410
-box -16 -16 50 50
-use nmos2metal120  nmos2metal120_0
-timestamp 1620722909
-transform 1 0 14238 0 1 2406
-box -16 -16 50 50
-use nmos_substrate  nmos_substrate_21
-timestamp 1620719712
-transform 1 0 14470 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_20
-timestamp 1620719712
-transform 1 0 13920 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_19
-timestamp 1620719712
-transform 1 0 15070 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_18
-timestamp 1620719712
-transform 1 0 15620 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_6
-timestamp 1620719712
-transform 1 0 14910 0 1 2360
-box -202 -100 1202 4100
-use NMOS120  NMOS120_0
-timestamp 1620719712
-transform 1 0 14302 0 1 2380
-box -80 -60 280 4060
-use nmos2metal  nmos2metal_13
-timestamp 1620719712
-transform 1 0 14708 0 1 2456
-box 0 0 200 200
-use nmos_substrate  nmos_substrate_17
-timestamp 1620719712
-transform 1 0 16220 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_16
-timestamp 1620719712
-transform 1 0 16820 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_15
-timestamp 1620719712
-transform 1 0 17420 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_5
-timestamp 1620719712
-transform 1 0 16458 0 1 2350
-box -202 -100 1202 4100
-use nmos2metal  nmos2metal_12
-timestamp 1620719712
-transform 1 0 16260 0 1 2454
-box 0 0 200 200
-use nmos_substrate  nmos_substrate_14
-timestamp 1620719712
-transform 1 0 19220 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_13
-timestamp 1620719712
-transform 1 0 18620 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_12
-timestamp 1620719712
-transform 1 0 18020 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_11
-timestamp 1620719712
-transform 1 0 19820 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_3
-timestamp 1620719712
-transform 1 0 18150 0 1 2350
-box -202 -100 1202 4100
-use NMOS520  NMOS520_4
-timestamp 1620719712
-transform 1 0 19758 0 1 2350
-box -202 -100 1202 4100
-use nmos_substrate  nmos_substrate_10
-timestamp 1620719712
-transform 1 0 21020 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_9
-timestamp 1620719712
-transform 1 0 20420 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_2
-timestamp 1620719712
-transform 1 0 21446 0 1 2360
-box -202 -100 1202 4100
-use PMOS520  PMOS520_2
-timestamp 1620719712
-transform 1 0 17220 0 1 7896
-box -502 -372 1500 4374
-use nmos2metal  nmos2metal_10
-timestamp 1620719712
-transform 1 0 15906 0 1 6062
-box 0 0 200 200
-use nmos2metal  nmos2metal_11
-timestamp 1620719712
-transform 1 0 17462 0 1 6056
-box 0 0 200 200
-use pmos2metaal  pmos2metaal_5
-timestamp 1620719712
-transform 1 0 18224 0 1 8002
-box -72 -66 272 268
-use PMOS520  PMOS520_1
-timestamp 1620719712
-transform 1 0 19218 0 1 7886
-box -502 -372 1500 4374
-use nmos2metal  nmos2metal_7
-timestamp 1620719712
-transform 1 0 17948 0 1 6054
-box 0 0 200 200
-use nmos2metal  nmos2metal_8
-timestamp 1620719712
-transform 1 0 19558 0 1 6054
-box 0 0 200 200
-use nmos2metal  nmos2metal_9
-timestamp 1620719712
-transform 1 0 19148 0 1 6054
-box 0 0 200 200
-use pmos2metaal  pmos2metaal_4
-timestamp 1620719712
-transform 1 0 20216 0 1 7982
-box -72 -66 272 268
-use PMOS520  PMOS520_0
-timestamp 1620719712
-transform 1 0 21214 0 1 7884
-box -502 -372 1500 4374
-use nmos2metal  nmos2metal_5
-timestamp 1620719712
-transform 1 0 21248 0 1 6054
-box 0 0 200 200
-use nmos2metal  nmos2metal_6
-timestamp 1620719712
-transform 1 0 20760 0 1 6046
-box 0 0 200 200
-use pmos2metaal  pmos2metaal_3
-timestamp 1620719712
-transform 1 0 17014 0 1 11590
-box -72 -66 272 268
-use pmos_substrate  pmos_substrate_5
-timestamp 1620719712
-transform 1 0 17606 0 1 13056
-box -66 -68 162 162
-use pmos2metaal  pmos2metaal_2
-timestamp 1620719712
-transform 1 0 19014 0 1 11582
-box -72 -66 272 268
-use pmos_substrate  pmos_substrate_4
-timestamp 1620719712
-transform 1 0 19656 0 1 13056
-box -66 -68 162 162
-use pmos_substrate  pmos_substrate_3
-timestamp 1620719712
-transform 1 0 18290 0 1 13056
-box -66 -68 162 162
-use pmos2metaal  pmos2metaal_1
-timestamp 1620719712
-transform 1 0 21014 0 1 11580
-box -72 -66 272 268
-use pmos_substrate  pmos_substrate_2
-timestamp 1620719712
-transform 1 0 20226 0 1 13056
-box -66 -68 162 162
-use pmos2metaal  pmos2metaal_0
-timestamp 1620719712
-transform 1 0 22206 0 1 7980
-box -72 -66 272 268
-use nmos_substrate  nmos_substrate_8
-timestamp 1620719712
-transform 1 0 22218 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_7
-timestamp 1620719712
-transform 1 0 21620 0 1 0
-box -26 -26 122 122
-use pmos_substrate  pmos_substrate_1
-timestamp 1620719712
-transform 1 0 22062 0 1 13056
-box -66 -68 162 162
-use pmos_substrate  pmos_substrate_0
-timestamp 1620719712
-transform 1 0 21496 0 1 13056
-box -66 -68 162 162
-use nmos_substrate  nmos_substrate_6
-timestamp 1620719712
-transform 1 0 22820 0 1 0
-box -26 -26 122 122
-use nmos2metal  nmos2metal_4
-timestamp 1620719712
-transform 1 0 22454 0 1 2462
-box 0 0 200 200
-use nmos_substrate  nmos_substrate_5
-timestamp 1620719712
-transform 1 0 23420 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_4
-timestamp 1620719712
-transform 1 0 24020 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_1
-timestamp 1620719712
-transform 1 0 23088 0 1 2350
-box -202 -100 1202 4100
-use nmos2metal  nmos2metal_2
-timestamp 1620719712
-transform 1 0 22882 0 1 6034
-box 0 0 200 200
-use nmos2metal  nmos2metal_3
-timestamp 1620719712
-transform 1 0 24092 0 1 6026
-box 0 0 200 200
-use nmos_substrate  nmos_substrate_3
-timestamp 1620719712
-transform 1 0 25220 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_2
-timestamp 1620719712
-transform 1 0 24620 0 1 0
-box -26 -26 122 122
-use NMOS520  NMOS520_0
-timestamp 1620719712
-transform 1 0 24788 0 1 2360
-box -202 -100 1202 4100
-use nmos2metal  nmos2metal_1
-timestamp 1620719712
-transform 1 0 24592 0 1 2460
-box 0 0 200 200
-use resistor200K  resistor200K_0
-timestamp 1620719712
-transform 0 1 26910 -1 0 10506
-box -700 -40 7704 102
-use nmos_substrate  nmos_substrate_1
-timestamp 1620719712
-transform 1 0 25820 0 1 0
-box -26 -26 122 122
-use nmos_substrate  nmos_substrate_0
-timestamp 1620719712
-transform 1 0 26420 0 1 0
-box -26 -26 122 122
-use nmos2metal  nmos2metal_0
-timestamp 1620719712
-transform 1 0 25790 0 1 2458
-box 0 0 200 200
-<< labels >>
-flabel poly s 19936 6370 20158 6624 0 FreeSans 3125 0 0 0 A
-flabel metal1 s 8076 3704 8076 3704 0 FreeSans 3125 0 0 0 E
-rlabel poly s 21236 7726 21236 7726 4 C
-flabel locali s 22970 7622 22970 7622 0 FreeSans 3125 0 0 0 H
-rlabel poly s 20276 6456 20276 6456 4 A
-rlabel poly s 18652 7708 18652 7708 4 C
-rlabel locali s 17818 6132 17818 6132 4 B
-rlabel locali s 21130 6132 21130 6132 4 D
-rlabel locali s 11914 2476 11914 2476 4 J
-rlabel metal1 s 8714 3658 8714 3658 4 E
-rlabel metal1 s 8372 2686 8372 2686 4 I
-rlabel locali s 26510 2526 26510 2526 4 K
-rlabel locali s 21532 1524 21532 1524 4 G
-rlabel locali s 2630 5638 2630 5638 4 F
-flabel metal1 s 11202 36 11202 36 0 FreeSans 3125 0 0 0 GND
-port 1 nsew
-flabel locali s 13292 8670 13292 8670 0 FreeSans 3125 0 0 0 Vref
-port 2 nsew
-flabel locali s 19130 1888 19294 2044 0 FreeSans 3125 0 0 0 En
-port 3 nsew
-flabel metal1 s 9822 13102 9822 13102 0 FreeSans 2000 0 0 0 VDD
-port 4 nsew
-<< properties >>
-string FIXED_BBOX 0 48 28540 13104
-<< end >>
diff --git a/caravel/mag/BGR.spice b/caravel/mag/BGR.spice
deleted file mode 100644
index 205c5f6..0000000
--- a/caravel/mag/BGR.spice
+++ /dev/null
@@ -1,55 +0,0 @@
-* SPICE3 file created from BGR.ext - technology: sky130A
-
-.option scale=5000u
-
-.subckt BGR GND Vref En
-X0 E GND GND sky130_fd_pr__pnp_05v0 area=1.29416e+09
-X1 A C w_16722_12162# w_16722_12162# sky130_fd_pr__pfet_g5v0d10v5 ad=72 pd=0 as=-1 ps=-1 w=4000 l=1000
-X2 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X3 C C w_16722_12162# w_16722_12162# sky130_fd_pr__pfet_g5v0d10v5 ad=0 pd=0 as=-0 ps=-0 w=4000 l=1000
-X4 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X5 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X6 H C w_16722_12162# w_16722_12162# sky130_fd_pr__pfet_g5v0d10v5 ad=113 pd=0 as=-0 ps=-0 w=4000 l=1000
-X7 I GND GND sky130_fd_pr__pnp_05v0 area=1.27541e+09
-X8 F GND GND sky130_fd_pr__pnp_05v0 area=113
-X9 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X10 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X11 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X12 E GND GND sky130_fd_pr__pnp_05v0 area=0
-X13 F Vref GND sky130_fd_pr__res_xhigh_po w=70 l=8720
-X14 E J GND sky130_fd_pr__res_xhigh_po w=70 l=980
-X15 w_16722_12162# K GND sky130_fd_pr__res_xhigh_po w=70 l=6924
-X16 C G GND GND sky130_fd_pr__nfet_g5v0d10v5 ad=0 pd=0 as=0 ps=0 w=4000 l=1000
-X17 B En li_16144_1712# GND sky130_fd_pr__nfet_g5v0d10v5 ad=1.29244e+09 pd=22081 as=897 ps=0 w=4000 l=1000
-X18 A A B GND sky130_fd_pr__nfet_g5v0d10v5 ad=0 pd=0 as=0 ps=0 w=4000 l=1000
-X19 D A C GND sky130_fd_pr__nfet_g5v0d10v5 ad=0 pd=0 as=0 ps=0 w=4000 l=1000
-X20 J En D GND sky130_fd_pr__nfet_g5v0d10v5 ad=337 pd=0 as=0 ps=0 w=4000 l=1000
-X21 Vref En H GND sky130_fd_pr__nfet_g5v0d10v5 ad=135 pd=0 as=0 ps=0 w=4000 l=1000
-X22 K En G GND sky130_fd_pr__nfet_g5v0d10v5 ad=8 pd=0 as=8 ps=0 w=4000 l=1000
-X23 G A GND GND sky130_fd_pr__nfet_g5v0d10v5 ad=0 pd=0 as=0 ps=0 w=4000 l=200
-C0 li_16144_1712# J 1.02fF
-C1 G C 0.06fF
-C2 li_16144_1712# G 0.38fF
-C3 Vref C 0.91fF
-C4 J G 0.83fF
-C5 En D 0.05fF
-C6 Vref H 0.12fF
-C7 w_16722_12162# C 0.12fF
-C8 Vref A 0.81fF
-C9 li_16144_1712# I 0.72fF
-C10 li_16144_1712# En 0.05fF
-C11 H w_16722_12162# 0.05fF
-C12 w_16722_12162# A 0.03fF
-C13 J En 0.47fF
-C14 En A 0.42fF
-C15 H C 0.06fF
-C16 En G 0.39fF
-C17 A C 0.66fF
-C18 li_16144_1712# GND 3.98fF
-C19 D GND 0.12fF
-C20 B GND 0.69fF
-C21 En GND 6.61fF
-C22 C GND 5.08fF
-C23 w_16722_12162# GND 59.23fF
-C24 I GND 4.44fF
-.ends
diff --git a/caravel/mag/NMOS120.ext b/caravel/mag/NMOS120.ext
deleted file mode 100644
index 08bef8b..0000000
--- a/caravel/mag/NMOS120.ext
+++ /dev/null
@@ -1,13 +0,0 @@
-timestamp 1618661559
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
-parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
-node "a_200_0#" 5700 0 200 0 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 320000 8160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n80_0#" 5700 0 -80 0 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 320000 8160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_0_n60#" 993 239.6 0 -60 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 824000 8640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device msubckt sky130_fd_pr__nfet_g5v0d10v5 0 0 1 1 l=200 w=4000 "SUB" "a_0_n60#" 400 0 "a_n80_0#" 4000 0 "a_200_0#" 4000 0
diff --git a/caravel/mag/NMOS120.mag b/caravel/mag/NMOS120.mag
deleted file mode 100644
index 9b6577f..0000000
--- a/caravel/mag/NMOS120.mag
+++ /dev/null
@@ -1,12 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< mvnmos >>
-rect 0 0 100 2000
-<< mvndiff >>
-rect -40 0 0 2000
-rect 100 0 140 2000
-<< poly >>
-rect 0 2000 100 2030
-rect 0 -30 100 0
-<< end >>
diff --git a/caravel/mag/NMOS520.ext b/caravel/mag/NMOS520.ext
deleted file mode 100644
index bd4aa6c..0000000
--- a/caravel/mag/NMOS520.ext
+++ /dev/null
@@ -1,13 +0,0 @@
-timestamp 1618661393
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__nfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
-parameters sky130_fd_pr__nfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
-node "a_1000_0#" 2259 0 1000 0 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 807592 8404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n202_0#" 2282 0 -202 0 mvndif 0 0 0 0 0 0 0 0 0 0 0 0 800200 8404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_0_n100#" 202 1190 0 -100 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4200000 10400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device msubckt sky130_fd_pr__nfet_g5v0d10v5 0 0 1 1 l=1000 w=4000 "SUB" "a_0_n100#" 2000 0 "a_n202_0#" 4000 0 "a_1000_0#" 4000 0
diff --git a/caravel/mag/NMOS520.mag b/caravel/mag/NMOS520.mag
deleted file mode 100644
index 481f138..0000000
--- a/caravel/mag/NMOS520.mag
+++ /dev/null
@@ -1,14 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< mvnmos >>
-rect 0 0 500 2000
-<< mvndiff >>
-rect -100 50 0 2000
-rect -101 0 0 50
-rect 500 1949 599 2000
-rect 500 0 601 1949
-<< poly >>
-rect 0 2000 500 2050
-rect 0 -50 500 0
-<< end >>
diff --git a/caravel/mag/PMOS520.ext b/caravel/mag/PMOS520.ext
deleted file mode 100644
index 66bc8aa..0000000
--- a/caravel/mag/PMOS520.ext
+++ /dev/null
@@ -1,14 +0,0 @@
-timestamp 1619510475
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__pfet_g5v0d10v5 l=l w=w a1=as p1=ps a2=ad p2=pd
-parameters sky130_fd_pr__pfet_20v0 l=l w=w a1=as a2=ad p1=ps p2=pd
-node "a_1000_0#" 3820 0 1000 0 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 800000 8400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n200_0#" 3820 0 -200 0 mvpdif 0 0 0 0 0 0 0 0 0 0 0 0 0 0 800000 8400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_0_n60#" 199 934 0 -60 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4120000 10240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "w_n502_n372#" 4049 28451.3 -502 -372 nw 0 0 0 0 9483760 13496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device msubckt sky130_fd_pr__pfet_g5v0d10v5 0 0 1 1 l=1000 w=4000 "w_n502_n372#" "a_0_n60#" 2000 0 "a_n200_0#" 4000 0 "a_1000_0#" 4000 0
diff --git a/caravel/mag/PMOS520.mag b/caravel/mag/PMOS520.mag
deleted file mode 100644
index 733d95f..0000000
--- a/caravel/mag/PMOS520.mag
+++ /dev/null
@@ -1,16 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< nwell >>
-rect -250 2049 750 2187
-rect -250 -11 749 2049
-rect -251 -186 749 -11
-<< mvpmos >>
-rect 0 0 500 2000
-<< mvpdiff >>
-rect -100 0 0 2000
-rect 500 0 600 2000
-<< poly >>
-rect 0 2000 500 2030
-rect 0 -30 500 0
-<< end >>
diff --git a/caravel/mag/bsim4v5.out b/caravel/mag/bsim4v5.out
deleted file mode 100644
index c13846b..0000000
--- a/caravel/mag/bsim4v5.out
+++ /dev/null
@@ -1,5 +0,0 @@
-BSIM4v5: Berkeley Short Channel IGFET Model-4
-Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
-
-++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
-Model = x16:sky130_fd_pr__nfet_g5v0d10v5__model.2
diff --git a/caravel/mag/nmos2metal.ext b/caravel/mag/nmos2metal.ext
deleted file mode 100644
index a355d09..0000000
--- a/caravel/mag/nmos2metal.ext
+++ /dev/null
@@ -1,8 +0,0 @@
-timestamp 1619503262
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-node "a_20_20#" 126 233.32 20 20 mvndc 0 0 0 0 0 0 0 0 0 0 0 0 25600 640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40000 800 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/caravel/mag/nmos2metal.mag b/caravel/mag/nmos2metal.mag
deleted file mode 100644
index af1bbe3..0000000
--- a/caravel/mag/nmos2metal.mag
+++ /dev/null
@@ -1,17 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1620719712
-<< mvndiff >>
-rect 20 151 180 180
-rect 20 49 49 151
-rect 151 49 180 151
-rect 20 20 180 49
-<< mvndiffc >>
-rect 49 49 151 151
-<< locali >>
-rect 0 151 200 200
-rect 0 49 49 151
-rect 151 49 200 151
-rect 0 0 200 49
-<< end >>
diff --git a/caravel/mag/nmos2metal120.mag b/caravel/mag/nmos2metal120.mag
deleted file mode 100644
index e3b0e03..0000000
--- a/caravel/mag/nmos2metal120.mag
+++ /dev/null
@@ -1,16 +0,0 @@
-magic
-tech sky130A
-timestamp 1620722909
-<< mvndiff >>
-rect -8 17 25 25
-rect -8 0 0 17
-rect 17 0 25 17
-rect -8 -8 25 0
-<< mvndiffc >>
-rect 0 0 17 17
-<< locali >>
-rect -8 17 25 25
-rect -8 0 0 17
-rect 17 0 25 17
-rect -8 -8 25 0
-<< end >>
diff --git a/caravel/mag/nmos_substrate.ext b/caravel/mag/nmos_substrate.ext
deleted file mode 100644
index 2981398..0000000
--- a/caravel/mag/nmos_substrate.ext
+++ /dev/null
@@ -1,7 +0,0 @@
-timestamp 1619685304
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-substrate "a_0_0#" 0 0 0 0 mvppd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9216 384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9216 384 9216 384 0 0 0 0 0 0 0 0 0 0
diff --git a/caravel/mag/nmos_substrate.mag b/caravel/mag/nmos_substrate.mag
deleted file mode 100644
index 073b4bf..0000000
--- a/caravel/mag/nmos_substrate.mag
+++ /dev/null
@@ -1,25 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< pwell >>
-rect -13 -13 61 61
-<< mvpsubdiff >>
-rect 0 32 48 48
-rect 0 15 15 32
-rect 32 15 48 32
-rect 0 0 48 15
-<< mvpsubdiffcont >>
-rect 15 15 32 32
-<< locali >>
-rect 0 32 48 48
-rect 0 15 15 32
-rect 32 15 48 32
-rect 0 0 48 15
-<< viali >>
-rect 15 15 32 32
-<< metal1 >>
-rect 0 32 48 48
-rect 0 15 15 32
-rect 32 15 48 32
-rect 0 0 48 15
-<< end >>
diff --git a/caravel/mag/pmos2metaal.mag b/caravel/mag/pmos2metaal.mag
deleted file mode 100644
index 2b6f1be..0000000
--- a/caravel/mag/pmos2metaal.mag
+++ /dev/null
@@ -1,18 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< nwell >>
-rect -36 -33 136 134
-<< mvpdiff >>
-rect 0 76 100 100
-rect 0 25 25 76
-rect 76 25 100 76
-rect 0 0 100 25
-<< mvpdiffc >>
-rect 25 25 76 76
-<< locali >>
-rect 0 76 100 100
-rect 0 25 25 76
-rect 76 25 100 76
-rect 0 0 100 25
-<< end >>
diff --git a/caravel/mag/pmos2metal.ext b/caravel/mag/pmos2metal.ext
deleted file mode 100644
index 4eee2ef..0000000
--- a/caravel/mag/pmos2metal.ext
+++ /dev/null
@@ -1,8 +0,0 @@
-timestamp 1619503365
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-node "a_20_20#" 203 233.32 20 20 mvpdc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25600 640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40000 800 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/caravel/mag/pmos_substrate.ext b/caravel/mag/pmos_substrate.ext
deleted file mode 100644
index de27ce4..0000000
--- a/caravel/mag/pmos_substrate.ext
+++ /dev/null
@@ -1,8 +0,0 @@
-timestamp 1619685549
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-node "w_n66_n68#" 1841 341.64 -66 -68 nw 0 0 0 0 52440 916 0 0 0 0 0 0 9216 384 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9216 384 9216 384 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/caravel/mag/pmos_substrate.mag b/caravel/mag/pmos_substrate.mag
deleted file mode 100644
index cd51c9a..0000000
--- a/caravel/mag/pmos_substrate.mag
+++ /dev/null
@@ -1,26 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1620719712
-<< nwell >>
-rect -66 -68 162 162
-<< mvnsubdiff >>
-rect 0 64 96 96
-rect 0 30 31 64
-rect 65 30 96 64
-rect 0 0 96 30
-<< mvnsubdiffcont >>
-rect 31 30 65 64
-<< locali >>
-rect 0 64 96 96
-rect 0 30 31 64
-rect 65 30 96 64
-rect 0 0 96 30
-<< viali >>
-rect 31 30 65 64
-<< metal1 >>
-rect 0 64 96 96
-rect 0 30 31 64
-rect 65 30 96 64
-rect 0 0 96 30
-<< end >>
diff --git a/caravel/mag/quit.mag b/caravel/mag/quit.mag
deleted file mode 100644
index 496ff0b..0000000
--- a/caravel/mag/quit.mag
+++ /dev/null
@@ -1,4 +0,0 @@
-magic
-tech sky130A
-timestamp 0
-<< end >>
diff --git a/caravel/mag/resistor200K.ext b/caravel/mag/resistor200K.ext
deleted file mode 100644
index 00ec5cc..0000000
--- a/caravel/mag/resistor200K.ext
+++ /dev/null
@@ -1,17 +0,0 @@
-timestamp 1618573519
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__res_xhigh_po l=l w=w
-parameters sky130_fd_pr__res_xhigh_po_5p73 l=l
-parameters sky130_fd_pr__res_xhigh_po_2p85 l=l
-parameters sky130_fd_pr__res_xhigh_po_1p41 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
-node "a_6964_n40#" 155 1048.15 6964 -40 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210160 3528 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_40_0#" 197829 0 40 0 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 484680 13988 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n700_n40#" 155 1048.15 -700 -40 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210160 3528 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device rsubckt sky130_fd_pr__res_xhigh_po 40 0 41 1 l=6924 w=70 "SUB" "a_40_0#" 0 0 "a_n700_n40#" 70 0 "a_6964_n40#" 70 0
diff --git a/caravel/mag/resistor200K.mag b/caravel/mag/resistor200K.mag
deleted file mode 100644
index 0de30e8..0000000
--- a/caravel/mag/resistor200K.mag
+++ /dev/null
@@ -1,9 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< xpolycontact >>
-rect -350 -20 20 51
-rect 3482 -20 3852 51
-<< xpolyres >>
-rect 20 0 3482 35
-<< end >>
diff --git a/caravel/mag/resistor273K.ext b/caravel/mag/resistor273K.ext
deleted file mode 100644
index ec66eea..0000000
--- a/caravel/mag/resistor273K.ext
+++ /dev/null
@@ -1,17 +0,0 @@
-timestamp 1619682155
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__res_xhigh_po l=l w=w
-parameters sky130_fd_pr__res_xhigh_po_5p73 l=l
-parameters sky130_fd_pr__res_xhigh_po_2p85 l=l
-parameters sky130_fd_pr__res_xhigh_po_1p41 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
-node "a_8730_n10#" 148 600.38 8730 -10 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79200 2120 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_10_0#" 249143 0 10 0 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 610400 17580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n430_n10#" 148 600.38 -430 -10 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79200 2120 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device rsubckt sky130_fd_pr__res_xhigh_po 10 0 11 1 l=8720 w=70 "SUB" "a_10_0#" 0 0 "a_n430_n10#" 70 0 "a_8730_n10#" 70 0
diff --git a/caravel/mag/resistor273K.mag b/caravel/mag/resistor273K.mag
deleted file mode 100644
index 56ab25c..0000000
--- a/caravel/mag/resistor273K.mag
+++ /dev/null
@@ -1,9 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< xpolycontact >>
-rect -215 -5 5 40
-rect 4365 -5 4585 40
-<< xpolyres >>
-rect 5 0 4365 35
-<< end >>
diff --git a/caravel/mag/resistor273K.spice b/caravel/mag/resistor273K.spice
deleted file mode 100644
index 0c30040..0000000
--- a/caravel/mag/resistor273K.spice
+++ /dev/null
@@ -1,7 +0,0 @@
-* SPICE3 file created from resistor273K.ext - technology: sky130A
-
-.option scale=10000u
-
-X0 a_n215_n5# a_4365_n5# SUB sky130_fd_pr__res_xhigh_po w=35 l=4360
-C0 a_4365_n5# SUB 0.60fF
-C1 a_n215_n5# SUB 0.60fF
diff --git a/caravel/mag/resistor30K.ext b/caravel/mag/resistor30K.ext
deleted file mode 100644
index 7b26010..0000000
--- a/caravel/mag/resistor30K.ext
+++ /dev/null
@@ -1,17 +0,0 @@
-timestamp 1618573301
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters sky130_fd_pr__res_xhigh_po l=l w=w
-parameters sky130_fd_pr__res_xhigh_po_5p73 l=l
-parameters sky130_fd_pr__res_xhigh_po_2p85 l=l
-parameters sky130_fd_pr__res_xhigh_po_1p41 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p69 l=l
-parameters sky130_fd_pr__res_xhigh_po_0p35 l=l
-node "a_1020_n20#" 123 641.977 1020 -20 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 102544 2232 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_40_0#" 28000 0 40 0 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68600 2100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "a_n402_n22#" 123 641.977 -402 -22 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 102544 2232 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-device rsubckt sky130_fd_pr__res_xhigh_po 40 0 41 1 l=980 w=70 "SUB" "a_40_0#" 0 0 "a_n402_n22#" 70 0 "a_1020_n20#" 70 0
diff --git a/caravel/mag/resistor30K.mag b/caravel/mag/resistor30K.mag
deleted file mode 100644
index a46ae87..0000000
--- a/caravel/mag/resistor30K.mag
+++ /dev/null
@@ -1,9 +0,0 @@
-magic
-tech sky130A
-timestamp 1620719712
-<< xpolycontact >>
-rect -201 -11 20 47
-rect 510 -10 731 48
-<< xpolyres >>
-rect 20 0 510 35
-<< end >>
diff --git a/caravel/mag/sky130A.tech b/caravel/mag/sky130A.tech
deleted file mode 100644
index 68f63ac..0000000
--- a/caravel/mag/sky130A.tech
+++ /dev/null
@@ -1,5289 +0,0 @@
-#------------------------------------------------------------------------
-# Copyright (c) 2020 R. Timothy Edwards
-# Revisions:  See below
-#
-# This file is an Open Source foundry process describing
-# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
-# process.  The file may be distributed under the terms
-# of the Apache 2.0 license agreement.
-#
-#------------------------------------------------------------------------
-tech
-  format 35
-  sky130A
-end
-
-version
- version 1.0.145-2-g19e1983
- description "SkyWater SKY130: Open Source rules and DRC"
- requires magic-8.3.111
-end
-
-#------------------------------------------------------------------------
-# Status 7/10/20: Rev 1 (alpha):
-# First public release
-# Status 8/14/20: Rev 2 (alpha):
-# Started updating with new device/model naming convention
-# Status 1/3/21: Taking out of beta and declaring an official release.
-#------------------------------------------------------------------------
-
-#------------------------------------------------------------------------
-# Supported device types
-#------------------------------------------------------------------------
-# device name			magic ID layer	description
-#------------------------------------------------------------------------
-# sky130_fd_pr__nfet_01v8	nfet		standard nFET
-# sky130_fd_pr__nfet_01v8	scnfet		standard nFET in standard cell**
-# sky130_fd_pr__special_nfet_latch npd		special nFET in SRAM cell
-# sky130_fd_pr__special_nfet_pass  npass	special nFET in SRAM cell
-# sky130_fd_pr__nfet_01v8_lvt	nfetlvt		low Vt nFET
-# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
-# sky130_fd_pr__pfet_01v8	pfet		standard pFET
-# sky130_fd_pr__pfet_01v8	scpfet		standard pFET in standard cell**
-# sky130_fd_pr__special_pfet_pass ppu		special pFET in SRAM cell
-# sky130_fd_pr__pfet_01v8_lvt	pfetlvt		low Vt pFET
-# sky130_fd_pr__pfet_01v8_mvt	pfetmvt		med Vt pFET
-# sky130_fd_pr__pfet_01v8_hvt	pfethvt		high Vt pFET
-# sky130_fd_pr__nfet_03v3_nvt	nnfet		native nFET
-# sky130_fd_pr__pfet_g5v0d10v5	mvpfet		thickox pFET
-# sky130_fd_pr__nfet_g5v0d10v5	mvnfet		thickox nFET
-# sky130_fd_pr__nfet_01v8_nvt	mvnnfet		thickox native nFET
-# sky130_fd_pr__diode_pw2nd_05v5 ndiode		n+ diff diode
-# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt	low Vt n+ diff diode
-# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode	diode with nndiff
-# sky130_fd_pr__diode_pw2nd_11v0 mvndiode	thickox n+ diff diode
-# sky130_fd_pr__diode_pd2nw_05v5 pdiode		p+ diff diode
-# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt	low Vt p+ diff diode
-# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt	high Vt p+ diff diode
-# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode	thickox p+ diff diode
-# sky130_fd_pr__npn_05v0	pbase		NPN in deep nwell
-# sky130_fd_pr__npn_11v0	pbase		thick oxide gated NPN
-# sky130_fd_pr__pnp_05v0	nbase		PNP
-# sky130_fd_pr__cap_mim_m3_1	mimcap		MiM cap 1st plate
-# sky130_fd_pr__cap_mim_m3_2	mimcap2		MiM cap 2nd plate
-# sky130_fd_pr__res_generic_nd	rdn		n+ diff resistor
-# sky130_fd_pr__res_generic_nd__hv mvrdn	thickox n+ diff resistor
-# sky130_fd_pr__res_generic_pd	rdp		p+ diff resistor
-# sky130_fd_pr__res_generic_pd__nv mvrdp	thickox p+ diff resistor
-# sky130_fd_pr__res_generic_l1	rli		local interconnect resistor
-# sky130_fd_pr__res_generic_po	npres		n+ poly resistor
-# sky130_fd_pr__res_high_po_*	ppres (*)	p+ poly resistor (300 Ohms/sq)
-# sky130_fd_pr__res_xhigh_po_*	xres (*)	p+ poly resistor (2k Ohms/sq)
-# sky130_fd_pr__cap_var_lvt	varactor	low Vt varactor
-# sky130_fd_pr__cap_var_hvt	varactorhvt	high Vt varactor
-# sky130_fd_pr__cap_var		mvvaractor	thickox varactor
-# sky130_fd_pr__res_iso_pw	rpw		pwell resistor (in deep nwell)
-# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd	ESD thickox nFET
-# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd	ESD thickox pFET
-#
-# (*) Note that ppres may extract into some generic type called
-# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
-# allowed, and these are created from fixed layouts like the types below.
-#
-# (**) nFET and pFET in standard cells are the same as devices
-# outside of the standard cell except for the DRC rule for
-# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
-#
-#-------------------------------------------------------------
-# The following devices are not extracted but are represented
-# only by script-generated subcells in the PDK.
-#-------------------------------------------------------------
-# sky130_fd_pr__esd_nfet_01v8		ESD nFET
-# sky130_fd_pr__esd_nfet_05v0_nvt	ESD native nFET
-# sky130_fd_pr__special_nfet_pass_flash	flash nFET device
-# sky130_fd_pr__esd_rf_diode_pw2nd_11v0	ESD n+ diode
-# sky130_fd_pr__esd_rf_diode_pd2nw_11v0	ESD p+ diode
-# sky130_fd_pr__cap_vpp_*		Vpp cap
-# sky130_fd_pr__ind_*			inductor
-# sky130_fd_pr__fuse_m4			metal fuse device
-#--------------------------------------------------------------
-
-#-----------------------------------------------------
-# Tile planes
-#-----------------------------------------------------
-
-planes
-  dwell,dw
-  well,w
-  active,a
-  locali,li1,li
-  metal1,m1
-  metal2,m2
-  metal3,m3
-  cap1,c1
-  metal4,m4
-  cap2,c2
-  metal5,m5
-  metali,mi
-  block,b
-  comment,c
-end
-
-#-----------------------------------------------------
-# Tile types
-#-----------------------------------------------------
-
-types
-# Deep nwell
-  dwell dnwell,dnw
-  dwell isosubstrate,isosub
-
-# Wells
-  well nwell,nw
-  well pwell,pw
-  well rpw,rpwell
- -well obswell
-  well pbase,npn
-  well nbase,pnp
-
-# Transistors
-  active nmos,ntransistor,nfet
- -active scnmos,scntransistor,scnfet
- -active npd,npdfet,sramnfet
- -active npass,npassfet,srampassfet
-  active pmos,ptransistor,pfet
- -active scpmos,scptransistor,scpfet
- -active scpmoshvt,scpfethvt
- -active ppu,ppufet,srampfet
-  active nnmos,nntransistor,nnfet
-  active mvnmos,mvntransistor,mvnfet
-  active mvpmos,mvptransistor,mvpfet
-  active mvnnmos,mvnntransistor,mvnnfet
- -active mvnmosesd,mvntransistoresd,mvnfetesd
- -active mvpmosesd,mvptransistoresd,mvpfetesd
-  active varactor,varact,var
-  active mvvaractor,mvvaract,mvvar
-
-  active pmoslvt,pfetlvt
-  active pmosmvt,pfetmvt
-  active pmoshvt,pfethvt
-  active nmoslvt,nfetlvt
-  active varactorhvt,varacthvt,varhvt
- -active nsonos,sonos
- -active sramnvar,corenvar,corenvaractor
- -active srampvar,corepvar,corepvaractor
-
-# Diffusions
- -active fomfill
-  active ndiff,ndiffusion,ndif
-  active pdiff,pdiffusion,pdif
-  active mvndiff,mvndiffusion,mvndif
-  active mvpdiff,mvpdiffusion,mvpdif
-  active ndiffc,ndcontact,ndc
-  active pdiffc,pdcontact,pdc
-  active mvndiffc,mvndcontact,mvndc
-  active mvpdiffc,mvpdcontact,mvpdc
-  active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
-  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
-  active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
-  active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
-  active psubdiffcont,psubstratepcontact,psc,ptapc
-  active nsubdiffcont,nsubstratencontact,nsc,ntapc
-  active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
-  active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
- -active obsactive
- -active mvobsactive
-
-# Poly
-  active poly,p,polysilicon
-  active polycont,pc,pcontact,polycut,polyc
-  active xpolycontact,xpolyc,xpc
- -active polyfill
-
-# Resistors
-  active npolyres,npres,mrp1
-  active ppolyres,ppres,xhrpoly
-  active xpolyres,xpres,xres,uhrpoly
-  active ndiffres,rnd,rdn,rndiff
-  active pdiffres,rpd,rdp,rpdiff
-  active mvndiffres,mvrnd,mvrdn,mvrndiff
-  active mvpdiffres,mvrpd,mvrdp,mvrpdiff
-  active rmp
-
-# Diodes
-  active pdiode,pdi
-  active ndiode,ndi
-  active nndiode,nndi
-  active pdiodec,pdic
-  active ndiodec,ndic
-  active nndiodec,nndic
-  active mvpdiode,mvpdi
-  active mvndiode,mvndi
-  active mvpdiodec,mvpdic
-  active mvndiodec,mvndic
-  active pdiodelvt,pdilvt
-  active pdiodehvt,pdihvt
-  active ndiodelvt,ndilvt
-  active pdiodelvtc,pdilvtc
-  active pdiodehvtc,pdihvtc
-  active ndiodelvtc,ndilvtc
-
-# Local Interconnect 
-  locali locali,li1,li
- -locali corelocali,coreli1,coreli
-  locali rlocali,rli1,rli
-  locali viali,vial,mcon,m1c,v0
- -locali obsli1,obsli
- -locali obsli1c,obsmcon
- -locali lifill
-
-# Metal 1
-  metal1 metal1,m1,met1
-  metal1 rmetal1,rm1,rmet1
-  metal1 via1,m2contact,m2cut,m2c,via,v,v1
- -metal1 obsm1
-  metal1 padl
- -metal1 m1fill
-
-# Metal 2
-  metal2 metal2,m2,met2
-  metal2 rmetal2,rm2,rmet2
-  metal2 via2,m3contact,m3cut,m3c,v2
- -metal2 obsm2
- -metal2 m2fill
-
-# Metal 3
-  metal3 metal3,m3,met3
-  metal3 rmetal3,rm3,rmet3
- -metal3 obsm3
-  metal3 via3,v3
- -metal3 m3fill
-
-  cap1 mimcap,mim,capm
-  cap1 mimcapcontact,mimcapc,mimcc,capmc
-
-# Metal 4
-  metal4 metal4,m4,met4
-  metal4 rmetal4,rm4,rmet4
- -metal4 obsm4
-  metal4 via4,v4
- -metal4 m4fill
-
-  cap2 mimcap2,mim2,capm2
-  cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
-
-# Metal 5
-  metal5 metal5,m5,met5
-  metal5 rm5,rmetal5,rmet5
- -metal5 obsm5
- -metal5 m5fill
-
-  metal5 mrdlcontact,mrdlc,pi1
-  metali metalrdl,mrdl,metrdl,rdl
- -metali obsmrdl
-  metali pi2
-  block  ubm
-
-# Miscellaneous
- -block  glass
- -block  fillblock,fillblock4
-  comment comment
- -comment obscomment
-# fixed resistor width identifiers
- -comment res0p35
- -comment res0p69
- -comment res1p41
- -comment res2p85
- -comment res5p73
-
-end
-
-#-----------------------------------------------------
-# Magic contact types
-#-----------------------------------------------------
-
-contact
-  pc       poly       locali
-  ndc      ndiff      locali
-  pdc      pdiff      locali
-  nsc      nsd        locali
-  psc      psd        locali
-  ndic     ndiode     locali
-  ndilvtc  ndiodelvt  locali
-  nndic    nndiode    locali
-  pdic     pdiode     locali
-  pdilvtc  pdiodelvt  locali
-  pdihvtc  pdiodehvt  locali
-  xpc      xpc        locali
-
-  mvndc   mvndiff   locali
-  mvpdc   mvpdiff   locali
-  mvnsc   mvnsd     locali
-  mvpsc   mvpsd     locali
-  mvndic  mvndiode  locali
-  mvpdic  mvpdiode  locali
-
-  mcon locali metal1
-  obsmcon obsli metal1
-
-  via1   metal1 metal2
-  via2   metal2 metal3
-  via3   metal3 metal4
-  via4   metal4 metal5
-  stackable
-
-  # MiM cap contacts are not stackable!
-  mimcc  mimcap metal4
-  mim2cc mimcap2 metal5
-
-  padl m1 m2 m3 m4 m5 glass
-
-  mrdlc metal5 mrdl
-  pi2   mrdl ubm
-end
-
-#-----------------------------------------------------
-# Layer aliases
-#-----------------------------------------------------
-
-aliases
-
-  allwellplane     nwell
-  allnwell	   nwell,obswell,pnp
-
-  allnfets	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
-  allpfets	   pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
-  allfets	   allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
-  allfetsstd	   nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
-  allfetsspecial   scnfet,scpfet,scpfethvt
-  allfetscore	   npass,npd,nsonos,ppu,corenvar,corepvar
-  allfetsnolvt	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
-
-  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
-  allnactive	   allnactivenonfet,allnfets
-  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
-  allnactivetap	   *nsd,*mvnsd,var,varhvt,mvvar,corenvar
-
-  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
-  allpactive	   allpactivenonfet,allpfets
-  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
-  allpactivetap    *psd,*mvpsd,corepvar
-
-  allactivenonfet  allnactivenonfet,allpactivenonfet
-  allactive	   allactivenonfet,allfets
-
-  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres
-
-  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
-  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
-  alldifflv        allndifflv,allpdifflv
-  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
-  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
-  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
-
-  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
-  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
-  alldiffmv        allndiffmv,allpdiffmv
-  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
-  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
-  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
-  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
-  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
-  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
-
-  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
-  alldiff	   alldifflv,alldiffmv,fomfill
-
-  allpolyres	   mrp1,xhrpoly,uhrpoly,rmp
-  allpolynonfet	   *poly,allpolyres,xpc
-  allpolynonres	   *poly,allfets,xpc
-
-  allpoly	   allpolynonfet,allfets
-  allpolynoncap	   *poly,xpc,allfets,allpolyres
-
-  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
-  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
-  allndiffcontmv   mvndc,mvnsc,mvndic
-  allpdiffcontmv   mvpdc,mvpsc,mvpdic
-  allndiffcont	   allndiffcontlv,allndiffcontmv
-  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
-  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
-  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
-  alldiffcont	   alldiffcontlv,alldiffcontmv
-
-  allcont	alldiffcont,pc
-
-  allres	allpolyres,allactiveres
-
-  allli		*locali,coreli,rli
-  allm1		*m1,rm1
-  allm2		*m2,rm2
-  allm3		*m3,rm3
-  allm4	   	*m4,rm4
-  allm5	   	*m5,rm5
-
-  allpad	padl
-
-  psub		pwell
-  
-end
-
-#-----------------------------------------------------
-# Layer drawing styles
-#-----------------------------------------------------
-
-styles
- styletype mos
-  dnwell    cwell
-  isosub    subcircuit
-  nwell     nwell
-  pwell	    pwell
-  rpwell    pwell 	ptransistor_stripes
-  ndiff     ndiffusion
-  fomfill   ndiffusion
-  pdiff     pdiffusion
-  nsd       ndiff_in_nwell
-  psd       pdiff_in_pwell
-  nfet      ntransistor    ntransistor_stripes
-  scnfet    ntransistor    ntransistor_stripes
-  npass	    ntransistor	   ntransistor_stripes
-  npd	    ntransistor	   ntransistor_stripes
-  pfet      ptransistor    ptransistor_stripes
-  scpfet    ptransistor    ptransistor_stripes
-  scpfethvt ptransistor    ptransistor_stripes implant2
-  ppu	    ptransistor	   ptransistor_stripes
-  var       polysilicon    ndiff_in_nwell
-  ndc       ndiffusion     metal1  contact_X'es
-  pdc       pdiffusion     metal1  contact_X'es
-  nsc       ndiff_in_nwell metal1  contact_X'es
-  psc       pdiff_in_pwell metal1  contact_X'es
-  corenvar  polysilicon    ndiff_in_nwell
-  corepvar  polysilicon    pdiff_in_pwell
-
-  pnp	    nwell ntransistor_stripes
-  npn	    pwell ptransistor_stripes
-
-  pfetlvt   ptransistor	ptransistor_stripes implant1
-  pfetmvt   ptransistor	ptransistor_stripes implant3
-  pfethvt   ptransistor ptransistor_stripes implant2
-  nfetlvt   ntransistor ntransistor_stripes implant1
-  nsonos    ntransistor implant3
-  varhvt    polysilicon ndiff_in_nwell implant2
-  nnfet	    ntransistor ndiff_in_nwell
-
-  mvndiff   ndiffusion     hvndiff_mask
-  mvpdiff   pdiffusion     hvpdiff_mask
-  mvnsd     ndiff_in_nwell hvndiff_mask
-  mvpsd     pdiff_in_pwell hvpdiff_mask
-  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
-  mvnfetesd ntransistor    ntransistor_stripes hvndiff_mask
-  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
-  mvpfet    ptransistor    ptransistor_stripes
-  mvpfetesd ptransistor    ptransistor_stripes
-  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
-  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
-  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
-  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
-  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
-
-  poly      polysilicon 
-  polyfill  polysilicon
-  pc        polysilicon    metal1  contact_X'es
-  npolyres  polysilicon    silicide_block nselect2
-  ppolyres  polysilicon    silicide_block pselect2
-  xpc	    polysilicon	   pselect2  metal1  contact_X'es
-  rmp	    polysilicon	   poly_resist_stripes
-
-  res0p35   implant1
-  res0p69   implant1
-  res1p41   implant1
-  res2p85   implant1
-  res5p73   implant1
-
-  pdiode    pdiffusion     pselect2
-  ndiode    ndiffusion     nselect2
-  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
-  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
-
-  nndiode   ndiffusion  nselect2 implant3
-  ndiodelvt ndiffusion	nselect2 implant1
-  pdiodelvt pdiffusion  pselect2 implant1
-  pdiodehvt pdiffusion  pselect2 implant2
-  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
-  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
-  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es
-
-  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
-  mvndiode    ndiffusion     nselect2 hvndiff_mask
-  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
-  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
-  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
-
-  locali    metal1
-  lifill    metal1
-  coreli    metal1
-  rli       metal1         poly_resist_stripes
-  mcon	    metal1	   metal2 via1arrow
-  obsli     metal1
-  obsmcon   metal1	   metal2 via1arrow
-
-  metal1    metal2
-  m1fill    metal2
-  rm1       metal2         poly_resist_stripes
-  obsm1     metal2
-  m2c       metal2         metal3  via2arrow
-  metal2    metal3
-  m2fill    metal3
-  rm2       metal3         poly_resist_stripes
-  obsm2     metal3
-  m3c       metal3         metal4  via3alt
-  metal3    metal4
-  m3fill    metal4
-  rm3       metal4         poly_resist_stripes
-  obsm3     metal4
-  mimcap    metal3         mems
-  mimcc     metal3         contact_X'es mems
-  mimcap2   metal4         mems
-  mim2cc    metal4         contact_X'es mems
-  via3      metal4         metal5  via4
-  metal4    metal5
-  m4fill    metal5
-  rm4       metal5         poly_resist_stripes
-  obsm4     metal5
-  via4      metal5         metal6  via5
-  metal5    metal6
-  m5fill    metal6
-  rm5       metal6         poly_resist_stripes
-  obsm5     metal6
-  mrdlc	    metal6  metal7  via6
-  metalrdl  metal7
-  obsmrdl   metal7
-  ubm	    metal8
-  pi2	    metal7  metal8  via7
-
-  glass	    overglass
-  mrp1      poly_resist    poly_resist_stripes
-  xhrpoly   poly_resist    silicide_block
-  uhrpoly   poly_resist
-  ndiffres  ndiffusion	   ndop_stripes
-  pdiffres  pdiffusion	   pdop_stripes
-  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
-  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
-  comment   comment
-  error_p   error_waffle
-  error_s   error_waffle
-  error_ps  error_waffle
-  fillblock cwell
-  fillblock4 cwell
-
-  obswell   cwell
-  obsactive implant4
-
-  padl      metal6 via6 overglass
-
-  magnet    substrate_field_implant
-  rotate    via3alt
-  fence     via5
-end
-
-#-----------------------------------------------------
-# Special paint/erase rules
-#-----------------------------------------------------
-
-compose
-  compose  nfet  poly  ndiff
-  compose  pfet  poly  pdiff
-  compose  var   poly  nsd
-
-  compose  mvnfet  poly  mvndiff
-  compose  mvpfet  poly  mvpdiff
-  compose  mvvar   poly  mvnsd
-
-  paint	 obsmcon locali	 via1
-  paint	 obsmcon obsm1	 obsli,obsm1
-  
-  paint  ndc     nwell  pdc
-  paint  nfet    nwell  pfet
-  paint  scnfet  nwell  scpfet
-  paint  ndiff   nwell  pdiff
-  paint  psd     nwell  nsd
-  paint  psc     nwell  nsc
-  paint  npd     nwell  ppu
-
-  paint  pdc     pwell  ndc
-  paint  pfet    pwell  nfet
-  paint  scpfet  pwell  scnfet
-  paint  pdiff   pwell  ndiff
-  paint  nsd     pwell  psd
-  paint  nsc     pwell  psc
-  paint  ppu     pwell  npd
-
-  paint  pdc	 coreli pdc
-  paint  ndc	 coreli ndc
-  paint  pc	 coreli pc
-  paint  nsc 	 coreli nsc
-  paint  psc 	 coreli psc
-  paint  viali 	 coreli viali
-
-  paint  coreli  pdc    pdc
-  paint  coreli  ndc    ndc
-  paint  coreli  pc     pc
-  paint  coreli  nsc    nsc
-  paint  coreli  psc    psc
-  paint  coreli  viali  viali
-
-  paint  m4      obsm4  m4
-  paint  m5      obsm5  m5
-end
-
-#-----------------------------------------------------
-# Electrical connectivity
-#-----------------------------------------------------
-
-connect
-  *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
-  pwell,*psd,*mvpsd,npn  pwell,*psd,*mvpsd,npn
-  *li,coreli,lifill	*li,coreli,lifill
-  *m1,m1fill,obsmcon	*m1,m1fill,obsmcon
-  *m2,m2fill	*m2,m2fill
-  *m3,m3fill	*m3,m3fill
-  *m4,m4fill	*m4,m4fill
-  *m5,m5fill	*m5,m5fill
-  *mimcap     *mimcap
-  *mimcap2    *mimcap2
-   allnactivenonfet	allnactivenonfet
-   allpactivenonfet	allpactivenonfet
-  *poly,xpc,allfets,polyfill	*poly,xpc,allfets,polyfill
-  # RDL connects to m5 (i.e., padl) through glass cut
-  *mrdl			*mrdl
-  glass			metrdl
-end
-
-#-----------------------------------------------------
-# CIF/GDS output layer definitions
-#-----------------------------------------------------
-# NOTE:  All values in this section MUST be multiples of 25 
-# or else magic will scale below the allowed layout grid size
-
-cifoutput
-
-#----------------------------------------------------------------
-style gdsii
-# NOTE: This section is used for actual GDS output
-#----------------------------------------------------------------
- scalefactor 10  nanometers
- options calma-permissive-labels
- gridlimit 5
-
-#----------------------------------------------------------------
-# Create a temp layer from the cell bounding box for use in
-# generating ID layers.  Note that "boundary", unlike "bbox",
-# requires the FIXED_BBOX property (abutment box) in the cell.
-#----------------------------------------------------------------
- templayer CELLBOUND
-	boundary
-
-#----------------------------------------------------------------
-# BOUND
-#----------------------------------------------------------------
- layer 	BOUND CELLBOUND
-	calma 235 4
-
-#----------------------------------------------------------------
-# DNWELL
-#----------------------------------------------------------------
-
- layer DNWELL	dnwell,pnp
-	calma	64 18
-
- layer PWRES    rpw
-	and	dnwell
-	calma	64 13
-
-#----------------------------------------------------------------
-# NWELL
-#----------------------------------------------------------------
-
- layer NWELL 	allnwell
-	bloat-all rpw dnwell
-	and-not rpw,pwell
- 	calma 	64 20
-
- layer WELLTXT
- 	labels allnwell noport
-	calma 64 5
-
- layer WELLPIN
- 	labels allnwell port
-	calma 64 16
-
-#----------------------------------------------------------------
-# SUB (text/port only)
-#----------------------------------------------------------------
-
- layer SUBTXT
- 	labels pwell noport
-	calma 64 59
-
- layer SUBPIN
- 	labels pwell port
-	calma 122 16
-
-#----------------------------------------------------------------
-# DIFF
-#----------------------------------------------------------------
-
- layer DIFF 	allnactivenontap,allpactivenontap,allactiveres
- 	calma 	65 20
-
- layer DIFFTXT
- 	labels allnactivenontap,allpactivenontap noport
-	calma	65 6
-
- layer DIFFPIN
- 	labels allnactivenontap,allpactivenontap port
-	calma	65 16
-
-#----------------------------------------------------------------
-# TAP
-#----------------------------------------------------------------
-
- layer TAP 	allnactivetap,allpactivetap
- 	labels 	allnactivetap,allpactivetap port
- 	calma 	65 44
-
- layer TAPTXT
- 	labels 	allnactivetap,allpactivetap noport
-	calma	65 5
-
-#----------------------------------------------------------------
-# FOM
-#----------------------------------------------------------------
-
- layer FOMFILL	fomfill
-	labels	fomfill
-	calma	23 28
-
-#----------------------------------------------------------------
-# PSDM, NSDM (PPLUS, NPLUS implants)
-#----------------------------------------------------------------
-
- templayer basePSDM pdiffres,mvpdiffres
-	grow	15
-	or	xhrpoly,uhrpoly,xpc
-	grow	110
-	bloat-or allpactivetap * 125 allnactivenontap 0
-	bloat-or allpactivenontap * 125 allnactivetap 0
-
- templayer baseNSDM ndiffres,mvndiffres
- 	grow	125
-	bloat-or allnactivetap * 125 allpactivenontap 0
-	bloat-or allnactivenontap * 125 allpactivetap 0
-
- templayer extendPSDM  basePSDM
-	bridge	380 380
-	and-not baseNSDM
-
- layer PSDM basePSDM,extendPSDM 
-	grow	185
-	shrink	185
-	close   265000
-	mask-hints PSDM
-	calma	94 20
-
- templayer extendNSDM  baseNSDM
-	bridge	380 380
-	and-not basePSDM
-
- layer NSDM baseNSDM,extendNSDM
-	grow	185
-	shrink	185
- 	close   265000
-	mask-hints NSDM
- 	calma	93 44
-
-#----------------------------------------------------------------
-# LVID
-#----------------------------------------------------------------
-
- layer LVID  nnfet
-        grow 100
-	calma 81 60
-
-#----------------------------------------------------------------
-# LVTN
-#----------------------------------------------------------------
-
- layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
-        grow 180
-	bridge	380 380
-	grow	185
-	shrink	185
-	close  265000
-	mask-hints LVTN
-	calma 125 44
-
-#----------------------------------------------------------------
-# HVTR
-#----------------------------------------------------------------
-
- layer HVTR  pfetmvt
-        grow 180
-	bridge	380 380
-	grow	185
-	shrink	185
-	close  265000
-	calma 18 20
-
-#----------------------------------------------------------------
-# HVTP
-#----------------------------------------------------------------
-
- layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
-        grow 180
-	bridge	380 380
-	grow	185
-	shrink	185
-	close 265000
-	mask-hints HVTP
-	calma 78 44
-
-#----------------------------------------------------------------
-# SONOS
-#----------------------------------------------------------------
-
- layer SONOS nsonos
-	grow 100
-	grow-min 410
-	bridge 500 410
-	grow 250
-	shrink 250
-	calma 80 20
-
-#----------------------------------------------------------------
-# SONOS requires COREID around area (areaid.ce).  Also, the
-# coreli layer indicates a cell needing COREID.  Also, devices
-# npd, npass, and ppu indicate a COREID cell.
-#----------------------------------------------------------------
-
- layer COREID
-	bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
-	mask-hints COREID
-	calma 81 2
-
-#----------------------------------------------------------------
-# STDCELL applies to all cells containing scnfet or scpfet.
-#----------------------------------------------------------------
-
- layer STDCELL scnfet
-	bloat-all scpfet,scpfethvt,scnfet CELLBOUND
-	mask-hints STDCELL
-	calma 81 4
-
-#----------------------------------------------------------------
-# ESDID is a marker layer for ESD devices in the padframe I/O.
-#----------------------------------------------------------------
-
- layer ESDID  
-	bloat-all mvnfetesd *mvndiff,*poly
-	bloat-all mvpfetesd *mvpdiff,*poly
-	grow 100
-	mask-hints ESDID
-	calma 81 19
-
-#----------------------------------------------------------------
-# NPNID and PNPID apply to bipolar transistors
-#----------------------------------------------------------------
-
- layer NPNID
-	bloat-all npn dnwell
-	mask-hints NPNID
-	calma	82 20
-
- templayer pnparea pnp
-	grow 400
-
- layer PNPID
-	bloat-all pnparea *psd
-	or pnparea
-	mask-hints PNPID
-	calma	82 44
-
-#----------------------------------------------------------------
-# RPM
-#----------------------------------------------------------------
-
- layer RPM
-	bloat-all xhrpoly xpc
-	grow 200
-	grow-min 1270
-	grow 420
-	shrink 420
-	calma 86 20
-
-#----------------------------------------------------------------
-# URPM (2kOhms/sq. poly implant)
-#----------------------------------------------------------------
-
- layer URPM
-	bloat-all uhrpoly xpc
-	grow 200
-	grow-min 1270
-	grow 420
-	shrink 420
-	calma 79 20
-
-#----------------------------------------------------------------
-# LDNTM (Tip implant for SONOS FETs)
-#----------------------------------------------------------------
-
- layer LDNTM
-	bloat-all nsonos *ndiff
-	grow 185
- 	grow 	345
- 	shrink 	345
-	calma 11 44
-
-#----------------------------------------------------------------
-# HVNTM (Tip implant for MV ndiff devices)
-#----------------------------------------------------------------
-
- templayer hvntm_block *mvpsd
-	grow 185
-
- layer HVNTM
-	bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
-	bloat-all mvvaractor *mvnsd
-	and-not hvntm_block
-        grow 185
- 	grow 	345
- 	shrink 	345
-	and-not hvntm_block
-	calma 125 20
-
-#----------------------------------------------------------------
-# POLY
-#----------------------------------------------------------------
-
- layer POLY 	allpoly
- 	calma 	66 20
-
- layer POLYTXT
-	labels  allpoly noport
-	calma	66 5
-
- layer POLYPIN
-	labels  allpoly port
-	calma	66 16
-
- layer POLYFILL	polyfill
-	labels 	polyfill
-	calma	28 28
-
-#----------------------------------------------------------------
-# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
-#----------------------------------------------------------------
-
- templayer thkox_area 	alldiffmv,mvvar
-	grow	185
-	bloat-all alldiffmv nwell
-	grow 345
-	shrink 345
-
- templayer large_ptap_mv thkox_area
-	shrink	420
-	grow	420
-
- templayer small_ptap_mv thkox_area
-	and-not large_ptap_mv
-	# (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
-	grow-min 840
-
- layer HVI 	thkox_area,small_ptap_mv
-	bridge	700 600
- 	grow 	345
- 	shrink 	345
-	mask-hints HVI
- 	calma 	75 20
-
-#----------------------------------------------------------------
-# CONT (LICON)
-#----------------------------------------------------------------
-
- layer CONT allcont
- 	squares-grid 0 170 170
- 	calma	66 44
-
- # Contact for pres is different than other LICON contacts
- # See rules LICON 1b, 1c (width/length) and 2b (spacing)
- templayer xpc_horiz xpc
-	shrink 1007
-	grow 1007
-
- layer CONT xpc
-	and-not xpc_horiz
-	# Force long edge vertical for contacts narrower than 2um
-	# Minimum space is 350 but 520 satisfies no. of contacts rule
- 	slots 80 190 520 80 2000 350
- 	calma	66 44
-
- layer CONT xpc
-	and xpc_horiz
-	# Force long edge vertical for contacts wider than 2um
-	# Minimum space is 350 but 520 satisfies no. of contacts rule
- 	slots 80 2000 350 80 190 520
- 	calma	66 44
-
-#----------------------------------------------------------------
-# NPC (Nitride poly cut)
-# surrounds CONT (LICON) on poly only (i.e., pc)
-#----------------------------------------------------------------
-
- # Avoids a common case of NPC bridges too close to other LICON shapes.
- templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
-	grow 90
-
- layer NPC pc
- 	squares-grid 0 170 170
-	grow 100
-	bridge 270 270
-	and-not diffcutarea
-	bridge 270 270
-	grow 130
-	shrink 130
-	mask-hints NPC
-	calma  95 20
-
- # NPC is also generated on xhrpoly and uhrpoly resistors
-
- layer NPC xpc,xhrpoly,uhrpoly
-        # xpc surrounds precision_resistor by 0.095um
-	grow 95
-	grow 130
-	shrink 130
-	calma  95 20
-
-#----------------------------------------------------------------
-# Device markers
-#----------------------------------------------------------------
-
- layer DIFFRES rdn,mvrdn,rdp,mvrdp
-	calma 65 13
-
- layer POLYRES mrp1
-	calma 66 13
-
- # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
- layer POLYSHORT rmp
-	calma 66 15
-
- # POLYRES extends to edge of contact cut
- layer POLYRES xhrpoly,uhrpoly
-	grow 60
-	and xpc
-	or xhrpoly,uhrpoly
-	calma 66 13
-
- layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
-        # To be done:  Expand to include anode, cathode, and guard ring
-	calma 81 23
-
-#----------------------------------------------------------------
-# LI
-#----------------------------------------------------------------
- layer LI allli
-	calma 67 20
-
- layer LITXT
- 	labels *locali,coreli noport
-	calma 67 5
-
- layer LIPIN
- 	labels *locali,coreli port
-	calma 67 16
-
- layer LIRES rli
-	labels rli
-	calma 67 13
-
- layer LIFILL	lifill
-	labels 	lifill
-	calma	56 28
-
-#----------------------------------------------------------------
-# MCON
-#----------------------------------------------------------------
- layer MCON mcon
- 	squares-grid 0 170 190
- 	calma 	67 44
-
-#----------------------------------------------------------------
-# MET1
-#----------------------------------------------------------------
- layer MET1 	allm1
- 	calma 	68 20
-
- layer MET1TXT
-	labels	allm1 noport
-	calma 	68 5
-
- layer MET1PIN
-	labels	allm1 port
-	calma 	68 16
-
- layer MET1RES rm1
-	labels rm1
-	calma 68 13
-
- layer MET1FILL m1fill
-	labels m1fill
-	calma 36 28
-
-#----------------------------------------------------------------
-# VIA1
-#----------------------------------------------------------------
- layer VIA1 	via1
- 	squares-grid 55 150 170
- 	calma 	68 44
-
-#----------------------------------------------------------------
-# MET2
-#----------------------------------------------------------------
- layer MET2 	allm2
- 	calma 	69 20
-
- layer MET2TXT
-	labels	allm2 noport
-	calma	69 5
-
- layer MET2PIN
-	labels	allm2 port
-	calma	69 16
-
- layer MET2RES rm2
-	labels rm2
-	calma 69 13
-
- layer MET2FILL m2fill
-	labels m2fill
-	calma 41 28
-
-#----------------------------------------------------------------
-# VIA2
-#----------------------------------------------------------------
- layer VIA2 	via2
- 	squares-grid 40 200 200
- 	calma 	69 44
-
-#----------------------------------------------------------------
-# MET3
-#----------------------------------------------------------------
- layer MET3 	allm3
- 	calma 	70 20
-
- layer MET3TXT
- 	labels 	allm3 noport
-	calma	70 5
-
- layer MET3PIN
-	labels	allm3 port
-	calma	70 16 
-
- layer MET3RES rm3
-	labels rm3
-	calma 70 13
-
- layer MET3FILL m3fill
-	labels m3fill
-	calma 34 28
-
-#----------------------------------------------------------------
-# VIA3
-#----------------------------------------------------------------
- layer VIA3	via3
-	or mimcc
- 	squares-grid 60 200 200
- 	calma 	70 44
-
-#----------------------------------------------------------------
-# MET4
-#----------------------------------------------------------------
- layer MET4 	allm4
- 	calma 	71 20
-
- layer MET4TXT
-	labels	allm4 noport
-	calma	71 5
-
- layer MET4PIN
-	labels	allm4 port
-	calma	71 16
-
- layer MET4RES rm4
-	labels rm4
-	calma 71 13
-
- layer MET4FILL m4fill
-	labels m4fill
-	calma 51 28
-
-#----------------------------------------------------------------
-# VIA4
-#----------------------------------------------------------------
- layer VIA4	via4
-	or mim2cc
- 	squares-grid 190 800 800
- 	calma 	71 44
-
-#----------------------------------------------------------------
-# MET5
-#----------------------------------------------------------------
- layer MET5 	allm5,m5fill
- 	calma 	72 20
-
- layer MET5TXT
-	labels	allm5 noport
-	calma	72 5
-
- layer MET5PIN
-	labels	allm5 port
-	calma	72 16
-
- layer MET5RES rm5
-	labels rm5
-	calma 72 13
-
- layer MET5FILL m5fill
-	labels m5fill
-	calma 59 28
-
-
-#----------------------------------------------------------------
-# RDL
-#----------------------------------------------------------------
-  layer RDL	*metrdl
-	calma   74 20
-
-  layer RDLTXT
-	labels	*metrdl noport
-	calma	74 5
-
-  layer RDLPIN
-	labels  *metrdl port
-	calma	74 16
-
-  layer PI1	*metrdl
-	and	padl,glass
-	# Test only---needs GDS layer number
-
-  layer	UBM	*metrdl
-	shrink	50000
-	grow	40000
-	# Test only---needs GDS layer number
-	
-  layer	PI2	*metrdl
-	shrink	50000
-	grow	25000
-	# Test only---needs GDS layer number
-
-
-#----------------------------------------------------------------
-# GLASS
-#----------------------------------------------------------------
- layer GLASS 	glass
- 	calma 	76 20
-
-#----------------------------------------------------------------
-# CAPM
-#----------------------------------------------------------------
- layer CAPM 	*mimcap
- 	labels 	mimcap
- 	calma 	89 44
-
- layer CAPM2 	*mimcap2
- 	labels 	mimcap2
- 	calma 	97 44
-
-#----------------------------------------------------------------
-# Chip top level marker for DRC latchup rules to check 15um
-# distance to taps (otherwise 6um is used)
-#----------------------------------------------------------------
-
- layer LOWTAPDENSITY
-	bbox top
-	# Clear 200um for pads + 50um for required high tap density
-	# in critical area.
-	shrink 250000
-	calma	81 14
-
-#----------------------------------------------------------------
-# FILLBLOCK
-#----------------------------------------------------------------
- layer FILLOBSFOM  obsactive
-	calma	22 24
-
- layer FILLOBSM1 fillblock,fillblock4
- 	calma 	62 24
-
- layer FILLOBSM2 fillblock,fillblock4
- 	calma 	105 52
-
- layer FILLOBSM3 fillblock,fillblock4
- 	calma 	107 24
-
- layer FILLOBSM4 fillblock,fillblock4
- 	calma 	112 4
-
- render	DNWELL 	cwell       -0.1    0.1
- render	NWELL	nwell        0.0    0.2062
- render DIFF	ndiffusion   0.2062 0.12
- render TAP	pdiffusion   0.2062 0.12
- render POLY	polysilicon  0.3262 0.18
- render CONT	via          0.5062 0.43
- render LI	metal1       0.9361 0.10
- render MCON	via          1.0361 0.34
- render MET1	metal2       1.3761 0.36
- render VIA1	via          1.7361 0.27
- render MET2	metal3       2.0061 0.36
- render VIA2	via          2.3661 0.42
- render MET3	metal4       2.7861 0.845
- render VIA3	via          3.6311 0.39
- render MET4	metal5       4.0211 0.845
- render VIA4	via          4.8661 0.505
- render MET5	metal6       5.3711 1.26
- render CAPM	metal8       2.4661 0.2
- render CAPM2	metal9       3.7311 0.2
- render RDL	metal7      11.8834 4.0
-
-#----------------------------------------------------------------
-style drc
-#----------------------------------------------------------------
-# NOTE:  This style is used for DRC only, not for GDS output
-#----------------------------------------------------------------
- scalefactor 10  nanometers
- options calma-permissive-labels
-
- # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
- templayer dnwell_shrink dnwell
- shrink 1030
-
- templayer nwell_missing dnwell
- grow 400
- and-not dnwell_shrink
- and-not nwell
-
- templayer pwell_in_dnwell dnwell
- and-not nwell
-
- # SONOS nFET devices must be in deep nwell
- templayer dnwell_missing nsonos
- and-not dnwell
-
- # SONOS nFET devices must be in cell with abutment box
- templayer abutment_box
-	boundary
-
- templayer bbox_missing nsonos
-	and-not abutment_box
-
- # Make sure nwell covers varactor poly
- templayer var_poly_no_nwell
-	bloat-all varactor,mvvaractor *poly
-	grow 150
-	and-not nwell
-
- # Define MiM cap bottom plate for spacing rule
- templayer mim_bottom
- bloat-all *mimcap *metal3
-
- # Define MiM2 cap bottom plate for spacing rule
- templayer mim2_bottom
- bloat-all *mimcap2 *metal4
-
- # Note that metal fill is performed by the foundry and so is not
- # an option for a cifoutput style.
-
- # Check latchup rule (15um minimum from tap LICON center to any
- # non-tap diffusion.  Note that to count as a tap, the diffusion
- # must be contacted to LI
-
- templayer ptap_reach psc,mvpsc
- and-not dnwell
- # grow total is 15um.  grow in 0.84um increments to ensure that
- # no nwell ring is crossed
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 840
- and-not nwell,dnwell
- grow 635
- and-not nwell,dnwell
-
- templayer ptap_missing *ndiff,*mvndiff
- and-not dnwell
- and-not ptap_reach
-
- templayer ntap_reach nsc,mvnsc
- # grow total is 15um.  grow in 1.27um increments to ensure that
- # no nwell ring is crossed.  There is no difference between
- # ntaps in and out of deep nwell.
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 1270
- and nwell,pnp
- grow 945
- and nwell,pnp
- 
- templayer ntap_missing *pdiff,*mvpdiff
- and-not pwell_in_dnwell
- and-not ntap_reach
-
- templayer dptap_reach psc,mvpsc
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 840
- and-not nwell
- and dnwell
- grow 635
- and-not nwell
- and dnwell
-
- templayer dptap_missing *ndiff,*mvndiff
- and dnwell
- and-not dptap_reach
-
- templayer pdiff_crosses_dnwell dnwell
- grow 20
- and-not dnwell
- and allpdifflv,allpdiffmv
-
- # MV nwell must be 2um from any other nwell
- templayer mvnwell
- bloat-all alldiffmv nwell
- grow-min 840
- bridge	700 600
-
- # Simple spacing checks to lvnwell must use CIF-DRC rule
- templayer allmvdiffnowell *mvndiff,*mvpsd
-
- templayer lvnwell nwell
- and-not mvnwell
-
- templayer nwell_with_tap
- bloat-all nsc,mvnsc nwell,pnp
-
- templayer nwell_missing_tap nwell,pnp
- and-not nwell_with_tap
-
- templayer tap_with_licon
- bloat-all psc,mvpsc psd,mvpsd
- bloat-all nsc,mvnsc nsd,mvnsd
-
- templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
- and-not tap_with_licon
-
- # Make sure varactor nwell contains no P diffusion
- templayer pdiff_in_varactor_well
- bloat-all varactor,mvvaractor nwell
- and allpactive
-
- # HVNTM spacing requires recreating HVNTM
- templayer hvntm_block *mvpsd
- grow 185
-
- templayer hvntm_generate
- bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
- bloat-all mvvaractor *mvnsd
- and-not hvntm_block
- grow 185
- grow    345
- shrink  345
- and-not hvntm_block
-
- templayer m1_small_hole allm1,obsm1,obsmcon
- close   140000
-
- templayer m1_hole_empty m1_small_hole
- and-not allm1,obsm1,obsmcon
-
- templayer m2_small_hole allm2,obsm2
- close   140000
-
- templayer m2_hole_empty m2_small_hole
- and-not allm2,obsm2
-
- templayer m1_huge allm1
- shrink 1500
- grow 1500
-
- templayer m1_large_halo m1_huge
- grow 280
- and-not m1_huge
- and allm1
-
- templayer m2_huge allm2
- shrink 1500
- grow 1500
-
- templayer m2_large_halo m2_huge
- grow 280
- and-not m2_huge
- and allm2
-
- templayer m3_huge allm3
- shrink 1500
- grow 1500
-
- templayer m3_large_halo m3_huge
- grow 400
- and-not m3_huge
- and allm3
-
- templayer m4_huge allm4
- shrink 1500
- grow 1500
-
- templayer m4_large_halo m4_huge
- grow 400
- and-not m4_huge
- and allm4
-
-
-#----------------------------------------------------------------
-style density
-#----------------------------------------------------------------
-# Style used by scripts to check for fill density
-#----------------------------------------------------------------
- scalefactor 10  nanometers
- options calma-permissive-labels
- gridlimit 5
-
- templayer fom_all alldiff,fomfill
-
- templayer poly_all allpoly,polyfill
-
- templayer li_all allli,lifill
-
- templayer m1_all allm1,m1fill
-
- templayer m2_all allm2,m2fill
-
- templayer m3_all allm3,m3fill
-
- templayer m4_all allm4,m4fill
-
- templayer m5_all allm5,m5fill
-
-#----------------------------------------------------------------
-style wafflefill variants (),(tiled)
-#----------------------------------------------------------------
-# Style used by scripts for automatically generating fill layers
-# NOTE: Be sure to generate output on flattened layout.
-#----------------------------------------------------------------
- scalefactor 10  nanometers
- options calma-permissive-labels
- gridlimit 5
-
-#----------------------------------------------------------------
-# Generate and retain a layer representing the bounding box.
-#
-# For variant ():
-# The bounding box is the full extent of geometry on the top level
-# cell.
-#
-# For variant (tiled):
-# Use with a script that breaks layout into flattened tiles and runs
-# fill individually on each.  The tiles should be larger than the
-# step size, and each should draw a layer "comment" the size of the
-# step box.
-#----------------------------------------------------------------
-
- variants ()
-     templayer	topbox
-	 bbox	top
-
- variants (tiled)
-     templayer	topbox comment
-	 # Each tile imposes the full keepout distance rule of
-	 # 3um on all sides.
-	 shrink 1500
-
- variants *
-
-#----------------------------------------------------------------
-# Generate guard-band around nwells to keep FOM from crossing
-# Spacing from LV nwell = Diff/Tap 9 = 0.34um
-# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
-# Enclosure by nwell = Diff/Tap 8 = 0.18um
-#----------------------------------------------------------------
-
- templayer mvnwell
- 	bloat-all alldiffmv nwell
-
- templayer lvnwell allnwell
-	and-not mvnwell
-
- templayer	well_shrink mvnwell
-	shrink 	250
-	or lvnwell
-	shrink	180
- templayer	well_guardband allnwell
-	grow	340
-	and-not	well_shrink
-
-#---------------------------------------------------
-# Diffusion and poly keep-out areas
-#---------------------------------------------------
- templayer      obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
-	or	rpw,pnp,npn
-        grow    500
-	or	well_guardband
-
- templayer      obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
-	or	rpw,pnp,npn
-	grow	1000
-
-#---------------------------------------------------
-# FOM and POLY fill
-#---------------------------------------------------
- templayer	fomfill_pass1 topbox
-        # slots   0 4080 1320 0 4080 1320 1360 0
-        slots   0 4080 1600 0 4080 1600 1360 0
-        and-not obstruct_fom
-	and	topbox
-        shrink  2035
-        grow    2035
-
-#---------------------------------------------------
-
- templayer      obstruct_poly_pass1 fomfill_pass1
-        grow    300
-	or	obstruct_poly
- templayer	polyfill_pass1 topbox
-        slots   0 720 360 0 720 360 240 0
-        and-not obstruct_poly_pass1
-	and	topbox
-        shrink  355
-        grow    355
-
-#---------------------------------------------------
-
- templayer      obstruct_fom_pass2 fomfill_pass1
-        grow    1290
-	or	polyfill_pass1
-        grow    300
-	or	obstruct_fom
- templayer	fomfill_pass2 topbox
-        slots   0 2500 1320 0 2500 1320 1360 0
-        and-not obstruct_fom_pass2
-	and	topbox
-        shrink  1245
-        grow    1245
-
-#---------------------------------------------------
-
- templayer      obstruct_poly_coarse polyfill_pass1
-	grow	60
-	or	fomfill_pass1,fomfill_pass2
-	grow	300
-	or	obstruct_poly
- templayer	polyfill_coarse topbox
-        slots   0 720 360 0 720 360 240 120
-        and-not obstruct_poly_coarse
-	and	topbox
-        shrink  355
-        grow    355
-
-#---------------------------------------------------
- templayer      obstruct_poly_medium polyfill_pass1,polyfill_coarse
-	grow	60
-	or	fomfill_pass1,fomfill_pass2
-        grow    300
-	or	obstruct_poly
- templayer	polyfill_medium topbox
-        slots   0 540 360 0 540 360 240 100
-        and-not obstruct_poly_medium
-	and	topbox
-        shrink  265
-        grow    265
-
-#---------------------------------------------------
- templayer      obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
-	grow	60
-	or	fomfill_pass1,fomfill_pass2
-	grow	300
-	or	obstruct_poly
- templayer	polyfill_fine topbox
-        slots   0 480 360 0 480 360 240 200
-        and-not obstruct_poly_fine
-	and	topbox
-        shrink  235
-        grow    235
-
-#---------------------------------------------------
-
- templayer      obstruct_fom_coarse fomfill_pass1,fomfill_pass2
-        grow    1290
-	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
-	grow	300
-	or	obstruct_fom
- templayer	fomfill_coarse topbox
-        slots   0 1500 1320 0 1500 1320 1360 0
-        and-not obstruct_fom_coarse
-	and	topbox
-        shrink  745
-        grow    745
-
-#---------------------------------------------------
-
- templayer      obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
-        grow    1290
-	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
-	grow	300
-	or	obstruct_fom
- templayer	fomfill_fine topbox
-        slots   0 500 400 0 500 400 160 0
-        and-not obstruct_fom_fine
-	and	topbox
-        shrink  245
-        grow    245
-
-#---------------------------------------------------
- layer  FOMFILL fomfill_pass1 
-	or	fomfill_pass2
-	or	fomfill_coarse
-	or	fomfill_fine
- 	calma 	23 28
-
- layer	POLYFILL polyfill_pass1 
-	or	 polyfill_coarse
-	or	 polyfill_medium
-	or	 polyfill_fine
- 	calma 	28 28
-
-#---------------------------------------------------------
-# LI fill
-# Note requirement that LI fill may not overlap (non-fill)
-# diff or poly.
-#---------------------------------------------------------
-
- templayer      obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
-        grow    2800
-	or	alldiff,allpoly
-	grow	200
- templayer	lifill_coarse topbox
-        # slots   0 3000 650 0 3000 650 700 0
-        slots   0 3000 900 0 3000 900 700 0
-        and-not obstruct_li_coarse
-	and	topbox
-        shrink  1495
-        grow    1495
-
- templayer      obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
-        grow    2500
-	or	lifill_coarse
-	grow	300
-	or	alldiff,allpoly
-        grow    200
- templayer	lifill_medium topbox
-        slots   0 1500 500 0 1500 500 700 0
-        and-not obstruct_li_medium
-	and	topbox
-        shrink  745
-        grow    745
-
- templayer      obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
-	or	lifill_coarse,lifill_medium
-	grow	300
-	or	alldiff,allpoly
-        grow    200
- templayer	lifill_fine topbox
-        slots   0 580 500 0 580 500 700 0
-        and-not obstruct_li_fine
-	and	topbox
-        shrink  285
-        grow    285
-
- layer	LIFILL  lifill_coarse
-	or	lifill_medium
-	or	lifill_fine
- 	calma 	56 28
-
-#---------------------------------------------------
-# MET1 fill
-#---------------------------------------------------
-
- templayer      obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
-        grow    3000
- templayer	met1fill_coarse topbox
-        # slots   0 2000 200 0 2000 200 700 0
-        slots   0 2000 800 0 2000 800 700 350
-        and-not obstruct_m1_coarse
-	and	topbox
-        shrink  995
-        grow    995
-
- templayer      obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
-        grow    2800
-	or	met1fill_coarse
-        grow    200
- templayer	met1fill_medium topbox
-        slots   0 1000 200 0 1000 200 700 0
-        and-not obstruct_m1_medium
-	and	topbox
-        shrink  495
-        grow    495
-
- templayer      obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
-        grow    300
-	or	met1fill_coarse,met1fill_medium
-        grow    200
- templayer	met1fill_fine topbox
-        slots   0 580 200 0 580 200 700 0
-        and-not obstruct_m1_fine
-	and	topbox
-        shrink  285
-        grow    285
-
- templayer      obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
-        grow    100
-	or	met1fill_coarse,met1fill_medium,met1fill_fine
-        grow    200
- templayer	met1fill_veryfine topbox
-        slots   0 300 200 0 300 200 100 50
-        and-not obstruct_m1_veryfine
-	and	topbox
-        shrink  145
-        grow    145
-
- layer	MET1FILL met1fill_coarse
-	or	met1fill_medium
-	or	met1fill_fine
-	or	met1fill_veryfine
- 	calma 	36 28
-
-#---------------------------------------------------
-# MET2 fill
-#---------------------------------------------------
- templayer      obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
-        grow    3000
- templayer	met2fill_coarse topbox
-        # slots   0 2000 200 0 2000 200 700 350
-        slots   0 2000 800 0 2000 800 700 350
-        and-not obstruct_m2
-	and	topbox
-        shrink  995
-        grow    995
-
- templayer      obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
-        grow    2800
-	or	met2fill_coarse
-        grow    200
- templayer	met2fill_medium topbox
-        slots   0 1000 200 0 1000 200 700 350
-        and-not obstruct_m2_medium
-	and	topbox
-        shrink  495
-        grow    495
-
- templayer      obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
-        grow    300
-	or	met2fill_coarse,met2fill_medium
-        grow    200
- templayer	met2fill_fine topbox
-        slots   0 580 200 0 580 200 700 350
-        and-not obstruct_m2_fine
-	and	topbox
-        shrink  285
-        grow    285
-
- templayer      obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
-        grow    100
-	or	met2fill_coarse,met2fill_medium,met2fill_fine
-        grow    200
- templayer	met2fill_veryfine topbox
-        slots   0 300 200 0 300 200 100 100
-        and-not obstruct_m2_veryfine
-	and	topbox
-        shrink  145
-        grow    145
-
- layer	MET2FILL met2fill_coarse
-	or met2fill_medium
-	or met2fill_fine
-	or met2fill_veryfine
- 	calma 	41 28
-
-#---------------------------------------------------
-# MET3 fill
-#---------------------------------------------------
- templayer      obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
-        grow    3000
- templayer	met3fill_coarse topbox
-        # slots   0 2000 300 0 2000 300 700 700
-        slots   0 2000 800 0 2000 800 700 350
-        and-not obstruct_m3
-	and	topbox
-        shrink  995
-        grow    995
-
- templayer      obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
-        grow    2700
-	or	met3fill_coarse
-        grow    300
- templayer	met3fill_medium topbox
-        slots   0 1000 300 0 1000 300 700 700
-        and-not obstruct_m3_medium
-	and	topbox
-        shrink  495
-        grow    495
-
- templayer      obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
-        grow    200
-	or	met3fill_coarse,met3fill_medium
-        grow    300
- templayer	met3fill_fine topbox
-        slots   0 580 300 0 580 300 700 700
-        and-not obstruct_m3_fine
-	and	topbox
-        shrink  285
-        grow    285
-
- templayer      obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
-	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
-        grow    100
-	or	met3fill_coarse,met3fill_medium,met3fill_fine
-        grow    300
- templayer	met3fill_veryfine topbox
-        slots   0 400 300 0 400 300 150 200
-        and-not obstruct_m3_veryfine
-	and	topbox
-        shrink  195
-        grow    195
-
- layer	MET3FILL met3fill_coarse
-	or	met3fill_medium
-	or	met3fill_fine
-	or	met3fill_veryfine
- 	calma 	34 28
-
-#---------------------------------------------------
-# MET4 fill
-#---------------------------------------------------
- templayer      obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
-        grow    3000
- templayer	met4fill_coarse topbox
-        # slots   0 2000 300 0 2000 300 700 1050
-        slots   0 2000 800 0 2000 800 700 350
-        and-not obstruct_m4
-	and	topbox
-        shrink  995
-        grow    995
-
- templayer      obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
-        grow    2700
-	or	met4fill_coarse
-        grow    300
- templayer	met4fill_medium topbox
-        slots   0 1000 300 0 1000 300 700 1050
-        and-not obstruct_m4_medium
-	and	topbox
-        shrink  495
-        grow    495
-
- templayer      obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
-        grow    200
-	or	met4fill_coarse,met4fill_medium
-        grow    300
- templayer	met4fill_fine topbox
-        slots   0 580 300 0 580 300 700 1050
-        and-not obstruct_m4_fine
-	and	topbox
-        shrink  285
-        grow    285
-
- templayer      obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
-	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
-        grow    100
-	or	met4fill_coarse,met4fill_medium,met4fill_fine
-        grow    300
- templayer	met4fill_veryfine topbox
-        slots   0 400 300 0 400 300 150 300
-        and-not obstruct_m4_veryfine
-	and	topbox
-        shrink  195
-        grow    195
-
- layer	MET4FILL met4fill_coarse
-	or	met4fill_medium
-	or	met4fill_fine
-	or	met4fill_veryfine
- 	calma 	51 28
-
-#---------------------------------------------------
-# MET5 fill
-#---------------------------------------------------
- templayer      obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
-        grow    3000
- templayer	met5fill_coarse topbox
-        slots   0 5000 1600 0 5000 1600 1000 100
-        and-not obstruct_m5
-	and	topbox
-        shrink  2495
-        grow    2495
-
- templayer      obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
-        grow    1400
-	or	met5fill_coarse
-        grow    1600
- templayer	met5fill_medium topbox
-        slots   0 3000 1600 0 3000 1600 1000 100
-        and-not obstruct_m5_medium
-	and	topbox
-        shrink  1495
-        grow    1495
-
- layer	MET5FILL met5fill_coarse
-	or	met5fill_medium
- 	calma 	59 28
-
-end
-
-#-----------------------------------------------------------------------
-cifinput
-#-----------------------------------------------------------------------
-# NOTE:  All values in this section MUST be multiples of 25 
-# or else magic will scale below the allowed layout grid size
-#-----------------------------------------------------------------------
-
-style  sky130 variants (),(vendor)
- scalefactor 10 nanometers
- gridlimit 5
-
- options ignore-unknown-layer-labels no-reconnect-labels
-
- ignore NPC
- ignore SEALID
- ignore CAPID
- ignore LDNTM
- ignore HVNTM
- ignore POLYMOD
- ignore LOWTAPDENSITY
- ignore FILLOBSPOLY
- ignore OUTLINE
-
- layer pnp NWELL,WELLTXT,WELLPIN
- and PNPID
- labels NWELL
- variants (vendor)
- labels WELLTXT port
- variants ()
- labels WELLTXT text
- variants *
- labels WELLPIN port
-
- layer nwell NWELL,WELLTXT,WELLPIN
- and-not PNPID
- labels NWELL
- variants (vendor)
- labels WELLTXT port
- variants ()
- labels WELLTXT text
- variants *
- labels WELLPIN port
-
- templayer nwellarea NWELL
- copyup nwelcheck
-
- # Copy nwell areas up for diffusion checks
- templayer xnwelcheck nwelcheck
- copyup nwelcheck
-
- templayer hvarea HVI
- copyup hvcheck
-
- # Copy high-voltage (HVI) areas up for diffusion checks
- templayer xhvcheck hvcheck
- copyup hvcheck
-
- # Always draw pwell under p-tap and n-diff.  This is not always
- # necessary but works better with deep nwell for correct extraction.
- layer pwell TAP,DIFF
- and-not NWELL,nwelcheck
- grow 130
- or SUBTXT,SUBPIN
- grow 420
- shrink 420
- variants (vendor)
- labels SUBTXT port
- variants ()
- labels SUBTXT text
- variants *
- labels SUBPIN port
-
- layer dnwell DNWELL
- labels DNWELL
-
- layer npn DNWELL
- and-not NWELL,nwelcheck
- and NPNID
-
- layer rpw PWRES
- and DNWELL
- labels PWRES
-
- templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
- and-not POLY
- and-not NWELL,nwelcheck
- and-not PSDM
- and-not DIODE
- and-not DIFFRES
- and-not HVI,hvcheck
- and NSDM
- and-not CORELI
- copyup ndifcheck
- labels DIFF
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer ndiff ndiffarea
-
- # Copy ndiff areas up for contact checks
- templayer xndifcheck ndifcheck
- copyup ndifcheck
-
- templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
- and-not POLY
- and-not NWELL,nwelcheck
- and-not PSDM
- and-not DIODE
- and-not DIFFRES
- and HVI,hvcheck
- and NSDM
- copyup ndifcheck
- labels DIFF
- labels DIFFTXT text
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer mvndiff mvndiffarea
-
- # Copy ndiff areas up for contact checks
- templayer mvxndifcheck mvndifcheck
- copyup mvndifcheck
-
- layer ndiode DIFF,barediff
- and NSDM
- and DIODE
- and-not NWELL,nwelcheck
- and-not POLY
- and-not PSDM
- and-not HVI,hvcheck
- and-not LVTN
- labels DIFF
-
- layer ndiodelvt DIFF,barediff
- and NSDM
- and DIODE
- and-not NWELL,nwelcheck
- and-not POLY
- and-not PSDM
- and-not HVI,hvcheck
- and LVTN
- labels DIFF
-
- templayer ndiodearea DIODE
- and NSDM
- and-not HVI,hvcheck
- and-not NWELL,nwelcheck
- copyup DIODE,NSDM
-
- layer ndiffres DIFFRES
- and NSDM
- and-not HVI,hvcheck
- labels DIFF
-
- templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
- and-not POLY
- and NWELL,nwelcheck
- and-not NSDM
- and-not DIODE
- and-not HVI,hvcheck
- and PSDM
- copyup pdifcheck
- labels DIFF 
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer pdiff pdiffarea
-
- layer mvndiode DIFF,barediff
- and NSDM
- and DIODE
- and HVI,hvcheck
- and-not POLY
- and-not PSDM
- and-not LVTN
- labels DIFF
-
- layer nndiode DIFF,barediff
- and NSDM
- and DIODE
- and HVI,hvcheck
- and-not POLY
- and-not PSDM
- and LVTN
- labels DIFF
-
- templayer mvndiodearea DIODE
- and NSDM
- and HVI,hvcheck
- and-not NWELL,nwelcheck
- copyup DIODE,NSDM
-
- layer mvndiffres DIFFRES
- and NSDM
- and HVI,hvcheck
- labels DIFF
-
- templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
- and-not POLY
- and NWELL,nwelcheck
- and-not NSDM
- and HVI,hvcheck
- and-not DIODE
- and-not DIFFRES
- and PSDM
- copyup mvpdifcheck
- labels DIFF
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer mvpdiff mvpdiffarea
-
- # Copy pdiff areas up for contact checks
- templayer xpdifcheck pdifcheck
- copyup pdifcheck
-
- layer pdiode DIFF,barediff
- and PSDM
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and-not LVTN
- and-not HVTP
- and DIODE
- labels DIFF
-
- layer pdiodelvt DIFF,barediff
- and PSDM
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and LVTN
- and-not HVTP
- and DIODE
- labels DIFF
-
- layer pdiodehvt DIFF,barediff
- and PSDM
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and-not LVTN
- and HVTP
- and DIODE
- labels DIFF
-
- templayer pdiodearea DIODE
- and PSDM
- and-not HVI,hvcheck
- copyup DIODE,PSDM
-
- # Define pfet areas as known pdiff, regardless of the presence of a well.
-
- templayer pfetarea DIFF,barediff
- and POLY
- or baretrans
- and-not NSDM
- and-not HVI,hvcheck
-
- layer pfet pfetarea
- and-not LVTN
- and-not HVTP
- and-not STDCELL
- and-not COREID
- labels DIFF
-
- layer scpfet pfetarea
- and-not LVTN
- and-not HVTP
- and STDCELL
- and-not COREID
- labels DIFF
-
- layer scpfethvt pfetarea
- and-not LVTN
- and HVTP
- and STDCELL
- labels DIFF
-
- layer ppu pfetarea
- and-not LVTN
- and HVTP
- and COREID
- # Shrink-grow operation eliminates the smaller parasitie device
- # shrink 70
- # grow 70
- labels DIFF
-
- layer pfetlvt pfetarea
- and LVTN
- labels DIFF
-
- layer pfetmvt pfetarea
- and HVTR
- labels DIFF
-
- layer pfethvt pfetarea
- and HVTP
- and-not STDCELL
- and-not COREID
- labels DIFF
-
- # Always force nwell under pfet (nwell encloses pdiff by 0.18)
- layer nwell pfetarea
- grow 180
-
- # Copy mvpdiff areas up for contact checks
- templayer mvxpdifcheck mvpdifcheck
- copyup mvpdifcheck
-
- layer mvpdiode DIFF,barediff
- and PSDM
- and-not POLY
- and-not NSDM
- and HVI,hvcheck
- and DIODE
- labels DIFF
-
- templayer mvpdiodearea DIODE
- and PSDM
- and HVI,hvcheck
- copyup DIODE,PSDM
-
- # Define pfet areas as known pdiff,
- # regardless of the presence of a
- # well.
-
- templayer mvpfetarea DIFF,barediff
- and POLY
- or baretrans
- and-not NSDM
- and HVI,hvcheck
-
- layer mvpfet mvpfetarea
- and-not ESDID
- labels DIFF
-
- layer mvpfetesd mvpfetarea
- and ESDID
- labels DIFF
-
- layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
- and-not NSDM
- and-not POLY
- and-not HVI,hvcheck
- and-not DIODE
- and-not DIFFRES
- labels DIFF
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer pdiffres DIFFRES
- and PSDM
- and NWELL,nwelcheck
- and-not HVI,hvcheck
- labels DIFF
-
- layer nfet DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not HVI,hvcheck
- and-not LVTN
- and-not SONOS
- and-not STDCELL
- and-not COREID
- labels DIFF
-
- layer scnfet DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not NWELL,nwelcheck
- and-not HVI,hvcheck
- and-not LVTN
- and-not SONOS
- and STDCELL
- labels DIFF
-
- layer npass DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not NWELL,nwelcheck
- and COREID
- labels DIFF
-
- layer npd DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not NWELL,nwelcheck
- and COREID
- # Shrink-grow operation eliminates the smaller npass device
- shrink 70
- grow 70
- labels DIFF
-
- # Devices abutting tap under gate are officially npd, not npass
- layer npd TAP
- grow 100
- and DIFF
- and POLY
- and-not PSDM
- and NSDM
- and-not NWELL,nwelcheck
- and COREID
- labels DIFF
-
- layer nfetlvt DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not HVI,hvcheck
- and LVTN
- and-not SONOS
- labels DIFF
-
- layer nsonos DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not HVI,hvcheck
- and LVTN
- and SONOS
- labels DIFF
-
- templayer nsdarea TAP
- and NSDM
- and NWELL,nwelcheck
- and-not POLY
- and-not PSDM
- and-not HVI,hvcheck
- and-not CORELI
- copyup nsubcheck
-
- layer nsd nsdarea
- labels TAP
-
- layer nsd TAP,TAPTXT
- and NSDM
- and-not POLY
- and-not HVI,hvcheck
- labels TAP
- labels TAPTXT text
-
- layer corenvar TAP
- and NSDM
- and POLY
- and COREID
- labels TAP
-
- templayer nsdexpand nsdarea
- grow 500
-
- # Copy nsub areas up for contact checks
- templayer xnsubcheck nsubcheck
- copyup nsubcheck
-
- templayer psdarea TAP
- and PSDM
- and-not NWELL,nwelcheck
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and-not pfetexpand
- copyup psubcheck
-
- layer psd psdarea
- labels TAP
-
- layer psd TAP
- and PSDM
- and-not POLY
- and-not HVI,hvcheck
- labels TAP
- labels TAPTXT text
-
- layer corepvar TAP
- and PSDM
- and POLY
- and COREID
- labels TAP
-
- templayer psdexpand psdarea
- grow 500
-
- layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
- and-not NSDM
- and-not POLY
- and HVI,hvcheck
- and mvpfetexpand
- labels DIFF
- variants (vendor)
- labels DIFFTXT port
- variants ()
- labels DIFFTXT text
- variants *
- labels DIFFPIN port
-
- layer mvpdiffres DIFFRES
- and PSDM
- and NWELL,nwelcheck
- and HVI,hvcheck
- and-not mvrdpioedge
- labels DIFF
-
- templayer mvnfetarea DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and-not LVTN
- and HVI,hvcheck
- grow 350
-
- templayer mvnnfetarea DIFF,TAP,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and LVTN
- and HVI,hvcheck
- and-not mvnfetarea
-
- layer mvnfetesd DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and HVI,hvcheck
- and ESDID
- and-not mvnnfetarea
- labels DIFF
-
- layer mvnfet DIFF,barediff
- and POLY
- or baretrans
- and-not PSDM
- and NSDM
- and HVI,hvcheck
- and-not ESDID
- and-not mvnnfetarea
- labels DIFF
-
- layer nnfet mvnnfetarea
- and LVID
- labels DIFF
-
- layer mvnnfet mvnnfetarea
- and-not LVID
- labels DIFF
-
- templayer mvnsdarea TAP
- and NSDM
- and NWELL,nwelcheck
- and-not POLY
- and-not PSDM
- and HVI,hvcheck
- copyup mvnsubcheck
-
- layer mvnsd mvnsdarea
- labels TAP
-
- layer mvnsd TAP,TAPTXT
- and NSDM
- and HVI,hvcheck
- labels TAP
- labels TAPTXT text
-
- templayer mvnsdexpand mvnsdarea
- grow 500
-
- # Copy nsub areas up for contact checks
- templayer mvxnsubcheck mvnsubcheck
- copyup mvnsubcheck
-
- templayer mvpsdarea DIFF,barediff
- and PSDM
- and-not NWELL,nwelcheck
- and-not POLY
- and-not NSDM
- and HVI,hvcheck
- and-not mvpfetexpand
- copyup mvpsubcheck
-
- layer mvpsd mvpsdarea
- labels DIFF
-
- layer mvpsd TAP,TAPTXT
- and PSDM
- and HVI,hvcheck
- labels TAP
- labels TAPTXT text
-
- templayer mvpsdexpand mvpsdarea
- grow 500
-
- # Copy psub areas up for contact checks
- templayer xpsubcheck psubcheck
- copyup psubcheck
-
- templayer mvxpsubcheck mvpsubcheck
- copyup mvpsubcheck
-
- layer psd TAP
- and-not PSDM
- and-not NSDM
- and-not POLY
- and-not HVI,hvcheck
- and-not pfetexpand
- and psdexpand
-
- layer nsd TAP
- and-not PSDM
- and-not NSDM
- and-not POLY
- and-not HVI,hvcheck
- and nsdexpand
-
- layer mvpsd TAP
- and-not PSDM
- and-not NSDM
- and-not POLY
- and HVI,hvcheck
- and-not mvpfetexpand
- and mvpsdexpand
-
- layer mvnsd TAP
- and-not PSDM
- and-not NSDM
- and-not POLY
- and HVI,hvcheck
- and mvnsdexpand
-
- templayer hresarea POLY
- and RPM
- grow 3000
-
- templayer uresarea POLY
- and URPM
- grow 3000
-
- templayer diffresarea DIFFRES
- and-not HVI,hvcheck
- grow 3000
-
- templayer mvdiffresarea DIFFRES
- and HVI,hvcheck
- grow 3000
-
- templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
-
- layer pfet POLY
- and DIFF
- and diffresarea
- and-not NSDM
- and-not STDCELL
-
- layer scpfet POLY
- and DIFF
- and diffresarea
- and-not HVTP
- and-not NSDM
- and STDCELL
-
- layer scpfethvt POLY
- and DIFF
- and diffresarea
- and HVTP
- and-not NSDM
- and STDCELL
-
- templayer xpolyterm RPM,URPM
- and POLY
- and-not POLYRES
- # add back the 0.06um contact surround in the direction of the resistor
- grow 60
- and POLY
-
- layer xpc xpolyterm
-
- templayer polyarea POLY,POLYTXT,POLYPIN
- and-not POLYRES
- and-not POLYSHORT
- and-not DIFF
- and-not TAP
- and-not RPM
- and-not URPM
- copyup polycheck
-
- layer poly polyarea
- labels POLY
- variants (vendor)
- labels POLYTXT port
- variants ()
- labels POLYTXT text
- variants *
- labels POLYPIN port
-
- # Copy (non-resistor) poly areas up for contact checks
- templayer xpolycheck polycheck
- copyup polycheck
-
- layer mrp1 POLY
- and POLYRES
- and-not RPM
- and-not URPM
- labels POLY
-
- layer rmp POLY
- and POLYSHORT
- labels POLY
-
- layer xhrpoly POLY
- and POLYRES
- and RPM
- and-not URPM
- and PSDM
- and NPC
- and-not xpolyterm
- labels POLY
-
- layer uhrpoly POLY
- and POLYRES
- and URPM
- and-not RPM
- and NPC
- and-not xpolyterm
- labels POLY
-
- templayer ndcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and-not NWELL,nwelcheck
- and-not HVI,hvcheck
-
- layer ndc ndcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or ndcbase
- labels CONT
-
- templayer nscbase CONT
- or barecont
- and LI
- or licont
- and DIFF,TAP
- and NSDM
- and NWELL,nwelcheck
- and-not HVI,hvcheck
-
- layer nsc nscbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or nscbase
- labels CONT
-
- templayer pdcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and NWELL,nwelcheck
- and-not HVI,hvcheck
-
- layer pdc pdcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdcbase
- labels CONT
-
- templayer pdcnowell CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and pfetexpand
- and-not HVI,hvcheck
-
- layer pdc pdcnowell
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdcnowell
- labels CONT
-
- templayer pscbase CONT
- or barecont
- and LI
- or licont
- and DIFF,TAP
- and PSDM
- and-not NWELL,nwelcheck
- and-not pfetexpand
- and-not HVI,hvcheck
-
- layer psc pscbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pscbase
- labels CONT
-
- templayer pcbase CONT
- or barecont
- and LI
- or licont
- and POLY
- and-not DIFF
- and-not RPM,URPM
-
- layer pc pcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pcbase
- labels CONT
-
- templayer ndicbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and DIODE
- and-not POLY
- and-not PSDM
- and-not HVI,hvcheck
- and-not LVTN
-
- layer ndic ndicbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or ndicbase
- labels CONT
-
- templayer ndilvtcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and DIODE
- and-not POLY
- and-not PSDM
- and-not HVI,hvcheck
- and LVTN
-
- layer ndilvtc ndilvtcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or ndilvtcbase
- labels CONT
-
- templayer pdicbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and DIODE
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and-not LVTN
- and-not HVTP
-
- layer pdic pdicbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdicbase
- labels CONT
-
- templayer pdilvtcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and DIODE
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and LVTN
- and-not HVTP
-
- layer pdilvtc pdilvtcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdilvtcbase
- labels CONT
-
- templayer pdihvtcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and DIODE
- and-not POLY
- and-not NSDM
- and-not HVI,hvcheck
- and-not LVTN
- and HVTP
-
- layer pdihvtc pdihvtcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdihvtcbase
- labels CONT
-
- templayer mvndcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and-not NWELL,nwelcheck
- and HVI,hvcheck
-
- layer mvndc mvndcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvndcbase
- labels CONT
-
- templayer mvnscbase CONT
- or barecont
- and LI
- or licont
- and DIFF,TAP
- and NSDM
- and NWELL,nwelcheck
- and HVI,hvcheck
-
- layer mvnsc mvnscbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvnscbase
- labels CONT
-
- templayer mvpdcbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and NWELL,nwelcheck
- and HVI,hvcheck
-
- layer mvpdc mvpdcbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpdcbase
- labels CONT
-
- templayer mvpdcnowell CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and mvpfetexpand
- and MET1
- and HVI,hvcheck
-
- layer mvpdc mvpdcnowell
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpdcnowell
- labels CONT
-
- templayer mvpscbase CONT
- or barecont
- and LI
- or licont
- and DIFF,TAP
- and PSDM
- and-not NWELL,nwelcheck
- and-not mvpfetexpand
- and HVI,hvcheck
-
- layer mvpsc mvpscbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpscbase
- labels CONT
-
- templayer mvndicbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and DIODE
- and-not POLY
- and-not PSDM
- and-not LVTN
- and HVI,hvcheck
-
- layer mvndic mvndicbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvndicbase
- labels CONT
-
- templayer nndicbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and NSDM
- and DIODE
- and-not POLY
- and-not PSDM
- and LVTN
- and HVI,hvcheck
-
- layer nndic nndicbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or nndicbase
- labels CONT
-
- templayer mvpdicbase CONT
- or barecont
- and LI
- or licont
- and DIFF
- and PSDM
- and DIODE
- and-not POLY
- and-not NSDM
- and HVI,hvcheck
-
- layer mvpdic mvpdicbase
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpdicbase
- labels CONT
-
- layer	fomfill  FOMFILL
- labels FOMFILL
-
- layer	polyfill POLYFILL
- labels POLYFILL
-
- layer coreli LI,LITXT,LIPIN
- and-not LIRES,LISHORT
- and COREID
- labels LI
- variants (vendor)
- labels LITXT port
- variants ()
- labels LITXT text
- variants *
- labels LIPIN port
-
- layer locali LI,LITXT,LIPIN
- and-not LIRES,LISHORT
- and-not COREID
- labels LI
- variants (vendor)
- labels LITXT port
- variants ()
- labels LITXT text
- variants *
- labels LIPIN port
-
- layer rli LI
- and LIRES,LISHORT
- labels LIRES,LISHORT
-
- layer	lifill LIFILL
- labels LIFILL
-
- layer mcon MCON
- grow 95
- shrink 95
- shrink 85
- grow 85
- or MCON
- labels MCON
-
- layer m1 MET1,MET1TXT,MET1PIN
- and-not MET1RES,MET1SHORT
- labels MET1
- variants (vendor)
- labels MET1TXT port
- variants ()
- labels MET1TXT text
- variants *
- labels MET1PIN port
-
- layer rm1 MET1
- and MET1RES,MET1SHORT
- labels MET1RES,MET1SHORT
-
- layer m1fill MET1FILL
- labels MET1FILL
-
- layer mimcap MET3
- and CAPM
- labels CAPM
-
- layer mimcc VIA3
- and CAPM
- grow 60
- grow 40
- shrink 40
- labels CAPM
-
- layer mimcap2 MET4
- and CAPM2
- labels CAPM2
-
- layer mim2cc VIA4
- and CAPM2
- grow 190
- grow 210
- shrink 210
- labels CAPM2
-
-
- templayer m2cbase VIA1
- and-not COREID
- grow 5
- or VIA1
- grow 50
-
- layer m2c m2cbase
- grow 30
- shrink 30
- shrink 130
- grow 130
- or m2cbase
-
- layer m2 MET2,MET2TXT,MET2PIN
- and-not MET2RES,MET2SHORT
- labels MET2
- variants (vendor)
- labels MET2TXT port
- variants ()
- labels MET2TXT text
- variants *
- labels MET2PIN port
-
- layer rm2 MET2
- and MET2RES,MET2SHORT
- labels MET2RES,MET2SHORT
-
- layer m2fill MET2FILL
- labels MET2FILL
-
- templayer m3cbase VIA2
- grow 40
-
- layer m3c m3cbase
- grow 60
- shrink 60
- shrink 140 
- grow 140
- or m3cbase
-
- layer m3 MET3,MET3TXT,MET3PIN
- and-not MET3RES,MET3SHORT
- labels MET3
- variants (vendor)
- labels MET3TXT port
- variants ()
- labels MET3TXT text
- variants *
- labels MET3PIN port
-
- layer rm3 MET3
- and MET3RES,MET3SHORT
- labels MET3RES,MET3SHORT
-
- layer m3fill MET3FILL
- labels MET3FILL
-
-
- templayer via3base VIA3
- and-not CAPM
- grow 60
-
- layer via3 via3base
- grow 40
- shrink 40
- shrink 160
- grow 160
- or via3base
-
- layer m4 MET4,MET4TXT,MET4PIN
- and-not MET4RES,MET4SHORT
- labels MET4
- variants (vendor)
- labels MET4TXT port
- variants ()
- labels MET4TXT text
- variants *
- labels MET4PIN port
-
- layer rm4 MET4
- and MET4RES,MET4SHORT
- labels MET4RES,MET4SHORT
-
- layer m4fill MET4FILL
- labels MET4FILL
-
- layer m5 MET5,MET5TXT,MET5PIN
- and-not MET5RES,MET5SHORT
- labels MET5
- variants (vendor)
- labels MET5TXT port
- variants ()
- labels MET5TXT text
- variants *
- labels MET5PIN port
-
- layer rm5 MET5
- and MET5RES,MET5SHORT
- labels MET5RES,MET5SHORT
-
- layer m5fill MET5FILL
- labels MET5FILL
-
- templayer via4base VIA4
- and-not CAPM2
- grow 190
-
- layer via4 via4base
- grow 210
- shrink 210
- shrink 590
- grow 590
- or via4base
-
- layer metrdl RDL,RDLTXT,RDLPIN
- labels RDL
- variants (vendor)
- labels RDLTXT port
- variants ()
- labels RDLTXT text
- variants *
- labels RDLPIN port
-
- # Find diffusion not covered in
- # NSDM or PSDM and pull it into
- # the next layer up
-
- templayer gentrans DIFF
- and-not PSDM
- and-not NSDM
- and POLY
- copyup baretrans
-
- templayer gendiff DIFF,TAP
- and-not PSDM
- and-not NSDM
- and-not POLY
- and-not COREID
- copyup barediff
-
- # Handle contacts found by copyup
-
- templayer ndiccopy CONT
- and LI
- and DIODE
- and NSDM
- and-not HVI,hvcheck
-
- layer ndic ndiccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or ndiccopy
- labels CONT
-
- templayer mvndiccopy CONT
- and LI
- and DIODE
- and NSDM
- and HVI,hvcheck
-
- layer mvndic mvndiccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvndiccopy
- labels CONT
-
- templayer pdiccopy CONT
- and LI
- and DIODE
- and PSDM
- and-not HVI,hvcheck
-
- layer pdic pdiccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdiccopy
- labels CONT
-
- templayer mvpdiccopy CONT
- and LI
- and DIODE
- and PSDM
- and HVI,hvcheck
-
- layer mvpdic mvpdiccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpdiccopy
- labels CONT
-
- templayer ndccopy CONT
- and ndifcheck
-
- layer ndc ndccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or ndccopy
- labels CONT
-
- templayer mvndccopy CONT
- and mvndifcheck
-
- layer mvndc mvndccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvndccopy
- labels CONT
-
- templayer pdccopy CONT
- and pdifcheck
-
- layer pdc pdccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pdccopy
- labels CONT
-
- templayer mvpdccopy CONT
- and mvpdifcheck
-
- layer mvpdc mvpdccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpdccopy
- labels CONT
-
- templayer pccopy CONT
- and polycheck
-
- layer pc pccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or pccopy
- labels CONT
-
- templayer nsccopy CONT
- and nsubcheck
-
- layer nsc nsccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or nsccopy
- labels CONT
-
- templayer mvnsccopy CONT
- and mvnsubcheck
-
- layer mvnsc mvnsccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvnsccopy
- labels CONT
-
- templayer psccopy CONT
- and psubcheck
-
- layer psc psccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or psccopy
- labels CONT
-
- templayer mvpsccopy CONT
- and mvpsubcheck
-
- layer mvpsc mvpsccopy
- grow 85
- shrink 85
- shrink 85
- grow 85
- or mvpsccopy
- labels CONT
-
- # Find contacts not covered in
- # metal and pull them into the
- # next layer up
- 
- templayer gencont CONT
- and LI
- and-not DIFF,TAP
- and-not POLY
- and-not DIODE
- and-not nsubcheck
- and-not psubcheck
- and-not mvnsubcheck
- and-not mvpsubcheck
- and-not CORELI
- copyup barelicont
-
- templayer barecont CONT
- and-not LI
- and-not nsubcheck
- and-not psubcheck
- and-not mvnsubcheck
- and-not mvpsubcheck
- and-not CORELI
- copyup barecont
-
- layer glass GLASS,PADTXT,PADPIN
- labels GLASS
- variants (vendor)
- labels PADTXT port
- variants ()
- labels PADTXT text
- variants *
- labels PADPIN port
-
- templayer boundary BOUND,STDCELL,PADCELL
- boundary
-
- layer comment LVSTEXT
- labels LVSTEXT text
-
- layer comment TTEXT
- labels TTEXT text
-
- layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
- labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
-
- layer obsactive  FILLOBSFOM
-
-# MOS Varactor
-
- layer var POLY
- and TAP
- and NSDM
- and NWELL,nwelcheck
- and-not HVI,hvcheck
- and-not HVTP
- # NOTE:  Else forms a varactor that is not in the vendor netlist.
- and-not COREID
- labels POLY
-
- layer varhvt POLY
- and TAP
- and NSDM
- and NWELL,nwelcheck
- and-not HVI,hvcheck
- and HVTP
- labels POLY
-
- layer mvvar POLY
- and TAP
- and NSDM
- and NWELL,nwelcheck
- and HVI,hvcheck
- labels POLY
-
- calma NWELL 64 20
- calma DIFF 65 20
- calma DNWELL 64 18
- calma PWRES 64 13
- calma TAP  65 44
- # LVTN
- calma LVTN 125 44
- # HVTR
- calma HVTR 18 20
- # HVTP
- calma HVTP 78 44
- # SONOS (TUNM)
- calma SONOS 80 20
- # NSDM (NPLUS)
- calma NSDM 93 44
- # PSDM (PPLUS)
- calma PSDM 94 20
- # HVI (THKOX)
- calma HVI 75 20
- # NPC
- calma NPC 95 20
- # P+ POLY MASK
- calma RPM 86 20
- calma URPM 79 20
- calma LDNTM 11 44
- calma HVNTM 125 20
- # Poly resistor ID mark
- calma POLYRES 66 13
- # Diffusion resistor ID mark
- calma DIFFRES 65 13
- calma POLY 66 20
- calma POLYMOD 66 83
- # 3.3V native FET ID mark
- calma LVID 81 60
- # Diode ID mark
- calma DIODE 81 23
- # Bipolar NPN mark
- calma NPNID 82 20
- # Bipolar PNP mark
- calma PNPID 82 44
- # Capacitor ID
- calma CAPID 82 64
- # Core area ID mark
- calma COREID 81 2
- # Standard cell ID mark
- calma STDCELL 81 4
- # Padframe cell ID mark
- calma PADCELL 81 3
- # Seal ring ID mark
- calma SEALID 81 1
- # Low tap density ID mark
- calma LOWTAPDENSITY 81 14
- # ESD area ID
- calma ESDID 81 19
- calma OUTLINE 236 0
- 
- # LICON
- calma CONT 66 44
- calma LI   67 20
- calma MCON 67 44
-
- calma MET1 68 20
- calma VIA1 68 44
- calma MET2 69 20
- calma VIA2 69 44
- calma MET3 70 20
- calma VIA3 70 44
- calma MET4 71 20
- calma VIA4 71 44
- calma MET5 72 20
- calma RDL 74 20
- calma GLASS 76 20
-
- calma SUBTXT  64 59
- calma PADTXT  76 5
- calma DIFFTXT 65 6
- calma TAPTXT  65 5
- calma WELLTXT  64 5
- calma LITXT 67 5
- calma POLYTXT 66 5
- calma MET1TXT 68 5
- calma MET2TXT 69 5
- calma MET3TXT 70 5
- calma MET4TXT 71 5
- calma MET5TXT 72 5
- calma RDLTXT 74 5
-
- calma LIRES 67 13
- calma MET1RES 68 13
- calma MET2RES 69 13
- calma MET3RES 70 13
- calma MET4RES 71 13
- calma MET5RES 72 13
-
- calma LIFILL   56 28
- calma MET1FILL 36 28
- calma MET2FILL 41 28
- calma MET3FILL 34 28
- calma MET4FILL 51 28
- calma MET5FILL 59 28
-
- calma POLYSHORT 66 15
- calma LISHORT 67 15
- calma MET1SHORT 68 15
- calma MET2SHORT 69 15
- calma MET3SHORT 70 15
- calma MET4SHORT 71 15
- calma MET5SHORT 72 15
-
- calma SUBPIN 122 16
- calma PADPIN 76 16
- calma DIFFPIN 65 16
- calma POLYPIN 66 16
- calma WELLPIN 64 16
- calma LIPIN 67 16
- calma MET1PIN 68 16
- calma MET2PIN 69 16
- calma MET3PIN 70 16
- calma MET4PIN 71 16
- calma MET5PIN 72 16
- calma RDLPIN 74 16
-
- calma BOUND 235 4
-
- calma LVSTEXT 83 44
-
- calma CAPM 89 44
- calma CAPM2 97 44
-
- calma FILLOBSM1  62  24
- calma FILLOBSM2  105 52
- calma FILLOBSM3  107 24
- calma FILLOBSM4  112  4
- calma FILLOBSFOM  22 24
- calma FILLOBSPOLY 33 24
-
- calma FOMFILL	  23  28
- calma POLYFILL	  28  28
- calma LIFILL	  56  28
- calma MET1FILL	  36  28
- calma MET2FILL	  41  28
- calma MET3FILL	  34  28
- calma MET4FILL	  51  28
- calma MET5FILL	  59  28
-
-#-----------------------------------------------------------------------
-
-style  rdlimport
- # This style is for reading shapes generated with the RDL layers
-
- scalefactor 10 nanometers
- gridlimit 5
-
- options ignore-unknown-layer-labels no-reconnect-labels
-
- layer mrdl RDL
- layer mrdlc RDLC
-
- calma RDL 10 0
- calma RDLC 20 0
-
-end
-
-#-----------------------------------------------------
-# Digital flow maze router cost parameters
-#-----------------------------------------------------
-
-mzrouter
-end
-
-#-----------------------------------------------------
-# Vendor DRC rules
-#-----------------------------------------------------
-
-drc
-
- style drc variants (fast),(full),(routing)
- scalefactor 10 
- cifstyle drc
-
- variants (fast),(full)
-
-#-----------------------------
-# DNWELL
-#-----------------------------
-
- width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
- spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
- spacing dnwell allnwell 4500 surround_ok \
-	"Deep N-well spacing to N-well < %d (nwell.7)"
-
- variants (full)
- cifmaxwidth nwell_missing 0 bend_illegal \
-	"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
- cifmaxwidth dnwell_missing 0 bend_illegal \
-	"SONOS nFET must be in Deep N-well (tunm.6a)"
-
- cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
-	"P+ diff cannot straddle Deep N-well (dnwell.5)"
- variants (fast),(full)
-
-#-----------------------------
-# NWELL
-#-----------------------------
-
- width allnwell 840 "N-well width < %d (nwell.1)"
- spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
-
- variants (full)
- cifmaxwidth nwell_missing_tap 0 bend_illegal \
-	"All nwells must contain metal-connected N+ taps (nwell.4)"
-
- cifspacing mvnwell lvnwell 2000 touching_illegal \
-	"Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
- cifspacing mvnwell mvnwell 2000 touching_ok \
-	"Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
- variants (fast),(full)
-
-#-----------------------------
-# DIFF
-#-----------------------------
-
- width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
-	150 "Diffusion width < %d (diff/tap.1)"
- width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
-	"MV Diffusion width < %d (diff/tap.14)"
-
- width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
- extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
- extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
- extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
- extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
- width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
- spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
-	"Diffusion spacing < %d (diff/tap.3)"
- spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
-	"MV Diffusion spacing < %d (diff/tap.15a)"
- spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
-	"MV Diffusion to MV tap spacing < %d (diff/tap.3)"
- spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
-	touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
- spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
-	"MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
- spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
-	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
- spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
-	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
- spacing *psd allnwell 130 touching_illegal \
-	"P-tap spacing to N-well < %d (diff/tap.11)"
- spacing *mvpsd allnwell 130 touching_illegal \
-	"P-tap spacing to N-well < %d (diff/tap.11)"
- surround *nsd allnwell 180 absence_illegal \
-	"N-well overlap of N-tap < %d (diff/tap.10)"
- surround *mvnsd allnwell 330 absence_illegal \
-	"N-well overlap of MV N-tap < %d (diff/tap.19)"
- surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
-	"N-well overlap of P-Diffusion < %d (diff/tap.8)"
- surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
-	"N-well overlap of P-Diffusion < %d (diff/tap.17)"
- surround mvvar allnwell 560 absence_illegal \
-	"N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
- spacing *mvndiode *mvndiode 1070 touching_ok \
-	"MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
-
-variants (full)
- cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
-	"MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
-variants (fast),(full)
-
- spacing allnfets allpactivenonfet 270 touching_illegal \
-	"nFET cannot abut P-diffusion (diff/tap.3)"
- spacing allpfets allnactivenonfet 270 touching_illegal \
-	"pFET cannot abut N-diffusion (diff/tap.3)"
-
- # Butting junction rules
- edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
-	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
- edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
-	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
- edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
-	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
- edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
-	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
-
- edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
-	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
- edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
-	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
- edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
-	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
- edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
-	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
-
- # Sandwiched butting junction restrictions
- edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
- edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
-
- area  *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
- area  *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
-
- angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
-
- variants (full)
- cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
-
- # Latchup rules
- cifmaxwidth ptap_missing 0 bend_illegal \
-	"N-diff distance to P-tap must be < 15.0um (LU.2)"
- cifmaxwidth dptap_missing 0 bend_illegal \
-	"N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
- cifmaxwidth ntap_missing 0 bend_illegal \
-	"P-diff distance to N-tap must be < 15.0um (LU.3)"
-
- variants (fast),(full)
-
-#-----------------------------
-# POLY
-#-----------------------------
-
- width allpoly,polyfill 150 "poly width < %d (poly.1a)"
- spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
-
- spacing allpolynonfet,polyfill \
-	*ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
-	75 corner_ok allfets \
-	"poly spacing to Diffusion < %d (poly.4)"
- spacing npres *nsd 480 touching_illegal \
-	"poly resistor spacing to N-tap < %d (poly.9)"
- overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
- overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
-	"N-Diffusion overhang of nFET < %d (poly.7)"
- overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
- overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
- overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
- overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
- rect_only allfets "No bends in transistors (poly.11)"
- rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
- extend  xpc/a xhrpoly,uhrpoly 2160 \
- 	"poly contact extends poly resistor by < %d (licon.1c + li.5)"
- spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
-	"Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
-
- spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
-	"Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
- spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
-	"Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
- spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
-	"Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
-
- angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
-
-#--------------------------------------------------------------------
-# HVTP
-#--------------------------------------------------------------------
-
- spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
-		360 touching_illegal \
-		"Min. spacing between pFET and HVTP < %d (hvtp.4)"
-
- spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
-		"Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
-
-#--------------------------------------------------------------------
-# LVTN
-#--------------------------------------------------------------------
-
- spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
-		allfetsnolvt 360 touching_illegal \
-		"Min. spacing between FET and LVTN < %d (lvtn.3a)"
-
- spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
-		740 touching_illegal \
-		"Min. spacing between LVTN and HVTP < %d (lvtn.9)"
-
- # Spacing across S/D direction requires edge rule
- edge4way allfetsnolvt allactivenonfet 415 \
-	~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
-	"Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
-
-#--------------------------------------------------------------------
-# NPC (Nitride poly Cut)
-#--------------------------------------------------------------------
-
-# Layer NPC is defined automatically around poly contacts (grow 0.1um)
-
-#--------------------------------------------------------------------
-# CONT (LICON, contact between poly/diff and LI)
-#--------------------------------------------------------------------
-
- width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
- width nsc/li 170 "N-tap contact width     < %d (licon.1)"
- width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
- width psc/li 170 "P-tap contact width     < %d (licon.1)"
- width ndic/li 170 "N-diode contact width < %d (licon.1)"
- width pdic/li 170 "P-diode contact width < %d (licon.1)"
- width pc/li  170 "poly contact width        < %d (licon.1)"
-
- width xpc/li  350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
- area  xpc/li  700000 350 "poly resistor contact length < 2.0um (licon.1c)"
- area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
-
- width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
- width mvnsc/li 170 "N-tap contact width     < %d (licon.1)"
- width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
- width mvpsc/li 170 "P-tap contact width     < %d (licon.1)"
- width mvndic/li 170 "N-diode contact width < %d (licon.1)"
- width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
-
- spacing allpdiffcont allndiffcont 170 touching_illegal \
-	"Diffusion contact spacing < %d (licon.2)"
- spacing allndiffcont allndiffcont 170 touching_ok \
-	"Diffusion contact spacing < %d (licon.2)"
- spacing allpdiffcont allpdiffcont 170 touching_ok \
-	"Diffusion contact spacing < %d (licon.2)"
- spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
-
- spacing pc alldiff 190 touching_illegal \
-	"poly contact spacing to diffusion < %d (licon.14)"
- spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
-	"poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
-
- spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
-	"Diffusion contact to gate < %d (licon.11)"
- spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
-	"Diffusion contact to standard cell gate < %d (licon.11)"
- spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
-	"Diffusion contact to SRAM gate < %d (licon.11)"
- spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
-	"Diffusion contact to gate < %d (licon.11)"
- spacing nsc varactor,varhvt 250 touching_illegal \
-	"Diffusion contact to varactor gate < %d (licon.10)"
- spacing mvnsc mvvar 250 touching_illegal \
-	"Diffusion contact to varactor gate < %d (licon.10)"
-
- surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
-	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
- surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
-	40 absence_illegal \
-	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
- surround ndic/a *ndi 40 absence_illegal \
-	"N-diode overlap of N-diode contact < %d (licon.5a)"
- surround pdic/a *pdi 40 absence_illegal \
-	"P-diode overlap of N-diode contact < %d (licon.5a)"
-
- spacing psc/a allnactivenontap 60 touching_illegal \
-	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
- spacing nsc/a allpactivenontap 60 touching_illegal \
-	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
-
- surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
-	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
- surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
-	 60 directional \
-	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
- surround ndic/a *ndi 60 directional \
-	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
- surround pdic/a *pdi 60 directional \
-	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
-
- surround nsc/a *nsd 120 directional \
-	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
- surround psc/a *psd 120 directional \
-	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"
-
- surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
-	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
- surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
-	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
- surround mvndic/a *mvndi 40 absence_illegal \
-	"N-diode overlap of N-diode contact < %d (licon.5a)"
- surround mvpdic/a *mvpdi 40 absence_illegal \
-	"P-diode overlap of N-diode contact < %d (licon.5a)"
-
- spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
-	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
- spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
-	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
-
- surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
-	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
- surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
-	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
- surround mvndic/a *mvndi 60 directional \
-	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
- surround mvpdic/a *mvpdi 60 directional \
-	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
-
- surround mvnsc/a *mvnsd 120 directional \
-	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
- surround mvpsc/a *mvpsd 120 directional \
-	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"
-
- surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
-	"poly overlap of poly contact < %d (licon.8)"
- surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
-	"poly overlap of poly contact < %d in one direction (licon.8a)"
-
- exact_overlap (allcont)/a
-
-#-------------------------------------------------------------
-# LI - Local interconnect layer
-#-------------------------------------------------------------
-
-variants *
-
- width *li 170 "Local interconnect width < %d (li.1)"
- width rli 290 "Local interconnect width < %d (li.7)"
-
- spacing *locali,rli *locali,rli,*obsli 170 touching_ok  \
-	"Local interconnect spacing < %d (li.3)"
-
- # Local interconnect in core (SRAM) cells has more relaxed rules.  There are
- # no special layers for the contacts in core cells, so they must be included
- # in the rule.
- width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
-	"Core local interconnect width < %d (li.c1)"
-
- spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
-	"Core local interconnect spacing < %d (li.c2)"
-
- surround pc/li *li,coreli 80 directional \
-	"Local interconnect overlap of poly contact < %d in one direction (li.5)"
-
- surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
-	*li,rli,coreli 80 directional \
-	"Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
-
- area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
-
- angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
- angles coreli 45 \
-	"Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
-
-#-------------------------------------------------------------
-# MCON - Contact between local interconnect and metal1
-#-------------------------------------------------------------
-
- width mcon/m1 170 "mcon.width < %d (mcon.1)"
- spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
-
- exact_overlap mcon/li
-
-#-------------------------------------------------------------
-# METAL1 -
-#-------------------------------------------------------------
-
- width *m1,rm1 140 "Metal1 width < %d (met1.1)"
- spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
- area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
-
- surround mcon/m1 *met1 30 absence_illegal \
-	"Metal1 overlap of local interconnect contact < %d (met1.4)"
- surround mcon/m1 *met1 60 directional \
-	"Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
-
- angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
-
-variants (fast),(full)
- widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
-	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
- widespacing *obsm1 3005 allm1 280 touching_ok \
-	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
-
-variants (full)
- cifmaxwidth m1_hole_empty 0 bend_illegal \
-	"Min area of metal1 holes > 0.14um^2 (met1.7)"
-
- cifspacing m1_large_halo m1_large_halo 280 touching_ok \
-	"Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
-variants *
-
-#--------------------------------------------------
-# VIA1
-#--------------------------------------------------
-
- width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
- spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
- surround v1/m1 *m1 30 directional \
-	"Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
- surround v1/m2 *m2 30 directional \
-	"Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
-
- exact_overlap v1/m1
-
-#--------------------------------------------------
-# METAL2 - 
-#--------------------------------------------------
-
- width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
- spacing allm2  allm2,obsm2,m2fill 140 touching_ok       "Metal2 spacing < %d (met2.2)"
- area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
-
- angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
-
-variants (fast),(full)
- widespacing allm2 3005 allm2,obsm2,m2fill  280 touching_ok \
-	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
- widespacing obsm2 3005 allm2  280 touching_ok \
-	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
-
-variants (full)
- cifmaxwidth m2_hole_empty 0 bend_illegal \
-	"Min area of metal2 holes > 0.14um^2 (met2.7)"
-
- cifspacing m2_large_halo m2_large_halo 280 touching_ok \
-	"Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
-variants *
-
-#--------------------------------------------------
-# VIA2
-#--------------------------------------------------
-
- width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
-
- spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
-
- surround v2/m2 *m2 45 directional \
-	"Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
- surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
-
- exact_overlap v2/m2
-
-#--------------------------------------------------
-# METAL3 - 
-#--------------------------------------------------
-
- width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
- spacing allm3 allm3,obsm3,m3fill  300 touching_ok "Metal3 spacing < %d (met3.2)"
- area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
-
- angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
-
-variants (fast),(full)
- widespacing allm3,m3fill 3005 allm3,obsm3  400 touching_ok \
-	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
- widespacing obsm3 3005 allm3  400 touching_ok \
-	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
-variants (full)
- cifspacing m3_large_halo m3_large_halo 400 touching_ok \
-	"Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
-variants *
-
-
-#--------------------------------------------------
-# VIA3 - Requires METAL5 Module
-#--------------------------------------------------
-
- width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
- spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
- surround v3/m3 *m3 30 directional \
-	"Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
- surround v3/m4 *m4 5 absence_illegal \
-	"Metal4 overlap of via3.< %d (met4.3 - via3.4)"
-
- exact_overlap v3/m3
-
-#-----------------------------
-# METAL4 - METAL4 Module
-#-----------------------------
-
-variants *
-
- width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
- spacing allm4  allm4,obsm4,m4fill 300 touching_ok      "Metal4 spacing < %d (met4.2)"
- area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
-
- angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
-
-variants (fast),(full)
- widespacing allm4,m4fill 3005 allm4,obsm4  400 touching_ok \
-	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
- widespacing obsm4 3005 allm4  400 touching_ok \
-	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
-variants (full)
- cifspacing m4_large_halo m4_large_halo 400 touching_ok \
-	"Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
-variants *
-
-#--------------------------------------------------
-# VIA4 - Requires METAL5 Module
-#--------------------------------------------------
-
- width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
- spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
- surround v4/m5 *m5 120 absence_illegal \
-	"Metal5 overlap of via4.< %d (met5.3 - via4.4)"
-
- exact_overlap v4/m4
-
-#-----------------------------
-# METAL5 - METAL5 Module
-#-----------------------------
-
- width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
- spacing allm5  allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
- area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
-
- angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
-
-
-
-variants (full)
-
- width metrdl 10000 "RDL width < %d (rdl.1)"
- spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
- surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
- spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
-
-variants (fast),(full)
-
-
-#--------------------------------------------------
-# NMOS, PMOS
-#--------------------------------------------------
-
- edge4way *poly allfetsstd 420 allfets 0 0 \
-	"Transistor width < %d (diff/tap.2)"
- edge4way *poly allfetsspecial 360 allfets 0 0 \
-	"Transistor in standard cell width < %d (diff/tap.2)"
- edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
-	"N-Transistor in SRAM core width < %d (diff/tap.2)"
- edge4way *poly ppu 140 allfets 0 0 \
-	"P-Transistor in SRAM core width < %d (diff/tap.2)"
-
- # Except:  Note that standard cells allow transistor width minimum 0.36um
- width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
-
- spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
-	"poly spacing to diffusion tap < %d (poly.5)"
- spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
-	"poly spacing to diffusion tap < %d (poly.5)"
- spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
-	"poly spacing to diffusion tap < %d (poly.5)"
- spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
-	"poly spacing to diffusion tap < %d (poly.5)"
-
- edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
-	"Butting P-tap spacing to NMOS gate < %d (poly.6)"
- edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
-	"Butting N-tap spacing to PMOS gate < %d (poly.6)"
- edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
-	"Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
- edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
-	"Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
-
- # No LV FETs in HV diff
- spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
-	"LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
-
- spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
-	"LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
-
- # No HV FETs in LV diff
- spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
-	"MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
-
- spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
-	"MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
-
- # Minimum length of MV FETs.  Note that this is larger than the minimum
- # width (0.29um), so an edge rule is required
-
- edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
-	"MV NMOS minimum length < %d (poly.13)"
-
- edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
-	"MV Varactor minimum length < %d (poly.13)"
-
- edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
-	"MV PMOS minimum length < %d (poly.13)"
-
-#--------------------------------------------------
-# mrp1 (N+ poly resistor)
-#--------------------------------------------------
-
-  width mrp1 330 "mrp1 resistor width < %d (poly.3)"
-
-#--------------------------------------------------
-# xhrpoly (P+ poly resistor)
-# uhrpoly (P+ poly resistor, 2kOhm/sq)
-#--------------------------------------------------
-
-  # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
-  width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
-  width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
-
-  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
-	"xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
-
-  spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
-	"Poly resistor spacing to poly < %d (poly.9)"
-
-  spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
-	"Poly resistor spacing to poly < %d (poly.9)"
-
-  spacing mrp1 *poly 480 touching_ok \
-	"Poly resistor spacing to poly < %d (poly.9)"
-
-  spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
-	"Poly resistor spacing to diffusion < %d (poly.9)"
-
-#------------------------------------
-# nsonos
-#------------------------------------
-
-variants (full)
-  cifmaxwidth bbox_missing 0 bend_illegal \
-	"SONOS transistor must be in cell with abutment box (tunm.8)"
-variants (fast),(full)
-
-#------------------------------------
-# MOS Varactor device rules
-#------------------------------------
-
- overhang *nsd var,varhvt 250 \
- "N-Tap overhang of Varactor < %d (var.4)"
-
- overhang *mvnsd mvvar 250 \
- "N-Tap overhang of Varactor < %d (var.4)"
-
- width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
- extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
-
-variants (full)
- cifmaxwidth var_poly_no_nwell 0 bend_illegal \
-	"N-well overlap of varactor poly < 0.15um (varac.5)"
-
- cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
-	"Varactor N-well must not contain P+ diffusion (varac.7)"
-variants (fast),(full)
-
-#-----------------------------------------------------------
-# MiM CAP (CAPM) - 
-#-----------------------------------------------------------
-
- width *mimcap 1000 "MiM cap width < %d (capm.1)"
- spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
- spacing *mimcap via3/m3 80 touching_illegal \
-	"MiM cap spacing to via3 < %d (capm.5 - via3.4)"
- surround *mimcc *mimcap 80 absence_illegal \
-	"MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
- rect_only *mimcap "MiM cap must be rectangular (capm.7)
-
- surround *mimcap *metal3/m3 140 absence_illegal \
-	"Metal3 must surround MiM cap by %d (capm.3)"
- spacing via2 *mimcap 100 touching_illegal \
-	"MiM cap spacing to via2 < %d (capm.8 - via2.4)"
- spacing *mimcap *metal3/m3 500 surround_ok \
-	"MiM cap spacing to unrelated metal3 < %d (capm.11)"
-
-variants (full)
- cifspacing mim_bottom mim_bottom 1200 touching_ok \
-	 "MiM cap bottom plate spacing < %d (capm.2b)"
-variants (fast),(full)
-
- # MiM cap contact rules (VIA3)
-
- width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
- spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
- surround mimcc/m4 *m4 5 directional \
-	"Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
- exact_overlap mimcc/c1
-
- width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
- spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
- spacing *mimcap2 via4/m4 10 touching_illegal \
-	"MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
- surround *mim2cc *mimcap2 10 absence_illegal \
-	"MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
- rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
-
- surround *mimcap2 *metal4/m4 140 absence_illegal \
-	"Metal4 must surround MiM2 cap by %d (cap2m.3)"
- spacing via3,mimcc *mimcap2 80 touching_illegal \
-	"MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
- spacing *mimcap2 *metal4/m4 500 surround_ok \
-	"MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
-
-variants (full)
- cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
- 	"MiM2 cap bottom plate spacing < %d (cap2m.2b)"
-variants (fast),(full)
-
- # MiM cap contact rules (VIA4)
-
- width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
- spacing mim2cc mim2cc 420 touching_ok \
-	"MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
- surround mim2cc/m5 *m5 120 absence_illegal \
-	"Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
- exact_overlap mim2cc/c2
-
-
-#----------------------------
-# HVNTM
-#----------------------------
-variants (full)
- cifspacing hvntm_generate hvntm_generate 700 touching_ok \
- 	"HVNTM spacing < %d (hvntm.2)"
-variants (fast),(full)
-
-#----------------------------
-# End DRC style
-#----------------------------
-
-end
-
-#----------------------------
-# LEF format definitions
-#----------------------------
-
-lef
-
- masterslice pwell  pwell PWELL substrate
- masterslice nwell  nwell NWELL
-
- routing li	li1 LI1 LI li
-
- routing m1	met1 MET1 m1
- routing m2	met2 MET2 m2
- routing m3	met3 MET3 m3
- routing m4	met4 MET4 m4
- routing m5	met5 MET5 m5
- routing mrdl	met6 MET6 m6 MRDL METRDL
-
- cut mcon  mcon MCON Mcon
- cut m2c  via via1 VIA VIA1 cont2 via12
- cut m3c  via2 VIA2 cont3 via23
- cut via3 via3 VIA3 cont4 via34
- cut via4 via4 VIA4 cont5 via45
-
- obs obsli   li1
- obs obsm1   met1
- obs obsm2   met2
- obs obsm3   met3
-
- obs obsm4   met4
- obs obsm5   met5
- obs obsmrdl met6
-
- # NOTE: obsmcon only used with li1, not obsli.
- obs obsmcon mcon
-
- # Vias on obstruction layers should be ignored, so cast to obstruction metal.
- obs obsm1   via
- obs obsm2   via2
- obs obsm3   via3
- obs obsm4   via4
-
-end
-
-#-----------------------------------------------------
-# Device and Parasitic extraction
-#-----------------------------------------------------
-
-
-extract
- style ngspice variants (),(orig),(si)
- cscale 1
- # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
- # dimensions must be in units of microns in the extract file.
- # Use extract style "ngspice(si)" to override this and produce
- # a file with SI units for length/area.
-
- variants (),(orig)
- lambda  1E6
- variants (si)
- lambda 1.0
- variants *
-
- units	microns
- step   7
- sidehalo 2
-
- # NOTE:  MiM cap layers have been purposely put out of order,
- # may want to reconsider.
-
- planeorder dwell 	0
- planeorder well 	1
- planeorder active 	2
- planeorder locali 	3
- planeorder metal1 	4
- planeorder metal2 	5
- planeorder metal3 	6
- planeorder metal4 	7
- planeorder metal5 	8
- planeorder metali	9
- planeorder block      10
- planeorder comment    11
- planeorder cap1       12
- planeorder cap2       13
-
- height	dnwell 	    -0.1    0.1
- height	nwell,pwell  0.0    0.2062
- height alldiff	     0.2062 0.12
- height fomfill	     0.2062 0.12
- height allpoly	     0.3262 0.18
- height polyfill     0.3262 0.18
- height alldiffcont  0.3262 0.61
- height pc	     0.5062 0.43
- height allli	     0.9361 0.10
- height mcon	     1.0361 0.34
- height allm1	     1.3761 0.36
- height m1fill	     1.3761 0.36
- height v1	     1.7361 0.27
- height allm2	     2.0061 0.36
- height m2fill	     1.3761 0.36
- height v2	     2.3661 0.42
- height allm3	     2.7861 0.845
- height m3fill	     1.3761 0.36
- height v3	     3.6311 0.39
- height allm4	     4.0211 0.845
- height m4fill	     1.3761 0.36
- height v4	     4.8661 0.505
- height allm5	     5.3711 1.26
- height m5fill	     1.3761 0.36
- height mimcap	     2.4661 0.2
- height mimcap2	     3.7311 0.2
- height mimcc	     2.6661 0.12
- height mim2cc	     3.9311 0.09
- height mrdlc	     6.6311 5.2523
- height mrdl	    11.8834 4.0
-
- # Antenna check parameters
- # Note that checks w/diode diffusion are not modeled
- model partial
- antenna poly sidewall 50 none
- antenna allcont surface 3 none
- antenna li sidewall 75 0 450
- antenna mcon surface 3 0 18
- antenna m1,m2,m3 sidewall 400 2600 400
- antenna v1 surface 3 0 18
- antenna v2 surface 6 0 36
- antenna m4,m5 sidewall 400 2600 400
- antenna v3,v4 surface 6 0 36
-
- tiedown alldiffnonfet
-
- substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
-
-# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
-
-# Resistances are in milliohms per square
-# Optional 3rd argument is the corner adjustment fraction
-# Device values come from trtc.cor (typical corner)
- resist (dnwell)/dwell          2200000
- resist (pwell)/well            3050000
- resist (nwell)/well            1700000
- resist (rpw)/well              3050000 0.5
- resist (*ndiff,nsd)/active 	 120000
- resist (*pdiff,*psd)/active	 197000
- resist (*mvndiff,mvnsd)/active  114000
- resist (*mvpdiff,*mvpsd)/active 191000
-
- resist ndiffres/active 	120000 0.5
- resist pdiffres/active 	197000 0.5
- resist mvndiffres/active 	114000 0.5
- resist mvpdiffres/active 	191000 0.5
- resist mrp1/active		 48200 0.5
- resist xhrpoly/active	        319800 0.5
- resist uhrpoly/active	       2000000 0.5
-
- resist (allpolynonres)/active   48200
- resist rmp/active   		 48200
-
- resist (allli)/locali		 12200
- resist (allm1)/metal1		   125
- resist (allm2)/metal2		   125
- resist (allm3)/metal3	            47
- resist (allm4)/metal4  	    47
- resist (allm5)/metal5  	    29
- resist mrdl/metali		     5
-
- contact ndc,nsc		 15000
- contact pdc,psc		 15000
- contact mvndc,mvnsc		 15000
- contact mvpdc,mvpsc	  	 15000
- contact pc			 15000
- contact mcon			152000
- contact m2c			  4500
- contact m3c			  3410
- contact mimcc			  4500
- contact mim2cc			  3410
- contact via3			  3410
- contact via4			   380
- contact mrdlc			     6
-
-#-------------------------------------------------------------------------
-# Parasitic capacitance values:  Use document (...)
-#-------------------------------------------------------------------------
-# This uses the new "default" definitions that determine the intervening
-# planes from the planeorder stack, take care of the reflexive sideoverlap
-# definitions, and generally clean up the section and make it more readable.
-#
-# Also uses "units microns" statement.  All values are taken from the
-# document PEX/xRC/cap_models.  Fringe capacitance values are approximated.
-# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
-#-------------------------------------------------------------------------
-# Remember that device capacitances to substrate are taken care of by the
-# models.  Thus, active and poly definitions ignore all "fet" types.
-# fet types are excluded when computing parasitic capacitance to
-# active from layers above them because poly is a shield; fet types are
-# included for parasitics from layers above to poly.  Resistor types
-# should be removed from all parasitic capacitance calculations, or else
-# they just create floating caps.  Technically, the capacitance probably
-# should be split between the two terminals.  Unsure of the correct model.
-#-------------------------------------------------------------------------
-
-#n-well
-# NOTE:  This value not found in PEX files
-defaultareacap     nwell well 120
-
-#n-active 
-# Rely on device models to capture *ndiff area cap
-# Do not extract parasitics from resistors
-# defaultareacap     allnactivenonfet active 790
-# defaultperimeter   allnactivenonfet active 280
-
-#p-active
-# Rely on device models to capture *pdiff area cap
-# Do not extract parasitics from resistors
-# defaultareacap     allpactivenonfet active 810
-# defaultperimeter   allpactivenonfet active 300
-
-#poly
-# Do not extract parasitics from resistors
-# defaultsidewall    allpolynonfet active  22
-# defaultareacap     allpolynonfet active  106
-# defaultperimeter   allpolynonfet active   57
-
- defaultsidewall    *poly active  23
- defaultareacap     *poly active nwell,obswell,pwell well  106
- defaultperimeter   *poly active nwell,obswell,pwell well  55
-
-#locali
- defaultsidewall    allli locali       33
- defaultareacap     allli locali nwell,obswell,pwell well  37
- defaultperimeter   allli locali nwell,obswell,pwell well  55
- defaultoverlap     allli locali nwell well 37
-
-#locali->diff
- defaultoverlap     allli locali allactivenonfet active 37
- defaultsideoverlap allli locali allactivenonfet active 55
-
-#locali->poly
- defaultoverlap     allli locali allpolynonres active 94
- defaultsideoverlap allli locali allpolynonres active 52
- defaultsideoverlap *poly active allli locali 25
-
-#metal1
- defaultsidewall    allm1 metal1      45
- defaultareacap     allm1 metal1 nwell,obswell,pwell well  26
- defaultperimeter   allm1 metal1 nwell,obswell,pwell well  41
- defaultoverlap     allm1 metal1 nwell well 26
-
-#metal1->diff
- defaultoverlap     allm1 metal1 allactivenonfet active 26
- defaultsideoverlap allm1 metal1 allactivenonfet active 41
-
-#metal1->poly
- defaultoverlap     allm1 metal1 allpolynonres active 45
- defaultsideoverlap allm1 metal1 allpolynonres active 47
- defaultsideoverlap *poly active allm1 metal1 17
-
-#metal1->locali
- defaultoverlap     allm1 metal1 allli locali 114
- defaultsideoverlap allm1 metal1 allli locali 59
- defaultsideoverlap allli locali allm1 metal1 35
-
-#metal2
- defaultsidewall    allm2 metal2      50
- defaultareacap     allm2 metal2 nwell,obswell,pwell well 17
- defaultperimeter   allm2 metal2 nwell,obswell,pwell well 41
- defaultoverlap     allm2 metal2 nwell well 38
-
-#metal2->diff
- defaultoverlap     allm2 metal2 allactivenonfet active 17
- defaultsideoverlap allm2 metal2 allactivenonfet active 41
-
-#metal2->poly
- defaultoverlap     allm2 metal2 allpolynonres active 24
- defaultsideoverlap allm2 metal2 allpolynonres active 41
- defaultsideoverlap *poly active allm2 metal2 11
-
-#metal2->locali
- defaultoverlap     allm2 metal2 allli locali 38
- defaultsideoverlap allm2 metal2 allli locali 46
- defaultsideoverlap allli locali allm2 metal2 22
-
-#metal2->metal1
- defaultoverlap     allm2 metal2 allm1 metal1 134
- defaultsideoverlap allm2 metal2 allm1 metal1 67
- defaultsideoverlap allm1 metal1 allm2 metal2 48
-
-#metal3
- defaultsidewall    allm3 metal3     63
- defaultoverlap     allm3 metal3 nwell well 12
- defaultareacap     allm3 metal3 nwell,obswell,pwell well 12
- defaultperimeter   allm3 metal3 nwell,obswell,pwell well 41
-
-#metal3->diff
- defaultoverlap     allm3 metal3 allactive active 12
- defaultsideoverlap allm3 metal3 allactive active 41
-
-#metal3->poly
- defaultoverlap     allm3 metal3 allpolynonres active 16
- defaultsideoverlap allm3 metal3 allpolynonres active 44
- defaultsideoverlap *poly active allm3 metal3 9
-
-#metal3->locali
- defaultoverlap     allm3 metal3 allli locali 21
- defaultsideoverlap allm3 metal3 allli locali 47
- defaultsideoverlap allli locali allm3 metal3 15
-
-#metal3->metal1
- defaultoverlap     allm3 metal3 allm1 metal1 35
- defaultsideoverlap allm3 metal3 allm1 metal1 55
- defaultsideoverlap allm1 metal1 allm3 metal3 27
-
-#metal3->metal2
- defaultoverlap     allm3 metal3 allm2 metal2 86
- defaultsideoverlap allm3 metal3 allm2 metal2 70
- defaultsideoverlap allm2 metal2 allm3 metal3 44
-
-#metal4
- defaultsidewall    allm4 metal4       67
-# defaultareacap     alltopm metal4 well  6
- areacap     	    allm4/m4 8
- defaultoverlap     allm4 metal4 nwell well 8
- defaultperimeter   allm4 metal4 well  37
-
-#metal4->diff
- defaultoverlap     allm4 metal4 allactivenonfet active 8
- defaultsideoverlap allm4 metal4 allactivenonfet active 37
-
-#metal4->poly
- defaultoverlap     allm4 metal4 allpolynonres active 10
- defaultsideoverlap allm4 metal4 allpolynonres active 38
- defaultsideoverlap *poly active allm4 metal4 6
-
-#metal4->locali
- defaultoverlap     allm4 metal4 allli locali 12
- defaultsideoverlap allm4 metal4 allli locali 40
- defaultsideoverlap allli locali allm4 metal4 10
-
-#metal4->metal1
- defaultoverlap     allm4 metal4 allm1 metal1 15
- defaultsideoverlap allm4 metal4 allm1 metal1 43
- defaultsideoverlap allm1 metal1 allm4 metal4 16
-
-#metal4->metal2
- defaultoverlap     allm4 metal4 allm2 metal2 20
- defaultsideoverlap allm4 metal4 allm2 metal2 46
- defaultsideoverlap allm2 metal2 allm4 metal4 22
-
-#metal4->metal3
- defaultoverlap     allm4 metal4 allm3 metal3 84
- defaultsideoverlap allm4 metal4 allm3 metal3 71
- defaultsideoverlap allm3 metal3 allm4 metal4 43
-
-#metal5
- defaultsidewall    allm5 metal5       127
-# defaultareacap     allm5 metal5 well  6
- areacap     	    allm5/m5 6
- defaultoverlap     allm5 metal5 nwell well 6
- defaultperimeter   allm5 metal5 well  39
-
-#metal5->diff
- defaultoverlap     allm5 metal5 allactivenonfet active 6
- defaultsideoverlap allm5 metal5 allactivenonfet active 39
-
-#metal5->poly
- defaultoverlap     allm5 metal5 allpolynonres active 7
- defaultsideoverlap allm5 metal5 allpolynonres active 40
- defaultsideoverlap *poly active allm5 metal5 6
-
-#metal5->locali
- defaultoverlap     allm5 metal5 allli locali 8
- defaultsideoverlap allm5 metal5 allli locali 41
- defaultsideoverlap allli locali allm5 metal5 8
-
-#metal5->metal1
- defaultoverlap     allm5 metal5 allm1 metal1 9
- defaultsideoverlap allm5 metal5 allm1 metal1 43
- defaultsideoverlap allm1 metal1 allm5 metal5 12
-
-#metal5->metal2
- defaultoverlap     allm5 metal5 allm2 metal2 11
- defaultsideoverlap allm5 metal5 allm2 metal2 46
- defaultsideoverlap allm2 metal2 allm5 metal5 16
-
-#metal5->metal3
- defaultoverlap     allm5 metal5 allm3 metal3 20
- defaultsideoverlap allm5 metal5 allm3 metal3 54
- defaultsideoverlap allm3 metal3 allm5 metal5 28
-
-#metal5->metal4
- defaultoverlap     allm5 metal5 allm4 metal4 68
- defaultsideoverlap allm5 metal5 allm4 metal4 83
- defaultsideoverlap allm4 metal4 allm5 metal5 47
-
-
-# Devices:  Base models (not subcircuit wrappers)
-
-variants (),(si)
-
- device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
-	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
-	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
-	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
-	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
-	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
-
- device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
-	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__special_nfet_latch npd \
-	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__special_nfet_latch npd \
-	*ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__special_nfet_pass npass \
-	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
-	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
-	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device subcircuit sky130_fd_pr__cap_var_lvt varactor \
-	*nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
- device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
-	*nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
- device subcircuit sky130_fd_pr__cap_var mvvaractor \
-	*mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
-
- # Bipolars
- device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
- device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
- device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
-
- # Ignore the extended-drain FET geometry that forms part of the high-voltage
- # bipolar devices.
- device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
- device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
-
- # Extended drain devices (must appear before the regular devices)
- device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
-	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
- device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
-	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
- device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
-	pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
-
- device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
-	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
-	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
-	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
-	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
-	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
- device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
-	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
-	a1=as p1=ps a2=ad p2=pd
-
- device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
- device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
- device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
- device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
- device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
- device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
-
- device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
-	xpc pwell,space/w error +res0p35 l=l
- device rsubcircuit sky130_fd_pr__res_high_po_0p69  xhrpoly \
-	xpc pwell,space/w error +res0p69 l=l
- device rsubcircuit sky130_fd_pr__res_high_po_1p41  xhrpoly \
-	xpc pwell,space/w error +res1p41 l=l
- device rsubcircuit sky130_fd_pr__res_high_po_2p85  xhrpoly \
-	xpc pwell,space/w error +res2p85 l=l
- device rsubcircuit sky130_fd_pr__res_high_po_5p73  xhrpoly \
-	xpc pwell,space/w error +res5p73 l=l
- device rsubcircuit sky130_fd_pr__res_high_po	    xhrpoly \
-	xpc pwell,space/w error l=l w=w
- device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35  uhrpoly \
-	xpc pwell,space/w error +res0p35 l=l
- device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69  uhrpoly \
-	xpc pwell,space/w error +res0p69 l=l
- device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41  uhrpoly \
-	xpc pwell,space/w error +res1p41 l=l
- device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85  uhrpoly \
-	xpc pwell,space/w error +res2p85 l=l
- device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73  uhrpoly \
-	xpc pwell,space/w error +res5p73 l=l
- device rsubcircuit sky130_fd_pr__res_xhigh_po	     uhrpoly \
-	xpc pwell,space/w error l=l w=w
-
- device rsubcircuit sky130_fd_pr__res_generic_nd     ndiffres \
-	*ndiff pwell,space/w  error l=l w=w
- device rsubcircuit sky130_fd_pr__res_generic_pd     pdiffres \
-	*pdiff nwell    error l=l w=w
- device rsubcircuit sky130_fd_pr__res_iso_pw   rpw \
-        pwell dnwell error l=l w=w
- device rsubcircuit sky130_fd_pr__res_generic_nd__hv  mvndiffres \
-	*mvndiff pwell,space/w error l=l w=w
- device rsubcircuit sky130_fd_pr__res_generic_pd__hv  mvpdiffres \
-	*mvpdiff nwell  error l=l w=w
-
- device resistor sky130_fd_pr__res_generic_po rmp *poly
- device resistor sky130_fd_pr__res_generic_po mrp1 *poly
-
- device subcircuit  sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
-	nwell a=area
- device subcircuit  sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
-	nwell a=area
- device subcircuit  sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
-	nwell a=area
- device subcircuit  sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
-	nwell a=area
-
- device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
-	pwell,space/w a=area
- device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
-	pwell,space/w a=area
- device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
-	pwell,space/w a=area
- device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
-	pwell,space/w a=area
-
-
- device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 w=w l=l
- device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
-
- variants (orig)
-
- device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell 
- device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell 
- device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell 
- device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell 
- device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell 
- device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
- device mosfet sky130_fd_pr__special_nfet_pass  npass ndiff,ndiffres,ndc pwell,space/w
- device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
- device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
- device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
- device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
-	pwell,space/w
-
- # Note that corenvar, corepvar are not considered devices, and extract as
- # parasitic capacitance instead (but cap values need to be added).
-
- # Extended drain devices (must appear before the regular devices)
- device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
-	dnwell pwell,space/w error
- device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
-	dnwell pwell,space/w error
- device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
-	pwell,space/w nwell error
-
- device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
- device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell 
- device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
- device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
- device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
- device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
-
- # These devices always extract as subcircuits
- device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
- device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
- device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
-
- device resistor sky130_fd_pr__res_generic_po rmp     *poly
- device resistor sky130_fd_pr__res_generic_l1 rli1    *li,coreli
- device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
- device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
- device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
- device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
- device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
-
- device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
- device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
- device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
- device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
- device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
- device resistor sky130_fd_pr__res_high_po xhrpoly xpc 
- device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
- device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
- device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
- device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
- device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
- device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc 
- device resistor sky130_fd_pr__res_generic_po  mrp1     *poly 
- device resistor sky130_fd_pr__res_generic_nd  ndiffres *ndiff 
- device resistor sky130_fd_pr__res_generic_pd  pdiffres *pdiff 
- device resistor mrdn_hv   mvndiffres *mvndiff 
- device resistor mrdp_hv   mvpdiffres *mvpdiff 
- device resistor sky130_fd_pr__res_iso_pw   rpw    pwell
-
- device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
- device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
- device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
- device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
-
- device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
- device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
- device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
- device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
-
- device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
- device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
- device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
-
- device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 1
- device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
-
-end
-
-#-----------------------------------------------------
-# Wiring tool definitions
-#-----------------------------------------------------
-
-wiring
- # All wiring values are in nanometers
- scalefactor 10
-
- contact mcon 170 li 0  0 m1 30 60
- contact v1  260 m1 0 30 m2  0 30
- contact v2  280 m2 0 45 m3 25  0
- contact v3  320 m3 0 30 m4  5  5
- contact v4 1180 m4 0    m5 120
-
- contact pc  170  poly 50 80 li 0 80
- contact pdc 170 pdiff 40 60 li 0 80
- contact ndc 170 ndiff 40 60 li 0 80
- contact psc 170   psd 40 60 li 0 80
- contact nsc 170   nsd 40 60 li 0 80
-
-end
-
-#-----------------------------------------------------
-# Plain old router. . . 
-#-----------------------------------------------------
-
-router
-end
-
-#------------------------------------------------------------
-# Plowing (restored in magic 8.2, need to fill this section)
-#------------------------------------------------------------
-
-plowing
-end
-
-#-----------------------------------------------------------------
-# No special plot layers defined (use default PNM color choices)
-#-----------------------------------------------------------------
-
-plot
-  style pnm
-     default
-     draw fillblock no_color_at_all
-     draw fillblock4 no_color_at_all
-     draw fomfill no_color_at_all
-     draw polyfill no_color_at_all
-     draw m1fill no_color_at_all
-     draw m2fill no_color_at_all
-     draw m3fill no_color_at_all
-     draw m4fill no_color_at_all
-     draw m5fill no_color_at_all
-     draw nwell cwell
-end
-
diff --git a/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.ext b/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.ext
deleted file mode 100644
index 8778668..0000000
--- a/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.ext
+++ /dev/null
@@ -1,43 +0,0 @@
-timestamp 1619689423
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-parameters :sky130_fd_pr__pnp_05v5_W3p40L3p40 m=1
-parameters sky130_fd_pr__pnp_05v0 a2=area
-node "0.068" 0 0 398 480 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "2.090" 0 0 398 177 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.345" 0 0 500 342 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.360" 0 0 224 454 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.310" 0 0 638 545 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.505" 0 0 719 342 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "2.450(nwell)" 0 0 398 621 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "3.720" 0 0 398 783 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.360" 0 0 397 148 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "adj. sides" 0 0 169 496 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "0.12 min" 0 0 169 517 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "Use 12 licons in base to match PNP model" 0 0 405 223 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "Use 28 licons in collector to match PNP model" 0 0 405 90 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_362_123#" 0 0 362 123 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_419_175#" 0 0 419 175 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_189_163#" 0 0 189 163 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_669_317#" 0 0 669 317 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_466_317#" 0 0 466 317 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_392_403#" 0 0 392 403 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_189_429#" 0 0 189 429 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_419_478#" 0 0 419 478 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_330_466#" 0 0 330 466 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_607_520#" 0 0 607 520 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_195_524#" 0 0 195 524 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_189_552#" 0 0 189 552 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_452_619#" 0 0 452 619 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_153_607#" 0 0 153 607 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "c_424_781#" 0 0 424 781 comment 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "a_330_330#" 209 426.213 330 330 pdif 0 0 0 0 0 0 0 0 0 0 18496 544 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24964 632 27556 664 0 0 0 0 0 0 0 0 0 0
-node "w_153_153#" 2269 1651.14 153 153 pnp 0 0 0 0 0 0 0 0 99648 2768 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99648 2768 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "w_0_0#" 0 0 0 0 pw 0 0 393516 5144 0 0 0 0 0 0 259772 5144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 259772 5144 0 0 0 0 0 0 0 0 0 0 0 0
-cap "a_330_330#" "w_153_153#" 359.586
-device msubckt sky130_fd_pr__pnp_05v0 153 153 154 154 "None" "w_153_153#" 0 0 "w_0_0#" 1960 0 "a_330_330#" 70 0
-subcap "a_330_330#" -108.625
diff --git a/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag b/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag
deleted file mode 100644
index 836e079..0000000
--- a/caravel/mag/sky130_fd_pr__pnp_05v5_W3p40L3p40.mag
+++ /dev/null
@@ -1,430 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1615375237
-<< pwell >>
-rect 26 669 770 770
-rect 26 127 127 669
-rect 669 127 770 669
-rect 26 26 770 127
-<< nbase >>
-rect 153 153 643 643
-<< pdiff >>
-rect 330 449 466 466
-rect 330 347 347 449
-rect 449 347 466 449
-rect 330 330 466 347
-<< pdiffc >>
-rect 347 347 449 449
-<< psubdiff >>
-rect 26 736 770 770
-rect 26 702 60 736
-rect 94 702 128 736
-rect 162 702 196 736
-rect 230 702 264 736
-rect 298 702 498 736
-rect 532 702 566 736
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-rect 26 669 770 702
-rect 26 668 127 669
-rect 26 634 60 668
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-rect 26 600 127 634
-rect 669 668 770 669
-rect 669 634 702 668
-rect 736 634 770 668
-rect 26 566 60 600
-rect 94 566 127 600
-rect 26 532 127 566
-rect 26 498 60 532
-rect 94 498 127 532
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-rect 26 264 60 298
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-rect 26 230 127 264
-rect 26 196 60 230
-rect 94 196 127 230
-rect 26 162 127 196
-rect 669 600 770 634
-rect 669 566 702 600
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-rect 669 532 770 566
-rect 669 498 702 532
-rect 736 498 770 532
-rect 669 298 770 498
-rect 669 264 702 298
-rect 736 264 770 298
-rect 669 230 770 264
-rect 669 196 702 230
-rect 736 196 770 230
-rect 26 128 60 162
-rect 94 128 127 162
-rect 26 127 127 128
-rect 669 162 770 196
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-rect 298 60 498 94
-rect 532 60 566 94
-rect 600 60 634 94
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-rect 736 60 770 94
-rect 26 26 770 60
-<< nsubdiff >>
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-rect 315 549 481 583
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-rect 535 315 607 481
-rect 535 281 549 315
-rect 583 281 607 315
-rect 535 261 607 281
-rect 189 247 607 261
-rect 189 213 213 247
-rect 247 213 281 247
-rect 315 213 481 247
-rect 515 213 549 247
-rect 583 213 607 247
-rect 189 189 607 213
-<< psubdiffcont >>
-rect 60 702 94 736
-rect 128 702 162 736
-rect 196 702 230 736
-rect 264 702 298 736
-rect 498 702 532 736
-rect 566 702 600 736
-rect 634 702 668 736
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-rect 60 634 94 668
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-rect 60 566 94 600
-rect 60 498 94 532
-rect 60 264 94 298
-rect 60 196 94 230
-rect 702 566 736 600
-rect 702 498 736 532
-rect 702 264 736 298
-rect 702 196 736 230
-rect 60 128 94 162
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-rect 60 60 94 94
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-rect 196 60 230 94
-rect 264 60 298 94
-rect 498 60 532 94
-rect 566 60 600 94
-rect 634 60 668 94
-rect 702 60 736 94
-<< nsubdiffcont >>
-rect 213 549 247 583
-rect 281 549 315 583
-rect 481 549 515 583
-rect 549 549 583 583
-rect 213 481 247 515
-rect 549 481 583 515
-rect 213 281 247 315
-rect 549 281 583 315
-rect 213 213 247 247
-rect 281 213 315 247
-rect 481 213 515 247
-rect 549 213 583 247
-<< locali >>
-rect 26 736 770 770
-rect 26 702 60 736
-rect 94 702 128 736
-rect 162 702 196 736
-rect 230 702 264 736
-rect 298 702 498 736
-rect 532 702 566 736
-rect 600 702 634 736
-rect 668 702 702 736
-rect 736 702 770 736
-rect 26 669 770 702
-rect 26 668 127 669
-rect 26 634 60 668
-rect 94 634 127 668
-rect 26 600 127 634
-rect 669 668 770 669
-rect 669 634 702 668
-rect 736 634 770 668
-rect 26 566 60 600
-rect 94 566 127 600
-rect 26 532 127 566
-rect 26 498 60 532
-rect 94 498 127 532
-rect 26 298 127 498
-rect 26 264 60 298
-rect 94 264 127 298
-rect 26 230 127 264
-rect 26 196 60 230
-rect 94 196 127 230
-rect 26 162 127 196
-rect 189 583 607 607
-rect 189 549 213 583
-rect 247 549 281 583
-rect 315 549 481 583
-rect 515 549 549 583
-rect 583 549 607 583
-rect 189 535 607 549
-rect 189 515 261 535
-rect 189 481 213 515
-rect 247 481 261 515
-rect 189 315 261 481
-rect 535 515 607 535
-rect 535 481 549 515
-rect 583 481 607 515
-rect 319 463 477 477
-rect 319 429 333 463
-rect 367 449 429 463
-rect 463 429 477 463
-rect 319 367 347 429
-rect 449 367 477 429
-rect 319 333 333 367
-rect 367 333 429 347
-rect 463 333 477 367
-rect 319 319 477 333
-rect 189 281 213 315
-rect 247 281 261 315
-rect 189 261 261 281
-rect 535 315 607 481
-rect 535 281 549 315
-rect 583 281 607 315
-rect 535 261 607 281
-rect 189 247 607 261
-rect 189 213 213 247
-rect 247 213 281 247
-rect 315 213 481 247
-rect 515 213 549 247
-rect 583 213 607 247
-rect 189 189 607 213
-rect 669 600 770 634
-rect 669 566 702 600
-rect 736 566 770 600
-rect 669 532 770 566
-rect 669 498 702 532
-rect 736 498 770 532
-rect 669 298 770 498
-rect 669 264 702 298
-rect 736 264 770 298
-rect 669 230 770 264
-rect 669 196 702 230
-rect 736 196 770 230
-rect 26 128 60 162
-rect 94 128 127 162
-rect 26 127 127 128
-rect 669 162 770 196
-rect 669 128 702 162
-rect 736 128 770 162
-rect 669 127 770 128
-rect 26 94 770 127
-rect 26 60 60 94
-rect 94 60 128 94
-rect 162 60 196 94
-rect 230 60 264 94
-rect 298 60 498 94
-rect 532 60 566 94
-rect 600 60 634 94
-rect 668 60 702 94
-rect 736 60 770 94
-rect 26 26 770 60
-<< viali >>
-rect 333 449 367 463
-rect 429 449 463 463
-rect 333 429 347 449
-rect 347 429 367 449
-rect 429 429 449 449
-rect 449 429 463 449
-rect 333 347 347 367
-rect 347 347 367 367
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-<< metal1 >>
-rect 315 463 481 481
-rect 315 429 333 463
-rect 367 429 429 463
-rect 463 429 481 463
-rect 315 367 481 429
-rect 315 333 333 367
-rect 367 333 429 367
-rect 463 333 481 367
-rect 315 315 481 333
-<< comment >>
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-tri 27 782 31 786 se
-tri 765 782 769 786 sw
-rect 769 782 770 795
-rect 26 781 371 782
-rect 424 781 770 782
-rect 26 769 27 781
-tri 27 777 31 781 ne
-tri 765 777 769 781 nw
-rect 769 769 770 781
-rect 153 620 154 633
-tri 154 620 158 624 se
-tri 638 620 642 624 sw
-rect 642 620 643 633
-rect 153 619 345 620
-rect 452 619 643 620
-rect 153 607 154 619
-tri 154 615 158 619 ne
-tri 638 615 642 619 nw
-rect 642 607 643 619
-rect 189 565 190 578
-tri 190 565 194 569 se
-tri 208 565 212 569 sw
-rect 212 565 213 578
-rect 189 564 213 565
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-tri 190 560 194 564 ne
-tri 199 560 201 563 se
-tri 208 560 212 564 nw
-tri 198 557 199 560 se
-rect 199 557 201 560
-tri 201 557 202 560 sw
-rect 197 556 198 557
-tri 198 556 199 557 nw
-rect 201 556 202 557
-rect 195 524 200 556
-rect 212 552 213 564
-rect 607 533 608 546
-tri 608 533 612 537 se
-tri 664 533 668 537 sw
-rect 668 533 669 546
-rect 607 532 669 533
-rect 607 520 608 532
-tri 608 528 612 532 ne
-tri 664 528 668 532 nw
-rect 668 520 669 532
-rect 330 479 331 492
-tri 331 479 335 483 se
-tri 461 479 465 483 sw
-rect 465 479 466 492
-rect 330 478 377 479
-rect 419 478 466 479
-rect 330 466 331 478
-tri 331 474 335 478 ne
-tri 461 474 465 478 nw
-rect 465 466 466 478
-rect 189 442 190 455
-tri 190 442 194 446 se
-tri 256 442 260 446 sw
-rect 260 442 261 455
-rect 189 441 261 442
-rect 189 429 190 441
-tri 190 437 194 441 ne
-tri 256 437 260 441 nw
-rect 260 429 261 441
-tri 390 404 392 406 se
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-rect 392 403 393 404
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-tri 403 401 406 404 nw
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-tri 395 398 396 400 ne
-tri 393 395 396 398 se
-rect 396 396 400 400
-tri 400 398 403 401 nw
-rect 396 395 397 396
-tri 397 395 398 396 nw
-tri 398 395 399 396 ne
-rect 399 395 400 396
-tri 400 395 403 398 sw
-tri 390 392 393 395 se
-tri 393 392 396 395 nw
-tri 400 392 403 395 ne
-tri 403 392 406 395 sw
-tri 390 390 392 392 ne
-tri 392 390 393 392 nw
-tri 403 390 404 392 ne
-tri 404 390 406 392 nw
-rect 466 330 467 343
-tri 467 330 471 334 se
-tri 530 330 534 334 sw
-rect 534 330 535 343
-rect 466 329 535 330
-rect 466 317 467 329
-tri 467 325 471 329 ne
-tri 530 325 534 329 nw
-rect 534 317 535 329
-rect 669 330 670 343
-tri 670 330 674 334 se
-tri 765 330 769 334 sw
-rect 769 330 770 343
-rect 669 329 770 330
-rect 669 317 670 329
-tri 670 325 674 329 ne
-tri 765 325 769 329 nw
-rect 769 317 770 329
-rect 189 176 190 189
-tri 190 176 194 180 se
-tri 602 176 606 180 sw
-rect 606 176 607 189
-rect 189 175 377 176
-rect 419 175 607 176
-rect 189 163 190 175
-tri 190 171 194 175 ne
-tri 602 171 606 175 nw
-rect 606 163 607 175
-rect 362 136 363 149
-tri 363 136 367 140 se
-tri 429 136 433 140 sw
-rect 433 136 434 149
-rect 362 135 434 136
-rect 362 123 363 135
-tri 363 131 367 135 ne
-tri 429 131 433 135 nw
-rect 433 123 434 135
-<< labels >>
-flabel comment s 405 90 405 90 0 FreeSans 180 0 0 0 Use 28 licons in collector to match PNP model
-flabel comment s 405 223 405 223 0 FreeSans 140 0 0 0 Use 12 licons in base to match PNP model
-flabel comment s 169 517 169 517 0 FreeSans 100 0 0 0 0.12 min
-flabel comment s 169 496 169 496 0 FreeSans 100 0 0 0 adj. sides
-flabel comment s 397 148 397 148 0 FreeSans 100 0 0 0 0.360
-flabel comment s 398 783 398 783 0 FreeSans 100 0 0 0 3.720
-flabel comment s 398 621 398 621 0 FreeSans 100 0 0 0 2.450(nwell)
-flabel comment s 719 342 719 342 0 FreeSans 100 0 0 0 0.505
-flabel comment s 638 545 638 545 0 FreeSans 100 0 0 0 0.310
-flabel comment s 224 454 224 454 0 FreeSans 100 0 0 0 0.360
-flabel comment s 500 342 500 342 0 FreeSans 100 0 0 0 0.345
-flabel comment s 398 177 398 177 0 FreeSans 100 0 0 0 2.090
-flabel comment s 398 480 398 480 0 FreeSans 100 0 0 0 0.068
-<< properties >>
-string gencell sky130_fd_pr__pnp_05v5_W3p40L3p40
-string GDS_FILE ~/Desktop/vsdflow/work/tools/openlane_working_dir/pdks/sky130A/libs.ref/sky130_fd_pr/gds/sky130_fd_pr.gds
-string GDS_END 3986574
-string GDS_START 3979106
-string parameter m=1
-string library sky130
-<< end >>
diff --git a/caravel/mag/user_project_wrapper.mag.gz b/caravel/mag/user_project_wrapper.mag.gz
deleted file mode 100644
index bcfbb26..0000000
--- a/caravel/mag/user_project_wrapper.mag.gz
+++ /dev/null
Binary files differ
diff --git a/caravel/mag/vdd_contact.ext b/caravel/mag/vdd_contact.ext
deleted file mode 100644
index 91b1568..0000000
--- a/caravel/mag/vdd_contact.ext
+++ /dev/null
@@ -1,8 +0,0 @@
-timestamp 1618641697
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-node "m1_0_0#" 1 2578 0 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 560000 3600 560000 3600 560000 3600 0 0 0 0 0 0
-substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/caravel/mag/vdd_contact.mag b/caravel/mag/vdd_contact.mag
deleted file mode 100644
index be611ad..0000000
--- a/caravel/mag/vdd_contact.mag
+++ /dev/null
@@ -1,14 +0,0 @@
-magic
-tech sky130A
-timestamp 1619505352
-<< locali >>
-rect -10 0 0 18
-rect 18 0 33 18
-<< viali >>
-rect 0 0 18 18
-<< metal1 >>
-rect -10 18 33 33
-rect -10 0 0 18
-rect 18 0 33 18
-rect -10 -15 33 0
-<< end >>