)]}'
{
  "commit": "485b8321cf8125750a4dd720a83dcd8a916a2ae6",
  "tree": "d76db7adbb0dc641eff7ddaf143af6664d4d8b09",
  "parents": [
    "a3affbca0aeaceca9b1bc8d458f32f3acf70365a"
  ],
  "author": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 15:43:59 2021 +0530"
  },
  "committer": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 15:43:59 2021 +0530"
  },
  "message": "Included PWM Verilog FIles\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "caa7ec5b2ec1429e82f50a448a63c1bf573d13bc",
      "old_mode": 33261,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "83865093ee596e5505b3e3cf16fa48fa099b9fb0",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    }
  ]
}