)]}'
{
  "commit": "45298af2e9f38330185c3210e3e79104fa97567b",
  "tree": "2f919b14562f0580036b4d9aeb35cbb404accc5b",
  "parents": [
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  "author": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 12:45:32 2021 +0530"
  },
  "committer": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Mon May 31 12:45:32 2021 +0530"
  },
  "message": "Updated PID Module Verilog files\n",
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