)]}'
{
  "commit": "09c149d0b678569bd7ae0b7823ea27ba0aec4da4",
  "tree": "b90c498cb5cfb2836ccae2b3e058b389696b3d6e",
  "parents": [
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  "author": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Fri Jun 04 19:33:10 2021 +0530"
  },
  "committer": {
    "name": "Baburaj",
    "email": "teche.raj2019@gmail.com",
    "time": "Fri Jun 04 19:33:10 2021 +0530"
  },
  "message": " Removed pwm and added ptc module\n",
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      "old_path": "verilog/gl/user_proj_example.v",
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}