diff --git a/Makefile b/Makefile
index 3e6c335..25a5e72 100644
--- a/Makefile
+++ b/Makefile
@@ -144,7 +144,7 @@
 run-precheck: check-precheck check-pdk check-caravel
 	$(eval TARGET_PATH := $(shell pwd))
 	cd $(PRECHECK_ROOT) && \
-	docker run -v $(PRECHECK_ROOT):/usr/local/bin -v $(TARGET_PATH):$(TARGET_PATH) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+	docker run -e TARGET_PATH=$(TARGET_PATH) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):/usr/local/bin -v $(TARGET_PATH):$(TARGET_PATH) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
 	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --pdk_root $(PDK_ROOT) --target_path $(TARGET_PATH) -rfc -c $(CARAVEL_ROOT) "
 
 # Install PDK using OL's Docker Image
diff --git a/verilog/dv/tbprog.v b/verilog/dv/tbprog.v
index 6800089..461b7d2 100644
--- a/verilog/dv/tbprog.v
+++ b/verilog/dv/tbprog.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
 `timescale 1ns / 1ps
 
 module tbprog #(
diff --git a/verilog/rtl/azadi_soc_top_dffram.v b/verilog/rtl/azadi_soc_top_dffram.v
index 51b0512..5b47cce 100644
--- a/verilog/rtl/azadi_soc_top_dffram.v
+++ b/verilog/rtl/azadi_soc_top_dffram.v
@@ -17448,47 +17448,31 @@
 	parameter adr_divisor_2 = 20;
 	parameter adr_period_2 = 24;
 	parameter adr_DC_2 = 28;
-	reg [7:0] ctrl;
+	reg [2:0] ctrl;
 	reg [15:0] period;
 	reg [15:0] DC_1;
 	reg [15:0] divisor;
-	reg [7:0] ctrl_2;
+	reg [2:0] ctrl_2;
 	reg [15:0] period_2;
 	reg [15:0] DC_2;
 	reg [15:0] divisor_2;
 	wire write;
 	assign write = we_i & ~re_i;
-	always @(posedge clk_i)
-		if (~rst_ni) begin
-			ctrl[4:2] <= 3'b000;
-			ctrl[0] <= 1'b0;
-			ctrl[1] <= 1'b0;
-			ctrl[7:5] <= 3'b000;
+	always @(posedge clk_i) begin
+		if (!rst_ni) begin
+			ctrl <= 3'b000;
 			DC_1 <= 16'b0000000000000000;
 			period <= 16'b0000000000000000;
 			divisor <= 16'b0000000000000000;
-			ctrl_2[4:2] <= 3'b000;
-			ctrl_2[0] <= 1'b0;
-			ctrl_2[7:5] <= 3'b000;
-			ctrl_2[1] <= 1'b0;
+			ctrl_2 <= 3'b000;
 			DC_2 <= 16'b0000000000000000;
 			period_2 <= 16'b0000000000000000;
 			divisor_2 <= 16'b0000000000000000;
 		end
-		else if (write)
+		else if (write) begin
 			case (addr_i)
-				adr_ctrl_1: begin
-					ctrl[0] <= wdata_i[0];
-					ctrl[1] <= 1'b1;
-					ctrl[4:2] <= wdata_i[4:2];
-					ctrl[7:5] <= wdata_i[7:5];
-				end
-				adr_ctrl_2: begin
-					ctrl_2[0] <= wdata_i[0];
-					ctrl_2[1] <= 1'b1;
-					ctrl_2[4:2] <= wdata_i[4:2];
-					ctrl_2[7:5] <= wdata_i[7:5];
-				end
+				adr_ctrl_1: ctrl <= wdata_i[2:0];
+				adr_ctrl_2: ctrl_2 <= wdata_i[2:0];
 				adr_divisor_1: divisor <= wdata_i[15:0];
 				adr_period_1: period <= wdata_i[15:0];
 				adr_DC_1: DC_1 <= wdata_i[15:0];
@@ -17496,6 +17480,8 @@
 				adr_period_2: period_2 <= wdata_i[15:0];
 				adr_DC_2: DC_2 <= wdata_i[15:0];
 			endcase
+		end
+	end
 	wire pwm_1;
 	assign pwm_1 = ctrl[1];
 	wire pwm_2;
@@ -17531,12 +17517,13 @@
 				end
 			end
 		end
-	always @(posedge clock_p1)
-		if (~rst_ni) begin
+	always @(posedge clock_p1 or negedge rst_ni)
+		if (!rst_ni) begin
 			pts <= 1'b0;
+			oe_pwm1 <= 1'b0;
 			period_counter1 <= 16'b0000000000000000;
 		end
-		else if (ctrl[2]) begin
+		else if (ctrl[0]) begin
 			if (pwm_1) begin
 				oe_pwm1 <= 1'b1;
 				if (period_counter1 >= period)
@@ -17549,17 +17536,14 @@
 					pts <= 1'b0;
 			end
 		end
-		else begin
-			pts <= 1'b0;
-			period_counter1 <= 16'b0000000000000000;
-			oe_pwm1 <= 1'b0;
-		end
-	always @(posedge clock_p2)
-		if (~rst_ni) begin
+
+	always @(posedge clock_p2 or negedge rst_ni)
+		if (!rst_ni) begin
 			pts_2 <= 1'b0;
+			oe_pwm2 <= 1'b0;
 			period_counter2 <= 16'b0000000000000000;
 		end
-		else if (ctrl_2[2]) begin
+		else if (ctrl_2[0]) begin
 			if (pwm_2) begin
 				oe_pwm2 <= 1'b1;
 				if (period_counter2 >= period_2)
@@ -17572,14 +17556,10 @@
 					pts_2 <= 1'b0;
 			end
 		end
-		else begin
-			pts_2 <= 1'b0;
-			period_counter2 <= 16'b0000000000000000;
-			oe_pwm2 <= 1'b0;
-		end
-	assign o_pwm = (ctrl[4] ? pts : 1'b0);
-	assign o_pwm_2 = (ctrl_2[4] ? pts_2 : 1'b0);
-	assign rdata_o = (addr_i == adr_ctrl_1 ? {8'h00, ctrl} : (addr_i == adr_divisor_1 ? divisor : (addr_i == adr_period_1 ? period : (addr_i == adr_DC_1 ? DC_1 : (addr_i == adr_DC_2 ? DC_2 : (addr_i == adr_period_2 ? period_2 : (addr_i == adr_divisor_2 ? divisor_2 : (addr_i == adr_ctrl_2 ? {8'h00, ctrl_2} : 32'b00000000000000000000000000000000))))))));
+
+	assign o_pwm = (ctrl[2] ? pts : 1'b0);
+	assign o_pwm_2 = (ctrl_2[2] ? pts_2 : 1'b0);
+	assign rdata_o = (addr_i == adr_ctrl_1 ? {13'h0, ctrl} : (addr_i == adr_divisor_1 ? divisor : (addr_i == adr_period_1 ? period : (addr_i == adr_DC_1 ? DC_1 : (addr_i == adr_DC_2 ? DC_2 : (addr_i == adr_period_2 ? period_2 : (addr_i == adr_divisor_2 ? divisor_2 : (addr_i == adr_ctrl_2 ? {13'h0, ctrl_2} : 32'b00000000000000000000000000000000))))))));
 endmodule
 module rr_arb_tree_252F1_F315E (
 	clk_i,