)]}'
{
  "commit": "55355ccaa856fa59654bcec462fd486f31b6403d",
  "tree": "009195f316489bf458cbf031bde277524af52384",
  "parents": [
    "236f5acde602751c4cafd3b0e7692b62cc419d59"
  ],
  "author": {
    "name": "zeeshanrafique23",
    "email": "zeeshanrafique23@gmail.com",
    "time": "Mon Jun 21 11:16:15 2021 +0500"
  },
  "committer": {
    "name": "zeeshanrafique23",
    "email": "zeeshanrafique23@gmail.com",
    "time": "Mon Jun 21 11:16:15 2021 +0500"
  },
  "message": "added design with 2KB of DFFRAM support\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "46dd37f9cf3c59087d37ff3854f8ed2715ab800f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/azadi_soc_top_dffram_2kb.v"
    }
  ]
}