)]}'
{
  "commit": "2ee2bc3d23c3e8ee75f9aa221a336b17cde27e18",
  "tree": "2b28dbe925de0cda871f5e3557253c57db6d84ab",
  "parents": [
    "1eb755f98f285d95a3819d935d5c9441ffc3fc76"
  ],
  "author": {
    "name": "zeeshanrafique23",
    "email": "zeeshanrafique23@gmail.com",
    "time": "Wed Jun 16 10:24:05 2021 +0500"
  },
  "committer": {
    "name": "zeeshanrafique23",
    "email": "zeeshanrafique23@gmail.com",
    "time": "Wed Jun 16 10:24:05 2021 +0500"
  },
  "message": "resolve the mismatch in  directionality of cell port issue\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "686626db2b2644eec40e9066e1a03485a6b55e39",
      "old_mode": 33188,
      "old_path": "verilog/rtl/azadi_soc_top_caravel.v",
      "new_id": "56b1e0ef2d3801956e6f9633d0fb5a5220a51475",
      "new_mode": 33188,
      "new_path": "verilog/rtl/azadi_soc_top_caravel.v"
    }
  ]
}