diff --git a/README.md b/README.md
index 5435e4a..cdb8719 100644
--- a/README.md
+++ b/README.md
@@ -8,13 +8,14 @@
 
 The LS130 cells are generated with the https://github.com/thesourcerer8/StdCellLib flow (which uses Librecell's lclayout and lctime), using the Tech.SKY130 configuration.
 
-The build report can be seen here: https://pdk.libresilicon.com/dist/StdCellLib_20201106_SKY130/Catalog/
-The cells were copied into this repository to avoid additional dependencies: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells/tree/release/cells
+The build report can be seen here: https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html
+The cells were copied into this repository to avoid additional dependencies: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/tree/main/cells
 
 A generator was developed to generate a Verilog file for all the cells that places each cell once and connects it to the IOs of the harness:
-https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/release/scripts/generator.pl The script needs to be run from the Catalog directory of your StdCellLib. The output is then used as https://github.com/thesourcerer8/caravel-stdcelllib-stdcells/blob/release/verilog/rtl/user_proj_example.v
+https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/scripts/generator.pl 
+The script needs to be run from the Catalog directory of your StdCellLib. The output is then used as https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/verilog/rtl/user_proj_example.v
 
-In the end I adapted https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/release/openlane/user_proj_example/config.tcl to use the cells as blackbox cells.
+In the end I adapted https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project/blob/main/openlane/user_proj_example/config.tcl to use the cells as blackbox cells.
 
 Build process: