diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 0adab80..025636f 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -83,7 +83,8 @@
     assign wdata = wbs_dat_i;
 
     // IO
-    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+    assign io_oeb[0] = 1'b1;
+    assign io_oeb[1] = 1'b0;
     assign RX_w = io_in[1];
     assign io_out[0] = TX_w;