diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b33e032..0adab80 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,17 +1,3 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
 
 `default_nettype none
 /*
@@ -76,7 +62,8 @@
 );
     wire clk;
     wire rst;
-
+    
+    wire RX_w,TX_w;	
     wire [`MPRJ_IO_PADS-1:0] io_in;
     wire [`MPRJ_IO_PADS-1:0] io_out;
     wire [`MPRJ_IO_PADS-1:0] io_oeb;
@@ -96,8 +83,9 @@
     assign wdata = wbs_dat_i;
 
     // IO
-    assign io_out = count;
     assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+    assign RX_w = io_in[1];
+    assign io_out[0] = TX_w;
 
     // IRQ
     assign irq = 3'b000;	// Unused
@@ -109,7 +97,7 @@
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
     assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
     assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
+/*
     counter #(
         .BITS(BITS)
     ) counter(
@@ -124,9 +112,207 @@
         .la_input(la_data_in[63:32]),
         .count(count)
     );
+*/
+    UART_top top(
+	.system_clk(clk),
+	.system_rst(rst),
+	.RX(RX_w),
+	.TX(TX_w)
+    );
 
 endmodule
+module UART_top(
+    input           system_clk      ,
+    input           system_rst      ,
+    input           RX              ,
+    output          TX                     
 
+  
+    );
+    
+
+    wire   busy   ;
+    wire [7:0]data_o_w;
+    wire  data_en_o_w;
+    wire corrupted_w;
+    
+    UART_transmitter uut(system_clk,system_rst,data_o_w,data_en_o_w,TX,busy);
+    UART_receiver uut2 (system_clk,system_rst,RX,data_o_w,data_en_o_w,corrupted_w);
+
+
+endmodule
+module UART_transmitter(
+    input           system_clk      ,
+    input           system_rst      ,
+    input   [7:0]   data            ,
+    input           data_en         ,
+
+
+    output    reg   TX=1            ,
+    output    reg   bitti=0    
+    );
+    reg [20:0]cycles_per_bit=868;
+    reg mesgul=1'b0;
+    reg [3:0] index=4'b0;
+    integer num_of_cycles=0;
+    wire  parity_bit  = data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0];
+
+    
+    wire [10:0] frame= {1'b1,parity_bit,data,1'b0};
+    
+
+    always @ (posedge system_clk ) begin
+           
+            if(!system_rst)begin
+                if(data_en && !mesgul && index==0) begin
+
+                        if(num_of_cycles==cycles_per_bit-1)begin
+                            num_of_cycles<=0;
+                            bitti        <= 1'b0;
+                            mesgul      <= 1'b1;
+                            TX          <= frame[index] ;  
+                            index       <= index + 1;
+                        end
+                        else begin
+                            num_of_cycles<= num_of_cycles+1;
+                            bitti        <= 1'b0;
+                            mesgul      <= 1'b1;
+                            TX          <= frame[index] ;  
+                        
+                        end
+                end
+                if(mesgul)begin
+                    if (index < 12) begin
+                        if(num_of_cycles==cycles_per_bit-1)begin
+                            num_of_cycles<=0;
+                            
+                            if(index==11)begin
+                                index       <= 1'b0;
+                                bitti        <= 1'b1;
+                                mesgul      <= 1'b0;
+                                TX          <= 1'b1;  
+                            end
+                            else begin
+                                TX          <= frame[index] ;
+                                index       <= index + 1;
+                            
+                            end
+                        end
+                        else begin
+                            
+                            
+                            if(index==11)begin
+                                index       <= 1'b0;
+                                bitti        <= 1'b1;
+                                mesgul      <= 1'b0;
+                                TX          <= 1'b1;  
+                                num_of_cycles<= 0;
+                            end
+                            else begin
+                                TX          <= frame[index] ;
+                                num_of_cycles<= num_of_cycles+1;
+                            end
+                        end
+                       
+                    end
+  
+                
+                
+                end
+            end
+            
+            else if ( system_rst) begin
+                bitti        <= 1'b0;
+                mesgul      <= 1'b0;
+                TX          <= 1'b1;
+                index       <= 4'd0;
+                num_of_cycles<=0;
+            end
+            
+           
+
+    end
+    
+  
+    
+endmodule
+
+module UART_receiver(
+    input           system_clk      ,
+    input           system_rst      ,
+    input           RX              ,
+  
+    
+    output  reg [7:0]   data            ,
+    output  reg     data_en=0,
+    output  reg     corrupted
+    );
+ 
+    reg[20:0] cycles_per_bit =868;
+    reg [3:0] index=4'd0;
+    integer num_of_cycles=0;
+    reg mesgul=0;
+    reg parity_bit=0;
+    reg stop_bit=0;
+
+    always @(posedge system_clk) begin
+        if( system_rst )begin
+            data_en<=0;
+            index<=4'd0;
+            num_of_cycles<=0;
+            mesgul<=0;
+        end
+        else if ( !system_rst ) begin
+
+            if(!mesgul && RX==0&& num_of_cycles ==(cycles_per_bit-1)/2)begin
+                data_en<=0;
+                mesgul <=1;
+                num_of_cycles <=  num_of_cycles+1;
+                
+            end
+            else if(mesgul&& num_of_cycles ==(cycles_per_bit-1)/2 ) begin
+                           
+                if(index <8) begin     
+                    data[index] <= RX;
+                    index <= index+1;
+                end
+                if(index==8)begin
+                    index <= index+1;
+                    parity_bit <= RX;
+                end
+                if(index==9) begin
+                    
+                    stop_bit <= RX;
+                    index <= index+1;
+  
+                        if(parity_bit==(data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]))begin
+                            corrupted <=0;
+                        end
+                        else begin 
+                            corrupted <=1;
+                        end
+                        
+                end
+                if(index==10)begin
+                    index <=0;
+                    mesgul<=0;
+                    data_en<=1;
+                   
+                end
+            end
+        end
+        
+        
+        if (!system_rst && num_of_cycles<cycles_per_bit-1) begin
+             num_of_cycles <=  num_of_cycles+1;
+
+        end
+        else if (!system_rst) begin
+            num_of_cycles <=0;
+        end
+    end
+endmodule
+/*
 module counter #(
     parameter BITS = 32
 )(
@@ -168,4 +354,5 @@
     end
 
 endmodule
+*/
 `default_nettype wire