)]}'
{
  "commit": "496112a959e05fc7df513b99034a90f4256fe8aa",
  "tree": "6855a39cfdc68791e3b5edc6e5113980fb4fcb23",
  "parents": [
    "6f6dd07626bf0b4f314968f5bcf3d14fc81aaf44"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Fri Apr 16 20:53:54 2021 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Fri Apr 16 20:53:54 2021 +0200"
  },
  "message": "Add CARAVEL_PATH for the testbenches\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3d78839648ae5e228739af3785cc2f378d636114",
      "old_mode": 57344,
      "old_path": "caravel",
      "new_id": "e68e07d00a87b1748f0b0d932c7f7810a25e8890",
      "new_mode": 57344,
      "new_path": "caravel"
    },
    {
      "type": "modify",
      "old_id": "a8d05b4f4423ae6c9bdd5656905f44f06bf15aa4",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/Makefile",
      "new_id": "b60690557db433831af90565f26768f75e358433",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "3574cd7c7527d4754580766fcd3ba8ed3c1727ee",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports.c",
      "new_id": "eb46b843b482f436ebd2f9be1abc84db2588bdac",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports.c"
    },
    {
      "type": "modify",
      "old_id": "33cf8acd92815a819bf13d4ba0c609d825e69320",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "39f3dcea285e930e84a54bdc70c6aed50915115d",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "257301c12577f19b839b4adc36dac8ccdb6cdcb4",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1.c",
      "new_id": "b77c8d529e8524c5453f6c4e10ab60ac50b7ae4b",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/la_test1.c"
    },
    {
      "type": "modify",
      "old_id": "44da75840daefeab023876b75cc4978713fdc8f4",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "597ace94623ca9515d582c6994b98cd3be646fcc",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "7c0556f5ff8b867d23b2530e5b840596d8c805ab",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2.c",
      "new_id": "1b8a3837fee8fb3d0cc51a3c33ea7b231425c034",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/la_test2.c"
    },
    {
      "type": "modify",
      "old_id": "7b31a5b186c8906f91eb6112d6c548d50b750dc7",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "d7f6e7b1637d396532115259553c4a2c7ad5f788",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a7424774af80f95e768373e17d2112faf9d3fffe",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/wb_port.c",
      "new_id": "46d778321900cd3fdb5b3e260e2aadd0f8b3bc83",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/wb_port.c"
    }
  ]
}