)]}'
{
  "commit": "2c77be4674254cf7614277d621e161db76115c48",
  "tree": "e0d70563a0507b4aab84414bcab3e1f5d80566e7",
  "parents": [
    "f875a8e3fffc6f32f2f44217e5748f60f5037b21"
  ],
  "author": {
    "name": "irem",
    "email": "iremnurcolak34@gmail.com",
    "time": "Fri Jun 18 13:28:39 2021 +0300"
  },
  "committer": {
    "name": "irem",
    "email": "iremnurcolak34@gmail.com",
    "time": "Fri Jun 18 13:28:39 2021 +0300"
  },
  "message": "clock frequency is made 50 MHz\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "025636f11e4d9716eeac152f9c0c327ae60071bb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "a32800c82234df083fb4431f53342c7726a89a4b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    }
  ]
}