
`default_nettype none
/*
 *-------------------------------------------------------------
 *
 * user_proj_example
 *
 * This is an example of a (trivially simple) user project,
 * showing how the user project can connect to the logic
 * analyzer, the wishbone bus, and the I/O pads.
 *
 * This project generates an integer count, which is output
 * on the user area GPIO pads (digital output only).  The
 * wishbone connection allows the project to be controlled
 * (start and stop) from the management SoC program.
 *
 * See the testbenches in directory "mprj_counter" for the
 * example programs that drive this user project.  The three
 * testbenches are "io_ports", "la_test1", and "la_test2".
 *
 *-------------------------------------------------------------
 */

module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vdda1,	// User area 1 3.3V supply
    inout vdda2,	// User area 2 3.3V supply
    inout vssa1,	// User area 1 analog ground
    inout vssa2,	// User area 2 analog ground
    inout vccd1,	// User area 1 1.8V supply
    inout vccd2,	// User area 2 1.8v supply
    inout vssd1,	// User area 1 digital ground
    inout vssd2,	// User area 2 digital ground
`endif

    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // IRQ
    output [2:0] irq
);
    wire clk;
    wire rst;
    
    wire RX_w,TX_w;	
    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] rdata; 
    wire [31:0] wdata;
    wire [BITS-1:0] count;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;

    // WB MI A
    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;

    // IO
    assign io_oeb[0] = 1'b1;
    assign io_oeb[1] = 1'b0;
    assign RX_w = io_in[1];
    assign io_out[0] = TX_w;
    assign io_oeb[(`MPRJ_IO_PADS-1):2] = {(`MPRJ_IO_PADS-3){rst}};
    // IRQ
    assign irq = 3'b000;	// Unused

    // LA
    assign la_data_out = {{(127-BITS){1'b0}}, count};
    // Assuming LA probes [63:32] are for controlling the count register  
    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
    // Assuming LA probes [65:64] are for controlling the count clk & reset  
    assign clk = wb_clk_i;
    assign rst = wb_rst_i;
/*
    counter #(
        .BITS(BITS)
    ) counter(
        .clk(clk),
        .reset(rst),
        .ready(wbs_ack_o),
        .valid(valid),
        .rdata(rdata),
        .wdata(wbs_dat_i),
        .wstrb(wstrb),
        .la_write(la_write),
        .la_input(la_data_in[63:32]),
        .count(count)
    );
*/
    UART_top top(
	.system_clk(clk),
	.system_rst(rst),
	.RX(RX_w),
	.TX(TX_w)
    );

endmodule
module UART_top(
    input           system_clk      ,
    input           system_rst      ,
    input           RX              ,
    output          TX                     

  
    );
    

    wire   busy   ;
    wire [7:0]data_o_w;
    wire  data_en_o_w;
    wire corrupted_w;
    
    UART_transmitter uut(system_clk,system_rst,data_o_w,data_en_o_w,TX,busy);
    UART_receiver uut2 (system_clk,system_rst,RX,data_o_w,data_en_o_w,corrupted_w);


endmodule
module UART_transmitter(
    input           system_clk      ,
    input           system_rst      ,
    input   [7:0]   data            ,
    input           data_en         ,


    output    reg   TX=1            ,
    output    reg   bitti=0    
    );
    reg [20:0]cycles_per_bit=434;
    reg mesgul=1'b0;
    reg [3:0] index=4'b0;
    integer num_of_cycles=0;
    wire  parity_bit  = data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0];

    
    wire [10:0] frame= {1'b1,parity_bit,data,1'b0};
    

    always @ (posedge system_clk ) begin
           
            if(!system_rst)begin
                if(data_en && !mesgul && index==0) begin

                        if(num_of_cycles==cycles_per_bit-1)begin
                            num_of_cycles<=0;
                            bitti        <= 1'b0;
                            mesgul      <= 1'b1;
                            TX          <= frame[index] ;  
                            index       <= index + 1;
                        end
                        else begin
                            num_of_cycles<= num_of_cycles+1;
                            bitti        <= 1'b0;
                            mesgul      <= 1'b1;
                            TX          <= frame[index] ;  
                        
                        end
                end
                if(mesgul)begin
                    if (index < 12) begin
                        if(num_of_cycles==cycles_per_bit-1)begin
                            num_of_cycles<=0;
                            
                            if(index==11)begin
                                index       <= 1'b0;
                                bitti        <= 1'b1;
                                mesgul      <= 1'b0;
                                TX          <= 1'b1;  
                            end
                            else begin
                                TX          <= frame[index] ;
                                index       <= index + 1;
                            
                            end
                        end
                        else begin
                            
                            
                            if(index==11)begin
                                index       <= 1'b0;
                                bitti        <= 1'b1;
                                mesgul      <= 1'b0;
                                TX          <= 1'b1;  
                                num_of_cycles<= 0;
                            end
                            else begin
                                TX          <= frame[index] ;
                                num_of_cycles<= num_of_cycles+1;
                            end
                        end
                       
                    end
  
                
                end
            end
            
            else if ( system_rst) begin
                bitti        <= 1'b0;
                mesgul      <= 1'b0;
                TX          <= 1'b1;
                index       <= 4'd0;
                num_of_cycles<=0;
            end
            
           
    end
    
  
endmodule

module UART_receiver(
    input           system_clk      ,
    input           system_rst      ,
    input           RX              ,
  
    
    output  reg [7:0]   data            ,
    output  reg     data_en=0,
    output  reg     corrupted
    );
 
    reg[20:0] cycles_per_bit =434;
    reg [3:0] index=4'd0;
    integer num_of_cycles=0;
    reg mesgul=0;
    reg parity_bit=0;
    reg stop_bit=0;

    always @(posedge system_clk) begin
        if( system_rst )begin
            data_en<=0;
            index<=4'd0;
            num_of_cycles<=0;
            mesgul<=0;
        end
        else if ( !system_rst ) begin

            if(!mesgul && RX==0&& num_of_cycles ==(cycles_per_bit-1)/2)begin
                data_en<=0;
                mesgul <=1;
                num_of_cycles <=  num_of_cycles+1;
                
            end
            else if(mesgul&& num_of_cycles ==(cycles_per_bit-1)/2 ) begin
                           
                if(index <8) begin     
                    data[index] <= RX;
                    index <= index+1;
                end
                if(index==8)begin
                    index <= index+1;
                    parity_bit <= RX;
                end
                if(index==9) begin
                    
                    stop_bit <= RX;
                    index <= index+1;
  
                        if(parity_bit==(data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]))begin
                            corrupted <=0;
                        end
                        else begin 
                            corrupted <=1;
                        end
                        
                end
                if(index==10)begin
                    index <=0;
                    mesgul<=0;
                    data_en<=1;
                   
                end
            end
        end
        
        
        if (!system_rst && num_of_cycles<cycles_per_bit-1) begin
             num_of_cycles <=  num_of_cycles+1;

        end
        else if (!system_rst) begin
            num_of_cycles <=0;
        end
    end
endmodule
/*
module counter #(
    parameter BITS = 32
)(
    input clk,
    input reset,
    input valid,
    input [3:0] wstrb,
    input [BITS-1:0] wdata,
    input [BITS-1:0] la_write,
    input [BITS-1:0] la_input,
    output ready,
    output [BITS-1:0] rdata,
    output [BITS-1:0] count
);
    reg ready;
    reg [BITS-1:0] count;
    reg [BITS-1:0] rdata;

    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
            ready <= 0;
        end else begin
            ready <= 1'b0;
            if (~|la_write) begin
                count <= count + 1;
            end
            if (valid && !ready) begin
                ready <= 1'b1;
                rdata <= count;
                if (wstrb[0]) count[7:0]   <= wdata[7:0];
                if (wstrb[1]) count[15:8]  <= wdata[15:8];
                if (wstrb[2]) count[23:16] <= wdata[23:16];
                if (wstrb[3]) count[31:24] <= wdata[31:24];
            end else if (|la_write) begin
                count <= la_write & la_input;
            end
        end
    end

endmodule
*/
`default_nettype wire