)]}'
{
  "commit": "37c76b83082668f92f35f69de5d498505425642e",
  "tree": "c0523ebdeb4b8958432438c9f1f7543754c80b08",
  "parents": [
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  ],
  "author": {
    "name": "manikandan-phd",
    "email": "manikandan_phd@outlook.com",
    "time": "Fri Jun 18 02:27:46 2021 +0530"
  },
  "committer": {
    "name": "manikandan-phd",
    "email": "manikandan_phd@outlook.com",
    "time": "Fri Jun 18 02:27:46 2021 +0530"
  },
  "message": "Submodule added\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f5e699b2be12e4d66215b22318d712de05b68e33",
      "new_mode": 33261,
      "new_path": "verilog/rtl/Per_32B.v"
    }
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}