Updates moving closer to MPW2 tapeout
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..3ea432b
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+utils/run_dir
diff --git a/amsat_txrx_ic b/amsat_txrx_ic
index 3a52ab7..c8a7cef 160000
--- a/amsat_txrx_ic
+++ b/amsat_txrx_ic
@@ -1 +1 @@
-Subproject commit 3a52ab7ea93bb3d79c7f5362fc47effe966304a0
+Subproject commit c8a7cefdd3930346ca9f74f1b72cdfaf730fc17b
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 6c15cc7..d28a5b1 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
index 8ba8660..b3a410a 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,13 +1,13 @@
---
project:
- description: "An analog project for Google sponsored Open MPW shuttles for SKY130."
+ description: "Amateur Radio Satellite Transceiver Protoype II - DAC, LO and mixer"
foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel_analog_user.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
+ git_url: "https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2.git"
+ organization: "N/A"
+ organization_url: "https://github.com/yrrapt/amsat_txrx_ic"
+ owner: "Thomas Parry"
process: "SKY130"
- project_name: "Caravel Analog User"
+ project_name: "Amsat_TXRX_IC"
project_id: "00000000"
tags:
- "Open MPW"
diff --git a/sourceme b/sourceme
new file mode 100644
index 0000000..a2f3c42
--- /dev/null
+++ b/sourceme
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+# define the location of the project
+export PROJECT_ROOT="$( cd "$( dirname "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )"
+
+# start the Python virtual environment
+source ~/.venvs/amsat_txrx_ic/bin/activate
\ No newline at end of file
diff --git a/utils/run_drc.sh b/utils/run_drc.sh
new file mode 100755
index 0000000..82e5af1
--- /dev/null
+++ b/utils/run_drc.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+# check the cell name has been provided by the user
+if [ $# -eq 0 ]; then
+ echo "No cell name provided"
+ exit 1
+fi
+
+# go into cell specific run folder
+cd ../temp
+if [ ! -d "$1" ]; then
+ mkdir -p "$1";
+fi
+cd "$1"
+
+# create a magic tcl command file
+echo "gds read ../../gds/user_analog_project_wrapper
+load $1
+flatten drc_cell
+load drc_cell" > magic_commands.tcl
+
+# run magic
+magic magic_commands.tcl &
diff --git a/utils/run_lvs.sh b/utils/run_lvs.sh
new file mode 100755
index 0000000..2ba33fc
--- /dev/null
+++ b/utils/run_lvs.sh
@@ -0,0 +1,64 @@
+#!/bin/bash
+
+# check the cell name has been provided by the user
+if [ $# -eq 0 ]; then
+ echo "No cell name provided"
+ exit 1
+fi
+
+mkdir -p run_dir
+
+# go into cell specific run folder
+cd run_dir
+if [ ! -d "$1" ]; then
+ mkdir -p "$1";
+fi
+cd "$1"
+
+# create a magic tcl command file
+echo "gds flatten true
+gds read ../../../gds/user_analog_project_wrapper.gds
+load $1
+extract all
+extract do all
+ext2spice lvs
+ext2spice -o $1_lvs.spice
+exit" > magic_commands.tcl
+
+# remove the old LVS export
+rm -f "$1_lvs.spice"
+
+# run magic
+magic -noconsole -dnull magic_commands.tcl
+
+# wait for new file to be generated
+printf "Waiting for LVS extracted netlist to be generated.."
+while [ ! -s "$1_lvs.spice" ]
+ do
+ printf "."
+ sleep 0.25
+done
+echo " "
+
+# move to the root directory and use xschem to generate a new netlist in LVS mode
+run_dir=$PWD
+cd $PROJECT_ROOT/xschem
+#cd $PROJECT_ROOT/amsat_txrx_ic/design
+xschem -n -q -o "$run_dir" --tcl "set top_subckt 1; set bus_replacement_char {[]}" "$PROJECT_ROOT/amsat_txrx_ic/design/$1/$1.sch"
+#xschem -n -q -o "$run_dir" --tcl "set top_subckt 1; set bus_replacement_char {[]}" "$1/$1.sch"
+cd $run_dir
+
+# include the digital cell definitions
+sed -i '$s,.end,.include '"$SKY130A"'\/libs.ref\/sky130_fd_sc_hd\/spice\/sky130_fd_sc_hd.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$SKY130A"'\/libs.ref\/sky130_fd_sc_hs\/spice\/sky130_fd_sc_hs.spice\n.end,g' "$1.spice"
+
+# include the library passive definitions
+#sed -i '$s,.end,.include '"$SKY130A"'\/libs.ref\/sky130_fd_pr\/spice\/sky130_fd_pr__res_xhigh_po_0p35.model.spice\n.end,g' "$1.spice"
+
+# now compare the xschem schematic netlist and the magic extracted netlist
+netgen -batch lvs "$1_lvs.spice "$1"" ""$1".spice "$1"" "$SKY130A/libs.tech/netgen/sky130A_setup.tcl"
+# netgen -batch lvs "$1_lvs.spice "$1"" ""$1".spice "$1"" "$SKY130A/libs.tech/netgen/sky130A_setup.tcl" lvs_report.out -json
+# netgen -batch lvs "$1_lvs.spice "$1"" ""$1".spice "$1"" lvs_report.out -json
+# netgen -batch lvs "$1_lvs.spice "$1"" ""$1".spice "$1"" "/usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl" lvs_report.out -json
+# netgen -batch lvs "$1_lvs.spice "$1"" ""$1".spice "$1"" "/usr/share/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl" lvs_report.out -json
+# netgen -batch lvs "dac_digital_interface_lvs.spice dac_digital_interface" "dac_digital_interface_library.spice dac_digital_interface" "/usr/share/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl" lvs_report.out -json
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/amsat_txrx_ic_mpw2.v
similarity index 88%
rename from verilog/rtl/user_analog_proj_example.v
rename to verilog/rtl/amsat_txrx_ic_mpw2.v
index 94412da..0037a22 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/amsat_txrx_ic_mpw2.v
@@ -78,7 +78,7 @@
*----------------------------------------------------------------
*/
-module user_analog_proj_example (
+module amsat_txrx_ic_mpw2 (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
@@ -177,44 +177,31 @@
// Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
// Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
- example_por por1 (
- `ifdef USE_POWER_PINS
- .vdd3v3(vdda1),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[3]), // 3.3V domain output
- .porb_l(io11), // 1.8V domain output
- .por_l(io12) // 1.8V domain output
- );
+ // example_por por1 (
+ // `ifdef USE_POWER_PINS
+ // .vdd3v3(vdda1),
+ // .vdd1v8(vccd1),
+ // .vss(vssa1),
+ // `endif
+ // .porb_h(gpio_analog[3]), // 3.3V domain output
+ // .porb_l(io11), // 1.8V domain output
+ // .por_l(io12) // 1.8V domain output
+ // );
// Instantiate 2nd POR with the analog power supply on one of the
// analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
// pad with io_clamp_high/low[0].
`ifdef USE_POWER_PINS
- assign isupply = io_analog[4];
- assign io_clamp_high[0] = isupply;
- assign io_clamp_low[0] = vssa1;
+ assign isupply = io_analog[4];
+ assign io_clamp_high[0] = isupply;
+ assign io_clamp_low[0] = vssa1;
- // Tie off remaining clamps
- assign io_clamp_high[2:1] = vssa1;
- assign io_clamp_low[2:1] = vssa1;
+ // Tie off remaining clamps
+ assign io_clamp_high[2:1] = vssa1;
+ assign io_clamp_low[2:1] = vssa1;
`endif
- // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
- // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
-
- example_por por2 (
- `ifdef USE_POWER_PINS
- .vdd3v3(isupply),
- .vdd1v8(vccd1),
- .vss(vssa1),
- `endif
- .porb_h(gpio_analog[7]), // 3.3V domain output
- .porb_l(io15), // 1.8V domain output
- .por_l(io16) // 1.8V domain output
- );
endmodule
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
deleted file mode 100644
index d318fba..0000000
--- a/verilog/rtl/example_por.v
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-`timescale 1 ns / 1 ps
-
-// This is just a copy of simple_por.v from the Caravel project, used
-// as an analog user project example.
-
-module example_por(
-`ifdef USE_POWER_PINS
- inout vdd3v3,
- inout vdd1v8,
- inout vss,
-`endif
- output porb_h,
- output porb_l,
- output por_l
-);
-
- wire mid, porb_h;
- reg inode;
-
- // This is a behavioral model! Actual circuit is a resitor dumping
- // current (slowly) from vdd3v3 onto a capacitor, and this fed into
- // two schmitt triggers for strong hysteresis/glitch tolerance.
-
- initial begin
- inode <= 1'b0;
- end
-
- // Emulate current source on capacitor as a 500ns delay either up or
- // down. Note that this is sped way up for verilog simulation; the
- // actual circuit is set to a 15ms delay.
-
- always @(posedge vdd3v3) begin
- #500 inode <= 1'b1;
- end
- always @(negedge vdd3v3) begin
- #500 inode <= 1'b0;
- end
-
- // Instantiate two shmitt trigger buffers in series
-
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VGND(vss),
- .VPB(vdd3v3),
- .VNB(vss),
-`endif
- .A(inode),
- .X(mid)
- );
-
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VGND(vss),
- .VPB(vdd3v3),
- .VNB(vss),
-`endif
- .A(mid),
- .X(porb_h)
- );
-
- sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
-`ifdef USE_POWER_PINS
- .VPWR(vdd3v3),
- .VPB(vdd3v3),
- .LVPWR(vdd1v8),
- .VNB(vss),
- .VGND(vss),
-`endif
- .A(porb_h),
- .X(porb_l)
- );
-
- // since this is behavioral anyway, but this should be
- // replaced by a proper inverter
- assign por_l = ~porb_l;
-endmodule
-`default_nettype wire
diff --git a/xschem/rf_section/rf_section.sch b/xschem/rf_section/rf_section.sch
new file mode 100644
index 0000000..621a537
--- /dev/null
+++ b/xschem/rf_section/rf_section.sch
@@ -0,0 +1,99 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1540 -200 1680 -200 { lab=#net1}
+N 1540 -180 1680 -180 { lab=#net2}
+N 1920 -200 2170 -200 { lab=#net3}
+N 1920 -180 2170 -180 { lab=#net4}
+N 980 -270 1260 -270 { lab=#net5}
+N 980 -250 1260 -250 { lab=#net6}
+N 2250 -760 2250 -260 { lab=vdd}
+N 1800 -760 1800 -290 { lab=vdd}
+N 1400 -760 1400 -330 { lab=vdd}
+N 860 -760 860 -360 { lab=vdd}
+N 860 -160 860 0 { lab=vss}
+N 1400 -90 1400 0 { lab=vss}
+N 1800 -90 1800 0 { lab=vss}
+N 2250 -120 2250 0 { lab=vss}
+N 430 -250 740 -250 { lab=#net7}
+N 430 -270 740 -270 { lab=#net8}
+N 720 -560 1000 -560 { lab=#net9}
+N 720 -540 1000 -540 { lab=#net10}
+N 1240 -560 1960 -560 { lab=#net11}
+N 1240 -540 1960 -540 { lab=#net12}
+N 2040 -480 2040 0 { lab=vss}
+N 2040 -760 2040 -620 { lab=vdd}
+N 1120 -450 1120 0 { lab=vss}
+N 1120 -760 1120 -650 { lab=vdd}
+N 280 -160 280 0 { lab=vss}
+N 280 -760 280 -360 { lab=vdd}
+N 570 -760 570 -650 { lab=vdd}
+N 570 -450 570 0 { lab=vss}
+N 40 -510 420 -510 { lab=vctl}
+N 40 -220 130 -220 { lab=vctl}
+N 40 -510 40 -220 { lab=vctl}
+N 0 -100 1160 -100 { lab=in_p}
+N 1160 -200 1160 -100 { lab=in_p}
+N 1160 -200 1260 -200 { lab=in_p}
+N 0 -80 1180 -80 { lab=in_n}
+N 1180 -180 1180 -80 { lab=in_n}
+N 1180 -180 1260 -180 { lab=in_n}
+N 1340 -360 1340 -330 { lab=bias[2]}
+N 1300 -360 1340 -360 { lab=bias[2]}
+N 2140 -560 2440 -560 { lab=out_osc_p}
+N 2040 -760 2250 -760 { lab=vdd}
+N 1400 -760 1800 -760 { lab=vdd}
+N 1120 -760 1400 -760 { lab=vdd}
+N 570 -760 860 -760 { lab=vdd}
+N 570 0 860 0 { lab=vss}
+N 1120 0 1400 0 { lab=vss}
+N 1400 0 1800 0 { lab=vss}
+N 2040 0 2250 0 { lab=vss}
+N 1800 0 2040 0 { lab=vss}
+N 1800 -760 2040 -760 { lab=vdd}
+N 860 0 1120 0 { lab=vss}
+N 860 -760 1120 -760 { lab=vdd}
+N 0 0 280 0 { lab=vss}
+N 0 -760 280 -760 { lab=vdd}
+N 280 -760 570 -760 { lab=vdd}
+N 280 0 570 0 { lab=vss}
+N 0 -510 40 -510 { lab=vctl}
+N 2140 -540 2440 -540 { lab=out_osc_n}
+N 2350 -200 2440 -200 { lab=out_mix_p}
+N 2350 -180 2440 -180 { lab=out_mix_n}
+C {io_driver/io_driver.sym} 2250 -190 0 0 {name=x1}
+C {lc_oscillator_buffer/lc_oscillator_buffer.sym} 1800 -190 0 0 {name=x2}
+C {upconvert/upconvert.sym} 1400 -190 0 0 {name=x3}
+C {io_driver/io_driver.sym} 2040 -550 0 0 {name=x4}
+C {lc_oscillator_buffer/lc_oscillator_buffer.sym} 1120 -550 0 0 {name=x5}
+C {lc_oscillator/lc_oscillator.sym} 570 -550 0 0 {name=x6}
+C {lc_oscillator_buffer/lc_oscillator_buffer.sym} 860 -260 0 0 {name=x7}
+C {iopin.sym} 0 0 0 1 {name=p1 lab=vss}
+C {iopin.sym} 0 -760 0 1 {name=p2 lab=vdd}
+C {lc_oscillator/lc_oscillator.sym} 280 -260 0 0 {name=x8}
+C {ipin.sym} 0 -660 0 0 {name=p3 lab=bias[7:0]}
+C {ipin.sym} 0 -510 0 0 {name=p4 lab=vctl}
+C {ipin.sym} 0 -100 0 0 {name=p5 lab=in_p}
+C {ipin.sym} 0 -80 0 0 {name=p6 lab=in_n}
+C {lab_pin.sym} 420 -590 0 0 {name=l1 sig_type=std_logic lab=bias[7]}
+C {lab_pin.sym} 1000 -610 0 0 {name=l2 sig_type=std_logic lab=bias[6]}
+C {lab_pin.sym} 1960 -590 0 0 {name=l3 sig_type=std_logic lab=bias[5]}
+C {lab_pin.sym} 130 -300 0 0 {name=l4 sig_type=std_logic lab=bias[4]}
+C {lab_pin.sym} 740 -320 0 0 {name=l5 sig_type=std_logic lab=bias[3]}
+C {lab_pin.sym} 1300 -360 0 0 {name=l6 sig_type=std_logic lab=bias[2]}
+C {lab_pin.sym} 1680 -250 0 0 {name=l7 sig_type=std_logic lab=bias[1]}
+C {lab_pin.sym} 2170 -230 0 0 {name=l8 sig_type=std_logic lab=bias[0]}
+C {lab_pin.sym} 1000 -490 0 0 {name=l9 sig_type=std_logic lab=en[1]}
+C {lab_pin.sym} 1960 -510 0 0 {name=l10 sig_type=std_logic lab=en[1]}
+C {lab_pin.sym} 740 -200 0 0 {name=l11 sig_type=std_logic lab=en[0]}
+C {lab_pin.sym} 1260 -130 0 0 {name=l12 sig_type=std_logic lab=en[0]}
+C {lab_pin.sym} 1680 -130 0 0 {name=l13 sig_type=std_logic lab=en[0]}
+C {lab_pin.sym} 2170 -150 0 0 {name=l14 sig_type=std_logic lab=en[0]}
+C {opin.sym} 2440 -560 0 0 {name=p7 lab=out_osc_p}
+C {opin.sym} 2440 -540 0 0 {name=p8 lab=out_osc_n}
+C {opin.sym} 2440 -200 0 0 {name=p9 lab=out_mix_p}
+C {opin.sym} 2440 -180 0 0 {name=p10 lab=out_mix_n}
+C {ipin.sym} 0 -620 0 0 {name=p11 lab=en[1:0]}
diff --git a/xschem/rf_section/rf_section.sym b/xschem/rf_section/rf_section.sym
new file mode 100644
index 0000000..135fd8d
--- /dev/null
+++ b/xschem/rf_section/rf_section.sym
@@ -0,0 +1,48 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -80 130 -80 {}
+L 4 -130 100 130 100 {}
+L 4 -130 -80 -130 100 {}
+L 4 130 -80 130 100 {}
+L 4 -150 60 -130 60 {}
+L 4 -150 80 -130 80 {}
+L 4 130 -40 150 -40 {}
+L 4 130 -20 150 -20 {}
+L 4 -150 20 -130 20 {}
+L 4 130 40 150 40 {}
+L 4 130 60 150 60 {}
+L 4 -150 -60 -130 -60 {}
+L 4 -150 -20 -130 -20 {}
+L 7 0 -100 0 -80 {}
+L 7 0 100 0 120 {}
+B 5 -2.5 -102.5 2.5 -97.5 {name=vdd dir=inout }
+B 5 -152.5 57.5 -147.5 62.5 {name=bias[7:0] dir=in }
+B 5 -152.5 77.5 -147.5 82.5 {name=en[1:0] dir=in }
+B 5 147.5 -42.5 152.5 -37.5 {name=out_osc_p dir=out }
+B 5 147.5 -22.5 152.5 -17.5 {name=out_osc_n dir=out }
+B 5 -152.5 17.5 -147.5 22.5 {name=vctl dir=in }
+B 5 147.5 37.5 152.5 42.5 {name=out_mix_p dir=out }
+B 5 147.5 57.5 152.5 62.5 {name=out_mix_n dir=out }
+B 5 -152.5 -62.5 -147.5 -57.5 {name=in_p dir=in }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=in_n dir=in }
+B 5 -2.5 117.5 2.5 122.5 {name=vss dir=inout }
+T {@symname} 37 104 0 0 0.3 0.3 {}
+T {@name} 45 108 0 0 0.2 0.2 {}
+T {vdd} 6 -75 0 1 0.2 0.2 {}
+T {bias[7:0]} -125 56 0 0 0.2 0.2 {}
+T {en[1:0]} -125 76 0 0 0.2 0.2 {}
+T {out_osc_p} 125 -44 0 1 0.2 0.2 {}
+T {out_osc_n} 125 -24 0 1 0.2 0.2 {}
+T {vctl} -125 16 0 0 0.2 0.2 {}
+T {out_mix_p} 125 36 0 1 0.2 0.2 {}
+T {out_mix_n} 125 56 0 1 0.2 0.2 {}
+T {in_p} -125 -64 0 0 0.2 0.2 {}
+T {in_n} -125 -24 0 0 0.2 0.2 {}
+T {vss} -6 95 2 1 0.2 0.2 {}
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
index 038829c..ada70a0 100644
--- a/xschem/user_analog_project_wrapper.sch
+++ b/xschem/user_analog_project_wrapper.sch
@@ -4,12 +4,39 @@
V {}
S {}
E {}
-C {devices/iopin.sym} 0 -940 0 1 {name=p1 lab=vdda1}
-C {devices/iopin.sym} 0 -920 0 1 {name=p2 lab=vdda2}
+N 0 -0 840 0 { lab=vssd2}
+N 840 -130 840 0 { lab=vssa1}
+N 490 -470 490 0 { lab=vssa1}
+N -0 -20 40 -20 { lab=vssd1}
+N 40 -20 40 0 { lab=vssa1}
+N 40 -80 40 -20 { lab=vssa1}
+N -0 -80 40 -80 { lab=vssa1}
+N -0 -60 40 -60 { lab=vssa2}
+N 470 -800 470 -630 { lab=vdda2}
+N 0 -800 470 -800 { lab=vdda2}
+N 820 -800 820 -290 { lab=vdda2}
+N 470 -800 820 -800 { lab=vdda2}
+N 860 -840 860 -290 { lab=vdda1}
+N 860 -860 860 -840 { lab=vdda1}
+N 0 -860 860 -860 { lab=vccd1}
+N 0 -840 40 -840 { lab=vccd2}
+N 40 -860 40 -840 { lab=vdda1}
+N 0 -820 40 -820 { lab=vdda1}
+N 40 -840 40 -820 { lab=vdda1}
+N 510 -860 510 -630 { lab=vdda1}
+N 980 -230 1140 -230 { lab=#net1}
+N 980 -190 1140 -190 { lab=#net2}
+N 1290 -860 1290 -270 { lab=vdda1}
+N 860 -860 1290 -860 { lab=vdda1}
+N 1290 -50 1290 0 { lab=vssa1}
+N 840 0 1290 0 { lab=vssa1}
+N 260 -860 260 -760 { lab=vdda1}
+C {devices/iopin.sym} 0 -820 0 1 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 0 -800 0 1 {name=p2 lab=vdda2}
C {devices/iopin.sym} 0 -80 0 1 {name=p3 lab=vssa1}
C {devices/iopin.sym} 0 -60 0 1 {name=p4 lab=vssa2}
-C {devices/iopin.sym} 0 -880 0 1 {name=p5 lab=vccd1}
-C {devices/iopin.sym} 0 -860 0 1 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 0 -860 0 1 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 0 -840 0 1 {name=p6 lab=vccd2}
C {devices/iopin.sym} 0 -20 0 1 {name=p7 lab=vssd1}
C {devices/iopin.sym} 0 0 0 1 {name=p8 lab=vssd2}
C {devices/ipin.sym} 0 -640 0 0 {name=p9 lab=wb_clk_i}
@@ -20,26 +47,40 @@
C {devices/ipin.sym} 0 -490 0 0 {name=p14 lab=wbs_sel_i[3:0]}
C {devices/ipin.sym} 0 -460 0 0 {name=p15 lab=wbs_dat_i[31:0]}
C {devices/ipin.sym} 0 -430 0 0 {name=p16 lab=wbs_adr_i[31:0]}
-C {devices/opin.sym} 1520 -620 0 0 {name=p17 lab=wbs_ack_o}
-C {devices/opin.sym} 1520 -600 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/opin.sym} 1720 -420 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 1720 -400 0 0 {name=p18 lab=wbs_dat_o[31:0]}
C {devices/ipin.sym} 0 -320 0 0 {name=p19 lab=la_data_in[127:0]}
-C {devices/opin.sym} 1520 -580 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/opin.sym} 1720 -380 0 0 {name=p20 lab=la_data_out[127:0]}
C {devices/ipin.sym} 0 -200 0 0 {name=p21 lab=io_in[26:0]}
C {devices/ipin.sym} 0 -180 0 0 {name=p22 lab=io_in_3v3[26:0]}
C {devices/ipin.sym} 0 -340 0 0 {name=p23 lab=user_clock2}
-C {devices/opin.sym} 1520 -560 0 0 {name=p24 lab=io_out[26:0]}
-C {devices/opin.sym} 1520 -540 0 0 {name=p25 lab=io_oeb[26:0]}
-C {devices/iopin.sym} 1520 -480 0 0 {name=p26 lab=gpio_analog[17:0]}
-C {devices/iopin.sym} 1520 -460 0 0 {name=p27 lab=gpio_noesd[17:0]}
-C {devices/iopin.sym} 1520 -440 0 0 {name=p29 lab=io_analog[10:0]}
-C {devices/iopin.sym} 1520 -420 0 0 {name=p30 lab=io_clamp_high[2:0]}
-C {devices/iopin.sym} 1520 -400 0 0 {name=p31 lab=io_clamp_low[2:0]}
-C {devices/opin.sym} 1520 -360 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/opin.sym} 1720 -360 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 1720 -340 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 1720 -280 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 1720 -260 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 1720 -240 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 1720 -220 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 1720 -200 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 1720 -160 0 0 {name=p32 lab=user_irq[2:0]}
C {devices/ipin.sym} 0 -300 0 0 {name=p28 lab=la_oenb[127:0]}
-C {dac/dac.sym} 420 -380 0 0 {name=x3}
-C {lab_pin.sym} 270 -430 0 0 {name=l1 sig_type=std_logic lab=gpio_analog[5]}
-C {lab_pin.sym} 270 -410 0 0 {name=l2 sig_type=std_logic lab=io_in[0]}
-C {lab_pin.sym} 270 -330 0 0 {name=l3 sig_type=std_logic lab=io_in[10:1]}
-C {lab_pin.sym} 270 -390 0 0 {name=l4 sig_type=std_logic lab=la_data_in[0]}
-C {lab_pin.sym} 270 -370 0 0 {name=l5 sig_type=std_logic lab=la_data_in[1]}
-C {lab_pin.sym} 270 -350 0 0 {name=l6 sig_type=std_logic lab=la_data_in[2]}
+C {dac/dac.sym} 840 -210 0 0 {name=x3}
+C {lab_pin.sym} 690 -240 0 0 {name=l2 sig_type=std_logic lab=io_in[0]}
+C {lab_pin.sym} 690 -160 0 0 {name=l3 sig_type=std_logic lab=io_in[10:1]}
+C {lab_pin.sym} 690 -220 0 0 {name=l4 sig_type=std_logic lab=la_data_in[3]}
+C {lab_pin.sym} 690 -200 0 0 {name=l5 sig_type=std_logic lab=la_data_in[4]}
+C {lab_pin.sym} 690 -180 0 0 {name=l6 sig_type=std_logic lab=la_data_in[5]}
+C {dac/dac.sym} 490 -550 0 0 {name=x1}
+C {lab_pin.sym} 340 -580 0 0 {name=l8 sig_type=std_logic lab=io_in[0]}
+C {lab_pin.sym} 340 -500 0 0 {name=l9 sig_type=std_logic lab=io_in[10:1]}
+C {lab_pin.sym} 340 -560 0 0 {name=l10 sig_type=std_logic lab=la_data_in[0]}
+C {lab_pin.sym} 340 -540 0 0 {name=l11 sig_type=std_logic lab=la_data_in[1]}
+C {lab_pin.sym} 340 -520 0 0 {name=l12 sig_type=std_logic lab=la_data_in[2]}
+C {rf_section/rf_section.sym} 1290 -170 0 0 {name=x2}
+C {test_bias/test_bias.sym} 260 -720 0 0 {name=x4[9:0]}
+C {lab_pin.sym} 340 -720 0 1 {name=l13 sig_type=std_logic lab=bias[9:0]}
+C {lab_pin.sym} 340 -600 0 0 {name=l1 sig_type=std_logic lab=bias[9]}
+C {lab_pin.sym} 690 -260 0 0 {name=l7 sig_type=std_logic lab=bias[8]}
+C {lab_pin.sym} 180 -720 0 0 {name=l14 sig_type=std_logic lab=gpio_analog[17:8]}
+C {lab_pin.sym} 1140 -110 0 0 {name=l15 sig_type=std_logic lab=bias[7:0]}
+C {lab_pin.sym} 1140 -150 0 0 {name=l16 sig_type=std_logic lab=gpio_analog[7]}
+C {lab_pin.sym} 1140 -90 0 0 {name=l17 sig_type=std_logic lab=la_data_in[7:6]}
