FULL RUN LOG:
 Executing Step 0 of 8: Extracting GDS Files
Step 0 done without fatal errors.
 Executing Step 1 of 8: Project License Check
{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
 SPDX COMPLIANCE Found 55 non-compliant files with the SPDX Standard. Check full log for more information
SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/README.md', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/verilog/rtl/picorv32.v', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/verilog/rtl/simpleuart.v', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/verilog/rtl/mgmt_soc.v', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/verilog/rtl/spimemio.v', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/10bitdac_cap_layout_design.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/5bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/10bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/9bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/INV.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/cap_28p.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/7bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/3bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/sky130A.tech', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/switch_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/6bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/2bitdac_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/res250_layout.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/cap_1p.ext', '/mnt/shuttles/mpw-two/slot-011/Potentiometric_Digit/Postlayout/8bitdac_layout.ext']
 Executing Step 2 of 8: YAML File Check
 YAML file valid!
Step 2 done without fatal errors.
 Detected Project Type is "analog"
 Executing Step 3 of 8: Project Compliance Checks
b'Going into /mnt/shuttles/mpw-two/caravel'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
 Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
verilog/rtl/DFFRAM.v: FAILED
verilog/rtl/DFFRAMBB.v: FAILED
verilog/rtl/__user_project_wrapper.v: FAILED
verilog/rtl/caravan.v: FAILED
verilog/rtl/caravan_netlists.v: FAILED
verilog/rtl/caravel.v: FAILED
verilog/rtl/chip_io.v: FAILED
verilog/rtl/chip_io_alt.v: FAILED
verilog/rtl/gpio_control_block.v: FAILED
verilog/rtl/housekeeping_spi.v: FAILED
verilog/rtl/mem_wb.v: FAILED
verilog/rtl/mgmt_core.v: FAILED
verilog/rtl/mgmt_protect.v: FAILED
verilog/rtl/mgmt_soc.v: FAILED
verilog/rtl/mprj_ctrl.v: FAILED
verilog/rtl/simple_spi_master.v: FAILED
verilog/rtl/sram_1rw1r_32_256_8_sky130.v: FAILED
verilog/rtl/storage.v: FAILED
scripts/generate_fill.py: FAILED
scripts/compositor.py: FAILED
 Makefile Checks Passed.
 Default config checks failed because: 
The parameter project_name in info.yaml is default
 Documentation Checks Passed.
 Executing Step 4 of 8: XOR Consistency Checks
 Running XOR Checks...
Total XOR differences = 0
 XOR Checks on User Project GDS Passed!
Step 4 done without fatal errors.
 Executing Step 5 of 8: DRC Violations Checks
 Running Magic DRC Checks...
 DRC Checks on User Project GDS Passed!
Step 5 done without fatal errors.
 Executing Step 6 of 8: KLayout DRC Violations Check
 Running Klayout DRC Checks...
 Klayout DRC Checks on User Project GDS Passed!
Step 6 done without fatal errors.
 Executing Klayout offgrid check.
 Klayout offgrid Checks on User Project GDS Passed!
Step 7 done without fatal errors.
 Klayout metal minimum clear area density Checks on User Project GDS Passed!
Step 7 done without fatal errors.
 SOME Checks FAILED !!!