timestamp 1616477680
version 8.3
tech sky130A
style ngspice()
scale 1000 1 1e+06
resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
use res250_layout res250_layout_0 1 0 -231 0 1 -33
use switch_layout switch_layout_0 1 0 8567 0 1 -111
use 5bitdac_layout 5bitdac_layout_0 1 0 34 0 1 6035
use 5bitdac_layout 5bitdac_layout_1 1 0 -16 0 1 -5989
node "gnd!" 24 9042.61 8626 -20 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4118 258 509733 19920 0 0 0 0 0 0 0 0
node "vdd!" 15 11109.5 9005 380 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2160 188 4069 272 4905 308 638861 28188 0 0 0 0
node "inp2" 24 101.923 -45 -12065 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1682 174 0 0 0 0 0 0 0 0 0 0 0 0
node "x2_out_v" 2636 8717.77 8160 -5487 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 233750 14278 0 0 0 0 0 0 0 0 0 0 0 0
node "d5" 14 102.678 8554 150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1886 174 0 0 0 0 0 0 0 0 0 0 0 0
node "out_v" 33 138.61 9775 228 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2573 228 588 106 0 0 0 0 0 0 0 0 0 0
node "x2_vref1" 63 235.018 -35 -225 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5248 392 0 0 0 0 0 0 0 0 0 0 0 0
node "x1_vref5" 81 318.356 -122 -90 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7853 526 0 0 0 0 0 0 0 0 0 0 0 0
node "d0" 380 1307.16 402 -519 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22446 1722 10041 812 0 0 0 0 0 0 0 0 0 0
node "d1" 437 2259.92 1931 -779 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52651 2818 24175 1378 0 0 0 0 0 0 0 0 0 0
node "d2" 551 4449.02 3663 1113 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158469 5458 65136 2164 0 0 0 0 0 0 0 0 0 0
node "d3" 1723 8101.08 5376 2424 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 236113 11620 39652 2054 0 0 0 0 0 0 0 0 0 0
node "d4" 6543 14647.8 6864 3261 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 269742 24096 10966 1030 0 0 0 0 0 0 0 0 0 0
node "x1_out_v" 3341 9283.48 8205 6546 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 215697 15428 0 0 0 0 0 0 0 0 0 0 0 0
node "inp1" 17 78.944 151 11827 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1120 136 0 0 0 0 0 0 0 0 0 0 0 0
substrate "SUB" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "vdd!" "d4" 26.366
cap "vdd!" "gnd!" 145.298
cap "gnd!" "d4" 95.9816
cap "x2_vref1" "x1_vref5" 24.1391
cap "5bitdac_layout_1/d4" "5bitdac_layout_1/switch_layout_0/INV_0/w_0_0#" 28.0797
cap "5bitdac_layout_1/d4" "5bitdac_layout_1/vdd!" 6.4016
cap "5bitdac_layout_1/switch_layout_0/dinb" "5bitdac_layout_1/d4" 26.4465
cap "5bitdac_layout_1/vdd!" "5bitdac_layout_1/d4" -75.3847
subcap "x2_out_v" -7382.3
subcap "x2_out_v" -8634.25
cap "d4" "5bitdac_layout_1/gnd!" -1.84
cap "5bitdac_layout_1/x1_out_v" "gnd!" 43.5052
cap "5bitdac_layout_1/4bitdac_layout_0/d3" "5bitdac_layout_1/4bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" 23.5492
cap "5bitdac_layout_1/4bitdac_layout_0/d3" "5bitdac_layout_1/4bitdac_layout_0/vdd!" 43.3656
cap "5bitdac_layout_1/4bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" "5bitdac_layout_1/4bitdac_layout_0/d3" 23.5492
cap "5bitdac_layout_1/x1_out_v" "d4" 28.4169
cap "vdd!" "5bitdac_layout_1/x1_out_v" 26.1448
cap "5bitdac_layout_1/x1_out_v" "d4" 12.4293
subcap "d1" -1422.49
subcap "d1" -2542.04
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 78.2202
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/INV_0/a_10_n215#" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 0.168235
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/dinb" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 29.301
cap "5bitdac_layout_1/4bitdac_layout_0/x1_out_v" "d3" 111.939
subcap "x1_vref5" -377.678
subcap "d0" -264.996
cap "res250_layout_0/a_205_n124#" "res250_layout_0/a_119_n123#" -7.21659
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" 128.459
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/vdd!" 127.32
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/dinb" 15.8851
subcap "d0" -1412.73
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/vdd!" 11.2269
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/dinb" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" 15.8851
subcap "d1" -1670.65
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_vout" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" 100.706
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/INV_0/w_0_0#" 47.9933
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/INV_0/a_80_n121#" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" 13.5882
subcap "d1" -1769.42
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/dinb" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" 13.5882
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/vdd!" 47.9933
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/vdd!" "d2" 67.6432
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/x1_out_v" "d2" 171.367
subcap "gnd!" -9883.92
subcap "x2_vref1" -269.501
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "res250_layout_0/a_119_n123#" 116.295
cap "res250_layout_0/a_205_n124#" "res250_layout_0/a_119_n123#" 69.1176
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/dinb" 6.5614
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/gnd!" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" 87.3763
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" 47.758
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_inp1" 6.31915
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/gnd!" 5.56375
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/dinb" 6.5614
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" "d1" 96.5773
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/vdd!" "d1" 47.1216
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_10_n215#" "d1" 464.713
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_10_n215#" -0.4256
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/gnd!" "d2" 72.5116
subcap "gnd!" -7393.57
subcap "vdd!" -9335.73
cap "switch_layout_0/din" "switch_layout_0/dinb" 0.184358
cap "switch_layout_0/vdd!" "switch_layout_0/INV_1/a_80_n121#" -3.09633
subcap "vdd!" -9621.26
cap "switch_layout_0/inp2" "switch_layout_0/w_908_86#" -3.55271e-15
cap "switch_layout_0/dd" "switch_layout_0/vdd!" 93.5561
subcap "out_v" -125.409
cap "switch_layout_0/inp1" "switch_layout_0/dd" 50.185
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_80_n121#" 5.73529
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_10_n215#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" 219.854
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" 7.82692
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_80_n121#" 5.73529
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_2/INV_0/a_10_n215#" 25.8457
subcap "d2" -3439.05
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/x2_out_v" "d2" 144.804
subcap "vdd!" -12809.3
subcap "vdd!" -10458.6
subcap "d2" -3148.79
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/switch_layout_0/INV_0/a_80_n121#" 1.66667
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/switch_layout_0/INV_0/a_10_n215#" 42.7953
cap "5bitdac_layout_0/4bitdac_layout_1/x2_out_v" "d3" 94.4934
subcap "d3" -7147.22
cap "d3" "5bitdac_layout_0/4bitdac_layout_1/x2_out_v" 3.83036
cap "d3" "5bitdac_layout_0/gnd!" 86.5552
subcap "d3" -8268.8
cap "d4" "gnd!" -8.36
cap "d4" "gnd!" -165.06
cap "5bitdac_layout_0/4bitdac_layout_1/gnd!" "5bitdac_layout_0/4bitdac_layout_1/d3" 281.897
cap "5bitdac_layout_0/4bitdac_layout_1/gnd!" "5bitdac_layout_0/4bitdac_layout_1/d3" 14.8228
cap "5bitdac_layout_0/4bitdac_layout_1/switch_layout_0/dinb" "5bitdac_layout_0/4bitdac_layout_1/d3" 2.46025
subcap "d4" -14196.3
cap "5bitdac_layout_0/x2_out_v" "d4" 2.36086
subcap "d4" -14132.3
cap "d4" "5bitdac_layout_0/x2_out_v" -123.453
cap "5bitdac_layout_0/4bitdac_layout_1/switch_layout_0/INV_0/a_n44_n51#" "5bitdac_layout_0/4bitdac_layout_1/vdd!" -165.6
subcap "d4" -14255.9
cap "5bitdac_layout_0/gnd!" "vdd!" 63.918
cap "5bitdac_layout_0/4bitdac_layout_1/switch_layout_0/inp1" "vdd!" 28.892
subcap "d4" -14246.9
cap "5bitdac_layout_0/x2_out_v" "vdd!" 22.156
cap "5bitdac_layout_0/gnd!" "5bitdac_layout_0/d4" 14.5124
cap "5bitdac_layout_0/gnd!" "5bitdac_layout_0/d4" -86.0489
subcap "x1_out_v" -8937.92
subcap "x1_out_v" -9133.01
cap "5bitdac_layout_0/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" "5bitdac_layout_0/inp1" 5.86667
merge "5bitdac_layout_0/4bitdac_layout_1/d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" -2876.64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17559 -3807 -28980 -2033 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2"
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" "5bitdac_layout_1/4bitdac_layout_0/d2"
merge "5bitdac_layout_1/4bitdac_layout_0/d2" "d2"
merge "switch_layout_0/vout" "out_v" 182.043 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 427 -92 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/d4" "5bitdac_layout_1/d4" -9336.83 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -127654 -15461 20854 -1030 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/d4" "d4"
merge "5bitdac_layout_0/inp1" "inp1" -63.0346 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3658 -90 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/d3" "5bitdac_layout_0/4bitdac_layout_1/d3" -5164.65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7486 -7965 -8784 -2054 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/d3" "5bitdac_layout_1/4bitdac_layout_0/d3"
merge "5bitdac_layout_1/4bitdac_layout_0/d3" "d3"
merge "5bitdac_layout_1/inp1" "res250_layout_0/a_205_n124#" -192.112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -17733 -230 0 0 0 0 0 0 0 0 0 0 0 0
merge "res250_layout_0/a_205_n124#" "x2_vref1"
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" -129.682 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13874 -264 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/din" "d0"
merge "5bitdac_layout_1/inp2" "inp2" -50.0983 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -459 -88 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/vdd!" "switch_layout_0/vdd!" -3459.37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -188493 -88 0 0 0 0 1259907 -11921 0 0 0 0
merge "switch_layout_0/vdd!" "5bitdac_layout_1/vdd!"
merge "5bitdac_layout_1/vdd!" "vdd!"
merge "5bitdac_layout_0/gnd!" "switch_layout_0/gnd!" -3085.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -51317 -144 275105 -8480 0 0 0 0 0 0 0 0
merge "switch_layout_0/gnd!" "5bitdac_layout_1/gnd!"
merge "5bitdac_layout_1/gnd!" "gnd!"
merge "switch_layout_0/SUB" "5bitdac_layout_0/SUB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/SUB" "res250_layout_0/SUB"
merge "res250_layout_0/SUB" "5bitdac_layout_1/SUB"
merge "5bitdac_layout_1/SUB" "SUB"
merge "5bitdac_layout_0/inp2" "res250_layout_0/a_119_n123#" -99.2767 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1709 -192 0 0 0 0 0 0 0 0 0 0 0 0
merge "res250_layout_0/a_119_n123#" "x1_vref5"
merge "5bitdac_layout_0/out_v" "switch_layout_0/inp1" -99.6201 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 427 -184 0 0 0 0 0 0 0 0 0 0 0 0
merge "switch_layout_0/inp1" "x1_out_v"
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" -1109.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -22745 -1620 167 -395 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" "d1"
merge "switch_layout_0/inp2" "5bitdac_layout_1/out_v" -398.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -86081 -146 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/out_v" "x2_out_v"
merge "switch_layout_0/din" "d5" -59.632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -360 -106 0 0 0 0 0 0 0 0 0 0 0 0