timestamp 1624221218
version 8.3
tech sky130A
style ngspice()
scale 1000 1 500000
resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
use 5bitdac_layout 5bitdac_layout_1 1 0 -32 0 1 -11978
use 5bitdac_layout 5bitdac_layout_0 1 0 68 0 1 12070
use switch_layout switch_layout_0 1 0 17134 0 1 -222
use res250_layout res250_layout_0 1 0 -462 0 1 -66
node "gnd!" 24 9042.61 17252 -40 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16472 516 2038932 39840 0 0 0 0 0 0 0 0
node "vdd!" 1 11109.5 18010 760 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8640 376 16276 544 19620 616 2555444 56376 0 0 0 0
node "inp2" 24 101.923 -90 -24130 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6728 348 0 0 0 0 0 0 0 0 0 0 0 0
node "x2_out_v" 2636 8717.77 16320 -10974 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 935000 28556 0 0 0 0 0 0 0 0 0 0 0 0
node "d5" 14 102.678 17108 300 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7544 348 0 0 0 0 0 0 0 0 0 0 0 0
node "out_v" 33 138.61 19550 456 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10292 456 2352 212 0 0 0 0 0 0 0 0 0 0
node "x2_vref1" 63 235.018 -70 -450 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20992 784 0 0 0 0 0 0 0 0 0 0 0 0
node "x1_vref5" 81 318.356 -244 -180 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31412 1052 0 0 0 0 0 0 0 0 0 0 0 0
node "d0" 380 1307.16 804 -1038 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89784 3444 40164 1624 0 0 0 0 0 0 0 0 0 0
node "d1" 437 2259.92 3862 -1558 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210604 5636 96700 2756 0 0 0 0 0 0 0 0 0 0
node "d2" 551 4449.02 7326 2226 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633876 10916 260544 4328 0 0 0 0 0 0 0 0 0 0
node "d3" 1723 8101.08 10752 4848 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 944452 23240 158608 4108 0 0 0 0 0 0 0 0 0 0
node "d4" 15 14647.8 13728 6522 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1078968 48192 43864 2060 0 0 0 0 0 0 0 0 0 0
node "x1_out_v" 3341 9283.48 16410 13092 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 862788 30856 0 0 0 0 0 0 0 0 0 0 0 0
node "inp1" 17 78.944 302 23654 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4480 272 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "x2_vref1" "x1_vref5" 24.1391
cap "d4" "gnd!" 95.9816
cap "gnd!" "vdd!" 145.298
cap "d4" "vdd!" 26.366
cap "5bitdac_layout_1/switch_layout_0/INV_0/w_0_0#" "5bitdac_layout_1/d4" 28.0797
cap "5bitdac_layout_1/d4" "5bitdac_layout_1/vdd!" 6.4016
cap "5bitdac_layout_1/vdd!" "5bitdac_layout_1/d4" -74.9847
cap "5bitdac_layout_1/switch_layout_0/dinb" "5bitdac_layout_1/d4" 26.4465
subcap "x2_out_v" -7382.3
subcap "x2_out_v" -8628.17
cap "d4" "5bitdac_layout_1/gnd!" -1.84
cap "5bitdac_layout_1/x1_out_v" "gnd!" 43.5052
cap "5bitdac_layout_1/4bitdac_layout_0/d3" "5bitdac_layout_1/4bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" 23.5492
cap "5bitdac_layout_1/4bitdac_layout_0/d3" "5bitdac_layout_1/4bitdac_layout_0/vdd!" 43.3656
cap "5bitdac_layout_1/4bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" "5bitdac_layout_1/4bitdac_layout_0/d3" 23.5492
cap "5bitdac_layout_1/x1_out_v" "d4" 28.4169
cap "d4" "5bitdac_layout_1/x1_out_v" 12.6043
cap "vdd!" "5bitdac_layout_1/x1_out_v" 26.1448
subcap "d1" -1442.63
subcap "d1" -2674.28
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/INV_0/w_20_n430#" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 0.168235
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 78.2202
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/switch_layout_0/dinb" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" 29.301
cap "5bitdac_layout_1/4bitdac_layout_0/x1_out_v" "d3" 111.939
subcap "x1_vref5" -377.678
subcap "d0" -265.775
cap "d0" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" 128.459
cap "x1_vref5" "x2_vref1" -7.21659
cap "d0" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/dinb" 15.8851
cap "d0" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/vdd!" 127.32
subcap "d0" -1384.1
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/vdd!" "d0" 12.0897
cap "d0" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/dinb" 15.8851
subcap "d1" -1615.7
cap "d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/INV_0/w_0_0#" 47.9933
cap "d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/INV_0/a_160_n242#" 13.5882
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_vout" "d1" 100.706
subcap "d1" -1766.08
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/vdd!" "d1" 47.9933
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_0/dinb" "d1" 13.5882
cap "d2" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/vdd!" 67.6432
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/x1_out_v" "d2" 171.367
subcap "gnd!" -9891.5
subcap "x2_vref1" -269.501
cap "d0" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" 47.758
cap "d0" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/dinb" 6.5614
cap "d0" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/gnd!" 87.3763
cap "d0" "x1_vref5" 116.295
cap "d0" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_inp1" 6.31915
cap "x2_vref1" "x1_vref5" 69.1176
cap "d0" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/gnd!" 6.25018
cap "d0" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/dinb" 6.5614
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/w_20_n430#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" -0.4256
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" "d1" 96.5773
cap "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/vdd!" "d1" 47.1216
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/w_20_n430#" "d1" 464.713
cap "d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/gnd!" 72.5116
subcap "gnd!" -7393.57
subcap "vdd!" -9328.51
cap "vdd!" "switch_layout_0/INV_1/a_160_n242#" -1.8578
cap "d5" "switch_layout_0/dinb" 0.184358
subcap "vdd!" -9509.53
cap "vdd!" "switch_layout_0/dd" 93.5561
cap "switch_layout_0/w_1816_172#" "x2_out_v" -3.55271e-15
cap "switch_layout_0/gnd!" "x2_out_v" 1.77636e-15
subcap "out_v" -120.235
cap "switch_layout_0/dd" "x1_out_v" 50.185
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/x2_vout" 7.82692
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/w_20_n430#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" 219.854
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/a_160_n242#" 5.73529
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/w_20_n430#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" 25.8457
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_0/INV_0/a_160_n242#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" 5.73529
subcap "d2" -3439.05
cap "d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/x2_out_v" 144.804
subcap "vdd!" -12819.2
subcap "vdd!" -10456.8
subcap "d2" -3148.79
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/switch_layout_0/INV_0/w_20_n430#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" 42.7953
cap "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/switch_layout_0/INV_0/a_160_n242#" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" 1.66667
cap "d3" "5bitdac_layout_0/4bitdac_layout_1/x2_out_v" 94.4934
subcap "d3" -7147.22
cap "d3" "5bitdac_layout_0/gnd!" 86.5552
cap "d3" "5bitdac_layout_0/4bitdac_layout_1/x2_out_v" 3.83036
subcap "d3" -8265.43
cap "gnd!" "d4" -8.36
cap "gnd!" "d4" -164.83
cap "5bitdac_layout_0/4bitdac_layout_1/gnd!" "5bitdac_layout_0/4bitdac_layout_1/d3" 281.897
cap "5bitdac_layout_0/4bitdac_layout_1/d3" "5bitdac_layout_0/4bitdac_layout_1/gnd!" 14.8228
cap "5bitdac_layout_0/4bitdac_layout_1/d3" "5bitdac_layout_0/4bitdac_layout_1/switch_layout_0/dinb" 2.46025
subcap "d4" -14194.4
cap "5bitdac_layout_0/x2_out_v" "d4" 2.36086
subcap "d4" -14128
cap "d4" "5bitdac_layout_0/x2_out_v" -123.453
cap "5bitdac_layout_0/4bitdac_layout_1/vdd!" "d3" -165.2
subcap "d4" -14256.4
cap "vdd!" "5bitdac_layout_0/4bitdac_layout_1/switch_layout_0/inp1" 28.892
cap "vdd!" "5bitdac_layout_0/gnd!" 63.918
subcap "d4" -14247.4
cap "vdd!" "5bitdac_layout_0/x2_out_v" 22.156
cap "5bitdac_layout_0/gnd!" "5bitdac_layout_0/d4" 14.5124
cap "5bitdac_layout_0/d4" "5bitdac_layout_0/gnd!" -86.0489
subcap "x1_out_v" -8938.37
subcap "x1_out_v" -9128.8
cap "inp1" "5bitdac_layout_0/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/x1_inp1" 5.86667
merge "5bitdac_layout_0/4bitdac_layout_1/d2" "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" -1161.48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127514 -2694 -144348 -2368 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/d2" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2"
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/d2" "5bitdac_layout_1/4bitdac_layout_0/d2"
merge "5bitdac_layout_1/4bitdac_layout_0/d2" "d2"
merge "switch_layout_0/vout" "out_v" 187.558 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10192 -184 0 0 0 0 0 0 0 0 0 0
merge "res250_layout_0/a_410_n248#" "5bitdac_layout_1/inp1" -192.112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -70932 -460 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/inp1" "x2_vref1"
merge "5bitdac_layout_0/d4" "5bitdac_layout_1/d4" -8438.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -447806 -28122 81826 -2060 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/d4" "d4"
merge "switch_layout_0/VSUBS" "res250_layout_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "res250_layout_0/VSUBS" "5bitdac_layout_0/VSUBS"
merge "5bitdac_layout_0/VSUBS" "5bitdac_layout_1/VSUBS"
merge "5bitdac_layout_1/VSUBS" "VSUBS"
merge "5bitdac_layout_0/inp1" "inp1" -63.0346 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -14632 -180 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/d3" "5bitdac_layout_0/4bitdac_layout_1/d3" -3807.9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80596 -11342 -46208 -4108 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/d3" "5bitdac_layout_1/4bitdac_layout_0/d3"
merge "5bitdac_layout_1/4bitdac_layout_0/d3" "d3"
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/switch_layout_1/din" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/din" -129.682 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55496 -528 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/switch_layout_2/din" "d0"
merge "5bitdac_layout_1/inp2" "inp2" -50.0983 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1836 -176 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/4bitdac_layout_1/vdd!" "switch_layout_0/vdd!" -3379.07 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -755550 -176 0 0 0 0 5039316 -23840 0 0 0 0
merge "switch_layout_0/vdd!" "5bitdac_layout_1/vdd!"
merge "5bitdac_layout_1/vdd!" "vdd!"
merge "5bitdac_layout_0/gnd!" "switch_layout_0/gnd!" -3203.74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -211815 -288 829860 -16957 0 0 0 0 0 0 0 0
merge "switch_layout_0/gnd!" "5bitdac_layout_1/gnd!"
merge "5bitdac_layout_1/gnd!" "gnd!"
merge "5bitdac_layout_0/out_v" "switch_layout_0/inp1" -99.6201 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1708 -368 0 0 0 0 0 0 0 0 0 0 0 0
merge "switch_layout_0/inp1" "x1_out_v"
merge "5bitdac_layout_0/4bitdac_layout_1/3bitdac_layout_1/2bitdac_layout_1/d1" "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" -300.06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -27840 -840 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/4bitdac_layout_0/3bitdac_layout_0/2bitdac_layout_0/d1" "d1"
merge "switch_layout_0/inp2" "5bitdac_layout_1/out_v" -398.8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -344324 -292 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_1/out_v" "x2_out_v"
merge "res250_layout_0/a_238_n246#" "5bitdac_layout_0/inp2" -99.2767 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6836 -384 0 0 0 0 0 0 0 0 0 0 0 0
merge "5bitdac_layout_0/inp2" "x1_vref5"
merge "switch_layout_0/din" "d5" -59.632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1440 -212 0 0 0 0 0 0 0 0 0 0 0 0