)]}'
{
  "commit": "f527929cfefb29ac47798f4218c8ecadf04171dd",
  "tree": "eec5a98eaaabf7d7c4ee8810c79ce74057b5ee7d",
  "parents": [
    "a9991772b5a8c84551cc5b4549ce29ef18645a1f"
  ],
  "author": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Tue Jun 08 15:36:53 2021 +0300"
  },
  "committer": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Tue Jun 08 15:36:53 2021 +0300"
  },
  "message": "Create dual_ram.v\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4f2d74347ca6c6aa227cf2e72feaee6cf998ebf8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/dual_ram.v"
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}