)]}'
{
  "commit": "b6122c80e076e3e3c9912cee67bca169d316c2b9",
  "tree": "a32b0f15ec53793676d242e166b4e851fb86bdaf",
  "parents": [
    "78b96fb06eb5656dc9c27a0bbfe1997d06098115"
  ],
  "author": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Mon Jun 07 20:49:11 2021 +0300"
  },
  "committer": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Mon Jun 07 20:49:11 2021 +0300"
  },
  "message": "Update Makefile\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d87238f0e5affdad2cdf0f2208e94beef2bb33bc",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "81f6ada79937373f9944468d774cbe40a57739e2",
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      "new_path": "verilog/dv/Makefile"
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}