)]}'
{
  "commit": "a9991772b5a8c84551cc5b4549ce29ef18645a1f",
  "tree": "20aaec00201a79bc9a877a97e2cfb6eb2468d409",
  "parents": [
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  "author": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Tue Jun 08 15:36:49 2021 +0300"
  },
  "committer": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Tue Jun 08 15:36:49 2021 +0300"
  },
  "message": "Create FIFO_v.v\n",
  "tree_diff": [
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      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "904db9369874bba8bbc397b8d5340ba77eb3aaa6",
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      "new_path": "verilog/rtl/FIFO_v.v"
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}
