)]}'
{
  "commit": "5b0c2417d724cd72338b1dba29897a65f4c6c047",
  "tree": "aa9d44e548b3a6a99a3e548649b4a5cbb8a51546",
  "parents": [
    "7ce6b7ac1a2bc38a8896cc508b100b8267981529"
  ],
  "author": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Mon Jun 07 10:49:54 2021 +0300"
  },
  "committer": {
    "name": "abdullahyildiz",
    "email": "abdullah.yildiz@yongatek.com",
    "time": "Mon Jun 07 10:49:54 2021 +0300"
  },
  "message": "Create Makefile\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ba50304a7fd231c3baafd540259fc9eef61a7f38",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_test/Makefile"
    }
  ]
}