)]}'
{
  "commit": "ff1d0fc3264d3f0ee530b30c30dcb03f3fa2c4ea",
  "tree": "a0f1c1b0ce5f3a424211c380cbb72971f6d789c9",
  "parents": [
    "15b80b21d8a106878bd9c928d91dad671caef23b"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:46:25 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat Jun 12 16:46:25 2021 -0700"
  },
  "message": "Figure out why csb0, web0, etc are changing\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6c6dcfd63a430582743183bf839379d7da0b3ef0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip_tb.v",
      "new_id": "a3d6459ac3ab72a130efd22796392ec13834db53",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip_tb.v"
    }
  ]
}