)]}'
{
  "commit": "fbb0983fbd80025a218e3a7c3089b91c7d4479ec",
  "tree": "0cae9d0567f9a138bb648631b13600b12c5e5779",
  "parents": [
    "386bcc4ffb128b10d78aa17640df0f45b91f25dc"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 07:35:54 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 07:35:54 2021 -0700"
  },
  "message": "Adding wrapper for control logic and SRAM modules\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d332b8a1a45c864b7b72ceffa65f49255bfb6934",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/test_chip.v"
    }
  ]
}