)]}'
{
  "commit": "f91aaa78cace6b2c624ced3f7c04807f83319b63",
  "tree": "a9828b179ac538355657b8fa0d50e9d1f144fd58",
  "parents": [
    "b9ee443811b1003548fb90ff7c6e9d95ab7b640e"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 08:07:13 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Thu May 13 08:07:13 2021 -0700"
  },
  "message": "Connected output port\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8937a9a00badb0da96553948c14ab95cce18506f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/test_chip.v",
      "new_id": "3b67b4df84338f907cec95b1ea11b4524f955f20",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/test_chip.v"
    }
  ]
}