)]}'
{
  "commit": "df0160f6b8bf4d2c49ef76c1ae3fa7597d79d906",
  "tree": "9c05a48448a589f3160c150a166551be5d6466ae",
  "parents": [
    "63f0643772fea425ae3445909bdb3ae89f67a971"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat May 29 21:21:10 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Sat May 29 21:21:10 2021 -0700"
  },
  "message": "New file with changed power pins\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "fe885ed77f4dcb502495638c824366947b150fc4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v"
    }
  ]
}