)]}'
{
  "commit": "dca58fabcb30648f59072d74a44064bbcf52ac6e",
  "tree": "12c8d854e68b57a05026aa8437825b821a079214",
  "parents": [
    "4b706b12d28b77a8325e97dca20fc4ec9055cf41"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 12:46:11 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Tue Jun 15 12:46:11 2021 -0700"
  },
  "message": "Used defines for splitting into fields\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "85d3dcecee779dcd3df0f8cd58deceb3c1591026",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "0bb19bded2c92ae6ba89ae96a85ec3643bed1714",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
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}