)]}'
{
  "commit": "da4b9cfb72fa2e044c64a6777ed8b9af138cc987",
  "tree": "a3baba4233d4bcb9214a9a33b2c21f4244844cfb",
  "parents": [
    "ad022ab9abe47e919730bf0378d498632b06cfc8"
  ],
  "author": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 18:38:50 2021 -0700"
  },
  "committer": {
    "name": "AmoghLonkar",
    "email": "alonkar@ucsc.edu",
    "time": "Mon May 17 18:38:50 2021 -0700"
  },
  "message": "Added rst conditions and needed to set web to low after writing. Mask/wdata when disabling is a small issue\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5ddb35cd1a9f568cf49f912363e31f8e81408c0d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/testchip/control_logic_tb.v",
      "new_id": "8272688503dceab6a89ee472fe333fe7b74c3936",
      "new_mode": 33188,
      "new_path": "verilog/rtl/testchip/control_logic_tb.v"
    }
  ]
}